1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 */ 117 #define KMS_DRIVER_MAJOR 3 118 #define KMS_DRIVER_MINOR 54 119 #define KMS_DRIVER_PATCHLEVEL 0 120 121 unsigned int amdgpu_vram_limit = UINT_MAX; 122 int amdgpu_vis_vram_limit; 123 int amdgpu_gart_size = -1; /* auto */ 124 int amdgpu_gtt_size = -1; /* auto */ 125 int amdgpu_moverate = -1; /* auto */ 126 int amdgpu_audio = -1; 127 int amdgpu_disp_priority; 128 int amdgpu_hw_i2c; 129 int amdgpu_pcie_gen2 = -1; 130 int amdgpu_msi = -1; 131 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 132 int amdgpu_dpm = -1; 133 int amdgpu_fw_load_type = -1; 134 int amdgpu_aspm = -1; 135 int amdgpu_runtime_pm = -1; 136 uint amdgpu_ip_block_mask = 0xffffffff; 137 int amdgpu_bapm = -1; 138 int amdgpu_deep_color; 139 int amdgpu_vm_size = -1; 140 int amdgpu_vm_fragment_size = -1; 141 int amdgpu_vm_block_size = -1; 142 int amdgpu_vm_fault_stop; 143 int amdgpu_vm_debug; 144 int amdgpu_vm_update_mode = -1; 145 int amdgpu_exp_hw_support; 146 int amdgpu_dc = -1; 147 int amdgpu_sched_jobs = 32; 148 int amdgpu_sched_hw_submission = 2; 149 uint amdgpu_pcie_gen_cap; 150 uint amdgpu_pcie_lane_cap; 151 u64 amdgpu_cg_mask = 0xffffffffffffffff; 152 uint amdgpu_pg_mask = 0xffffffff; 153 uint amdgpu_sdma_phase_quantum = 32; 154 char *amdgpu_disable_cu; 155 char *amdgpu_virtual_display; 156 bool enforce_isolation; 157 /* 158 * OverDrive(bit 14) disabled by default 159 * GFX DCS(bit 19) disabled by default 160 */ 161 uint amdgpu_pp_feature_mask = 0xfff7bfff; 162 uint amdgpu_force_long_training; 163 int amdgpu_lbpw = -1; 164 int amdgpu_compute_multipipe = -1; 165 int amdgpu_gpu_recovery = -1; /* auto */ 166 int amdgpu_emu_mode; 167 uint amdgpu_smu_memory_pool_size; 168 int amdgpu_smu_pptable_id = -1; 169 /* 170 * FBC (bit 0) disabled by default 171 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 172 * - With this, for multiple monitors in sync(e.g. with the same model), 173 * mclk switching will be allowed. And the mclk will be not foced to the 174 * highest. That helps saving some idle power. 175 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 176 * PSR (bit 3) disabled by default 177 * EDP NO POWER SEQUENCING (bit 4) disabled by default 178 */ 179 uint amdgpu_dc_feature_mask = 2; 180 uint amdgpu_dc_debug_mask; 181 uint amdgpu_dc_visual_confirm; 182 int amdgpu_async_gfx_ring = 1; 183 int amdgpu_mcbp = -1; 184 int amdgpu_discovery = -1; 185 int amdgpu_mes; 186 int amdgpu_mes_kiq; 187 int amdgpu_noretry = -1; 188 int amdgpu_force_asic_type = -1; 189 int amdgpu_tmz = -1; /* auto */ 190 uint amdgpu_freesync_vid_mode; 191 int amdgpu_reset_method = -1; /* auto */ 192 int amdgpu_num_kcq = -1; 193 int amdgpu_smartshift_bias; 194 int amdgpu_use_xgmi_p2p = 1; 195 int amdgpu_vcnfw_log; 196 int amdgpu_sg_display = -1; /* auto */ 197 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 198 199 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 200 201 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 202 "DRM_UT_CORE", 203 "DRM_UT_DRIVER", 204 "DRM_UT_KMS", 205 "DRM_UT_PRIME", 206 "DRM_UT_ATOMIC", 207 "DRM_UT_VBL", 208 "DRM_UT_STATE", 209 "DRM_UT_LEASE", 210 "DRM_UT_DP", 211 "DRM_UT_DRMRES"); 212 213 struct amdgpu_mgpu_info mgpu_info = { 214 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 215 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 216 mgpu_info.delayed_reset_work, 217 amdgpu_drv_delayed_reset_work_handler, 0), 218 }; 219 int amdgpu_ras_enable = -1; 220 uint amdgpu_ras_mask = 0xffffffff; 221 int amdgpu_bad_page_threshold = -1; 222 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 223 .timeout_fatal_disable = false, 224 .period = 0x0, /* default to 0x0 (timeout disable) */ 225 }; 226 227 /** 228 * DOC: vramlimit (int) 229 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 230 */ 231 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 232 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 233 234 /** 235 * DOC: vis_vramlimit (int) 236 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 237 */ 238 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 239 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 240 241 /** 242 * DOC: gartsize (uint) 243 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 244 * The default is -1 (The size depends on asic). 245 */ 246 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 247 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 248 249 /** 250 * DOC: gttsize (int) 251 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 252 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 253 */ 254 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 255 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 256 257 /** 258 * DOC: moverate (int) 259 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 260 */ 261 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 262 module_param_named(moverate, amdgpu_moverate, int, 0600); 263 264 /** 265 * DOC: audio (int) 266 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 267 */ 268 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 269 module_param_named(audio, amdgpu_audio, int, 0444); 270 271 /** 272 * DOC: disp_priority (int) 273 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 274 */ 275 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 276 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 277 278 /** 279 * DOC: hw_i2c (int) 280 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 281 */ 282 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 283 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 284 285 /** 286 * DOC: pcie_gen2 (int) 287 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 288 */ 289 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 290 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 291 292 /** 293 * DOC: msi (int) 294 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 295 */ 296 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 297 module_param_named(msi, amdgpu_msi, int, 0444); 298 299 /** 300 * DOC: lockup_timeout (string) 301 * Set GPU scheduler timeout value in ms. 302 * 303 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 304 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 305 * to the default timeout. 306 * 307 * - With one value specified, the setting will apply to all non-compute jobs. 308 * - With multiple values specified, the first one will be for GFX. 309 * The second one is for Compute. The third and fourth ones are 310 * for SDMA and Video. 311 * 312 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 313 * jobs is 10000. The timeout for compute is 60000. 314 */ 315 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 316 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 317 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 318 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 319 320 /** 321 * DOC: dpm (int) 322 * Override for dynamic power management setting 323 * (0 = disable, 1 = enable) 324 * The default is -1 (auto). 325 */ 326 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 327 module_param_named(dpm, amdgpu_dpm, int, 0444); 328 329 /** 330 * DOC: fw_load_type (int) 331 * Set different firmware loading type for debugging, if supported. 332 * Set to 0 to force direct loading if supported by the ASIC. Set 333 * to -1 to select the default loading mode for the ASIC, as defined 334 * by the driver. The default is -1 (auto). 335 */ 336 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 337 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 338 339 /** 340 * DOC: aspm (int) 341 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 342 */ 343 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 344 module_param_named(aspm, amdgpu_aspm, int, 0444); 345 346 /** 347 * DOC: runpm (int) 348 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 349 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 350 * Setting the value to 0 disables this functionality. 351 */ 352 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 353 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 354 355 /** 356 * DOC: ip_block_mask (uint) 357 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 358 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 359 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 360 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 361 */ 362 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 363 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 364 365 /** 366 * DOC: bapm (int) 367 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 368 * The default -1 (auto, enabled) 369 */ 370 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 371 module_param_named(bapm, amdgpu_bapm, int, 0444); 372 373 /** 374 * DOC: deep_color (int) 375 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 376 */ 377 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 378 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 379 380 /** 381 * DOC: vm_size (int) 382 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 383 */ 384 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 385 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 386 387 /** 388 * DOC: vm_fragment_size (int) 389 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 390 */ 391 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 392 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 393 394 /** 395 * DOC: vm_block_size (int) 396 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 397 */ 398 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 399 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 400 401 /** 402 * DOC: vm_fault_stop (int) 403 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 404 */ 405 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 406 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 407 408 /** 409 * DOC: vm_debug (int) 410 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 411 */ 412 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 413 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 414 415 /** 416 * DOC: vm_update_mode (int) 417 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 418 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 419 */ 420 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 421 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 422 423 /** 424 * DOC: exp_hw_support (int) 425 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 426 */ 427 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 428 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 429 430 /** 431 * DOC: dc (int) 432 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 433 */ 434 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 435 module_param_named(dc, amdgpu_dc, int, 0444); 436 437 /** 438 * DOC: sched_jobs (int) 439 * Override the max number of jobs supported in the sw queue. The default is 32. 440 */ 441 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 442 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 443 444 /** 445 * DOC: sched_hw_submission (int) 446 * Override the max number of HW submissions. The default is 2. 447 */ 448 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 449 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 450 451 /** 452 * DOC: ppfeaturemask (hexint) 453 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 454 * The default is the current set of stable power features. 455 */ 456 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 457 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 458 459 /** 460 * DOC: forcelongtraining (uint) 461 * Force long memory training in resume. 462 * The default is zero, indicates short training in resume. 463 */ 464 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 465 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 466 467 /** 468 * DOC: pcie_gen_cap (uint) 469 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 470 * The default is 0 (automatic for each asic). 471 */ 472 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 473 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 474 475 /** 476 * DOC: pcie_lane_cap (uint) 477 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 478 * The default is 0 (automatic for each asic). 479 */ 480 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 481 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 482 483 /** 484 * DOC: cg_mask (ullong) 485 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 486 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 487 */ 488 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 489 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 490 491 /** 492 * DOC: pg_mask (uint) 493 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 494 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 495 */ 496 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 497 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 498 499 /** 500 * DOC: sdma_phase_quantum (uint) 501 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 502 */ 503 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 504 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 505 506 /** 507 * DOC: disable_cu (charp) 508 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 509 */ 510 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 511 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 512 513 /** 514 * DOC: virtual_display (charp) 515 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 516 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 517 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 518 * device at 26:00.0. The default is NULL. 519 */ 520 MODULE_PARM_DESC(virtual_display, 521 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 522 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 523 524 /** 525 * DOC: lbpw (int) 526 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 527 */ 528 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 529 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 530 531 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 532 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 533 534 /** 535 * DOC: gpu_recovery (int) 536 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 537 */ 538 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 539 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 540 541 /** 542 * DOC: emu_mode (int) 543 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 544 */ 545 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 546 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 547 548 /** 549 * DOC: ras_enable (int) 550 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 551 */ 552 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 553 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 554 555 /** 556 * DOC: ras_mask (uint) 557 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 558 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 559 */ 560 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 561 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 562 563 /** 564 * DOC: timeout_fatal_disable (bool) 565 * Disable Watchdog timeout fatal error event 566 */ 567 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 568 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 569 570 /** 571 * DOC: timeout_period (uint) 572 * Modify the watchdog timeout max_cycles as (1 << period) 573 */ 574 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 575 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 576 577 /** 578 * DOC: si_support (int) 579 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 581 * otherwise using amdgpu driver. 582 */ 583 #ifdef CONFIG_DRM_AMDGPU_SI 584 585 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 586 int amdgpu_si_support = 0; 587 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 588 #else 589 int amdgpu_si_support = 1; 590 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 591 #endif 592 593 module_param_named(si_support, amdgpu_si_support, int, 0444); 594 #endif 595 596 /** 597 * DOC: cik_support (int) 598 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 599 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 600 * otherwise using amdgpu driver. 601 */ 602 #ifdef CONFIG_DRM_AMDGPU_CIK 603 604 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 605 int amdgpu_cik_support = 0; 606 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 607 #else 608 int amdgpu_cik_support = 1; 609 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 610 #endif 611 612 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 613 #endif 614 615 /** 616 * DOC: smu_memory_pool_size (uint) 617 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 618 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 619 */ 620 MODULE_PARM_DESC(smu_memory_pool_size, 621 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 622 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 623 624 /** 625 * DOC: async_gfx_ring (int) 626 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 627 */ 628 MODULE_PARM_DESC(async_gfx_ring, 629 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 630 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 631 632 /** 633 * DOC: mcbp (int) 634 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 635 */ 636 MODULE_PARM_DESC(mcbp, 637 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 638 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 639 640 /** 641 * DOC: discovery (int) 642 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 643 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 644 */ 645 MODULE_PARM_DESC(discovery, 646 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 647 module_param_named(discovery, amdgpu_discovery, int, 0444); 648 649 /** 650 * DOC: mes (int) 651 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 652 * (0 = disabled (default), 1 = enabled) 653 */ 654 MODULE_PARM_DESC(mes, 655 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 656 module_param_named(mes, amdgpu_mes, int, 0444); 657 658 /** 659 * DOC: mes_kiq (int) 660 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 661 * (0 = disabled (default), 1 = enabled) 662 */ 663 MODULE_PARM_DESC(mes_kiq, 664 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 665 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 666 667 /** 668 * DOC: noretry (int) 669 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 670 * do not support per-process XNACK this also disables retry page faults. 671 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 672 */ 673 MODULE_PARM_DESC(noretry, 674 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 675 module_param_named(noretry, amdgpu_noretry, int, 0644); 676 677 /** 678 * DOC: force_asic_type (int) 679 * A non negative value used to specify the asic type for all supported GPUs. 680 */ 681 MODULE_PARM_DESC(force_asic_type, 682 "A non negative value used to specify the asic type for all supported GPUs"); 683 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 684 685 /** 686 * DOC: use_xgmi_p2p (int) 687 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 688 */ 689 MODULE_PARM_DESC(use_xgmi_p2p, 690 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 691 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 692 693 694 #ifdef CONFIG_HSA_AMD 695 /** 696 * DOC: sched_policy (int) 697 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 698 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 699 * assigns queues to HQDs. 700 */ 701 int sched_policy = KFD_SCHED_POLICY_HWS; 702 module_param(sched_policy, int, 0444); 703 MODULE_PARM_DESC(sched_policy, 704 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 705 706 /** 707 * DOC: hws_max_conc_proc (int) 708 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 709 * number of VMIDs assigned to the HWS, which is also the default. 710 */ 711 int hws_max_conc_proc = -1; 712 module_param(hws_max_conc_proc, int, 0444); 713 MODULE_PARM_DESC(hws_max_conc_proc, 714 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 715 716 /** 717 * DOC: cwsr_enable (int) 718 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 719 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 720 * disables it. 721 */ 722 int cwsr_enable = 1; 723 module_param(cwsr_enable, int, 0444); 724 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 725 726 /** 727 * DOC: max_num_of_queues_per_device (int) 728 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 729 * is 4096. 730 */ 731 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 732 module_param(max_num_of_queues_per_device, int, 0444); 733 MODULE_PARM_DESC(max_num_of_queues_per_device, 734 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 735 736 /** 737 * DOC: send_sigterm (int) 738 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 739 * but just print errors on dmesg. Setting 1 enables sending sigterm. 740 */ 741 int send_sigterm; 742 module_param(send_sigterm, int, 0444); 743 MODULE_PARM_DESC(send_sigterm, 744 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 745 746 /** 747 * DOC: debug_largebar (int) 748 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 749 * system. This limits the VRAM size reported to ROCm applications to the visible 750 * size, usually 256MB. 751 * Default value is 0, diabled. 752 */ 753 int debug_largebar; 754 module_param(debug_largebar, int, 0444); 755 MODULE_PARM_DESC(debug_largebar, 756 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 757 758 /** 759 * DOC: ignore_crat (int) 760 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 761 * table to get information about AMD APUs. This option can serve as a workaround on 762 * systems with a broken CRAT table. 763 * 764 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 765 * whether use CRAT) 766 */ 767 int ignore_crat; 768 module_param(ignore_crat, int, 0444); 769 MODULE_PARM_DESC(ignore_crat, 770 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 771 772 /** 773 * DOC: halt_if_hws_hang (int) 774 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 775 * Setting 1 enables halt on hang. 776 */ 777 int halt_if_hws_hang; 778 module_param(halt_if_hws_hang, int, 0644); 779 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 780 781 /** 782 * DOC: hws_gws_support(bool) 783 * Assume that HWS supports GWS barriers regardless of what firmware version 784 * check says. Default value: false (rely on MEC2 firmware version check). 785 */ 786 bool hws_gws_support; 787 module_param(hws_gws_support, bool, 0444); 788 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 789 790 /** 791 * DOC: queue_preemption_timeout_ms (int) 792 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 793 */ 794 int queue_preemption_timeout_ms = 9000; 795 module_param(queue_preemption_timeout_ms, int, 0644); 796 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 797 798 /** 799 * DOC: debug_evictions(bool) 800 * Enable extra debug messages to help determine the cause of evictions 801 */ 802 bool debug_evictions; 803 module_param(debug_evictions, bool, 0644); 804 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 805 806 /** 807 * DOC: no_system_mem_limit(bool) 808 * Disable system memory limit, to support multiple process shared memory 809 */ 810 bool no_system_mem_limit; 811 module_param(no_system_mem_limit, bool, 0644); 812 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 813 814 /** 815 * DOC: no_queue_eviction_on_vm_fault (int) 816 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 817 */ 818 int amdgpu_no_queue_eviction_on_vm_fault; 819 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 820 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 821 #endif 822 823 /** 824 * DOC: mtype_local (int) 825 */ 826 int amdgpu_mtype_local; 827 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 828 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 829 830 /** 831 * DOC: pcie_p2p (bool) 832 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 833 */ 834 #ifdef CONFIG_HSA_AMD_P2P 835 bool pcie_p2p = true; 836 module_param(pcie_p2p, bool, 0444); 837 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 838 #endif 839 840 /** 841 * DOC: dcfeaturemask (uint) 842 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 843 * The default is the current set of stable display features. 844 */ 845 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 846 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 847 848 /** 849 * DOC: dcdebugmask (uint) 850 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 851 */ 852 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 853 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 854 855 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 856 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 857 858 /** 859 * DOC: abmlevel (uint) 860 * Override the default ABM (Adaptive Backlight Management) level used for DC 861 * enabled hardware. Requires DMCU to be supported and loaded. 862 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 863 * default. Values 1-4 control the maximum allowable brightness reduction via 864 * the ABM algorithm, with 1 being the least reduction and 4 being the most 865 * reduction. 866 * 867 * Defaults to 0, or disabled. Userspace can still override this level later 868 * after boot. 869 */ 870 uint amdgpu_dm_abm_level; 871 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 872 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 873 874 int amdgpu_backlight = -1; 875 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 876 module_param_named(backlight, amdgpu_backlight, bint, 0444); 877 878 /** 879 * DOC: tmz (int) 880 * Trusted Memory Zone (TMZ) is a method to protect data being written 881 * to or read from memory. 882 * 883 * The default value: 0 (off). TODO: change to auto till it is completed. 884 */ 885 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 886 module_param_named(tmz, amdgpu_tmz, int, 0444); 887 888 /** 889 * DOC: freesync_video (uint) 890 * Enable the optimization to adjust front porch timing to achieve seamless 891 * mode change experience when setting a freesync supported mode for which full 892 * modeset is not needed. 893 * 894 * The Display Core will add a set of modes derived from the base FreeSync 895 * video mode into the corresponding connector's mode list based on commonly 896 * used refresh rates and VRR range of the connected display, when users enable 897 * this feature. From the userspace perspective, they can see a seamless mode 898 * change experience when the change between different refresh rates under the 899 * same resolution. Additionally, userspace applications such as Video playback 900 * can read this modeset list and change the refresh rate based on the video 901 * frame rate. Finally, the userspace can also derive an appropriate mode for a 902 * particular refresh rate based on the FreeSync Mode and add it to the 903 * connector's mode list. 904 * 905 * Note: This is an experimental feature. 906 * 907 * The default value: 0 (off). 908 */ 909 MODULE_PARM_DESC( 910 freesync_video, 911 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 912 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 913 914 /** 915 * DOC: reset_method (int) 916 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 917 */ 918 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 919 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 920 921 /** 922 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 923 * threshold value of faulty pages detected by RAS ECC, which may 924 * result in the GPU entering bad status when the number of total 925 * faulty pages by ECC exceeds the threshold value. 926 */ 927 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 928 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 929 930 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 931 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 932 933 /** 934 * DOC: vcnfw_log (int) 935 * Enable vcnfw log output for debugging, the default is disabled. 936 */ 937 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 938 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 939 940 /** 941 * DOC: sg_display (int) 942 * Disable S/G (scatter/gather) display (i.e., display from system memory). 943 * This option is only relevant on APUs. Set this option to 0 to disable 944 * S/G display if you experience flickering or other issues under memory 945 * pressure and report the issue. 946 */ 947 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 948 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 949 950 /** 951 * DOC: smu_pptable_id (int) 952 * Used to override pptable id. id = 0 use VBIOS pptable. 953 * id > 0 use the soft pptable with specicfied id. 954 */ 955 MODULE_PARM_DESC(smu_pptable_id, 956 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 957 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 958 959 /** 960 * DOC: partition_mode (int) 961 * Used to override the default SPX mode. 962 */ 963 MODULE_PARM_DESC( 964 user_partt_mode, 965 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 966 0 = AMDGPU_SPX_PARTITION_MODE, \ 967 1 = AMDGPU_DPX_PARTITION_MODE, \ 968 2 = AMDGPU_TPX_PARTITION_MODE, \ 969 3 = AMDGPU_QPX_PARTITION_MODE, \ 970 4 = AMDGPU_CPX_PARTITION_MODE)"); 971 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 972 973 974 /** 975 * DOC: enforce_isolation (bool) 976 * enforce process isolation between graphics and compute via using the same reserved vmid. 977 */ 978 module_param(enforce_isolation, bool, 0444); 979 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 980 981 /* These devices are not supported by amdgpu. 982 * They are supported by the mach64, r128, radeon drivers 983 */ 984 static const u16 amdgpu_unsupported_pciidlist[] = { 985 /* mach64 */ 986 0x4354, 987 0x4358, 988 0x4554, 989 0x4742, 990 0x4744, 991 0x4749, 992 0x474C, 993 0x474D, 994 0x474E, 995 0x474F, 996 0x4750, 997 0x4751, 998 0x4752, 999 0x4753, 1000 0x4754, 1001 0x4755, 1002 0x4756, 1003 0x4757, 1004 0x4758, 1005 0x4759, 1006 0x475A, 1007 0x4C42, 1008 0x4C44, 1009 0x4C47, 1010 0x4C49, 1011 0x4C4D, 1012 0x4C4E, 1013 0x4C50, 1014 0x4C51, 1015 0x4C52, 1016 0x4C53, 1017 0x5654, 1018 0x5655, 1019 0x5656, 1020 /* r128 */ 1021 0x4c45, 1022 0x4c46, 1023 0x4d46, 1024 0x4d4c, 1025 0x5041, 1026 0x5042, 1027 0x5043, 1028 0x5044, 1029 0x5045, 1030 0x5046, 1031 0x5047, 1032 0x5048, 1033 0x5049, 1034 0x504A, 1035 0x504B, 1036 0x504C, 1037 0x504D, 1038 0x504E, 1039 0x504F, 1040 0x5050, 1041 0x5051, 1042 0x5052, 1043 0x5053, 1044 0x5054, 1045 0x5055, 1046 0x5056, 1047 0x5057, 1048 0x5058, 1049 0x5245, 1050 0x5246, 1051 0x5247, 1052 0x524b, 1053 0x524c, 1054 0x534d, 1055 0x5446, 1056 0x544C, 1057 0x5452, 1058 /* radeon */ 1059 0x3150, 1060 0x3151, 1061 0x3152, 1062 0x3154, 1063 0x3155, 1064 0x3E50, 1065 0x3E54, 1066 0x4136, 1067 0x4137, 1068 0x4144, 1069 0x4145, 1070 0x4146, 1071 0x4147, 1072 0x4148, 1073 0x4149, 1074 0x414A, 1075 0x414B, 1076 0x4150, 1077 0x4151, 1078 0x4152, 1079 0x4153, 1080 0x4154, 1081 0x4155, 1082 0x4156, 1083 0x4237, 1084 0x4242, 1085 0x4336, 1086 0x4337, 1087 0x4437, 1088 0x4966, 1089 0x4967, 1090 0x4A48, 1091 0x4A49, 1092 0x4A4A, 1093 0x4A4B, 1094 0x4A4C, 1095 0x4A4D, 1096 0x4A4E, 1097 0x4A4F, 1098 0x4A50, 1099 0x4A54, 1100 0x4B48, 1101 0x4B49, 1102 0x4B4A, 1103 0x4B4B, 1104 0x4B4C, 1105 0x4C57, 1106 0x4C58, 1107 0x4C59, 1108 0x4C5A, 1109 0x4C64, 1110 0x4C66, 1111 0x4C67, 1112 0x4E44, 1113 0x4E45, 1114 0x4E46, 1115 0x4E47, 1116 0x4E48, 1117 0x4E49, 1118 0x4E4A, 1119 0x4E4B, 1120 0x4E50, 1121 0x4E51, 1122 0x4E52, 1123 0x4E53, 1124 0x4E54, 1125 0x4E56, 1126 0x5144, 1127 0x5145, 1128 0x5146, 1129 0x5147, 1130 0x5148, 1131 0x514C, 1132 0x514D, 1133 0x5157, 1134 0x5158, 1135 0x5159, 1136 0x515A, 1137 0x515E, 1138 0x5460, 1139 0x5462, 1140 0x5464, 1141 0x5548, 1142 0x5549, 1143 0x554A, 1144 0x554B, 1145 0x554C, 1146 0x554D, 1147 0x554E, 1148 0x554F, 1149 0x5550, 1150 0x5551, 1151 0x5552, 1152 0x5554, 1153 0x564A, 1154 0x564B, 1155 0x564F, 1156 0x5652, 1157 0x5653, 1158 0x5657, 1159 0x5834, 1160 0x5835, 1161 0x5954, 1162 0x5955, 1163 0x5974, 1164 0x5975, 1165 0x5960, 1166 0x5961, 1167 0x5962, 1168 0x5964, 1169 0x5965, 1170 0x5969, 1171 0x5a41, 1172 0x5a42, 1173 0x5a61, 1174 0x5a62, 1175 0x5b60, 1176 0x5b62, 1177 0x5b63, 1178 0x5b64, 1179 0x5b65, 1180 0x5c61, 1181 0x5c63, 1182 0x5d48, 1183 0x5d49, 1184 0x5d4a, 1185 0x5d4c, 1186 0x5d4d, 1187 0x5d4e, 1188 0x5d4f, 1189 0x5d50, 1190 0x5d52, 1191 0x5d57, 1192 0x5e48, 1193 0x5e4a, 1194 0x5e4b, 1195 0x5e4c, 1196 0x5e4d, 1197 0x5e4f, 1198 0x6700, 1199 0x6701, 1200 0x6702, 1201 0x6703, 1202 0x6704, 1203 0x6705, 1204 0x6706, 1205 0x6707, 1206 0x6708, 1207 0x6709, 1208 0x6718, 1209 0x6719, 1210 0x671c, 1211 0x671d, 1212 0x671f, 1213 0x6720, 1214 0x6721, 1215 0x6722, 1216 0x6723, 1217 0x6724, 1218 0x6725, 1219 0x6726, 1220 0x6727, 1221 0x6728, 1222 0x6729, 1223 0x6738, 1224 0x6739, 1225 0x673e, 1226 0x6740, 1227 0x6741, 1228 0x6742, 1229 0x6743, 1230 0x6744, 1231 0x6745, 1232 0x6746, 1233 0x6747, 1234 0x6748, 1235 0x6749, 1236 0x674A, 1237 0x6750, 1238 0x6751, 1239 0x6758, 1240 0x6759, 1241 0x675B, 1242 0x675D, 1243 0x675F, 1244 0x6760, 1245 0x6761, 1246 0x6762, 1247 0x6763, 1248 0x6764, 1249 0x6765, 1250 0x6766, 1251 0x6767, 1252 0x6768, 1253 0x6770, 1254 0x6771, 1255 0x6772, 1256 0x6778, 1257 0x6779, 1258 0x677B, 1259 0x6840, 1260 0x6841, 1261 0x6842, 1262 0x6843, 1263 0x6849, 1264 0x684C, 1265 0x6850, 1266 0x6858, 1267 0x6859, 1268 0x6880, 1269 0x6888, 1270 0x6889, 1271 0x688A, 1272 0x688C, 1273 0x688D, 1274 0x6898, 1275 0x6899, 1276 0x689b, 1277 0x689c, 1278 0x689d, 1279 0x689e, 1280 0x68a0, 1281 0x68a1, 1282 0x68a8, 1283 0x68a9, 1284 0x68b0, 1285 0x68b8, 1286 0x68b9, 1287 0x68ba, 1288 0x68be, 1289 0x68bf, 1290 0x68c0, 1291 0x68c1, 1292 0x68c7, 1293 0x68c8, 1294 0x68c9, 1295 0x68d8, 1296 0x68d9, 1297 0x68da, 1298 0x68de, 1299 0x68e0, 1300 0x68e1, 1301 0x68e4, 1302 0x68e5, 1303 0x68e8, 1304 0x68e9, 1305 0x68f1, 1306 0x68f2, 1307 0x68f8, 1308 0x68f9, 1309 0x68fa, 1310 0x68fe, 1311 0x7100, 1312 0x7101, 1313 0x7102, 1314 0x7103, 1315 0x7104, 1316 0x7105, 1317 0x7106, 1318 0x7108, 1319 0x7109, 1320 0x710A, 1321 0x710B, 1322 0x710C, 1323 0x710E, 1324 0x710F, 1325 0x7140, 1326 0x7141, 1327 0x7142, 1328 0x7143, 1329 0x7144, 1330 0x7145, 1331 0x7146, 1332 0x7147, 1333 0x7149, 1334 0x714A, 1335 0x714B, 1336 0x714C, 1337 0x714D, 1338 0x714E, 1339 0x714F, 1340 0x7151, 1341 0x7152, 1342 0x7153, 1343 0x715E, 1344 0x715F, 1345 0x7180, 1346 0x7181, 1347 0x7183, 1348 0x7186, 1349 0x7187, 1350 0x7188, 1351 0x718A, 1352 0x718B, 1353 0x718C, 1354 0x718D, 1355 0x718F, 1356 0x7193, 1357 0x7196, 1358 0x719B, 1359 0x719F, 1360 0x71C0, 1361 0x71C1, 1362 0x71C2, 1363 0x71C3, 1364 0x71C4, 1365 0x71C5, 1366 0x71C6, 1367 0x71C7, 1368 0x71CD, 1369 0x71CE, 1370 0x71D2, 1371 0x71D4, 1372 0x71D5, 1373 0x71D6, 1374 0x71DA, 1375 0x71DE, 1376 0x7200, 1377 0x7210, 1378 0x7211, 1379 0x7240, 1380 0x7243, 1381 0x7244, 1382 0x7245, 1383 0x7246, 1384 0x7247, 1385 0x7248, 1386 0x7249, 1387 0x724A, 1388 0x724B, 1389 0x724C, 1390 0x724D, 1391 0x724E, 1392 0x724F, 1393 0x7280, 1394 0x7281, 1395 0x7283, 1396 0x7284, 1397 0x7287, 1398 0x7288, 1399 0x7289, 1400 0x728B, 1401 0x728C, 1402 0x7290, 1403 0x7291, 1404 0x7293, 1405 0x7297, 1406 0x7834, 1407 0x7835, 1408 0x791e, 1409 0x791f, 1410 0x793f, 1411 0x7941, 1412 0x7942, 1413 0x796c, 1414 0x796d, 1415 0x796e, 1416 0x796f, 1417 0x9400, 1418 0x9401, 1419 0x9402, 1420 0x9403, 1421 0x9405, 1422 0x940A, 1423 0x940B, 1424 0x940F, 1425 0x94A0, 1426 0x94A1, 1427 0x94A3, 1428 0x94B1, 1429 0x94B3, 1430 0x94B4, 1431 0x94B5, 1432 0x94B9, 1433 0x9440, 1434 0x9441, 1435 0x9442, 1436 0x9443, 1437 0x9444, 1438 0x9446, 1439 0x944A, 1440 0x944B, 1441 0x944C, 1442 0x944E, 1443 0x9450, 1444 0x9452, 1445 0x9456, 1446 0x945A, 1447 0x945B, 1448 0x945E, 1449 0x9460, 1450 0x9462, 1451 0x946A, 1452 0x946B, 1453 0x947A, 1454 0x947B, 1455 0x9480, 1456 0x9487, 1457 0x9488, 1458 0x9489, 1459 0x948A, 1460 0x948F, 1461 0x9490, 1462 0x9491, 1463 0x9495, 1464 0x9498, 1465 0x949C, 1466 0x949E, 1467 0x949F, 1468 0x94C0, 1469 0x94C1, 1470 0x94C3, 1471 0x94C4, 1472 0x94C5, 1473 0x94C6, 1474 0x94C7, 1475 0x94C8, 1476 0x94C9, 1477 0x94CB, 1478 0x94CC, 1479 0x94CD, 1480 0x9500, 1481 0x9501, 1482 0x9504, 1483 0x9505, 1484 0x9506, 1485 0x9507, 1486 0x9508, 1487 0x9509, 1488 0x950F, 1489 0x9511, 1490 0x9515, 1491 0x9517, 1492 0x9519, 1493 0x9540, 1494 0x9541, 1495 0x9542, 1496 0x954E, 1497 0x954F, 1498 0x9552, 1499 0x9553, 1500 0x9555, 1501 0x9557, 1502 0x955f, 1503 0x9580, 1504 0x9581, 1505 0x9583, 1506 0x9586, 1507 0x9587, 1508 0x9588, 1509 0x9589, 1510 0x958A, 1511 0x958B, 1512 0x958C, 1513 0x958D, 1514 0x958E, 1515 0x958F, 1516 0x9590, 1517 0x9591, 1518 0x9593, 1519 0x9595, 1520 0x9596, 1521 0x9597, 1522 0x9598, 1523 0x9599, 1524 0x959B, 1525 0x95C0, 1526 0x95C2, 1527 0x95C4, 1528 0x95C5, 1529 0x95C6, 1530 0x95C7, 1531 0x95C9, 1532 0x95CC, 1533 0x95CD, 1534 0x95CE, 1535 0x95CF, 1536 0x9610, 1537 0x9611, 1538 0x9612, 1539 0x9613, 1540 0x9614, 1541 0x9615, 1542 0x9616, 1543 0x9640, 1544 0x9641, 1545 0x9642, 1546 0x9643, 1547 0x9644, 1548 0x9645, 1549 0x9647, 1550 0x9648, 1551 0x9649, 1552 0x964a, 1553 0x964b, 1554 0x964c, 1555 0x964e, 1556 0x964f, 1557 0x9710, 1558 0x9711, 1559 0x9712, 1560 0x9713, 1561 0x9714, 1562 0x9715, 1563 0x9802, 1564 0x9803, 1565 0x9804, 1566 0x9805, 1567 0x9806, 1568 0x9807, 1569 0x9808, 1570 0x9809, 1571 0x980A, 1572 0x9900, 1573 0x9901, 1574 0x9903, 1575 0x9904, 1576 0x9905, 1577 0x9906, 1578 0x9907, 1579 0x9908, 1580 0x9909, 1581 0x990A, 1582 0x990B, 1583 0x990C, 1584 0x990D, 1585 0x990E, 1586 0x990F, 1587 0x9910, 1588 0x9913, 1589 0x9917, 1590 0x9918, 1591 0x9919, 1592 0x9990, 1593 0x9991, 1594 0x9992, 1595 0x9993, 1596 0x9994, 1597 0x9995, 1598 0x9996, 1599 0x9997, 1600 0x9998, 1601 0x9999, 1602 0x999A, 1603 0x999B, 1604 0x999C, 1605 0x999D, 1606 0x99A0, 1607 0x99A2, 1608 0x99A4, 1609 /* radeon secondary ids */ 1610 0x3171, 1611 0x3e70, 1612 0x4164, 1613 0x4165, 1614 0x4166, 1615 0x4168, 1616 0x4170, 1617 0x4171, 1618 0x4172, 1619 0x4173, 1620 0x496e, 1621 0x4a69, 1622 0x4a6a, 1623 0x4a6b, 1624 0x4a70, 1625 0x4a74, 1626 0x4b69, 1627 0x4b6b, 1628 0x4b6c, 1629 0x4c6e, 1630 0x4e64, 1631 0x4e65, 1632 0x4e66, 1633 0x4e67, 1634 0x4e68, 1635 0x4e69, 1636 0x4e6a, 1637 0x4e71, 1638 0x4f73, 1639 0x5569, 1640 0x556b, 1641 0x556d, 1642 0x556f, 1643 0x5571, 1644 0x5854, 1645 0x5874, 1646 0x5940, 1647 0x5941, 1648 0x5b70, 1649 0x5b72, 1650 0x5b73, 1651 0x5b74, 1652 0x5b75, 1653 0x5d44, 1654 0x5d45, 1655 0x5d6d, 1656 0x5d6f, 1657 0x5d72, 1658 0x5d77, 1659 0x5e6b, 1660 0x5e6d, 1661 0x7120, 1662 0x7124, 1663 0x7129, 1664 0x712e, 1665 0x712f, 1666 0x7162, 1667 0x7163, 1668 0x7166, 1669 0x7167, 1670 0x7172, 1671 0x7173, 1672 0x71a0, 1673 0x71a1, 1674 0x71a3, 1675 0x71a7, 1676 0x71bb, 1677 0x71e0, 1678 0x71e1, 1679 0x71e2, 1680 0x71e6, 1681 0x71e7, 1682 0x71f2, 1683 0x7269, 1684 0x726b, 1685 0x726e, 1686 0x72a0, 1687 0x72a8, 1688 0x72b1, 1689 0x72b3, 1690 0x793f, 1691 }; 1692 1693 static const struct pci_device_id pciidlist[] = { 1694 #ifdef CONFIG_DRM_AMDGPU_SI 1695 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1696 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1697 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1698 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1699 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1700 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1701 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1702 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1703 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1704 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1705 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1706 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1707 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1708 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1710 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1711 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1712 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1713 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1714 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1715 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1716 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1717 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1718 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1719 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1720 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1722 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1729 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1730 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1731 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1732 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1737 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1738 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1739 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1740 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1741 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1742 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1743 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1744 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1745 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1746 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1747 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1748 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1749 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1750 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1751 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1752 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1753 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1754 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1755 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1756 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1757 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1758 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1759 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1760 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1761 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1762 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1763 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1764 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1765 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1766 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1767 #endif 1768 #ifdef CONFIG_DRM_AMDGPU_CIK 1769 /* Kaveri */ 1770 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1772 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1774 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1775 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1776 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1777 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1778 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1779 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1781 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1782 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1783 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1784 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1785 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1786 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1787 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1788 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1789 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1790 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1791 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1792 /* Bonaire */ 1793 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1794 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1795 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1796 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1797 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1798 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1799 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1800 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1801 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1802 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1803 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1804 /* Hawaii */ 1805 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1806 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1807 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1808 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1809 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1810 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1811 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1812 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1813 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1814 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1815 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1816 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1817 /* Kabini */ 1818 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1820 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1822 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1823 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1824 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1825 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1826 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1827 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1828 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1829 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1831 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1832 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1833 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1834 /* mullins */ 1835 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1836 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1837 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1838 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1839 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1840 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1841 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1842 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1843 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1844 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1845 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1846 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1847 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1848 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1849 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1850 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1851 #endif 1852 /* topaz */ 1853 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1854 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1855 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1856 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1857 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1858 /* tonga */ 1859 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1860 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1861 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1862 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1863 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1864 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1865 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1866 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1867 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1868 /* fiji */ 1869 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1870 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1871 /* carrizo */ 1872 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1873 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1874 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1875 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1876 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1877 /* stoney */ 1878 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1879 /* Polaris11 */ 1880 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1881 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1882 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1883 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1884 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1885 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1886 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1887 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1888 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1889 /* Polaris10 */ 1890 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1891 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1892 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1893 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1894 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1895 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1896 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1897 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1898 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1899 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1900 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1901 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1902 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1903 /* Polaris12 */ 1904 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1905 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1906 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1907 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1908 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1909 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1910 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1911 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1912 /* VEGAM */ 1913 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1914 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1915 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1916 /* Vega 10 */ 1917 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1918 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1919 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1920 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1921 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1922 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1923 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1924 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1925 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1926 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1927 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1928 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1929 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1930 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1931 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1932 /* Vega 12 */ 1933 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1934 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1935 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1936 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1937 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1938 /* Vega 20 */ 1939 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1940 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1941 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1942 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1943 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1944 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1945 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1946 /* Raven */ 1947 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1948 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1949 /* Arcturus */ 1950 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1951 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1952 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1953 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1954 /* Navi10 */ 1955 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1956 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1957 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1958 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1959 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1960 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1961 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1962 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1963 /* Navi14 */ 1964 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1965 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1966 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1967 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1968 1969 /* Renoir */ 1970 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1971 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1972 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1973 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1974 1975 /* Navi12 */ 1976 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1977 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1978 1979 /* Sienna_Cichlid */ 1980 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1981 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1982 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1983 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1984 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1985 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1986 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1987 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1988 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1989 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1990 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1991 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1992 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1993 1994 /* Yellow Carp */ 1995 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1996 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1997 1998 /* Navy_Flounder */ 1999 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2000 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2001 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2002 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2003 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2004 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2005 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2006 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2007 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2008 2009 /* DIMGREY_CAVEFISH */ 2010 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2011 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2012 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2013 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2014 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2015 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2016 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2017 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2018 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2019 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2020 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2021 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2022 2023 /* Aldebaran */ 2024 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2025 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2026 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2027 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2028 2029 /* CYAN_SKILLFISH */ 2030 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2031 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2032 2033 /* BEIGE_GOBY */ 2034 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2035 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2036 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2037 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2038 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2039 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2040 2041 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2042 .class = PCI_CLASS_DISPLAY_VGA << 8, 2043 .class_mask = 0xffffff, 2044 .driver_data = CHIP_IP_DISCOVERY }, 2045 2046 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2047 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2048 .class_mask = 0xffffff, 2049 .driver_data = CHIP_IP_DISCOVERY }, 2050 2051 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2052 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2053 .class_mask = 0xffffff, 2054 .driver_data = CHIP_IP_DISCOVERY }, 2055 2056 {0, 0, 0} 2057 }; 2058 2059 MODULE_DEVICE_TABLE(pci, pciidlist); 2060 2061 static const struct drm_driver amdgpu_kms_driver; 2062 2063 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2064 { 2065 struct pci_dev *p = NULL; 2066 int i; 2067 2068 /* 0 - GPU 2069 * 1 - audio 2070 * 2 - USB 2071 * 3 - UCSI 2072 */ 2073 for (i = 1; i < 4; i++) { 2074 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2075 adev->pdev->bus->number, i); 2076 if (p) { 2077 pm_runtime_get_sync(&p->dev); 2078 pm_runtime_mark_last_busy(&p->dev); 2079 pm_runtime_put_autosuspend(&p->dev); 2080 pci_dev_put(p); 2081 } 2082 } 2083 } 2084 2085 static int amdgpu_pci_probe(struct pci_dev *pdev, 2086 const struct pci_device_id *ent) 2087 { 2088 struct drm_device *ddev; 2089 struct amdgpu_device *adev; 2090 unsigned long flags = ent->driver_data; 2091 int ret, retry = 0, i; 2092 bool supports_atomic = false; 2093 2094 /* skip devices which are owned by radeon */ 2095 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2096 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2097 return -ENODEV; 2098 } 2099 2100 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2101 amdgpu_aspm = 0; 2102 2103 if (amdgpu_virtual_display || 2104 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2105 supports_atomic = true; 2106 2107 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2108 DRM_INFO("This hardware requires experimental hardware support.\n" 2109 "See modparam exp_hw_support\n"); 2110 return -ENODEV; 2111 } 2112 /* differentiate between P10 and P11 asics with the same DID */ 2113 if (pdev->device == 0x67FF && 2114 (pdev->revision == 0xE3 || 2115 pdev->revision == 0xE7 || 2116 pdev->revision == 0xF3 || 2117 pdev->revision == 0xF7)) { 2118 flags &= ~AMD_ASIC_MASK; 2119 flags |= CHIP_POLARIS10; 2120 } 2121 2122 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2123 * however, SME requires an indirect IOMMU mapping because the encryption 2124 * bit is beyond the DMA mask of the chip. 2125 */ 2126 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2127 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2128 dev_info(&pdev->dev, 2129 "SME is not compatible with RAVEN\n"); 2130 return -ENOTSUPP; 2131 } 2132 2133 #ifdef CONFIG_DRM_AMDGPU_SI 2134 if (!amdgpu_si_support) { 2135 switch (flags & AMD_ASIC_MASK) { 2136 case CHIP_TAHITI: 2137 case CHIP_PITCAIRN: 2138 case CHIP_VERDE: 2139 case CHIP_OLAND: 2140 case CHIP_HAINAN: 2141 dev_info(&pdev->dev, 2142 "SI support provided by radeon.\n"); 2143 dev_info(&pdev->dev, 2144 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2145 ); 2146 return -ENODEV; 2147 } 2148 } 2149 #endif 2150 #ifdef CONFIG_DRM_AMDGPU_CIK 2151 if (!amdgpu_cik_support) { 2152 switch (flags & AMD_ASIC_MASK) { 2153 case CHIP_KAVERI: 2154 case CHIP_BONAIRE: 2155 case CHIP_HAWAII: 2156 case CHIP_KABINI: 2157 case CHIP_MULLINS: 2158 dev_info(&pdev->dev, 2159 "CIK support provided by radeon.\n"); 2160 dev_info(&pdev->dev, 2161 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2162 ); 2163 return -ENODEV; 2164 } 2165 } 2166 #endif 2167 2168 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2169 if (IS_ERR(adev)) 2170 return PTR_ERR(adev); 2171 2172 adev->dev = &pdev->dev; 2173 adev->pdev = pdev; 2174 ddev = adev_to_drm(adev); 2175 2176 if (!supports_atomic) 2177 ddev->driver_features &= ~DRIVER_ATOMIC; 2178 2179 ret = pci_enable_device(pdev); 2180 if (ret) 2181 return ret; 2182 2183 pci_set_drvdata(pdev, ddev); 2184 2185 ret = amdgpu_driver_load_kms(adev, flags); 2186 if (ret) 2187 goto err_pci; 2188 2189 retry_init: 2190 ret = drm_dev_register(ddev, flags); 2191 if (ret == -EAGAIN && ++retry <= 3) { 2192 DRM_INFO("retry init %d\n", retry); 2193 /* Don't request EX mode too frequently which is attacking */ 2194 msleep(5000); 2195 goto retry_init; 2196 } else if (ret) { 2197 goto err_pci; 2198 } 2199 2200 ret = amdgpu_xcp_dev_register(adev, ent); 2201 if (ret) 2202 goto err_pci; 2203 2204 /* 2205 * 1. don't init fbdev on hw without DCE 2206 * 2. don't init fbdev if there are no connectors 2207 */ 2208 if (adev->mode_info.mode_config_initialized && 2209 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2210 /* select 8 bpp console on low vram cards */ 2211 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2212 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2213 else 2214 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2215 } 2216 2217 ret = amdgpu_debugfs_init(adev); 2218 if (ret) 2219 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2220 2221 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2222 /* only need to skip on ATPX */ 2223 if (amdgpu_device_supports_px(ddev)) 2224 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2225 /* we want direct complete for BOCO */ 2226 if (amdgpu_device_supports_boco(ddev)) 2227 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2228 DPM_FLAG_SMART_SUSPEND | 2229 DPM_FLAG_MAY_SKIP_RESUME); 2230 pm_runtime_use_autosuspend(ddev->dev); 2231 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2232 2233 pm_runtime_allow(ddev->dev); 2234 2235 pm_runtime_mark_last_busy(ddev->dev); 2236 pm_runtime_put_autosuspend(ddev->dev); 2237 2238 /* 2239 * For runpm implemented via BACO, PMFW will handle the 2240 * timing for BACO in and out: 2241 * - put ASIC into BACO state only when both video and 2242 * audio functions are in D3 state. 2243 * - pull ASIC out of BACO state when either video or 2244 * audio function is in D0 state. 2245 * Also, at startup, PMFW assumes both functions are in 2246 * D0 state. 2247 * 2248 * So if snd driver was loaded prior to amdgpu driver 2249 * and audio function was put into D3 state, there will 2250 * be no PMFW-aware D-state transition(D0->D3) on runpm 2251 * suspend. Thus the BACO will be not correctly kicked in. 2252 * 2253 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2254 * into D0 state. Then there will be a PMFW-aware D-state 2255 * transition(D0->D3) on runpm suspend. 2256 */ 2257 if (amdgpu_device_supports_baco(ddev) && 2258 !(adev->flags & AMD_IS_APU) && 2259 (adev->asic_type >= CHIP_NAVI10)) 2260 amdgpu_get_secondary_funcs(adev); 2261 } 2262 2263 return 0; 2264 2265 err_pci: 2266 pci_disable_device(pdev); 2267 return ret; 2268 } 2269 2270 static void 2271 amdgpu_pci_remove(struct pci_dev *pdev) 2272 { 2273 struct drm_device *dev = pci_get_drvdata(pdev); 2274 struct amdgpu_device *adev = drm_to_adev(dev); 2275 2276 amdgpu_xcp_dev_unplug(adev); 2277 drm_dev_unplug(dev); 2278 2279 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2280 pm_runtime_get_sync(dev->dev); 2281 pm_runtime_forbid(dev->dev); 2282 } 2283 2284 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2285 !amdgpu_sriov_vf(adev)) { 2286 bool need_to_reset_gpu = false; 2287 2288 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2289 struct amdgpu_hive_info *hive; 2290 2291 hive = amdgpu_get_xgmi_hive(adev); 2292 if (hive->device_remove_count == 0) 2293 need_to_reset_gpu = true; 2294 hive->device_remove_count++; 2295 amdgpu_put_xgmi_hive(hive); 2296 } else { 2297 need_to_reset_gpu = true; 2298 } 2299 2300 /* Workaround for ASICs need to reset SMU. 2301 * Called only when the first device is removed. 2302 */ 2303 if (need_to_reset_gpu) { 2304 struct amdgpu_reset_context reset_context; 2305 2306 adev->shutdown = true; 2307 memset(&reset_context, 0, sizeof(reset_context)); 2308 reset_context.method = AMD_RESET_METHOD_NONE; 2309 reset_context.reset_req_dev = adev; 2310 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2311 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2312 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2313 } 2314 } 2315 2316 amdgpu_driver_unload_kms(dev); 2317 2318 /* 2319 * Flush any in flight DMA operations from device. 2320 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2321 * StatusTransactions Pending bit. 2322 */ 2323 pci_disable_device(pdev); 2324 pci_wait_for_pending_transaction(pdev); 2325 } 2326 2327 static void 2328 amdgpu_pci_shutdown(struct pci_dev *pdev) 2329 { 2330 struct drm_device *dev = pci_get_drvdata(pdev); 2331 struct amdgpu_device *adev = drm_to_adev(dev); 2332 2333 if (amdgpu_ras_intr_triggered()) 2334 return; 2335 2336 /* if we are running in a VM, make sure the device 2337 * torn down properly on reboot/shutdown. 2338 * unfortunately we can't detect certain 2339 * hypervisors so just do this all the time. 2340 */ 2341 if (!amdgpu_passthrough(adev)) 2342 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2343 amdgpu_device_ip_suspend(adev); 2344 adev->mp1_state = PP_MP1_STATE_NONE; 2345 } 2346 2347 /** 2348 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2349 * 2350 * @work: work_struct. 2351 */ 2352 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2353 { 2354 struct list_head device_list; 2355 struct amdgpu_device *adev; 2356 int i, r; 2357 struct amdgpu_reset_context reset_context; 2358 2359 memset(&reset_context, 0, sizeof(reset_context)); 2360 2361 mutex_lock(&mgpu_info.mutex); 2362 if (mgpu_info.pending_reset == true) { 2363 mutex_unlock(&mgpu_info.mutex); 2364 return; 2365 } 2366 mgpu_info.pending_reset = true; 2367 mutex_unlock(&mgpu_info.mutex); 2368 2369 /* Use a common context, just need to make sure full reset is done */ 2370 reset_context.method = AMD_RESET_METHOD_NONE; 2371 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2372 2373 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2374 adev = mgpu_info.gpu_ins[i].adev; 2375 reset_context.reset_req_dev = adev; 2376 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2377 if (r) { 2378 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2379 r, adev_to_drm(adev)->unique); 2380 } 2381 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2382 r = -EALREADY; 2383 } 2384 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2385 adev = mgpu_info.gpu_ins[i].adev; 2386 flush_work(&adev->xgmi_reset_work); 2387 adev->gmc.xgmi.pending_reset = false; 2388 } 2389 2390 /* reset function will rebuild the xgmi hive info , clear it now */ 2391 for (i = 0; i < mgpu_info.num_dgpu; i++) 2392 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2393 2394 INIT_LIST_HEAD(&device_list); 2395 2396 for (i = 0; i < mgpu_info.num_dgpu; i++) 2397 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2398 2399 /* unregister the GPU first, reset function will add them back */ 2400 list_for_each_entry(adev, &device_list, reset_list) 2401 amdgpu_unregister_gpu_instance(adev); 2402 2403 /* Use a common context, just need to make sure full reset is done */ 2404 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2405 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2406 2407 if (r) { 2408 DRM_ERROR("reinit gpus failure"); 2409 return; 2410 } 2411 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2412 adev = mgpu_info.gpu_ins[i].adev; 2413 if (!adev->kfd.init_complete) 2414 amdgpu_amdkfd_device_init(adev); 2415 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2416 } 2417 } 2418 2419 static int amdgpu_pmops_prepare(struct device *dev) 2420 { 2421 struct drm_device *drm_dev = dev_get_drvdata(dev); 2422 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2423 2424 /* Return a positive number here so 2425 * DPM_FLAG_SMART_SUSPEND works properly 2426 */ 2427 if (amdgpu_device_supports_boco(drm_dev)) 2428 return pm_runtime_suspended(dev); 2429 2430 /* if we will not support s3 or s2i for the device 2431 * then skip suspend 2432 */ 2433 if (!amdgpu_acpi_is_s0ix_active(adev) && 2434 !amdgpu_acpi_is_s3_active(adev)) 2435 return 1; 2436 2437 return 0; 2438 } 2439 2440 static void amdgpu_pmops_complete(struct device *dev) 2441 { 2442 /* nothing to do */ 2443 } 2444 2445 static int amdgpu_pmops_suspend(struct device *dev) 2446 { 2447 struct drm_device *drm_dev = dev_get_drvdata(dev); 2448 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2449 2450 if (amdgpu_acpi_is_s0ix_active(adev)) 2451 adev->in_s0ix = true; 2452 else if (amdgpu_acpi_is_s3_active(adev)) 2453 adev->in_s3 = true; 2454 if (!adev->in_s0ix && !adev->in_s3) 2455 return 0; 2456 return amdgpu_device_suspend(drm_dev, true); 2457 } 2458 2459 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2460 { 2461 struct drm_device *drm_dev = dev_get_drvdata(dev); 2462 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2463 2464 if (amdgpu_acpi_should_gpu_reset(adev)) 2465 return amdgpu_asic_reset(adev); 2466 2467 return 0; 2468 } 2469 2470 static int amdgpu_pmops_resume(struct device *dev) 2471 { 2472 struct drm_device *drm_dev = dev_get_drvdata(dev); 2473 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2474 int r; 2475 2476 if (!adev->in_s0ix && !adev->in_s3) 2477 return 0; 2478 2479 /* Avoids registers access if device is physically gone */ 2480 if (!pci_device_is_present(adev->pdev)) 2481 adev->no_hw_access = true; 2482 2483 r = amdgpu_device_resume(drm_dev, true); 2484 if (amdgpu_acpi_is_s0ix_active(adev)) 2485 adev->in_s0ix = false; 2486 else 2487 adev->in_s3 = false; 2488 return r; 2489 } 2490 2491 static int amdgpu_pmops_freeze(struct device *dev) 2492 { 2493 struct drm_device *drm_dev = dev_get_drvdata(dev); 2494 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2495 int r; 2496 2497 adev->in_s4 = true; 2498 r = amdgpu_device_suspend(drm_dev, true); 2499 adev->in_s4 = false; 2500 if (r) 2501 return r; 2502 2503 if (amdgpu_acpi_should_gpu_reset(adev)) 2504 return amdgpu_asic_reset(adev); 2505 return 0; 2506 } 2507 2508 static int amdgpu_pmops_thaw(struct device *dev) 2509 { 2510 struct drm_device *drm_dev = dev_get_drvdata(dev); 2511 2512 return amdgpu_device_resume(drm_dev, true); 2513 } 2514 2515 static int amdgpu_pmops_poweroff(struct device *dev) 2516 { 2517 struct drm_device *drm_dev = dev_get_drvdata(dev); 2518 2519 return amdgpu_device_suspend(drm_dev, true); 2520 } 2521 2522 static int amdgpu_pmops_restore(struct device *dev) 2523 { 2524 struct drm_device *drm_dev = dev_get_drvdata(dev); 2525 2526 return amdgpu_device_resume(drm_dev, true); 2527 } 2528 2529 static int amdgpu_runtime_idle_check_display(struct device *dev) 2530 { 2531 struct pci_dev *pdev = to_pci_dev(dev); 2532 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2533 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2534 2535 if (adev->mode_info.num_crtc) { 2536 struct drm_connector *list_connector; 2537 struct drm_connector_list_iter iter; 2538 int ret = 0; 2539 2540 /* XXX: Return busy if any displays are connected to avoid 2541 * possible display wakeups after runtime resume due to 2542 * hotplug events in case any displays were connected while 2543 * the GPU was in suspend. Remove this once that is fixed. 2544 */ 2545 mutex_lock(&drm_dev->mode_config.mutex); 2546 drm_connector_list_iter_begin(drm_dev, &iter); 2547 drm_for_each_connector_iter(list_connector, &iter) { 2548 if (list_connector->status == connector_status_connected) { 2549 ret = -EBUSY; 2550 break; 2551 } 2552 } 2553 drm_connector_list_iter_end(&iter); 2554 mutex_unlock(&drm_dev->mode_config.mutex); 2555 2556 if (ret) 2557 return ret; 2558 2559 if (adev->dc_enabled) { 2560 struct drm_crtc *crtc; 2561 2562 drm_for_each_crtc(crtc, drm_dev) { 2563 drm_modeset_lock(&crtc->mutex, NULL); 2564 if (crtc->state->active) 2565 ret = -EBUSY; 2566 drm_modeset_unlock(&crtc->mutex); 2567 if (ret < 0) 2568 break; 2569 } 2570 } else { 2571 mutex_lock(&drm_dev->mode_config.mutex); 2572 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2573 2574 drm_connector_list_iter_begin(drm_dev, &iter); 2575 drm_for_each_connector_iter(list_connector, &iter) { 2576 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2577 ret = -EBUSY; 2578 break; 2579 } 2580 } 2581 2582 drm_connector_list_iter_end(&iter); 2583 2584 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2585 mutex_unlock(&drm_dev->mode_config.mutex); 2586 } 2587 if (ret) 2588 return ret; 2589 } 2590 2591 return 0; 2592 } 2593 2594 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2595 { 2596 struct pci_dev *pdev = to_pci_dev(dev); 2597 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2598 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2599 int ret, i; 2600 2601 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2602 pm_runtime_forbid(dev); 2603 return -EBUSY; 2604 } 2605 2606 ret = amdgpu_runtime_idle_check_display(dev); 2607 if (ret) 2608 return ret; 2609 2610 /* wait for all rings to drain before suspending */ 2611 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2612 struct amdgpu_ring *ring = adev->rings[i]; 2613 2614 if (ring && ring->sched.ready) { 2615 ret = amdgpu_fence_wait_empty(ring); 2616 if (ret) 2617 return -EBUSY; 2618 } 2619 } 2620 2621 adev->in_runpm = true; 2622 if (amdgpu_device_supports_px(drm_dev)) 2623 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2624 2625 /* 2626 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2627 * proper cleanups and put itself into a state ready for PNP. That 2628 * can address some random resuming failure observed on BOCO capable 2629 * platforms. 2630 * TODO: this may be also needed for PX capable platform. 2631 */ 2632 if (amdgpu_device_supports_boco(drm_dev)) 2633 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2634 2635 ret = amdgpu_device_suspend(drm_dev, false); 2636 if (ret) { 2637 adev->in_runpm = false; 2638 if (amdgpu_device_supports_boco(drm_dev)) 2639 adev->mp1_state = PP_MP1_STATE_NONE; 2640 return ret; 2641 } 2642 2643 if (amdgpu_device_supports_boco(drm_dev)) 2644 adev->mp1_state = PP_MP1_STATE_NONE; 2645 2646 if (amdgpu_device_supports_px(drm_dev)) { 2647 /* Only need to handle PCI state in the driver for ATPX 2648 * PCI core handles it for _PR3. 2649 */ 2650 amdgpu_device_cache_pci_state(pdev); 2651 pci_disable_device(pdev); 2652 pci_ignore_hotplug(pdev); 2653 pci_set_power_state(pdev, PCI_D3cold); 2654 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2655 } else if (amdgpu_device_supports_boco(drm_dev)) { 2656 /* nothing to do */ 2657 } else if (amdgpu_device_supports_baco(drm_dev)) { 2658 amdgpu_device_baco_enter(drm_dev); 2659 } 2660 2661 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2662 2663 return 0; 2664 } 2665 2666 static int amdgpu_pmops_runtime_resume(struct device *dev) 2667 { 2668 struct pci_dev *pdev = to_pci_dev(dev); 2669 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2670 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2671 int ret; 2672 2673 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2674 return -EINVAL; 2675 2676 /* Avoids registers access if device is physically gone */ 2677 if (!pci_device_is_present(adev->pdev)) 2678 adev->no_hw_access = true; 2679 2680 if (amdgpu_device_supports_px(drm_dev)) { 2681 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2682 2683 /* Only need to handle PCI state in the driver for ATPX 2684 * PCI core handles it for _PR3. 2685 */ 2686 pci_set_power_state(pdev, PCI_D0); 2687 amdgpu_device_load_pci_state(pdev); 2688 ret = pci_enable_device(pdev); 2689 if (ret) 2690 return ret; 2691 pci_set_master(pdev); 2692 } else if (amdgpu_device_supports_boco(drm_dev)) { 2693 /* Only need to handle PCI state in the driver for ATPX 2694 * PCI core handles it for _PR3. 2695 */ 2696 pci_set_master(pdev); 2697 } else if (amdgpu_device_supports_baco(drm_dev)) { 2698 amdgpu_device_baco_exit(drm_dev); 2699 } 2700 ret = amdgpu_device_resume(drm_dev, false); 2701 if (ret) { 2702 if (amdgpu_device_supports_px(drm_dev)) 2703 pci_disable_device(pdev); 2704 return ret; 2705 } 2706 2707 if (amdgpu_device_supports_px(drm_dev)) 2708 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2709 adev->in_runpm = false; 2710 return 0; 2711 } 2712 2713 static int amdgpu_pmops_runtime_idle(struct device *dev) 2714 { 2715 struct drm_device *drm_dev = dev_get_drvdata(dev); 2716 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2717 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2718 int ret = 1; 2719 2720 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2721 pm_runtime_forbid(dev); 2722 return -EBUSY; 2723 } 2724 2725 ret = amdgpu_runtime_idle_check_display(dev); 2726 2727 pm_runtime_mark_last_busy(dev); 2728 pm_runtime_autosuspend(dev); 2729 return ret; 2730 } 2731 2732 long amdgpu_drm_ioctl(struct file *filp, 2733 unsigned int cmd, unsigned long arg) 2734 { 2735 struct drm_file *file_priv = filp->private_data; 2736 struct drm_device *dev; 2737 long ret; 2738 2739 dev = file_priv->minor->dev; 2740 ret = pm_runtime_get_sync(dev->dev); 2741 if (ret < 0) 2742 goto out; 2743 2744 ret = drm_ioctl(filp, cmd, arg); 2745 2746 pm_runtime_mark_last_busy(dev->dev); 2747 out: 2748 pm_runtime_put_autosuspend(dev->dev); 2749 return ret; 2750 } 2751 2752 static const struct dev_pm_ops amdgpu_pm_ops = { 2753 .prepare = amdgpu_pmops_prepare, 2754 .complete = amdgpu_pmops_complete, 2755 .suspend = amdgpu_pmops_suspend, 2756 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2757 .resume = amdgpu_pmops_resume, 2758 .freeze = amdgpu_pmops_freeze, 2759 .thaw = amdgpu_pmops_thaw, 2760 .poweroff = amdgpu_pmops_poweroff, 2761 .restore = amdgpu_pmops_restore, 2762 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2763 .runtime_resume = amdgpu_pmops_runtime_resume, 2764 .runtime_idle = amdgpu_pmops_runtime_idle, 2765 }; 2766 2767 static int amdgpu_flush(struct file *f, fl_owner_t id) 2768 { 2769 struct drm_file *file_priv = f->private_data; 2770 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2771 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2772 2773 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2774 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2775 2776 return timeout >= 0 ? 0 : timeout; 2777 } 2778 2779 static const struct file_operations amdgpu_driver_kms_fops = { 2780 .owner = THIS_MODULE, 2781 .open = drm_open, 2782 .flush = amdgpu_flush, 2783 .release = drm_release, 2784 .unlocked_ioctl = amdgpu_drm_ioctl, 2785 .mmap = drm_gem_mmap, 2786 .poll = drm_poll, 2787 .read = drm_read, 2788 #ifdef CONFIG_COMPAT 2789 .compat_ioctl = amdgpu_kms_compat_ioctl, 2790 #endif 2791 #ifdef CONFIG_PROC_FS 2792 .show_fdinfo = drm_show_fdinfo, 2793 #endif 2794 }; 2795 2796 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2797 { 2798 struct drm_file *file; 2799 2800 if (!filp) 2801 return -EINVAL; 2802 2803 if (filp->f_op != &amdgpu_driver_kms_fops) 2804 return -EINVAL; 2805 2806 file = filp->private_data; 2807 *fpriv = file->driver_priv; 2808 return 0; 2809 } 2810 2811 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2812 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2813 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2814 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2815 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2816 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2817 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2818 /* KMS */ 2819 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2820 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2821 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2822 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2823 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2824 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2825 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2826 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2827 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2828 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2829 }; 2830 2831 static const struct drm_driver amdgpu_kms_driver = { 2832 .driver_features = 2833 DRIVER_ATOMIC | 2834 DRIVER_GEM | 2835 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2836 DRIVER_SYNCOBJ_TIMELINE, 2837 .open = amdgpu_driver_open_kms, 2838 .postclose = amdgpu_driver_postclose_kms, 2839 .lastclose = amdgpu_driver_lastclose_kms, 2840 .ioctls = amdgpu_ioctls_kms, 2841 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2842 .dumb_create = amdgpu_mode_dumb_create, 2843 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2844 .fops = &amdgpu_driver_kms_fops, 2845 .release = &amdgpu_driver_release_kms, 2846 #ifdef CONFIG_PROC_FS 2847 .show_fdinfo = amdgpu_show_fdinfo, 2848 #endif 2849 2850 .gem_prime_import = amdgpu_gem_prime_import, 2851 2852 .name = DRIVER_NAME, 2853 .desc = DRIVER_DESC, 2854 .date = DRIVER_DATE, 2855 .major = KMS_DRIVER_MAJOR, 2856 .minor = KMS_DRIVER_MINOR, 2857 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2858 }; 2859 2860 const struct drm_driver amdgpu_partition_driver = { 2861 .driver_features = 2862 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2863 DRIVER_SYNCOBJ_TIMELINE, 2864 .open = amdgpu_driver_open_kms, 2865 .postclose = amdgpu_driver_postclose_kms, 2866 .lastclose = amdgpu_driver_lastclose_kms, 2867 .ioctls = amdgpu_ioctls_kms, 2868 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2869 .dumb_create = amdgpu_mode_dumb_create, 2870 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2871 .fops = &amdgpu_driver_kms_fops, 2872 .release = &amdgpu_driver_release_kms, 2873 2874 .gem_prime_import = amdgpu_gem_prime_import, 2875 2876 .name = DRIVER_NAME, 2877 .desc = DRIVER_DESC, 2878 .date = DRIVER_DATE, 2879 .major = KMS_DRIVER_MAJOR, 2880 .minor = KMS_DRIVER_MINOR, 2881 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2882 }; 2883 2884 static struct pci_error_handlers amdgpu_pci_err_handler = { 2885 .error_detected = amdgpu_pci_error_detected, 2886 .mmio_enabled = amdgpu_pci_mmio_enabled, 2887 .slot_reset = amdgpu_pci_slot_reset, 2888 .resume = amdgpu_pci_resume, 2889 }; 2890 2891 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2892 &amdgpu_vram_mgr_attr_group, 2893 &amdgpu_gtt_mgr_attr_group, 2894 &amdgpu_flash_attr_group, 2895 NULL, 2896 }; 2897 2898 static struct pci_driver amdgpu_kms_pci_driver = { 2899 .name = DRIVER_NAME, 2900 .id_table = pciidlist, 2901 .probe = amdgpu_pci_probe, 2902 .remove = amdgpu_pci_remove, 2903 .shutdown = amdgpu_pci_shutdown, 2904 .driver.pm = &amdgpu_pm_ops, 2905 .err_handler = &amdgpu_pci_err_handler, 2906 .dev_groups = amdgpu_sysfs_groups, 2907 }; 2908 2909 static int __init amdgpu_init(void) 2910 { 2911 int r; 2912 2913 if (drm_firmware_drivers_only()) 2914 return -EINVAL; 2915 2916 r = amdgpu_sync_init(); 2917 if (r) 2918 goto error_sync; 2919 2920 r = amdgpu_fence_slab_init(); 2921 if (r) 2922 goto error_fence; 2923 2924 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2925 amdgpu_register_atpx_handler(); 2926 amdgpu_acpi_detect(); 2927 2928 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2929 amdgpu_amdkfd_init(); 2930 2931 /* let modprobe override vga console setting */ 2932 return pci_register_driver(&amdgpu_kms_pci_driver); 2933 2934 error_fence: 2935 amdgpu_sync_fini(); 2936 2937 error_sync: 2938 return r; 2939 } 2940 2941 static void __exit amdgpu_exit(void) 2942 { 2943 amdgpu_amdkfd_fini(); 2944 pci_unregister_driver(&amdgpu_kms_pci_driver); 2945 amdgpu_unregister_atpx_handler(); 2946 amdgpu_acpi_release(); 2947 amdgpu_sync_fini(); 2948 amdgpu_fence_slab_fini(); 2949 mmu_notifier_synchronize(); 2950 amdgpu_xcp_drv_release(); 2951 } 2952 2953 module_init(amdgpu_init); 2954 module_exit(amdgpu_exit); 2955 2956 MODULE_AUTHOR(DRIVER_AUTHOR); 2957 MODULE_DESCRIPTION(DRIVER_DESC); 2958 MODULE_LICENSE("GPL and additional rights"); 2959