1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 */ 63 #define KMS_DRIVER_MAJOR 3 64 #define KMS_DRIVER_MINOR 9 65 #define KMS_DRIVER_PATCHLEVEL 0 66 67 int amdgpu_vram_limit = 0; 68 int amdgpu_gart_size = -1; /* auto */ 69 int amdgpu_moverate = -1; /* auto */ 70 int amdgpu_benchmarking = 0; 71 int amdgpu_testing = 0; 72 int amdgpu_audio = -1; 73 int amdgpu_disp_priority = 0; 74 int amdgpu_hw_i2c = 0; 75 int amdgpu_pcie_gen2 = -1; 76 int amdgpu_msi = -1; 77 int amdgpu_lockup_timeout = 0; 78 int amdgpu_dpm = -1; 79 int amdgpu_smc_load_fw = 1; 80 int amdgpu_aspm = -1; 81 int amdgpu_runtime_pm = -1; 82 unsigned amdgpu_ip_block_mask = 0xffffffff; 83 int amdgpu_bapm = -1; 84 int amdgpu_deep_color = 0; 85 int amdgpu_vm_size = 64; 86 int amdgpu_vm_block_size = -1; 87 int amdgpu_vm_fault_stop = 0; 88 int amdgpu_vm_debug = 0; 89 int amdgpu_vram_page_split = 1024; 90 int amdgpu_exp_hw_support = 0; 91 int amdgpu_sched_jobs = 32; 92 int amdgpu_sched_hw_submission = 2; 93 int amdgpu_powerplay = -1; 94 int amdgpu_powercontainment = 1; 95 int amdgpu_sclk_deep_sleep_en = 1; 96 unsigned amdgpu_pcie_gen_cap = 0; 97 unsigned amdgpu_pcie_lane_cap = 0; 98 unsigned amdgpu_cg_mask = 0xffffffff; 99 unsigned amdgpu_pg_mask = 0xffffffff; 100 char *amdgpu_disable_cu = NULL; 101 char *amdgpu_virtual_display = NULL; 102 unsigned amdgpu_pp_feature_mask = 0xffffffff; 103 104 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 105 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 106 107 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 108 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 109 110 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 111 module_param_named(moverate, amdgpu_moverate, int, 0600); 112 113 MODULE_PARM_DESC(benchmark, "Run benchmark"); 114 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 115 116 MODULE_PARM_DESC(test, "Run tests"); 117 module_param_named(test, amdgpu_testing, int, 0444); 118 119 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 120 module_param_named(audio, amdgpu_audio, int, 0444); 121 122 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 123 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 124 125 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 126 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 127 128 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 129 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 130 131 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 132 module_param_named(msi, amdgpu_msi, int, 0444); 133 134 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 135 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 136 137 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 138 module_param_named(dpm, amdgpu_dpm, int, 0444); 139 140 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 141 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 142 143 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 144 module_param_named(aspm, amdgpu_aspm, int, 0444); 145 146 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 147 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 148 149 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 150 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 151 152 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 153 module_param_named(bapm, amdgpu_bapm, int, 0444); 154 155 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 156 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 157 158 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 159 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 160 161 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 162 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 163 164 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 165 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 166 167 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 168 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 169 170 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); 171 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 172 173 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 174 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 175 176 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 177 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 178 179 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 180 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 181 182 MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 183 module_param_named(powerplay, amdgpu_powerplay, int, 0444); 184 185 MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)"); 186 module_param_named(powercontainment, amdgpu_powercontainment, int, 0444); 187 188 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 189 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); 190 191 MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)"); 192 module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444); 193 194 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 195 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 196 197 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 198 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 199 200 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 201 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 202 203 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 204 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 205 206 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 207 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 208 209 MODULE_PARM_DESC(virtual_display, 210 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 211 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 212 213 static const struct pci_device_id pciidlist[] = { 214 #ifdef CONFIG_DRM_AMDGPU_SI 215 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 216 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 217 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 218 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 219 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 220 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 221 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 222 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 223 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 224 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 225 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 226 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 227 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 228 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 229 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 230 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 231 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 232 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 233 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 234 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 235 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 236 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 237 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 238 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 239 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 240 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 241 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 242 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 243 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 244 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 245 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 246 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 247 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 248 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 249 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 250 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 251 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 252 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 253 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 254 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 255 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 256 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 257 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 258 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 259 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 260 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 261 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 262 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 263 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 264 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 265 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 266 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 267 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 268 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 269 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 270 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 271 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 272 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 273 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 274 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 275 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 276 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 277 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 278 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 279 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 280 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 281 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 282 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 283 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 284 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 285 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 286 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 287 #endif 288 #ifdef CONFIG_DRM_AMDGPU_CIK 289 /* Kaveri */ 290 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 291 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 292 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 293 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 294 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 295 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 296 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 297 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 298 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 299 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 300 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 301 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 302 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 303 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 304 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 305 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 306 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 307 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 308 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 309 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 310 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 311 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 312 /* Bonaire */ 313 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 314 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 315 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 316 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 317 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 318 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 319 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 320 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 321 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 322 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 323 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 324 /* Hawaii */ 325 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 326 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 327 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 328 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 329 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 330 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 331 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 332 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 333 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 334 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 335 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 336 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 337 /* Kabini */ 338 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 339 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 340 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 341 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 342 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 343 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 344 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 345 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 346 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 347 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 348 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 349 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 350 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 351 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 352 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 353 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 354 /* mullins */ 355 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 356 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 357 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 358 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 359 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 360 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 361 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 362 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 363 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 364 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 365 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 366 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 367 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 368 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 369 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 370 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 371 #endif 372 /* topaz */ 373 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 374 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 375 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 376 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 377 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 378 /* tonga */ 379 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 380 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 381 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 382 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 383 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 384 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 385 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 386 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 387 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 388 /* fiji */ 389 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 390 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 391 /* carrizo */ 392 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 393 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 394 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 395 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 396 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 397 /* stoney */ 398 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 399 /* Polaris11 */ 400 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 401 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 402 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 403 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 404 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 405 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 406 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 407 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 408 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 409 /* Polaris10 */ 410 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 411 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 412 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 413 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 414 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 415 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 416 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 417 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 418 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 419 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 420 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 421 422 {0, 0, 0} 423 }; 424 425 MODULE_DEVICE_TABLE(pci, pciidlist); 426 427 static struct drm_driver kms_driver; 428 429 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 430 { 431 struct apertures_struct *ap; 432 bool primary = false; 433 434 ap = alloc_apertures(1); 435 if (!ap) 436 return -ENOMEM; 437 438 ap->ranges[0].base = pci_resource_start(pdev, 0); 439 ap->ranges[0].size = pci_resource_len(pdev, 0); 440 441 #ifdef CONFIG_X86 442 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 443 #endif 444 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 445 kfree(ap); 446 447 return 0; 448 } 449 450 static int amdgpu_pci_probe(struct pci_dev *pdev, 451 const struct pci_device_id *ent) 452 { 453 unsigned long flags = ent->driver_data; 454 int ret; 455 456 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 457 DRM_INFO("This hardware requires experimental hardware support.\n" 458 "See modparam exp_hw_support\n"); 459 return -ENODEV; 460 } 461 462 /* 463 * Initialize amdkfd before starting radeon. If it was not loaded yet, 464 * defer radeon probing 465 */ 466 ret = amdgpu_amdkfd_init(); 467 if (ret == -EPROBE_DEFER) 468 return ret; 469 470 /* Get rid of things like offb */ 471 ret = amdgpu_kick_out_firmware_fb(pdev); 472 if (ret) 473 return ret; 474 475 return drm_get_pci_dev(pdev, ent, &kms_driver); 476 } 477 478 static void 479 amdgpu_pci_remove(struct pci_dev *pdev) 480 { 481 struct drm_device *dev = pci_get_drvdata(pdev); 482 483 drm_put_dev(dev); 484 } 485 486 static void 487 amdgpu_pci_shutdown(struct pci_dev *pdev) 488 { 489 /* if we are running in a VM, make sure the device 490 * torn down properly on reboot/shutdown. 491 * unfortunately we can't detect certain 492 * hypervisors so just do this all the time. 493 */ 494 amdgpu_pci_remove(pdev); 495 } 496 497 static int amdgpu_pmops_suspend(struct device *dev) 498 { 499 struct pci_dev *pdev = to_pci_dev(dev); 500 501 struct drm_device *drm_dev = pci_get_drvdata(pdev); 502 return amdgpu_device_suspend(drm_dev, true, true); 503 } 504 505 static int amdgpu_pmops_resume(struct device *dev) 506 { 507 struct pci_dev *pdev = to_pci_dev(dev); 508 struct drm_device *drm_dev = pci_get_drvdata(pdev); 509 510 /* GPU comes up enabled by the bios on resume */ 511 if (amdgpu_device_is_px(drm_dev)) { 512 pm_runtime_disable(dev); 513 pm_runtime_set_active(dev); 514 pm_runtime_enable(dev); 515 } 516 517 return amdgpu_device_resume(drm_dev, true, true); 518 } 519 520 static int amdgpu_pmops_freeze(struct device *dev) 521 { 522 struct pci_dev *pdev = to_pci_dev(dev); 523 524 struct drm_device *drm_dev = pci_get_drvdata(pdev); 525 return amdgpu_device_suspend(drm_dev, false, true); 526 } 527 528 static int amdgpu_pmops_thaw(struct device *dev) 529 { 530 struct pci_dev *pdev = to_pci_dev(dev); 531 532 struct drm_device *drm_dev = pci_get_drvdata(pdev); 533 return amdgpu_device_resume(drm_dev, false, true); 534 } 535 536 static int amdgpu_pmops_poweroff(struct device *dev) 537 { 538 struct pci_dev *pdev = to_pci_dev(dev); 539 540 struct drm_device *drm_dev = pci_get_drvdata(pdev); 541 return amdgpu_device_suspend(drm_dev, true, true); 542 } 543 544 static int amdgpu_pmops_restore(struct device *dev) 545 { 546 struct pci_dev *pdev = to_pci_dev(dev); 547 548 struct drm_device *drm_dev = pci_get_drvdata(pdev); 549 return amdgpu_device_resume(drm_dev, false, true); 550 } 551 552 static int amdgpu_pmops_runtime_suspend(struct device *dev) 553 { 554 struct pci_dev *pdev = to_pci_dev(dev); 555 struct drm_device *drm_dev = pci_get_drvdata(pdev); 556 int ret; 557 558 if (!amdgpu_device_is_px(drm_dev)) { 559 pm_runtime_forbid(dev); 560 return -EBUSY; 561 } 562 563 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 564 drm_kms_helper_poll_disable(drm_dev); 565 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 566 567 ret = amdgpu_device_suspend(drm_dev, false, false); 568 pci_save_state(pdev); 569 pci_disable_device(pdev); 570 pci_ignore_hotplug(pdev); 571 if (amdgpu_is_atpx_hybrid()) 572 pci_set_power_state(pdev, PCI_D3cold); 573 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 574 pci_set_power_state(pdev, PCI_D3hot); 575 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 576 577 return 0; 578 } 579 580 static int amdgpu_pmops_runtime_resume(struct device *dev) 581 { 582 struct pci_dev *pdev = to_pci_dev(dev); 583 struct drm_device *drm_dev = pci_get_drvdata(pdev); 584 int ret; 585 586 if (!amdgpu_device_is_px(drm_dev)) 587 return -EINVAL; 588 589 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 590 591 if (amdgpu_is_atpx_hybrid() || 592 !amdgpu_has_atpx_dgpu_power_cntl()) 593 pci_set_power_state(pdev, PCI_D0); 594 pci_restore_state(pdev); 595 ret = pci_enable_device(pdev); 596 if (ret) 597 return ret; 598 pci_set_master(pdev); 599 600 ret = amdgpu_device_resume(drm_dev, false, false); 601 drm_kms_helper_poll_enable(drm_dev); 602 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 603 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 604 return 0; 605 } 606 607 static int amdgpu_pmops_runtime_idle(struct device *dev) 608 { 609 struct pci_dev *pdev = to_pci_dev(dev); 610 struct drm_device *drm_dev = pci_get_drvdata(pdev); 611 struct drm_crtc *crtc; 612 613 if (!amdgpu_device_is_px(drm_dev)) { 614 pm_runtime_forbid(dev); 615 return -EBUSY; 616 } 617 618 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 619 if (crtc->enabled) { 620 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 621 return -EBUSY; 622 } 623 } 624 625 pm_runtime_mark_last_busy(dev); 626 pm_runtime_autosuspend(dev); 627 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 628 return 1; 629 } 630 631 long amdgpu_drm_ioctl(struct file *filp, 632 unsigned int cmd, unsigned long arg) 633 { 634 struct drm_file *file_priv = filp->private_data; 635 struct drm_device *dev; 636 long ret; 637 dev = file_priv->minor->dev; 638 ret = pm_runtime_get_sync(dev->dev); 639 if (ret < 0) 640 return ret; 641 642 ret = drm_ioctl(filp, cmd, arg); 643 644 pm_runtime_mark_last_busy(dev->dev); 645 pm_runtime_put_autosuspend(dev->dev); 646 return ret; 647 } 648 649 static const struct dev_pm_ops amdgpu_pm_ops = { 650 .suspend = amdgpu_pmops_suspend, 651 .resume = amdgpu_pmops_resume, 652 .freeze = amdgpu_pmops_freeze, 653 .thaw = amdgpu_pmops_thaw, 654 .poweroff = amdgpu_pmops_poweroff, 655 .restore = amdgpu_pmops_restore, 656 .runtime_suspend = amdgpu_pmops_runtime_suspend, 657 .runtime_resume = amdgpu_pmops_runtime_resume, 658 .runtime_idle = amdgpu_pmops_runtime_idle, 659 }; 660 661 static const struct file_operations amdgpu_driver_kms_fops = { 662 .owner = THIS_MODULE, 663 .open = drm_open, 664 .release = drm_release, 665 .unlocked_ioctl = amdgpu_drm_ioctl, 666 .mmap = amdgpu_mmap, 667 .poll = drm_poll, 668 .read = drm_read, 669 #ifdef CONFIG_COMPAT 670 .compat_ioctl = amdgpu_kms_compat_ioctl, 671 #endif 672 }; 673 674 static struct drm_driver kms_driver = { 675 .driver_features = 676 DRIVER_USE_AGP | 677 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 678 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, 679 .dev_priv_size = 0, 680 .load = amdgpu_driver_load_kms, 681 .open = amdgpu_driver_open_kms, 682 .preclose = amdgpu_driver_preclose_kms, 683 .postclose = amdgpu_driver_postclose_kms, 684 .lastclose = amdgpu_driver_lastclose_kms, 685 .set_busid = drm_pci_set_busid, 686 .unload = amdgpu_driver_unload_kms, 687 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 688 .enable_vblank = amdgpu_enable_vblank_kms, 689 .disable_vblank = amdgpu_disable_vblank_kms, 690 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 691 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 692 #if defined(CONFIG_DEBUG_FS) 693 .debugfs_init = amdgpu_debugfs_init, 694 .debugfs_cleanup = amdgpu_debugfs_cleanup, 695 #endif 696 .irq_preinstall = amdgpu_irq_preinstall, 697 .irq_postinstall = amdgpu_irq_postinstall, 698 .irq_uninstall = amdgpu_irq_uninstall, 699 .irq_handler = amdgpu_irq_handler, 700 .ioctls = amdgpu_ioctls_kms, 701 .gem_free_object_unlocked = amdgpu_gem_object_free, 702 .gem_open_object = amdgpu_gem_object_open, 703 .gem_close_object = amdgpu_gem_object_close, 704 .dumb_create = amdgpu_mode_dumb_create, 705 .dumb_map_offset = amdgpu_mode_dumb_mmap, 706 .dumb_destroy = drm_gem_dumb_destroy, 707 .fops = &amdgpu_driver_kms_fops, 708 709 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 710 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 711 .gem_prime_export = amdgpu_gem_prime_export, 712 .gem_prime_import = drm_gem_prime_import, 713 .gem_prime_pin = amdgpu_gem_prime_pin, 714 .gem_prime_unpin = amdgpu_gem_prime_unpin, 715 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 716 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 717 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 718 .gem_prime_vmap = amdgpu_gem_prime_vmap, 719 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 720 721 .name = DRIVER_NAME, 722 .desc = DRIVER_DESC, 723 .date = DRIVER_DATE, 724 .major = KMS_DRIVER_MAJOR, 725 .minor = KMS_DRIVER_MINOR, 726 .patchlevel = KMS_DRIVER_PATCHLEVEL, 727 }; 728 729 static struct drm_driver *driver; 730 static struct pci_driver *pdriver; 731 732 static struct pci_driver amdgpu_kms_pci_driver = { 733 .name = DRIVER_NAME, 734 .id_table = pciidlist, 735 .probe = amdgpu_pci_probe, 736 .remove = amdgpu_pci_remove, 737 .shutdown = amdgpu_pci_shutdown, 738 .driver.pm = &amdgpu_pm_ops, 739 }; 740 741 742 743 static int __init amdgpu_init(void) 744 { 745 amdgpu_sync_init(); 746 amdgpu_fence_slab_init(); 747 if (vgacon_text_force()) { 748 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 749 return -EINVAL; 750 } 751 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 752 driver = &kms_driver; 753 pdriver = &amdgpu_kms_pci_driver; 754 driver->num_ioctls = amdgpu_max_kms_ioctl; 755 amdgpu_register_atpx_handler(); 756 /* let modprobe override vga console setting */ 757 return drm_pci_init(driver, pdriver); 758 } 759 760 static void __exit amdgpu_exit(void) 761 { 762 amdgpu_amdkfd_fini(); 763 drm_pci_exit(driver, pdriver); 764 amdgpu_unregister_atpx_handler(); 765 amdgpu_sync_fini(); 766 amdgpu_fence_slab_fini(); 767 } 768 769 module_init(amdgpu_init); 770 module_exit(amdgpu_exit); 771 772 MODULE_AUTHOR(DRIVER_AUTHOR); 773 MODULE_DESCRIPTION(DRIVER_DESC); 774 MODULE_LICENSE("GPL and additional rights"); 775