1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 * - 3.42.0 - Add 16bpc fixed point display support 99 */ 100 #define KMS_DRIVER_MAJOR 3 101 #define KMS_DRIVER_MINOR 42 102 #define KMS_DRIVER_PATCHLEVEL 0 103 104 int amdgpu_vram_limit; 105 int amdgpu_vis_vram_limit; 106 int amdgpu_gart_size = -1; /* auto */ 107 int amdgpu_gtt_size = -1; /* auto */ 108 int amdgpu_moverate = -1; /* auto */ 109 int amdgpu_benchmarking; 110 int amdgpu_testing; 111 int amdgpu_audio = -1; 112 int amdgpu_disp_priority; 113 int amdgpu_hw_i2c; 114 int amdgpu_pcie_gen2 = -1; 115 int amdgpu_msi = -1; 116 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 117 int amdgpu_dpm = -1; 118 int amdgpu_fw_load_type = -1; 119 int amdgpu_aspm = -1; 120 int amdgpu_runtime_pm = -1; 121 uint amdgpu_ip_block_mask = 0xffffffff; 122 int amdgpu_bapm = -1; 123 int amdgpu_deep_color; 124 int amdgpu_vm_size = -1; 125 int amdgpu_vm_fragment_size = -1; 126 int amdgpu_vm_block_size = -1; 127 int amdgpu_vm_fault_stop; 128 int amdgpu_vm_debug; 129 int amdgpu_vm_update_mode = -1; 130 int amdgpu_exp_hw_support; 131 int amdgpu_dc = -1; 132 int amdgpu_sched_jobs = 32; 133 int amdgpu_sched_hw_submission = 2; 134 uint amdgpu_pcie_gen_cap; 135 uint amdgpu_pcie_lane_cap; 136 uint amdgpu_cg_mask = 0xffffffff; 137 uint amdgpu_pg_mask = 0xffffffff; 138 uint amdgpu_sdma_phase_quantum = 32; 139 char *amdgpu_disable_cu = NULL; 140 char *amdgpu_virtual_display = NULL; 141 142 /* 143 * OverDrive(bit 14) disabled by default 144 * GFX DCS(bit 19) disabled by default 145 */ 146 uint amdgpu_pp_feature_mask = 0xfff7bfff; 147 uint amdgpu_force_long_training; 148 int amdgpu_job_hang_limit; 149 int amdgpu_lbpw = -1; 150 int amdgpu_compute_multipipe = -1; 151 int amdgpu_gpu_recovery = -1; /* auto */ 152 int amdgpu_emu_mode; 153 uint amdgpu_smu_memory_pool_size; 154 int amdgpu_smu_pptable_id = -1; 155 /* 156 * FBC (bit 0) disabled by default 157 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 158 * - With this, for multiple monitors in sync(e.g. with the same model), 159 * mclk switching will be allowed. And the mclk will be not foced to the 160 * highest. That helps saving some idle power. 161 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 162 * PSR (bit 3) disabled by default 163 * EDP NO POWER SEQUENCING (bit 4) disabled by default 164 */ 165 uint amdgpu_dc_feature_mask = 2; 166 uint amdgpu_dc_debug_mask; 167 int amdgpu_async_gfx_ring = 1; 168 int amdgpu_mcbp; 169 int amdgpu_discovery = -1; 170 int amdgpu_mes; 171 int amdgpu_noretry = -1; 172 int amdgpu_force_asic_type = -1; 173 int amdgpu_tmz = -1; /* auto */ 174 uint amdgpu_freesync_vid_mode; 175 int amdgpu_reset_method = -1; /* auto */ 176 int amdgpu_num_kcq = -1; 177 int amdgpu_smartshift_bias; 178 179 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 180 181 struct amdgpu_mgpu_info mgpu_info = { 182 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 183 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 184 mgpu_info.delayed_reset_work, 185 amdgpu_drv_delayed_reset_work_handler, 0), 186 }; 187 int amdgpu_ras_enable = -1; 188 uint amdgpu_ras_mask = 0xffffffff; 189 int amdgpu_bad_page_threshold = -1; 190 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 191 .timeout_fatal_disable = false, 192 .period = 0x0, /* default to 0x0 (timeout disable) */ 193 }; 194 195 /** 196 * DOC: vramlimit (int) 197 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 198 */ 199 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 200 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 201 202 /** 203 * DOC: vis_vramlimit (int) 204 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 205 */ 206 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 207 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 208 209 /** 210 * DOC: gartsize (uint) 211 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 212 */ 213 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 214 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 215 216 /** 217 * DOC: gttsize (int) 218 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 219 * otherwise 3/4 RAM size). 220 */ 221 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 222 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 223 224 /** 225 * DOC: moverate (int) 226 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 227 */ 228 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 229 module_param_named(moverate, amdgpu_moverate, int, 0600); 230 231 /** 232 * DOC: benchmark (int) 233 * Run benchmarks. The default is 0 (Skip benchmarks). 234 */ 235 MODULE_PARM_DESC(benchmark, "Run benchmark"); 236 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 237 238 /** 239 * DOC: test (int) 240 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 241 */ 242 MODULE_PARM_DESC(test, "Run tests"); 243 module_param_named(test, amdgpu_testing, int, 0444); 244 245 /** 246 * DOC: audio (int) 247 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 248 */ 249 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 250 module_param_named(audio, amdgpu_audio, int, 0444); 251 252 /** 253 * DOC: disp_priority (int) 254 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 255 */ 256 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 257 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 258 259 /** 260 * DOC: hw_i2c (int) 261 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 262 */ 263 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 264 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 265 266 /** 267 * DOC: pcie_gen2 (int) 268 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 269 */ 270 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 271 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 272 273 /** 274 * DOC: msi (int) 275 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 276 */ 277 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 278 module_param_named(msi, amdgpu_msi, int, 0444); 279 280 /** 281 * DOC: lockup_timeout (string) 282 * Set GPU scheduler timeout value in ms. 283 * 284 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 285 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 286 * to the default timeout. 287 * 288 * - With one value specified, the setting will apply to all non-compute jobs. 289 * - With multiple values specified, the first one will be for GFX. 290 * The second one is for Compute. The third and fourth ones are 291 * for SDMA and Video. 292 * 293 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 294 * jobs is 10000. The timeout for compute is 60000. 295 */ 296 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 297 "for passthrough or sriov, 10000 for all jobs." 298 " 0: keep default value. negative: infinity timeout), " 299 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 300 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 301 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 302 303 /** 304 * DOC: dpm (int) 305 * Override for dynamic power management setting 306 * (0 = disable, 1 = enable) 307 * The default is -1 (auto). 308 */ 309 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 310 module_param_named(dpm, amdgpu_dpm, int, 0444); 311 312 /** 313 * DOC: fw_load_type (int) 314 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 315 */ 316 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 317 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 318 319 /** 320 * DOC: aspm (int) 321 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 322 */ 323 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 324 module_param_named(aspm, amdgpu_aspm, int, 0444); 325 326 /** 327 * DOC: runpm (int) 328 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 329 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 330 */ 331 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 332 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 333 334 /** 335 * DOC: ip_block_mask (uint) 336 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 337 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 338 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 339 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 340 */ 341 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 342 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 343 344 /** 345 * DOC: bapm (int) 346 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 347 * The default -1 (auto, enabled) 348 */ 349 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 350 module_param_named(bapm, amdgpu_bapm, int, 0444); 351 352 /** 353 * DOC: deep_color (int) 354 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 355 */ 356 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 357 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 358 359 /** 360 * DOC: vm_size (int) 361 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 362 */ 363 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 364 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 365 366 /** 367 * DOC: vm_fragment_size (int) 368 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 369 */ 370 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 371 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 372 373 /** 374 * DOC: vm_block_size (int) 375 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 376 */ 377 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 378 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 379 380 /** 381 * DOC: vm_fault_stop (int) 382 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 383 */ 384 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 385 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 386 387 /** 388 * DOC: vm_debug (int) 389 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 390 */ 391 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 392 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 393 394 /** 395 * DOC: vm_update_mode (int) 396 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 397 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 398 */ 399 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 400 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 401 402 /** 403 * DOC: exp_hw_support (int) 404 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 405 */ 406 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 407 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 408 409 /** 410 * DOC: dc (int) 411 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 412 */ 413 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 414 module_param_named(dc, amdgpu_dc, int, 0444); 415 416 /** 417 * DOC: sched_jobs (int) 418 * Override the max number of jobs supported in the sw queue. The default is 32. 419 */ 420 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 421 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 422 423 /** 424 * DOC: sched_hw_submission (int) 425 * Override the max number of HW submissions. The default is 2. 426 */ 427 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 428 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 429 430 /** 431 * DOC: ppfeaturemask (hexint) 432 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 433 * The default is the current set of stable power features. 434 */ 435 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 436 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 437 438 /** 439 * DOC: forcelongtraining (uint) 440 * Force long memory training in resume. 441 * The default is zero, indicates short training in resume. 442 */ 443 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 444 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 445 446 /** 447 * DOC: pcie_gen_cap (uint) 448 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 449 * The default is 0 (automatic for each asic). 450 */ 451 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 452 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 453 454 /** 455 * DOC: pcie_lane_cap (uint) 456 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 457 * The default is 0 (automatic for each asic). 458 */ 459 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 460 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 461 462 /** 463 * DOC: cg_mask (uint) 464 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 465 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 466 */ 467 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 468 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 469 470 /** 471 * DOC: pg_mask (uint) 472 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 473 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 474 */ 475 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 476 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 477 478 /** 479 * DOC: sdma_phase_quantum (uint) 480 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 481 */ 482 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 483 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 484 485 /** 486 * DOC: disable_cu (charp) 487 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 488 */ 489 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 490 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 491 492 /** 493 * DOC: virtual_display (charp) 494 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 495 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 496 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 497 * device at 26:00.0. The default is NULL. 498 */ 499 MODULE_PARM_DESC(virtual_display, 500 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 501 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 502 503 /** 504 * DOC: job_hang_limit (int) 505 * Set how much time allow a job hang and not drop it. The default is 0. 506 */ 507 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 508 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 509 510 /** 511 * DOC: lbpw (int) 512 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 513 */ 514 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 515 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 516 517 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 518 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 519 520 /** 521 * DOC: gpu_recovery (int) 522 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 523 */ 524 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 525 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 526 527 /** 528 * DOC: emu_mode (int) 529 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 530 */ 531 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 532 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 533 534 /** 535 * DOC: ras_enable (int) 536 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 537 */ 538 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 539 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 540 541 /** 542 * DOC: ras_mask (uint) 543 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 544 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 545 */ 546 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 547 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 548 549 /** 550 * DOC: timeout_fatal_disable (bool) 551 * Disable Watchdog timeout fatal error event 552 */ 553 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 554 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 555 556 /** 557 * DOC: timeout_period (uint) 558 * Modify the watchdog timeout max_cycles as (1 << period) 559 */ 560 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 561 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 562 563 /** 564 * DOC: si_support (int) 565 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 566 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 567 * otherwise using amdgpu driver. 568 */ 569 #ifdef CONFIG_DRM_AMDGPU_SI 570 571 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 572 int amdgpu_si_support = 0; 573 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 574 #else 575 int amdgpu_si_support = 1; 576 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 577 #endif 578 579 module_param_named(si_support, amdgpu_si_support, int, 0444); 580 #endif 581 582 /** 583 * DOC: cik_support (int) 584 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 585 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 586 * otherwise using amdgpu driver. 587 */ 588 #ifdef CONFIG_DRM_AMDGPU_CIK 589 590 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 591 int amdgpu_cik_support = 0; 592 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 593 #else 594 int amdgpu_cik_support = 1; 595 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 596 #endif 597 598 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 599 #endif 600 601 /** 602 * DOC: smu_memory_pool_size (uint) 603 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 604 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 605 */ 606 MODULE_PARM_DESC(smu_memory_pool_size, 607 "reserve gtt for smu debug usage, 0 = disable," 608 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 609 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 610 611 /** 612 * DOC: async_gfx_ring (int) 613 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 614 */ 615 MODULE_PARM_DESC(async_gfx_ring, 616 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 617 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 618 619 /** 620 * DOC: mcbp (int) 621 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 622 */ 623 MODULE_PARM_DESC(mcbp, 624 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 625 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 626 627 /** 628 * DOC: discovery (int) 629 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 630 * (-1 = auto (default), 0 = disabled, 1 = enabled) 631 */ 632 MODULE_PARM_DESC(discovery, 633 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 634 module_param_named(discovery, amdgpu_discovery, int, 0444); 635 636 /** 637 * DOC: mes (int) 638 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 639 * (0 = disabled (default), 1 = enabled) 640 */ 641 MODULE_PARM_DESC(mes, 642 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 643 module_param_named(mes, amdgpu_mes, int, 0444); 644 645 /** 646 * DOC: noretry (int) 647 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 648 * do not support per-process XNACK this also disables retry page faults. 649 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 650 */ 651 MODULE_PARM_DESC(noretry, 652 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 653 module_param_named(noretry, amdgpu_noretry, int, 0644); 654 655 /** 656 * DOC: force_asic_type (int) 657 * A non negative value used to specify the asic type for all supported GPUs. 658 */ 659 MODULE_PARM_DESC(force_asic_type, 660 "A non negative value used to specify the asic type for all supported GPUs"); 661 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 662 663 664 665 #ifdef CONFIG_HSA_AMD 666 /** 667 * DOC: sched_policy (int) 668 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 669 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 670 * assigns queues to HQDs. 671 */ 672 int sched_policy = KFD_SCHED_POLICY_HWS; 673 module_param(sched_policy, int, 0444); 674 MODULE_PARM_DESC(sched_policy, 675 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 676 677 /** 678 * DOC: hws_max_conc_proc (int) 679 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 680 * number of VMIDs assigned to the HWS, which is also the default. 681 */ 682 int hws_max_conc_proc = 8; 683 module_param(hws_max_conc_proc, int, 0444); 684 MODULE_PARM_DESC(hws_max_conc_proc, 685 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 686 687 /** 688 * DOC: cwsr_enable (int) 689 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 690 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 691 * disables it. 692 */ 693 int cwsr_enable = 1; 694 module_param(cwsr_enable, int, 0444); 695 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 696 697 /** 698 * DOC: max_num_of_queues_per_device (int) 699 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 700 * is 4096. 701 */ 702 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 703 module_param(max_num_of_queues_per_device, int, 0444); 704 MODULE_PARM_DESC(max_num_of_queues_per_device, 705 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 706 707 /** 708 * DOC: send_sigterm (int) 709 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 710 * but just print errors on dmesg. Setting 1 enables sending sigterm. 711 */ 712 int send_sigterm; 713 module_param(send_sigterm, int, 0444); 714 MODULE_PARM_DESC(send_sigterm, 715 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 716 717 /** 718 * DOC: debug_largebar (int) 719 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 720 * system. This limits the VRAM size reported to ROCm applications to the visible 721 * size, usually 256MB. 722 * Default value is 0, diabled. 723 */ 724 int debug_largebar; 725 module_param(debug_largebar, int, 0444); 726 MODULE_PARM_DESC(debug_largebar, 727 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 728 729 /** 730 * DOC: ignore_crat (int) 731 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 732 * table to get information about AMD APUs. This option can serve as a workaround on 733 * systems with a broken CRAT table. 734 * 735 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 736 * whehter use CRAT) 737 */ 738 int ignore_crat; 739 module_param(ignore_crat, int, 0444); 740 MODULE_PARM_DESC(ignore_crat, 741 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 742 743 /** 744 * DOC: halt_if_hws_hang (int) 745 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 746 * Setting 1 enables halt on hang. 747 */ 748 int halt_if_hws_hang; 749 module_param(halt_if_hws_hang, int, 0644); 750 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 751 752 /** 753 * DOC: hws_gws_support(bool) 754 * Assume that HWS supports GWS barriers regardless of what firmware version 755 * check says. Default value: false (rely on MEC2 firmware version check). 756 */ 757 bool hws_gws_support; 758 module_param(hws_gws_support, bool, 0444); 759 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 760 761 /** 762 * DOC: queue_preemption_timeout_ms (int) 763 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 764 */ 765 int queue_preemption_timeout_ms = 9000; 766 module_param(queue_preemption_timeout_ms, int, 0644); 767 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 768 769 /** 770 * DOC: debug_evictions(bool) 771 * Enable extra debug messages to help determine the cause of evictions 772 */ 773 bool debug_evictions; 774 module_param(debug_evictions, bool, 0644); 775 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 776 777 /** 778 * DOC: no_system_mem_limit(bool) 779 * Disable system memory limit, to support multiple process shared memory 780 */ 781 bool no_system_mem_limit; 782 module_param(no_system_mem_limit, bool, 0644); 783 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 784 785 /** 786 * DOC: no_queue_eviction_on_vm_fault (int) 787 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 788 */ 789 int amdgpu_no_queue_eviction_on_vm_fault = 0; 790 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 791 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 792 #endif 793 794 /** 795 * DOC: dcfeaturemask (uint) 796 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 797 * The default is the current set of stable display features. 798 */ 799 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 800 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 801 802 /** 803 * DOC: dcdebugmask (uint) 804 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 805 */ 806 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 807 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 808 809 /** 810 * DOC: abmlevel (uint) 811 * Override the default ABM (Adaptive Backlight Management) level used for DC 812 * enabled hardware. Requires DMCU to be supported and loaded. 813 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 814 * default. Values 1-4 control the maximum allowable brightness reduction via 815 * the ABM algorithm, with 1 being the least reduction and 4 being the most 816 * reduction. 817 * 818 * Defaults to 0, or disabled. Userspace can still override this level later 819 * after boot. 820 */ 821 uint amdgpu_dm_abm_level; 822 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 823 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 824 825 int amdgpu_backlight = -1; 826 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 827 module_param_named(backlight, amdgpu_backlight, bint, 0444); 828 829 /** 830 * DOC: tmz (int) 831 * Trusted Memory Zone (TMZ) is a method to protect data being written 832 * to or read from memory. 833 * 834 * The default value: 0 (off). TODO: change to auto till it is completed. 835 */ 836 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 837 module_param_named(tmz, amdgpu_tmz, int, 0444); 838 839 /** 840 * DOC: freesync_video (uint) 841 * Enable the optimization to adjust front porch timing to achieve seamless 842 * mode change experience when setting a freesync supported mode for which full 843 * modeset is not needed. 844 * 845 * The Display Core will add a set of modes derived from the base FreeSync 846 * video mode into the corresponding connector's mode list based on commonly 847 * used refresh rates and VRR range of the connected display, when users enable 848 * this feature. From the userspace perspective, they can see a seamless mode 849 * change experience when the change between different refresh rates under the 850 * same resolution. Additionally, userspace applications such as Video playback 851 * can read this modeset list and change the refresh rate based on the video 852 * frame rate. Finally, the userspace can also derive an appropriate mode for a 853 * particular refresh rate based on the FreeSync Mode and add it to the 854 * connector's mode list. 855 * 856 * Note: This is an experimental feature. 857 * 858 * The default value: 0 (off). 859 */ 860 MODULE_PARM_DESC( 861 freesync_video, 862 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 863 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 864 865 /** 866 * DOC: reset_method (int) 867 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 868 */ 869 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 870 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 871 872 /** 873 * DOC: bad_page_threshold (int) 874 * Bad page threshold is to specify the threshold value of faulty pages 875 * detected by RAS ECC, that may result in GPU entering bad status if total 876 * faulty pages by ECC exceed threshold value and leave it for user's further 877 * check. 878 */ 879 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 880 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 881 882 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 883 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 884 885 /** 886 * DOC: smu_pptable_id (int) 887 * Used to override pptable id. id = 0 use VBIOS pptable. 888 * id > 0 use the soft pptable with specicfied id. 889 */ 890 MODULE_PARM_DESC(smu_pptable_id, 891 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 892 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 893 894 static const struct pci_device_id pciidlist[] = { 895 #ifdef CONFIG_DRM_AMDGPU_SI 896 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 897 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 898 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 899 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 900 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 901 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 902 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 903 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 904 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 905 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 906 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 907 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 908 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 909 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 910 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 911 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 912 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 913 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 914 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 915 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 916 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 917 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 918 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 919 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 920 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 921 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 922 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 923 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 924 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 925 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 926 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 927 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 928 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 929 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 930 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 931 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 932 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 933 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 934 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 935 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 936 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 937 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 938 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 939 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 940 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 941 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 942 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 943 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 944 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 945 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 946 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 947 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 948 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 949 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 950 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 951 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 952 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 953 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 954 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 955 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 956 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 957 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 958 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 959 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 960 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 961 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 962 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 963 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 964 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 965 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 966 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 967 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 968 #endif 969 #ifdef CONFIG_DRM_AMDGPU_CIK 970 /* Kaveri */ 971 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 972 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 973 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 974 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 975 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 976 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 977 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 978 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 979 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 980 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 981 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 982 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 983 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 984 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 985 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 986 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 987 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 988 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 989 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 990 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 991 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 992 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 993 /* Bonaire */ 994 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 995 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 996 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 997 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 998 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 999 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1000 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1001 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1002 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1003 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1004 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1005 /* Hawaii */ 1006 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1007 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1008 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1009 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1010 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1011 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1012 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1013 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1014 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1015 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1016 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1017 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1018 /* Kabini */ 1019 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1020 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1021 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1022 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1023 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1024 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1025 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1026 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1027 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1028 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1029 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1030 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1031 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1032 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1033 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1034 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1035 /* mullins */ 1036 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1037 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1038 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1039 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1040 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1041 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1042 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1043 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1044 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1045 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1046 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1047 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1048 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1049 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1050 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1051 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1052 #endif 1053 /* topaz */ 1054 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1055 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1056 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1057 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1058 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1059 /* tonga */ 1060 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1061 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1062 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1063 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1064 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1065 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1066 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1067 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1068 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1069 /* fiji */ 1070 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1071 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1072 /* carrizo */ 1073 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1074 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1075 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1076 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1077 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1078 /* stoney */ 1079 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1080 /* Polaris11 */ 1081 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1082 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1083 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1084 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1085 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1086 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1087 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1088 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1089 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1090 /* Polaris10 */ 1091 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1092 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1093 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1094 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1095 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1096 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1097 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1098 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1099 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1100 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1101 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1102 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1103 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1104 /* Polaris12 */ 1105 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1106 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1107 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1108 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1109 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1110 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1111 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1112 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1113 /* VEGAM */ 1114 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1115 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1116 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1117 /* Vega 10 */ 1118 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1119 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1120 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1121 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1122 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1123 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1124 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1125 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1126 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1127 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1128 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1129 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1130 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1131 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1132 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1133 /* Vega 12 */ 1134 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1135 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1136 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1137 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1138 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1139 /* Vega 20 */ 1140 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1141 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1142 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1143 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1144 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1145 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1146 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1147 /* Raven */ 1148 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1149 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1150 /* Arcturus */ 1151 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1152 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1153 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1154 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1155 /* Navi10 */ 1156 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1157 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1158 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1159 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1160 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1161 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1162 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1163 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1164 /* Navi14 */ 1165 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1166 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1167 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1168 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1169 1170 /* Renoir */ 1171 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1172 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1173 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1174 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1175 1176 /* Navi12 */ 1177 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1178 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1179 1180 /* Sienna_Cichlid */ 1181 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1182 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1183 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1184 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1185 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1186 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1187 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1188 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1189 1190 /* Van Gogh */ 1191 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1192 1193 /* Yellow Carp */ 1194 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1195 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1196 1197 /* Navy_Flounder */ 1198 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1199 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1200 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1201 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1202 1203 /* DIMGREY_CAVEFISH */ 1204 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1205 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1206 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1207 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1208 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1209 1210 /* Aldebaran */ 1211 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1212 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1213 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1214 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1215 1216 /* BEIGE_GOBY */ 1217 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1218 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1219 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1220 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1221 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1222 1223 {0, 0, 0} 1224 }; 1225 1226 MODULE_DEVICE_TABLE(pci, pciidlist); 1227 1228 static const struct drm_driver amdgpu_kms_driver; 1229 1230 static int amdgpu_pci_probe(struct pci_dev *pdev, 1231 const struct pci_device_id *ent) 1232 { 1233 struct drm_device *ddev; 1234 struct amdgpu_device *adev; 1235 unsigned long flags = ent->driver_data; 1236 int ret, retry = 0; 1237 bool supports_atomic = false; 1238 1239 if (!amdgpu_virtual_display && 1240 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1241 supports_atomic = true; 1242 1243 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1244 DRM_INFO("This hardware requires experimental hardware support.\n" 1245 "See modparam exp_hw_support\n"); 1246 return -ENODEV; 1247 } 1248 1249 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1250 * however, SME requires an indirect IOMMU mapping because the encryption 1251 * bit is beyond the DMA mask of the chip. 1252 */ 1253 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1254 dev_info(&pdev->dev, 1255 "SME is not compatible with RAVEN\n"); 1256 return -ENOTSUPP; 1257 } 1258 1259 #ifdef CONFIG_DRM_AMDGPU_SI 1260 if (!amdgpu_si_support) { 1261 switch (flags & AMD_ASIC_MASK) { 1262 case CHIP_TAHITI: 1263 case CHIP_PITCAIRN: 1264 case CHIP_VERDE: 1265 case CHIP_OLAND: 1266 case CHIP_HAINAN: 1267 dev_info(&pdev->dev, 1268 "SI support provided by radeon.\n"); 1269 dev_info(&pdev->dev, 1270 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1271 ); 1272 return -ENODEV; 1273 } 1274 } 1275 #endif 1276 #ifdef CONFIG_DRM_AMDGPU_CIK 1277 if (!amdgpu_cik_support) { 1278 switch (flags & AMD_ASIC_MASK) { 1279 case CHIP_KAVERI: 1280 case CHIP_BONAIRE: 1281 case CHIP_HAWAII: 1282 case CHIP_KABINI: 1283 case CHIP_MULLINS: 1284 dev_info(&pdev->dev, 1285 "CIK support provided by radeon.\n"); 1286 dev_info(&pdev->dev, 1287 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1288 ); 1289 return -ENODEV; 1290 } 1291 } 1292 #endif 1293 1294 /* Get rid of things like offb */ 1295 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1296 if (ret) 1297 return ret; 1298 1299 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1300 if (IS_ERR(adev)) 1301 return PTR_ERR(adev); 1302 1303 adev->dev = &pdev->dev; 1304 adev->pdev = pdev; 1305 ddev = adev_to_drm(adev); 1306 1307 if (!supports_atomic) 1308 ddev->driver_features &= ~DRIVER_ATOMIC; 1309 1310 ret = pci_enable_device(pdev); 1311 if (ret) 1312 return ret; 1313 1314 pci_set_drvdata(pdev, ddev); 1315 1316 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1317 if (ret) 1318 goto err_pci; 1319 1320 retry_init: 1321 ret = drm_dev_register(ddev, ent->driver_data); 1322 if (ret == -EAGAIN && ++retry <= 3) { 1323 DRM_INFO("retry init %d\n", retry); 1324 /* Don't request EX mode too frequently which is attacking */ 1325 msleep(5000); 1326 goto retry_init; 1327 } else if (ret) { 1328 goto err_pci; 1329 } 1330 1331 ret = amdgpu_debugfs_init(adev); 1332 if (ret) 1333 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1334 1335 return 0; 1336 1337 err_pci: 1338 pci_disable_device(pdev); 1339 return ret; 1340 } 1341 1342 static void 1343 amdgpu_pci_remove(struct pci_dev *pdev) 1344 { 1345 struct drm_device *dev = pci_get_drvdata(pdev); 1346 1347 drm_dev_unplug(dev); 1348 amdgpu_driver_unload_kms(dev); 1349 1350 /* 1351 * Flush any in flight DMA operations from device. 1352 * Clear the Bus Master Enable bit and then wait on the PCIe Device 1353 * StatusTransactions Pending bit. 1354 */ 1355 pci_disable_device(pdev); 1356 pci_wait_for_pending_transaction(pdev); 1357 } 1358 1359 static void 1360 amdgpu_pci_shutdown(struct pci_dev *pdev) 1361 { 1362 struct drm_device *dev = pci_get_drvdata(pdev); 1363 struct amdgpu_device *adev = drm_to_adev(dev); 1364 1365 if (amdgpu_ras_intr_triggered()) 1366 return; 1367 1368 /* if we are running in a VM, make sure the device 1369 * torn down properly on reboot/shutdown. 1370 * unfortunately we can't detect certain 1371 * hypervisors so just do this all the time. 1372 */ 1373 if (!amdgpu_passthrough(adev)) 1374 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1375 amdgpu_device_ip_suspend(adev); 1376 adev->mp1_state = PP_MP1_STATE_NONE; 1377 } 1378 1379 /** 1380 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 1381 * 1382 * @work: work_struct. 1383 */ 1384 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 1385 { 1386 struct list_head device_list; 1387 struct amdgpu_device *adev; 1388 int i, r; 1389 struct amdgpu_reset_context reset_context; 1390 1391 memset(&reset_context, 0, sizeof(reset_context)); 1392 1393 mutex_lock(&mgpu_info.mutex); 1394 if (mgpu_info.pending_reset == true) { 1395 mutex_unlock(&mgpu_info.mutex); 1396 return; 1397 } 1398 mgpu_info.pending_reset = true; 1399 mutex_unlock(&mgpu_info.mutex); 1400 1401 /* Use a common context, just need to make sure full reset is done */ 1402 reset_context.method = AMD_RESET_METHOD_NONE; 1403 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 1404 1405 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1406 adev = mgpu_info.gpu_ins[i].adev; 1407 reset_context.reset_req_dev = adev; 1408 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 1409 if (r) { 1410 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 1411 r, adev_to_drm(adev)->unique); 1412 } 1413 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 1414 r = -EALREADY; 1415 } 1416 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1417 adev = mgpu_info.gpu_ins[i].adev; 1418 flush_work(&adev->xgmi_reset_work); 1419 adev->gmc.xgmi.pending_reset = false; 1420 } 1421 1422 /* reset function will rebuild the xgmi hive info , clear it now */ 1423 for (i = 0; i < mgpu_info.num_dgpu; i++) 1424 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 1425 1426 INIT_LIST_HEAD(&device_list); 1427 1428 for (i = 0; i < mgpu_info.num_dgpu; i++) 1429 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 1430 1431 /* unregister the GPU first, reset function will add them back */ 1432 list_for_each_entry(adev, &device_list, reset_list) 1433 amdgpu_unregister_gpu_instance(adev); 1434 1435 /* Use a common context, just need to make sure full reset is done */ 1436 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 1437 r = amdgpu_do_asic_reset(&device_list, &reset_context); 1438 1439 if (r) { 1440 DRM_ERROR("reinit gpus failure"); 1441 return; 1442 } 1443 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1444 adev = mgpu_info.gpu_ins[i].adev; 1445 if (!adev->kfd.init_complete) 1446 amdgpu_amdkfd_device_init(adev); 1447 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1448 } 1449 return; 1450 } 1451 1452 static int amdgpu_pmops_prepare(struct device *dev) 1453 { 1454 struct drm_device *drm_dev = dev_get_drvdata(dev); 1455 1456 /* Return a positive number here so 1457 * DPM_FLAG_SMART_SUSPEND works properly 1458 */ 1459 if (amdgpu_device_supports_boco(drm_dev)) 1460 return pm_runtime_suspended(dev) && 1461 pm_suspend_via_firmware(); 1462 1463 return 0; 1464 } 1465 1466 static void amdgpu_pmops_complete(struct device *dev) 1467 { 1468 /* nothing to do */ 1469 } 1470 1471 static int amdgpu_pmops_suspend(struct device *dev) 1472 { 1473 struct drm_device *drm_dev = dev_get_drvdata(dev); 1474 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1475 int r; 1476 1477 if (amdgpu_acpi_is_s0ix_supported(adev)) 1478 adev->in_s0ix = true; 1479 adev->in_s3 = true; 1480 r = amdgpu_device_suspend(drm_dev, true); 1481 adev->in_s3 = false; 1482 1483 return r; 1484 } 1485 1486 static int amdgpu_pmops_resume(struct device *dev) 1487 { 1488 struct drm_device *drm_dev = dev_get_drvdata(dev); 1489 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1490 int r; 1491 1492 r = amdgpu_device_resume(drm_dev, true); 1493 if (amdgpu_acpi_is_s0ix_supported(adev)) 1494 adev->in_s0ix = false; 1495 return r; 1496 } 1497 1498 static int amdgpu_pmops_freeze(struct device *dev) 1499 { 1500 struct drm_device *drm_dev = dev_get_drvdata(dev); 1501 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1502 int r; 1503 1504 adev->in_s4 = true; 1505 r = amdgpu_device_suspend(drm_dev, true); 1506 adev->in_s4 = false; 1507 if (r) 1508 return r; 1509 return amdgpu_asic_reset(adev); 1510 } 1511 1512 static int amdgpu_pmops_thaw(struct device *dev) 1513 { 1514 struct drm_device *drm_dev = dev_get_drvdata(dev); 1515 1516 return amdgpu_device_resume(drm_dev, true); 1517 } 1518 1519 static int amdgpu_pmops_poweroff(struct device *dev) 1520 { 1521 struct drm_device *drm_dev = dev_get_drvdata(dev); 1522 1523 return amdgpu_device_suspend(drm_dev, true); 1524 } 1525 1526 static int amdgpu_pmops_restore(struct device *dev) 1527 { 1528 struct drm_device *drm_dev = dev_get_drvdata(dev); 1529 1530 return amdgpu_device_resume(drm_dev, true); 1531 } 1532 1533 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1534 { 1535 struct pci_dev *pdev = to_pci_dev(dev); 1536 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1537 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1538 int ret, i; 1539 1540 if (!adev->runpm) { 1541 pm_runtime_forbid(dev); 1542 return -EBUSY; 1543 } 1544 1545 /* wait for all rings to drain before suspending */ 1546 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1547 struct amdgpu_ring *ring = adev->rings[i]; 1548 if (ring && ring->sched.ready) { 1549 ret = amdgpu_fence_wait_empty(ring); 1550 if (ret) 1551 return -EBUSY; 1552 } 1553 } 1554 1555 adev->in_runpm = true; 1556 if (amdgpu_device_supports_px(drm_dev)) 1557 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1558 1559 ret = amdgpu_device_suspend(drm_dev, false); 1560 if (ret) { 1561 adev->in_runpm = false; 1562 return ret; 1563 } 1564 1565 if (amdgpu_device_supports_px(drm_dev)) { 1566 /* Only need to handle PCI state in the driver for ATPX 1567 * PCI core handles it for _PR3. 1568 */ 1569 amdgpu_device_cache_pci_state(pdev); 1570 pci_disable_device(pdev); 1571 pci_ignore_hotplug(pdev); 1572 pci_set_power_state(pdev, PCI_D3cold); 1573 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1574 } else if (amdgpu_device_supports_boco(drm_dev)) { 1575 /* nothing to do */ 1576 } else if (amdgpu_device_supports_baco(drm_dev)) { 1577 amdgpu_device_baco_enter(drm_dev); 1578 } 1579 1580 return 0; 1581 } 1582 1583 static int amdgpu_pmops_runtime_resume(struct device *dev) 1584 { 1585 struct pci_dev *pdev = to_pci_dev(dev); 1586 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1587 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1588 int ret; 1589 1590 if (!adev->runpm) 1591 return -EINVAL; 1592 1593 /* Avoids registers access if device is physically gone */ 1594 if (!pci_device_is_present(adev->pdev)) 1595 adev->no_hw_access = true; 1596 1597 if (amdgpu_device_supports_px(drm_dev)) { 1598 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1599 1600 /* Only need to handle PCI state in the driver for ATPX 1601 * PCI core handles it for _PR3. 1602 */ 1603 pci_set_power_state(pdev, PCI_D0); 1604 amdgpu_device_load_pci_state(pdev); 1605 ret = pci_enable_device(pdev); 1606 if (ret) 1607 return ret; 1608 pci_set_master(pdev); 1609 } else if (amdgpu_device_supports_boco(drm_dev)) { 1610 /* Only need to handle PCI state in the driver for ATPX 1611 * PCI core handles it for _PR3. 1612 */ 1613 pci_set_master(pdev); 1614 } else if (amdgpu_device_supports_baco(drm_dev)) { 1615 amdgpu_device_baco_exit(drm_dev); 1616 } 1617 ret = amdgpu_device_resume(drm_dev, false); 1618 if (ret) 1619 return ret; 1620 1621 if (amdgpu_device_supports_px(drm_dev)) 1622 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1623 adev->in_runpm = false; 1624 return 0; 1625 } 1626 1627 static int amdgpu_pmops_runtime_idle(struct device *dev) 1628 { 1629 struct drm_device *drm_dev = dev_get_drvdata(dev); 1630 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1631 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1632 int ret = 1; 1633 1634 if (!adev->runpm) { 1635 pm_runtime_forbid(dev); 1636 return -EBUSY; 1637 } 1638 1639 if (amdgpu_device_has_dc_support(adev)) { 1640 struct drm_crtc *crtc; 1641 1642 drm_for_each_crtc(crtc, drm_dev) { 1643 drm_modeset_lock(&crtc->mutex, NULL); 1644 if (crtc->state->active) 1645 ret = -EBUSY; 1646 drm_modeset_unlock(&crtc->mutex); 1647 if (ret < 0) 1648 break; 1649 } 1650 1651 } else { 1652 struct drm_connector *list_connector; 1653 struct drm_connector_list_iter iter; 1654 1655 mutex_lock(&drm_dev->mode_config.mutex); 1656 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1657 1658 drm_connector_list_iter_begin(drm_dev, &iter); 1659 drm_for_each_connector_iter(list_connector, &iter) { 1660 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1661 ret = -EBUSY; 1662 break; 1663 } 1664 } 1665 1666 drm_connector_list_iter_end(&iter); 1667 1668 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1669 mutex_unlock(&drm_dev->mode_config.mutex); 1670 } 1671 1672 if (ret == -EBUSY) 1673 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1674 1675 pm_runtime_mark_last_busy(dev); 1676 pm_runtime_autosuspend(dev); 1677 return ret; 1678 } 1679 1680 long amdgpu_drm_ioctl(struct file *filp, 1681 unsigned int cmd, unsigned long arg) 1682 { 1683 struct drm_file *file_priv = filp->private_data; 1684 struct drm_device *dev; 1685 long ret; 1686 dev = file_priv->minor->dev; 1687 ret = pm_runtime_get_sync(dev->dev); 1688 if (ret < 0) 1689 goto out; 1690 1691 ret = drm_ioctl(filp, cmd, arg); 1692 1693 pm_runtime_mark_last_busy(dev->dev); 1694 out: 1695 pm_runtime_put_autosuspend(dev->dev); 1696 return ret; 1697 } 1698 1699 static const struct dev_pm_ops amdgpu_pm_ops = { 1700 .prepare = amdgpu_pmops_prepare, 1701 .complete = amdgpu_pmops_complete, 1702 .suspend = amdgpu_pmops_suspend, 1703 .resume = amdgpu_pmops_resume, 1704 .freeze = amdgpu_pmops_freeze, 1705 .thaw = amdgpu_pmops_thaw, 1706 .poweroff = amdgpu_pmops_poweroff, 1707 .restore = amdgpu_pmops_restore, 1708 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1709 .runtime_resume = amdgpu_pmops_runtime_resume, 1710 .runtime_idle = amdgpu_pmops_runtime_idle, 1711 }; 1712 1713 static int amdgpu_flush(struct file *f, fl_owner_t id) 1714 { 1715 struct drm_file *file_priv = f->private_data; 1716 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1717 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1718 1719 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1720 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1721 1722 return timeout >= 0 ? 0 : timeout; 1723 } 1724 1725 static const struct file_operations amdgpu_driver_kms_fops = { 1726 .owner = THIS_MODULE, 1727 .open = drm_open, 1728 .flush = amdgpu_flush, 1729 .release = drm_release, 1730 .unlocked_ioctl = amdgpu_drm_ioctl, 1731 .mmap = drm_gem_mmap, 1732 .poll = drm_poll, 1733 .read = drm_read, 1734 #ifdef CONFIG_COMPAT 1735 .compat_ioctl = amdgpu_kms_compat_ioctl, 1736 #endif 1737 #ifdef CONFIG_PROC_FS 1738 .show_fdinfo = amdgpu_show_fdinfo 1739 #endif 1740 }; 1741 1742 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1743 { 1744 struct drm_file *file; 1745 1746 if (!filp) 1747 return -EINVAL; 1748 1749 if (filp->f_op != &amdgpu_driver_kms_fops) { 1750 return -EINVAL; 1751 } 1752 1753 file = filp->private_data; 1754 *fpriv = file->driver_priv; 1755 return 0; 1756 } 1757 1758 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1759 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1760 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1761 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1762 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1763 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1764 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1765 /* KMS */ 1766 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1767 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1768 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1769 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1770 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1771 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1772 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1773 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1774 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1775 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1776 }; 1777 1778 static const struct drm_driver amdgpu_kms_driver = { 1779 .driver_features = 1780 DRIVER_ATOMIC | 1781 DRIVER_GEM | 1782 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1783 DRIVER_SYNCOBJ_TIMELINE, 1784 .open = amdgpu_driver_open_kms, 1785 .postclose = amdgpu_driver_postclose_kms, 1786 .lastclose = amdgpu_driver_lastclose_kms, 1787 .irq_handler = amdgpu_irq_handler, 1788 .ioctls = amdgpu_ioctls_kms, 1789 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1790 .dumb_create = amdgpu_mode_dumb_create, 1791 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1792 .fops = &amdgpu_driver_kms_fops, 1793 .release = &amdgpu_driver_release_kms, 1794 1795 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1796 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1797 .gem_prime_import = amdgpu_gem_prime_import, 1798 .gem_prime_mmap = drm_gem_prime_mmap, 1799 1800 .name = DRIVER_NAME, 1801 .desc = DRIVER_DESC, 1802 .date = DRIVER_DATE, 1803 .major = KMS_DRIVER_MAJOR, 1804 .minor = KMS_DRIVER_MINOR, 1805 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1806 }; 1807 1808 static struct pci_error_handlers amdgpu_pci_err_handler = { 1809 .error_detected = amdgpu_pci_error_detected, 1810 .mmio_enabled = amdgpu_pci_mmio_enabled, 1811 .slot_reset = amdgpu_pci_slot_reset, 1812 .resume = amdgpu_pci_resume, 1813 }; 1814 1815 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1816 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1817 extern const struct attribute_group amdgpu_vbios_version_attr_group; 1818 1819 static const struct attribute_group *amdgpu_sysfs_groups[] = { 1820 &amdgpu_vram_mgr_attr_group, 1821 &amdgpu_gtt_mgr_attr_group, 1822 &amdgpu_vbios_version_attr_group, 1823 NULL, 1824 }; 1825 1826 1827 static struct pci_driver amdgpu_kms_pci_driver = { 1828 .name = DRIVER_NAME, 1829 .id_table = pciidlist, 1830 .probe = amdgpu_pci_probe, 1831 .remove = amdgpu_pci_remove, 1832 .shutdown = amdgpu_pci_shutdown, 1833 .driver.pm = &amdgpu_pm_ops, 1834 .err_handler = &amdgpu_pci_err_handler, 1835 .dev_groups = amdgpu_sysfs_groups, 1836 }; 1837 1838 static int __init amdgpu_init(void) 1839 { 1840 int r; 1841 1842 if (vgacon_text_force()) { 1843 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1844 return -EINVAL; 1845 } 1846 1847 r = amdgpu_sync_init(); 1848 if (r) 1849 goto error_sync; 1850 1851 r = amdgpu_fence_slab_init(); 1852 if (r) 1853 goto error_fence; 1854 1855 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1856 amdgpu_register_atpx_handler(); 1857 amdgpu_acpi_detect(); 1858 1859 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1860 amdgpu_amdkfd_init(); 1861 1862 /* let modprobe override vga console setting */ 1863 return pci_register_driver(&amdgpu_kms_pci_driver); 1864 1865 error_fence: 1866 amdgpu_sync_fini(); 1867 1868 error_sync: 1869 return r; 1870 } 1871 1872 static void __exit amdgpu_exit(void) 1873 { 1874 amdgpu_amdkfd_fini(); 1875 pci_unregister_driver(&amdgpu_kms_pci_driver); 1876 amdgpu_unregister_atpx_handler(); 1877 amdgpu_sync_fini(); 1878 amdgpu_fence_slab_fini(); 1879 mmu_notifier_synchronize(); 1880 } 1881 1882 module_init(amdgpu_init); 1883 module_exit(amdgpu_exit); 1884 1885 MODULE_AUTHOR(DRIVER_AUTHOR); 1886 MODULE_DESCRIPTION(DRIVER_DESC); 1887 MODULE_LICENSE("GPL and additional rights"); 1888