1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 105 * - 3.48.0 - Add IP discovery version info to HW INFO 106 * - 3.49.0 - Add gang submit into CS IOCTL 107 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 108 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 109 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 110 */ 111 #define KMS_DRIVER_MAJOR 3 112 #define KMS_DRIVER_MINOR 51 113 #define KMS_DRIVER_PATCHLEVEL 0 114 115 unsigned int amdgpu_vram_limit = UINT_MAX; 116 int amdgpu_vis_vram_limit; 117 int amdgpu_gart_size = -1; /* auto */ 118 int amdgpu_gtt_size = -1; /* auto */ 119 int amdgpu_moverate = -1; /* auto */ 120 int amdgpu_audio = -1; 121 int amdgpu_disp_priority; 122 int amdgpu_hw_i2c; 123 int amdgpu_pcie_gen2 = -1; 124 int amdgpu_msi = -1; 125 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 126 int amdgpu_dpm = -1; 127 int amdgpu_fw_load_type = -1; 128 int amdgpu_aspm = -1; 129 int amdgpu_runtime_pm = -1; 130 uint amdgpu_ip_block_mask = 0xffffffff; 131 int amdgpu_bapm = -1; 132 int amdgpu_deep_color; 133 int amdgpu_vm_size = -1; 134 int amdgpu_vm_fragment_size = -1; 135 int amdgpu_vm_block_size = -1; 136 int amdgpu_vm_fault_stop; 137 int amdgpu_vm_debug; 138 int amdgpu_vm_update_mode = -1; 139 int amdgpu_exp_hw_support; 140 int amdgpu_dc = -1; 141 int amdgpu_sched_jobs = 32; 142 int amdgpu_sched_hw_submission = 2; 143 uint amdgpu_pcie_gen_cap; 144 uint amdgpu_pcie_lane_cap; 145 u64 amdgpu_cg_mask = 0xffffffffffffffff; 146 uint amdgpu_pg_mask = 0xffffffff; 147 uint amdgpu_sdma_phase_quantum = 32; 148 char *amdgpu_disable_cu = NULL; 149 char *amdgpu_virtual_display = NULL; 150 151 /* 152 * OverDrive(bit 14) disabled by default 153 * GFX DCS(bit 19) disabled by default 154 */ 155 uint amdgpu_pp_feature_mask = 0xfff7bfff; 156 uint amdgpu_force_long_training; 157 int amdgpu_job_hang_limit; 158 int amdgpu_lbpw = -1; 159 int amdgpu_compute_multipipe = -1; 160 int amdgpu_gpu_recovery = -1; /* auto */ 161 int amdgpu_emu_mode; 162 uint amdgpu_smu_memory_pool_size; 163 int amdgpu_smu_pptable_id = -1; 164 /* 165 * FBC (bit 0) disabled by default 166 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 167 * - With this, for multiple monitors in sync(e.g. with the same model), 168 * mclk switching will be allowed. And the mclk will be not foced to the 169 * highest. That helps saving some idle power. 170 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 171 * PSR (bit 3) disabled by default 172 * EDP NO POWER SEQUENCING (bit 4) disabled by default 173 */ 174 uint amdgpu_dc_feature_mask = 2; 175 uint amdgpu_dc_debug_mask; 176 uint amdgpu_dc_visual_confirm; 177 int amdgpu_async_gfx_ring = 1; 178 int amdgpu_mcbp; 179 int amdgpu_discovery = -1; 180 int amdgpu_mes; 181 int amdgpu_mes_kiq; 182 int amdgpu_noretry = -1; 183 int amdgpu_force_asic_type = -1; 184 int amdgpu_tmz = -1; /* auto */ 185 uint amdgpu_freesync_vid_mode; 186 int amdgpu_reset_method = -1; /* auto */ 187 int amdgpu_num_kcq = -1; 188 int amdgpu_smartshift_bias; 189 int amdgpu_use_xgmi_p2p = 1; 190 int amdgpu_vcnfw_log; 191 int amdgpu_sg_display = -1; /* auto */ 192 193 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 194 195 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 196 "DRM_UT_CORE", 197 "DRM_UT_DRIVER", 198 "DRM_UT_KMS", 199 "DRM_UT_PRIME", 200 "DRM_UT_ATOMIC", 201 "DRM_UT_VBL", 202 "DRM_UT_STATE", 203 "DRM_UT_LEASE", 204 "DRM_UT_DP", 205 "DRM_UT_DRMRES"); 206 207 struct amdgpu_mgpu_info mgpu_info = { 208 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 209 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 210 mgpu_info.delayed_reset_work, 211 amdgpu_drv_delayed_reset_work_handler, 0), 212 }; 213 int amdgpu_ras_enable = -1; 214 uint amdgpu_ras_mask = 0xffffffff; 215 int amdgpu_bad_page_threshold = -1; 216 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 217 .timeout_fatal_disable = false, 218 .period = 0x0, /* default to 0x0 (timeout disable) */ 219 }; 220 221 /** 222 * DOC: vramlimit (int) 223 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 224 */ 225 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 226 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 227 228 /** 229 * DOC: vis_vramlimit (int) 230 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 231 */ 232 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 233 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 234 235 /** 236 * DOC: gartsize (uint) 237 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 238 * The default is -1 (The size depends on asic). 239 */ 240 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 241 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 242 243 /** 244 * DOC: gttsize (int) 245 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 246 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 247 */ 248 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 249 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 250 251 /** 252 * DOC: moverate (int) 253 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 254 */ 255 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 256 module_param_named(moverate, amdgpu_moverate, int, 0600); 257 258 /** 259 * DOC: audio (int) 260 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 261 */ 262 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 263 module_param_named(audio, amdgpu_audio, int, 0444); 264 265 /** 266 * DOC: disp_priority (int) 267 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 268 */ 269 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 270 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 271 272 /** 273 * DOC: hw_i2c (int) 274 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 275 */ 276 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 277 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 278 279 /** 280 * DOC: pcie_gen2 (int) 281 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 282 */ 283 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 284 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 285 286 /** 287 * DOC: msi (int) 288 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 289 */ 290 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 291 module_param_named(msi, amdgpu_msi, int, 0444); 292 293 /** 294 * DOC: lockup_timeout (string) 295 * Set GPU scheduler timeout value in ms. 296 * 297 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 298 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 299 * to the default timeout. 300 * 301 * - With one value specified, the setting will apply to all non-compute jobs. 302 * - With multiple values specified, the first one will be for GFX. 303 * The second one is for Compute. The third and fourth ones are 304 * for SDMA and Video. 305 * 306 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 307 * jobs is 10000. The timeout for compute is 60000. 308 */ 309 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 310 "for passthrough or sriov, 10000 for all jobs." 311 " 0: keep default value. negative: infinity timeout), " 312 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 313 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 314 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 315 316 /** 317 * DOC: dpm (int) 318 * Override for dynamic power management setting 319 * (0 = disable, 1 = enable) 320 * The default is -1 (auto). 321 */ 322 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 323 module_param_named(dpm, amdgpu_dpm, int, 0444); 324 325 /** 326 * DOC: fw_load_type (int) 327 * Set different firmware loading type for debugging, if supported. 328 * Set to 0 to force direct loading if supported by the ASIC. Set 329 * to -1 to select the default loading mode for the ASIC, as defined 330 * by the driver. The default is -1 (auto). 331 */ 332 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 333 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 334 335 /** 336 * DOC: aspm (int) 337 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 338 */ 339 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 340 module_param_named(aspm, amdgpu_aspm, int, 0444); 341 342 /** 343 * DOC: runpm (int) 344 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 345 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 346 * Setting the value to 0 disables this functionality. 347 */ 348 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 349 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 350 351 /** 352 * DOC: ip_block_mask (uint) 353 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 354 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 355 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 356 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 357 */ 358 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 359 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 360 361 /** 362 * DOC: bapm (int) 363 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 364 * The default -1 (auto, enabled) 365 */ 366 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 367 module_param_named(bapm, amdgpu_bapm, int, 0444); 368 369 /** 370 * DOC: deep_color (int) 371 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 372 */ 373 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 374 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 375 376 /** 377 * DOC: vm_size (int) 378 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 379 */ 380 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 381 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 382 383 /** 384 * DOC: vm_fragment_size (int) 385 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 386 */ 387 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 388 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 389 390 /** 391 * DOC: vm_block_size (int) 392 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 393 */ 394 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 395 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 396 397 /** 398 * DOC: vm_fault_stop (int) 399 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 400 */ 401 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 402 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 403 404 /** 405 * DOC: vm_debug (int) 406 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 407 */ 408 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 409 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 410 411 /** 412 * DOC: vm_update_mode (int) 413 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 414 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 415 */ 416 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 417 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 418 419 /** 420 * DOC: exp_hw_support (int) 421 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 422 */ 423 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 424 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 425 426 /** 427 * DOC: dc (int) 428 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 429 */ 430 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 431 module_param_named(dc, amdgpu_dc, int, 0444); 432 433 /** 434 * DOC: sched_jobs (int) 435 * Override the max number of jobs supported in the sw queue. The default is 32. 436 */ 437 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 438 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 439 440 /** 441 * DOC: sched_hw_submission (int) 442 * Override the max number of HW submissions. The default is 2. 443 */ 444 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 445 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 446 447 /** 448 * DOC: ppfeaturemask (hexint) 449 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 450 * The default is the current set of stable power features. 451 */ 452 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 453 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 454 455 /** 456 * DOC: forcelongtraining (uint) 457 * Force long memory training in resume. 458 * The default is zero, indicates short training in resume. 459 */ 460 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 461 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 462 463 /** 464 * DOC: pcie_gen_cap (uint) 465 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 466 * The default is 0 (automatic for each asic). 467 */ 468 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 469 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 470 471 /** 472 * DOC: pcie_lane_cap (uint) 473 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 474 * The default is 0 (automatic for each asic). 475 */ 476 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 477 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 478 479 /** 480 * DOC: cg_mask (ullong) 481 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 482 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 483 */ 484 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 485 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 486 487 /** 488 * DOC: pg_mask (uint) 489 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 490 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 491 */ 492 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 493 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 494 495 /** 496 * DOC: sdma_phase_quantum (uint) 497 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 498 */ 499 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 500 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 501 502 /** 503 * DOC: disable_cu (charp) 504 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 505 */ 506 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 507 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 508 509 /** 510 * DOC: virtual_display (charp) 511 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 512 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 513 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 514 * device at 26:00.0. The default is NULL. 515 */ 516 MODULE_PARM_DESC(virtual_display, 517 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 518 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 519 520 /** 521 * DOC: job_hang_limit (int) 522 * Set how much time allow a job hang and not drop it. The default is 0. 523 */ 524 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 525 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 526 527 /** 528 * DOC: lbpw (int) 529 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 530 */ 531 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 532 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 533 534 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 535 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 536 537 /** 538 * DOC: gpu_recovery (int) 539 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 540 */ 541 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 542 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 543 544 /** 545 * DOC: emu_mode (int) 546 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 547 */ 548 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 549 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 550 551 /** 552 * DOC: ras_enable (int) 553 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 554 */ 555 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 556 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 557 558 /** 559 * DOC: ras_mask (uint) 560 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 561 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 562 */ 563 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 564 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 565 566 /** 567 * DOC: timeout_fatal_disable (bool) 568 * Disable Watchdog timeout fatal error event 569 */ 570 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 571 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 572 573 /** 574 * DOC: timeout_period (uint) 575 * Modify the watchdog timeout max_cycles as (1 << period) 576 */ 577 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 578 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 579 580 /** 581 * DOC: si_support (int) 582 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 583 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 584 * otherwise using amdgpu driver. 585 */ 586 #ifdef CONFIG_DRM_AMDGPU_SI 587 588 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 589 int amdgpu_si_support = 0; 590 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 591 #else 592 int amdgpu_si_support = 1; 593 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 594 #endif 595 596 module_param_named(si_support, amdgpu_si_support, int, 0444); 597 #endif 598 599 /** 600 * DOC: cik_support (int) 601 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 602 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 603 * otherwise using amdgpu driver. 604 */ 605 #ifdef CONFIG_DRM_AMDGPU_CIK 606 607 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 608 int amdgpu_cik_support = 0; 609 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 610 #else 611 int amdgpu_cik_support = 1; 612 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 613 #endif 614 615 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 616 #endif 617 618 /** 619 * DOC: smu_memory_pool_size (uint) 620 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 621 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 622 */ 623 MODULE_PARM_DESC(smu_memory_pool_size, 624 "reserve gtt for smu debug usage, 0 = disable," 625 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 626 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 627 628 /** 629 * DOC: async_gfx_ring (int) 630 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 631 */ 632 MODULE_PARM_DESC(async_gfx_ring, 633 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 634 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 635 636 /** 637 * DOC: mcbp (int) 638 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 639 */ 640 MODULE_PARM_DESC(mcbp, 641 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 642 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 643 644 /** 645 * DOC: discovery (int) 646 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 647 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 648 */ 649 MODULE_PARM_DESC(discovery, 650 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 651 module_param_named(discovery, amdgpu_discovery, int, 0444); 652 653 /** 654 * DOC: mes (int) 655 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 656 * (0 = disabled (default), 1 = enabled) 657 */ 658 MODULE_PARM_DESC(mes, 659 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 660 module_param_named(mes, amdgpu_mes, int, 0444); 661 662 /** 663 * DOC: mes_kiq (int) 664 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 665 * (0 = disabled (default), 1 = enabled) 666 */ 667 MODULE_PARM_DESC(mes_kiq, 668 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 669 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 670 671 /** 672 * DOC: noretry (int) 673 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 674 * do not support per-process XNACK this also disables retry page faults. 675 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 676 */ 677 MODULE_PARM_DESC(noretry, 678 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 679 module_param_named(noretry, amdgpu_noretry, int, 0644); 680 681 /** 682 * DOC: force_asic_type (int) 683 * A non negative value used to specify the asic type for all supported GPUs. 684 */ 685 MODULE_PARM_DESC(force_asic_type, 686 "A non negative value used to specify the asic type for all supported GPUs"); 687 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 688 689 /** 690 * DOC: use_xgmi_p2p (int) 691 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 692 */ 693 MODULE_PARM_DESC(use_xgmi_p2p, 694 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 695 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 696 697 698 #ifdef CONFIG_HSA_AMD 699 /** 700 * DOC: sched_policy (int) 701 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 702 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 703 * assigns queues to HQDs. 704 */ 705 int sched_policy = KFD_SCHED_POLICY_HWS; 706 module_param(sched_policy, int, 0444); 707 MODULE_PARM_DESC(sched_policy, 708 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 709 710 /** 711 * DOC: hws_max_conc_proc (int) 712 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 713 * number of VMIDs assigned to the HWS, which is also the default. 714 */ 715 int hws_max_conc_proc = -1; 716 module_param(hws_max_conc_proc, int, 0444); 717 MODULE_PARM_DESC(hws_max_conc_proc, 718 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 719 720 /** 721 * DOC: cwsr_enable (int) 722 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 723 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 724 * disables it. 725 */ 726 int cwsr_enable = 1; 727 module_param(cwsr_enable, int, 0444); 728 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 729 730 /** 731 * DOC: max_num_of_queues_per_device (int) 732 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 733 * is 4096. 734 */ 735 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 736 module_param(max_num_of_queues_per_device, int, 0444); 737 MODULE_PARM_DESC(max_num_of_queues_per_device, 738 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 739 740 /** 741 * DOC: send_sigterm (int) 742 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 743 * but just print errors on dmesg. Setting 1 enables sending sigterm. 744 */ 745 int send_sigterm; 746 module_param(send_sigterm, int, 0444); 747 MODULE_PARM_DESC(send_sigterm, 748 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 749 750 /** 751 * DOC: debug_largebar (int) 752 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 753 * system. This limits the VRAM size reported to ROCm applications to the visible 754 * size, usually 256MB. 755 * Default value is 0, diabled. 756 */ 757 int debug_largebar; 758 module_param(debug_largebar, int, 0444); 759 MODULE_PARM_DESC(debug_largebar, 760 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 761 762 /** 763 * DOC: ignore_crat (int) 764 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 765 * table to get information about AMD APUs. This option can serve as a workaround on 766 * systems with a broken CRAT table. 767 * 768 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 769 * whether use CRAT) 770 */ 771 int ignore_crat; 772 module_param(ignore_crat, int, 0444); 773 MODULE_PARM_DESC(ignore_crat, 774 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 775 776 /** 777 * DOC: halt_if_hws_hang (int) 778 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 779 * Setting 1 enables halt on hang. 780 */ 781 int halt_if_hws_hang; 782 module_param(halt_if_hws_hang, int, 0644); 783 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 784 785 /** 786 * DOC: hws_gws_support(bool) 787 * Assume that HWS supports GWS barriers regardless of what firmware version 788 * check says. Default value: false (rely on MEC2 firmware version check). 789 */ 790 bool hws_gws_support; 791 module_param(hws_gws_support, bool, 0444); 792 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 793 794 /** 795 * DOC: queue_preemption_timeout_ms (int) 796 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 797 */ 798 int queue_preemption_timeout_ms = 9000; 799 module_param(queue_preemption_timeout_ms, int, 0644); 800 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 801 802 /** 803 * DOC: debug_evictions(bool) 804 * Enable extra debug messages to help determine the cause of evictions 805 */ 806 bool debug_evictions; 807 module_param(debug_evictions, bool, 0644); 808 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 809 810 /** 811 * DOC: no_system_mem_limit(bool) 812 * Disable system memory limit, to support multiple process shared memory 813 */ 814 bool no_system_mem_limit; 815 module_param(no_system_mem_limit, bool, 0644); 816 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 817 818 /** 819 * DOC: no_queue_eviction_on_vm_fault (int) 820 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 821 */ 822 int amdgpu_no_queue_eviction_on_vm_fault = 0; 823 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 824 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 825 #endif 826 827 /** 828 * DOC: pcie_p2p (bool) 829 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 830 */ 831 #ifdef CONFIG_HSA_AMD_P2P 832 bool pcie_p2p = true; 833 module_param(pcie_p2p, bool, 0444); 834 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 835 #endif 836 837 /** 838 * DOC: dcfeaturemask (uint) 839 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 840 * The default is the current set of stable display features. 841 */ 842 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 843 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 844 845 /** 846 * DOC: dcdebugmask (uint) 847 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 848 */ 849 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 850 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 851 852 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 853 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 854 855 /** 856 * DOC: abmlevel (uint) 857 * Override the default ABM (Adaptive Backlight Management) level used for DC 858 * enabled hardware. Requires DMCU to be supported and loaded. 859 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 860 * default. Values 1-4 control the maximum allowable brightness reduction via 861 * the ABM algorithm, with 1 being the least reduction and 4 being the most 862 * reduction. 863 * 864 * Defaults to 0, or disabled. Userspace can still override this level later 865 * after boot. 866 */ 867 uint amdgpu_dm_abm_level; 868 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 869 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 870 871 int amdgpu_backlight = -1; 872 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 873 module_param_named(backlight, amdgpu_backlight, bint, 0444); 874 875 /** 876 * DOC: tmz (int) 877 * Trusted Memory Zone (TMZ) is a method to protect data being written 878 * to or read from memory. 879 * 880 * The default value: 0 (off). TODO: change to auto till it is completed. 881 */ 882 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 883 module_param_named(tmz, amdgpu_tmz, int, 0444); 884 885 /** 886 * DOC: freesync_video (uint) 887 * Enable the optimization to adjust front porch timing to achieve seamless 888 * mode change experience when setting a freesync supported mode for which full 889 * modeset is not needed. 890 * 891 * The Display Core will add a set of modes derived from the base FreeSync 892 * video mode into the corresponding connector's mode list based on commonly 893 * used refresh rates and VRR range of the connected display, when users enable 894 * this feature. From the userspace perspective, they can see a seamless mode 895 * change experience when the change between different refresh rates under the 896 * same resolution. Additionally, userspace applications such as Video playback 897 * can read this modeset list and change the refresh rate based on the video 898 * frame rate. Finally, the userspace can also derive an appropriate mode for a 899 * particular refresh rate based on the FreeSync Mode and add it to the 900 * connector's mode list. 901 * 902 * Note: This is an experimental feature. 903 * 904 * The default value: 0 (off). 905 */ 906 MODULE_PARM_DESC( 907 freesync_video, 908 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 909 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 910 911 /** 912 * DOC: reset_method (int) 913 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 914 */ 915 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 916 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 917 918 /** 919 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 920 * threshold value of faulty pages detected by RAS ECC, which may 921 * result in the GPU entering bad status when the number of total 922 * faulty pages by ECC exceeds the threshold value. 923 */ 924 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 925 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 926 927 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 928 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 929 930 /** 931 * DOC: vcnfw_log (int) 932 * Enable vcnfw log output for debugging, the default is disabled. 933 */ 934 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 935 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 936 937 /** 938 * DOC: sg_display (int) 939 * Disable S/G (scatter/gather) display (i.e., display from system memory). 940 * This option is only relevant on APUs. Set this option to 0 to disable 941 * S/G display if you experience flickering or other issues under memory 942 * pressure and report the issue. 943 */ 944 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 945 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 946 947 /** 948 * DOC: smu_pptable_id (int) 949 * Used to override pptable id. id = 0 use VBIOS pptable. 950 * id > 0 use the soft pptable with specicfied id. 951 */ 952 MODULE_PARM_DESC(smu_pptable_id, 953 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 954 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 955 956 /* These devices are not supported by amdgpu. 957 * They are supported by the mach64, r128, radeon drivers 958 */ 959 static const u16 amdgpu_unsupported_pciidlist[] = { 960 /* mach64 */ 961 0x4354, 962 0x4358, 963 0x4554, 964 0x4742, 965 0x4744, 966 0x4749, 967 0x474C, 968 0x474D, 969 0x474E, 970 0x474F, 971 0x4750, 972 0x4751, 973 0x4752, 974 0x4753, 975 0x4754, 976 0x4755, 977 0x4756, 978 0x4757, 979 0x4758, 980 0x4759, 981 0x475A, 982 0x4C42, 983 0x4C44, 984 0x4C47, 985 0x4C49, 986 0x4C4D, 987 0x4C4E, 988 0x4C50, 989 0x4C51, 990 0x4C52, 991 0x4C53, 992 0x5654, 993 0x5655, 994 0x5656, 995 /* r128 */ 996 0x4c45, 997 0x4c46, 998 0x4d46, 999 0x4d4c, 1000 0x5041, 1001 0x5042, 1002 0x5043, 1003 0x5044, 1004 0x5045, 1005 0x5046, 1006 0x5047, 1007 0x5048, 1008 0x5049, 1009 0x504A, 1010 0x504B, 1011 0x504C, 1012 0x504D, 1013 0x504E, 1014 0x504F, 1015 0x5050, 1016 0x5051, 1017 0x5052, 1018 0x5053, 1019 0x5054, 1020 0x5055, 1021 0x5056, 1022 0x5057, 1023 0x5058, 1024 0x5245, 1025 0x5246, 1026 0x5247, 1027 0x524b, 1028 0x524c, 1029 0x534d, 1030 0x5446, 1031 0x544C, 1032 0x5452, 1033 /* radeon */ 1034 0x3150, 1035 0x3151, 1036 0x3152, 1037 0x3154, 1038 0x3155, 1039 0x3E50, 1040 0x3E54, 1041 0x4136, 1042 0x4137, 1043 0x4144, 1044 0x4145, 1045 0x4146, 1046 0x4147, 1047 0x4148, 1048 0x4149, 1049 0x414A, 1050 0x414B, 1051 0x4150, 1052 0x4151, 1053 0x4152, 1054 0x4153, 1055 0x4154, 1056 0x4155, 1057 0x4156, 1058 0x4237, 1059 0x4242, 1060 0x4336, 1061 0x4337, 1062 0x4437, 1063 0x4966, 1064 0x4967, 1065 0x4A48, 1066 0x4A49, 1067 0x4A4A, 1068 0x4A4B, 1069 0x4A4C, 1070 0x4A4D, 1071 0x4A4E, 1072 0x4A4F, 1073 0x4A50, 1074 0x4A54, 1075 0x4B48, 1076 0x4B49, 1077 0x4B4A, 1078 0x4B4B, 1079 0x4B4C, 1080 0x4C57, 1081 0x4C58, 1082 0x4C59, 1083 0x4C5A, 1084 0x4C64, 1085 0x4C66, 1086 0x4C67, 1087 0x4E44, 1088 0x4E45, 1089 0x4E46, 1090 0x4E47, 1091 0x4E48, 1092 0x4E49, 1093 0x4E4A, 1094 0x4E4B, 1095 0x4E50, 1096 0x4E51, 1097 0x4E52, 1098 0x4E53, 1099 0x4E54, 1100 0x4E56, 1101 0x5144, 1102 0x5145, 1103 0x5146, 1104 0x5147, 1105 0x5148, 1106 0x514C, 1107 0x514D, 1108 0x5157, 1109 0x5158, 1110 0x5159, 1111 0x515A, 1112 0x515E, 1113 0x5460, 1114 0x5462, 1115 0x5464, 1116 0x5548, 1117 0x5549, 1118 0x554A, 1119 0x554B, 1120 0x554C, 1121 0x554D, 1122 0x554E, 1123 0x554F, 1124 0x5550, 1125 0x5551, 1126 0x5552, 1127 0x5554, 1128 0x564A, 1129 0x564B, 1130 0x564F, 1131 0x5652, 1132 0x5653, 1133 0x5657, 1134 0x5834, 1135 0x5835, 1136 0x5954, 1137 0x5955, 1138 0x5974, 1139 0x5975, 1140 0x5960, 1141 0x5961, 1142 0x5962, 1143 0x5964, 1144 0x5965, 1145 0x5969, 1146 0x5a41, 1147 0x5a42, 1148 0x5a61, 1149 0x5a62, 1150 0x5b60, 1151 0x5b62, 1152 0x5b63, 1153 0x5b64, 1154 0x5b65, 1155 0x5c61, 1156 0x5c63, 1157 0x5d48, 1158 0x5d49, 1159 0x5d4a, 1160 0x5d4c, 1161 0x5d4d, 1162 0x5d4e, 1163 0x5d4f, 1164 0x5d50, 1165 0x5d52, 1166 0x5d57, 1167 0x5e48, 1168 0x5e4a, 1169 0x5e4b, 1170 0x5e4c, 1171 0x5e4d, 1172 0x5e4f, 1173 0x6700, 1174 0x6701, 1175 0x6702, 1176 0x6703, 1177 0x6704, 1178 0x6705, 1179 0x6706, 1180 0x6707, 1181 0x6708, 1182 0x6709, 1183 0x6718, 1184 0x6719, 1185 0x671c, 1186 0x671d, 1187 0x671f, 1188 0x6720, 1189 0x6721, 1190 0x6722, 1191 0x6723, 1192 0x6724, 1193 0x6725, 1194 0x6726, 1195 0x6727, 1196 0x6728, 1197 0x6729, 1198 0x6738, 1199 0x6739, 1200 0x673e, 1201 0x6740, 1202 0x6741, 1203 0x6742, 1204 0x6743, 1205 0x6744, 1206 0x6745, 1207 0x6746, 1208 0x6747, 1209 0x6748, 1210 0x6749, 1211 0x674A, 1212 0x6750, 1213 0x6751, 1214 0x6758, 1215 0x6759, 1216 0x675B, 1217 0x675D, 1218 0x675F, 1219 0x6760, 1220 0x6761, 1221 0x6762, 1222 0x6763, 1223 0x6764, 1224 0x6765, 1225 0x6766, 1226 0x6767, 1227 0x6768, 1228 0x6770, 1229 0x6771, 1230 0x6772, 1231 0x6778, 1232 0x6779, 1233 0x677B, 1234 0x6840, 1235 0x6841, 1236 0x6842, 1237 0x6843, 1238 0x6849, 1239 0x684C, 1240 0x6850, 1241 0x6858, 1242 0x6859, 1243 0x6880, 1244 0x6888, 1245 0x6889, 1246 0x688A, 1247 0x688C, 1248 0x688D, 1249 0x6898, 1250 0x6899, 1251 0x689b, 1252 0x689c, 1253 0x689d, 1254 0x689e, 1255 0x68a0, 1256 0x68a1, 1257 0x68a8, 1258 0x68a9, 1259 0x68b0, 1260 0x68b8, 1261 0x68b9, 1262 0x68ba, 1263 0x68be, 1264 0x68bf, 1265 0x68c0, 1266 0x68c1, 1267 0x68c7, 1268 0x68c8, 1269 0x68c9, 1270 0x68d8, 1271 0x68d9, 1272 0x68da, 1273 0x68de, 1274 0x68e0, 1275 0x68e1, 1276 0x68e4, 1277 0x68e5, 1278 0x68e8, 1279 0x68e9, 1280 0x68f1, 1281 0x68f2, 1282 0x68f8, 1283 0x68f9, 1284 0x68fa, 1285 0x68fe, 1286 0x7100, 1287 0x7101, 1288 0x7102, 1289 0x7103, 1290 0x7104, 1291 0x7105, 1292 0x7106, 1293 0x7108, 1294 0x7109, 1295 0x710A, 1296 0x710B, 1297 0x710C, 1298 0x710E, 1299 0x710F, 1300 0x7140, 1301 0x7141, 1302 0x7142, 1303 0x7143, 1304 0x7144, 1305 0x7145, 1306 0x7146, 1307 0x7147, 1308 0x7149, 1309 0x714A, 1310 0x714B, 1311 0x714C, 1312 0x714D, 1313 0x714E, 1314 0x714F, 1315 0x7151, 1316 0x7152, 1317 0x7153, 1318 0x715E, 1319 0x715F, 1320 0x7180, 1321 0x7181, 1322 0x7183, 1323 0x7186, 1324 0x7187, 1325 0x7188, 1326 0x718A, 1327 0x718B, 1328 0x718C, 1329 0x718D, 1330 0x718F, 1331 0x7193, 1332 0x7196, 1333 0x719B, 1334 0x719F, 1335 0x71C0, 1336 0x71C1, 1337 0x71C2, 1338 0x71C3, 1339 0x71C4, 1340 0x71C5, 1341 0x71C6, 1342 0x71C7, 1343 0x71CD, 1344 0x71CE, 1345 0x71D2, 1346 0x71D4, 1347 0x71D5, 1348 0x71D6, 1349 0x71DA, 1350 0x71DE, 1351 0x7200, 1352 0x7210, 1353 0x7211, 1354 0x7240, 1355 0x7243, 1356 0x7244, 1357 0x7245, 1358 0x7246, 1359 0x7247, 1360 0x7248, 1361 0x7249, 1362 0x724A, 1363 0x724B, 1364 0x724C, 1365 0x724D, 1366 0x724E, 1367 0x724F, 1368 0x7280, 1369 0x7281, 1370 0x7283, 1371 0x7284, 1372 0x7287, 1373 0x7288, 1374 0x7289, 1375 0x728B, 1376 0x728C, 1377 0x7290, 1378 0x7291, 1379 0x7293, 1380 0x7297, 1381 0x7834, 1382 0x7835, 1383 0x791e, 1384 0x791f, 1385 0x793f, 1386 0x7941, 1387 0x7942, 1388 0x796c, 1389 0x796d, 1390 0x796e, 1391 0x796f, 1392 0x9400, 1393 0x9401, 1394 0x9402, 1395 0x9403, 1396 0x9405, 1397 0x940A, 1398 0x940B, 1399 0x940F, 1400 0x94A0, 1401 0x94A1, 1402 0x94A3, 1403 0x94B1, 1404 0x94B3, 1405 0x94B4, 1406 0x94B5, 1407 0x94B9, 1408 0x9440, 1409 0x9441, 1410 0x9442, 1411 0x9443, 1412 0x9444, 1413 0x9446, 1414 0x944A, 1415 0x944B, 1416 0x944C, 1417 0x944E, 1418 0x9450, 1419 0x9452, 1420 0x9456, 1421 0x945A, 1422 0x945B, 1423 0x945E, 1424 0x9460, 1425 0x9462, 1426 0x946A, 1427 0x946B, 1428 0x947A, 1429 0x947B, 1430 0x9480, 1431 0x9487, 1432 0x9488, 1433 0x9489, 1434 0x948A, 1435 0x948F, 1436 0x9490, 1437 0x9491, 1438 0x9495, 1439 0x9498, 1440 0x949C, 1441 0x949E, 1442 0x949F, 1443 0x94C0, 1444 0x94C1, 1445 0x94C3, 1446 0x94C4, 1447 0x94C5, 1448 0x94C6, 1449 0x94C7, 1450 0x94C8, 1451 0x94C9, 1452 0x94CB, 1453 0x94CC, 1454 0x94CD, 1455 0x9500, 1456 0x9501, 1457 0x9504, 1458 0x9505, 1459 0x9506, 1460 0x9507, 1461 0x9508, 1462 0x9509, 1463 0x950F, 1464 0x9511, 1465 0x9515, 1466 0x9517, 1467 0x9519, 1468 0x9540, 1469 0x9541, 1470 0x9542, 1471 0x954E, 1472 0x954F, 1473 0x9552, 1474 0x9553, 1475 0x9555, 1476 0x9557, 1477 0x955f, 1478 0x9580, 1479 0x9581, 1480 0x9583, 1481 0x9586, 1482 0x9587, 1483 0x9588, 1484 0x9589, 1485 0x958A, 1486 0x958B, 1487 0x958C, 1488 0x958D, 1489 0x958E, 1490 0x958F, 1491 0x9590, 1492 0x9591, 1493 0x9593, 1494 0x9595, 1495 0x9596, 1496 0x9597, 1497 0x9598, 1498 0x9599, 1499 0x959B, 1500 0x95C0, 1501 0x95C2, 1502 0x95C4, 1503 0x95C5, 1504 0x95C6, 1505 0x95C7, 1506 0x95C9, 1507 0x95CC, 1508 0x95CD, 1509 0x95CE, 1510 0x95CF, 1511 0x9610, 1512 0x9611, 1513 0x9612, 1514 0x9613, 1515 0x9614, 1516 0x9615, 1517 0x9616, 1518 0x9640, 1519 0x9641, 1520 0x9642, 1521 0x9643, 1522 0x9644, 1523 0x9645, 1524 0x9647, 1525 0x9648, 1526 0x9649, 1527 0x964a, 1528 0x964b, 1529 0x964c, 1530 0x964e, 1531 0x964f, 1532 0x9710, 1533 0x9711, 1534 0x9712, 1535 0x9713, 1536 0x9714, 1537 0x9715, 1538 0x9802, 1539 0x9803, 1540 0x9804, 1541 0x9805, 1542 0x9806, 1543 0x9807, 1544 0x9808, 1545 0x9809, 1546 0x980A, 1547 0x9900, 1548 0x9901, 1549 0x9903, 1550 0x9904, 1551 0x9905, 1552 0x9906, 1553 0x9907, 1554 0x9908, 1555 0x9909, 1556 0x990A, 1557 0x990B, 1558 0x990C, 1559 0x990D, 1560 0x990E, 1561 0x990F, 1562 0x9910, 1563 0x9913, 1564 0x9917, 1565 0x9918, 1566 0x9919, 1567 0x9990, 1568 0x9991, 1569 0x9992, 1570 0x9993, 1571 0x9994, 1572 0x9995, 1573 0x9996, 1574 0x9997, 1575 0x9998, 1576 0x9999, 1577 0x999A, 1578 0x999B, 1579 0x999C, 1580 0x999D, 1581 0x99A0, 1582 0x99A2, 1583 0x99A4, 1584 /* radeon secondary ids */ 1585 0x3171, 1586 0x3e70, 1587 0x4164, 1588 0x4165, 1589 0x4166, 1590 0x4168, 1591 0x4170, 1592 0x4171, 1593 0x4172, 1594 0x4173, 1595 0x496e, 1596 0x4a69, 1597 0x4a6a, 1598 0x4a6b, 1599 0x4a70, 1600 0x4a74, 1601 0x4b69, 1602 0x4b6b, 1603 0x4b6c, 1604 0x4c6e, 1605 0x4e64, 1606 0x4e65, 1607 0x4e66, 1608 0x4e67, 1609 0x4e68, 1610 0x4e69, 1611 0x4e6a, 1612 0x4e71, 1613 0x4f73, 1614 0x5569, 1615 0x556b, 1616 0x556d, 1617 0x556f, 1618 0x5571, 1619 0x5854, 1620 0x5874, 1621 0x5940, 1622 0x5941, 1623 0x5b72, 1624 0x5b73, 1625 0x5b74, 1626 0x5b75, 1627 0x5d44, 1628 0x5d45, 1629 0x5d6d, 1630 0x5d6f, 1631 0x5d72, 1632 0x5d77, 1633 0x5e6b, 1634 0x5e6d, 1635 0x7120, 1636 0x7124, 1637 0x7129, 1638 0x712e, 1639 0x712f, 1640 0x7162, 1641 0x7163, 1642 0x7166, 1643 0x7167, 1644 0x7172, 1645 0x7173, 1646 0x71a0, 1647 0x71a1, 1648 0x71a3, 1649 0x71a7, 1650 0x71bb, 1651 0x71e0, 1652 0x71e1, 1653 0x71e2, 1654 0x71e6, 1655 0x71e7, 1656 0x71f2, 1657 0x7269, 1658 0x726b, 1659 0x726e, 1660 0x72a0, 1661 0x72a8, 1662 0x72b1, 1663 0x72b3, 1664 0x793f, 1665 }; 1666 1667 static const struct pci_device_id pciidlist[] = { 1668 #ifdef CONFIG_DRM_AMDGPU_SI 1669 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1670 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1671 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1672 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1673 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1674 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1675 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1676 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1677 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1678 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1679 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1680 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1681 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1682 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1683 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1684 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1685 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1686 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1687 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1688 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1689 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1690 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1691 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1692 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1693 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1694 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1700 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1701 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1703 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1704 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1705 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1706 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1708 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1710 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1711 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1717 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1718 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1719 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1720 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1721 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1722 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1723 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1724 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1725 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1729 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1730 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1731 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1732 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1733 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1734 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1735 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1737 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1738 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1739 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1740 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1741 #endif 1742 #ifdef CONFIG_DRM_AMDGPU_CIK 1743 /* Kaveri */ 1744 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1745 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1746 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1747 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1748 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1752 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1753 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1754 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1755 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1756 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1757 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1758 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1759 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1760 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1761 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1763 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1764 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1765 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1766 /* Bonaire */ 1767 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1768 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1769 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1770 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1771 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1772 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1773 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1774 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1775 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1776 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1777 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1778 /* Hawaii */ 1779 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1780 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1781 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1782 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1783 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1784 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1785 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1786 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1787 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1788 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1789 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1790 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1791 /* Kabini */ 1792 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1793 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1794 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1795 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1796 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1797 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1798 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1800 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1801 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1802 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1803 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1804 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1805 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1806 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1807 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1808 /* mullins */ 1809 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1814 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1815 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1816 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1817 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1818 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1822 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1823 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1824 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1825 #endif 1826 /* topaz */ 1827 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1828 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1829 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1830 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1831 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1832 /* tonga */ 1833 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1834 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1835 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1836 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1837 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1838 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1839 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1840 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1841 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1842 /* fiji */ 1843 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1844 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1845 /* carrizo */ 1846 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1847 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1848 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1849 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1850 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1851 /* stoney */ 1852 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1853 /* Polaris11 */ 1854 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1855 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1856 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1857 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1858 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1859 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1860 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1861 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1862 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1863 /* Polaris10 */ 1864 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1865 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1866 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1867 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1868 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1869 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1870 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1871 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1872 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1873 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1874 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1875 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1876 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1877 /* Polaris12 */ 1878 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1879 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1880 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1881 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1882 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1883 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1884 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1885 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1886 /* VEGAM */ 1887 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1888 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1889 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1890 /* Vega 10 */ 1891 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1893 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1894 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1895 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1896 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1897 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1898 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1899 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1900 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1901 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1902 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1903 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1904 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1905 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1906 /* Vega 12 */ 1907 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1908 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1909 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1910 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1911 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1912 /* Vega 20 */ 1913 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1914 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1915 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1916 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1917 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1918 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1919 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1920 /* Raven */ 1921 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1922 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1923 /* Arcturus */ 1924 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1925 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1926 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1927 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1928 /* Navi10 */ 1929 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1930 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1931 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1932 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1933 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1934 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1935 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1936 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1937 /* Navi14 */ 1938 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1939 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1940 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1941 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1942 1943 /* Renoir */ 1944 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1945 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1946 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1947 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1948 1949 /* Navi12 */ 1950 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1951 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1952 1953 /* Sienna_Cichlid */ 1954 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1955 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1956 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1957 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1958 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1959 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1960 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1961 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1962 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1963 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1964 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1965 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1966 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1967 1968 /* Yellow Carp */ 1969 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1970 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1971 1972 /* Navy_Flounder */ 1973 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1974 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1975 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1976 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1977 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1978 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1979 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1980 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1981 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1982 1983 /* DIMGREY_CAVEFISH */ 1984 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1985 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1986 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1987 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1988 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1989 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1990 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1991 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1992 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1993 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1994 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1995 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1996 1997 /* Aldebaran */ 1998 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1999 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2000 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2001 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2002 2003 /* CYAN_SKILLFISH */ 2004 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2005 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2006 2007 /* BEIGE_GOBY */ 2008 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2009 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2010 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2011 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2012 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2013 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2014 2015 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2016 .class = PCI_CLASS_DISPLAY_VGA << 8, 2017 .class_mask = 0xffffff, 2018 .driver_data = CHIP_IP_DISCOVERY }, 2019 2020 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2021 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2022 .class_mask = 0xffffff, 2023 .driver_data = CHIP_IP_DISCOVERY }, 2024 2025 {0, 0, 0} 2026 }; 2027 2028 MODULE_DEVICE_TABLE(pci, pciidlist); 2029 2030 static const struct drm_driver amdgpu_kms_driver; 2031 2032 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2033 { 2034 struct pci_dev *p = NULL; 2035 int i; 2036 2037 /* 0 - GPU 2038 * 1 - audio 2039 * 2 - USB 2040 * 3 - UCSI 2041 */ 2042 for (i = 1; i < 4; i++) { 2043 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2044 adev->pdev->bus->number, i); 2045 if (p) { 2046 pm_runtime_get_sync(&p->dev); 2047 pm_runtime_mark_last_busy(&p->dev); 2048 pm_runtime_put_autosuspend(&p->dev); 2049 pci_dev_put(p); 2050 } 2051 } 2052 } 2053 2054 static int amdgpu_pci_probe(struct pci_dev *pdev, 2055 const struct pci_device_id *ent) 2056 { 2057 struct drm_device *ddev; 2058 struct amdgpu_device *adev; 2059 unsigned long flags = ent->driver_data; 2060 int ret, retry = 0, i; 2061 bool supports_atomic = false; 2062 2063 /* skip devices which are owned by radeon */ 2064 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2065 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2066 return -ENODEV; 2067 } 2068 2069 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2070 amdgpu_aspm = 0; 2071 2072 if (amdgpu_virtual_display || 2073 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2074 supports_atomic = true; 2075 2076 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2077 DRM_INFO("This hardware requires experimental hardware support.\n" 2078 "See modparam exp_hw_support\n"); 2079 return -ENODEV; 2080 } 2081 /* differentiate between P10 and P11 asics with the same DID */ 2082 if (pdev->device == 0x67FF && 2083 (pdev->revision == 0xE3 || 2084 pdev->revision == 0xE7 || 2085 pdev->revision == 0xF3 || 2086 pdev->revision == 0xF7)) { 2087 flags &= ~AMD_ASIC_MASK; 2088 flags |= CHIP_POLARIS10; 2089 } 2090 2091 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2092 * however, SME requires an indirect IOMMU mapping because the encryption 2093 * bit is beyond the DMA mask of the chip. 2094 */ 2095 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2096 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2097 dev_info(&pdev->dev, 2098 "SME is not compatible with RAVEN\n"); 2099 return -ENOTSUPP; 2100 } 2101 2102 #ifdef CONFIG_DRM_AMDGPU_SI 2103 if (!amdgpu_si_support) { 2104 switch (flags & AMD_ASIC_MASK) { 2105 case CHIP_TAHITI: 2106 case CHIP_PITCAIRN: 2107 case CHIP_VERDE: 2108 case CHIP_OLAND: 2109 case CHIP_HAINAN: 2110 dev_info(&pdev->dev, 2111 "SI support provided by radeon.\n"); 2112 dev_info(&pdev->dev, 2113 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2114 ); 2115 return -ENODEV; 2116 } 2117 } 2118 #endif 2119 #ifdef CONFIG_DRM_AMDGPU_CIK 2120 if (!amdgpu_cik_support) { 2121 switch (flags & AMD_ASIC_MASK) { 2122 case CHIP_KAVERI: 2123 case CHIP_BONAIRE: 2124 case CHIP_HAWAII: 2125 case CHIP_KABINI: 2126 case CHIP_MULLINS: 2127 dev_info(&pdev->dev, 2128 "CIK support provided by radeon.\n"); 2129 dev_info(&pdev->dev, 2130 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2131 ); 2132 return -ENODEV; 2133 } 2134 } 2135 #endif 2136 2137 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2138 if (IS_ERR(adev)) 2139 return PTR_ERR(adev); 2140 2141 adev->dev = &pdev->dev; 2142 adev->pdev = pdev; 2143 ddev = adev_to_drm(adev); 2144 2145 if (!supports_atomic) 2146 ddev->driver_features &= ~DRIVER_ATOMIC; 2147 2148 ret = pci_enable_device(pdev); 2149 if (ret) 2150 return ret; 2151 2152 pci_set_drvdata(pdev, ddev); 2153 2154 ret = amdgpu_driver_load_kms(adev, flags); 2155 if (ret) 2156 goto err_pci; 2157 2158 retry_init: 2159 ret = drm_dev_register(ddev, flags); 2160 if (ret == -EAGAIN && ++retry <= 3) { 2161 DRM_INFO("retry init %d\n", retry); 2162 /* Don't request EX mode too frequently which is attacking */ 2163 msleep(5000); 2164 goto retry_init; 2165 } else if (ret) { 2166 goto err_pci; 2167 } 2168 2169 /* 2170 * 1. don't init fbdev on hw without DCE 2171 * 2. don't init fbdev if there are no connectors 2172 */ 2173 if (adev->mode_info.mode_config_initialized && 2174 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2175 /* select 8 bpp console on low vram cards */ 2176 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2177 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2178 else 2179 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2180 } 2181 2182 ret = amdgpu_debugfs_init(adev); 2183 if (ret) 2184 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2185 2186 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2187 /* only need to skip on ATPX */ 2188 if (amdgpu_device_supports_px(ddev)) 2189 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2190 /* we want direct complete for BOCO */ 2191 if (amdgpu_device_supports_boco(ddev)) 2192 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2193 DPM_FLAG_SMART_SUSPEND | 2194 DPM_FLAG_MAY_SKIP_RESUME); 2195 pm_runtime_use_autosuspend(ddev->dev); 2196 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2197 2198 pm_runtime_allow(ddev->dev); 2199 2200 pm_runtime_mark_last_busy(ddev->dev); 2201 pm_runtime_put_autosuspend(ddev->dev); 2202 2203 /* 2204 * For runpm implemented via BACO, PMFW will handle the 2205 * timing for BACO in and out: 2206 * - put ASIC into BACO state only when both video and 2207 * audio functions are in D3 state. 2208 * - pull ASIC out of BACO state when either video or 2209 * audio function is in D0 state. 2210 * Also, at startup, PMFW assumes both functions are in 2211 * D0 state. 2212 * 2213 * So if snd driver was loaded prior to amdgpu driver 2214 * and audio function was put into D3 state, there will 2215 * be no PMFW-aware D-state transition(D0->D3) on runpm 2216 * suspend. Thus the BACO will be not correctly kicked in. 2217 * 2218 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2219 * into D0 state. Then there will be a PMFW-aware D-state 2220 * transition(D0->D3) on runpm suspend. 2221 */ 2222 if (amdgpu_device_supports_baco(ddev) && 2223 !(adev->flags & AMD_IS_APU) && 2224 (adev->asic_type >= CHIP_NAVI10)) 2225 amdgpu_get_secondary_funcs(adev); 2226 } 2227 2228 return 0; 2229 2230 err_pci: 2231 pci_disable_device(pdev); 2232 return ret; 2233 } 2234 2235 static void 2236 amdgpu_pci_remove(struct pci_dev *pdev) 2237 { 2238 struct drm_device *dev = pci_get_drvdata(pdev); 2239 struct amdgpu_device *adev = drm_to_adev(dev); 2240 2241 drm_dev_unplug(dev); 2242 2243 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2244 pm_runtime_get_sync(dev->dev); 2245 pm_runtime_forbid(dev->dev); 2246 } 2247 2248 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2249 !amdgpu_sriov_vf(adev)) { 2250 bool need_to_reset_gpu = false; 2251 2252 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2253 struct amdgpu_hive_info *hive; 2254 2255 hive = amdgpu_get_xgmi_hive(adev); 2256 if (hive->device_remove_count == 0) 2257 need_to_reset_gpu = true; 2258 hive->device_remove_count++; 2259 amdgpu_put_xgmi_hive(hive); 2260 } else { 2261 need_to_reset_gpu = true; 2262 } 2263 2264 /* Workaround for ASICs need to reset SMU. 2265 * Called only when the first device is removed. 2266 */ 2267 if (need_to_reset_gpu) { 2268 struct amdgpu_reset_context reset_context; 2269 2270 adev->shutdown = true; 2271 memset(&reset_context, 0, sizeof(reset_context)); 2272 reset_context.method = AMD_RESET_METHOD_NONE; 2273 reset_context.reset_req_dev = adev; 2274 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2275 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2276 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2277 } 2278 } 2279 2280 amdgpu_driver_unload_kms(dev); 2281 2282 /* 2283 * Flush any in flight DMA operations from device. 2284 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2285 * StatusTransactions Pending bit. 2286 */ 2287 pci_disable_device(pdev); 2288 pci_wait_for_pending_transaction(pdev); 2289 } 2290 2291 static void 2292 amdgpu_pci_shutdown(struct pci_dev *pdev) 2293 { 2294 struct drm_device *dev = pci_get_drvdata(pdev); 2295 struct amdgpu_device *adev = drm_to_adev(dev); 2296 2297 if (amdgpu_ras_intr_triggered()) 2298 return; 2299 2300 /* if we are running in a VM, make sure the device 2301 * torn down properly on reboot/shutdown. 2302 * unfortunately we can't detect certain 2303 * hypervisors so just do this all the time. 2304 */ 2305 if (!amdgpu_passthrough(adev)) 2306 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2307 amdgpu_device_ip_suspend(adev); 2308 adev->mp1_state = PP_MP1_STATE_NONE; 2309 } 2310 2311 /** 2312 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2313 * 2314 * @work: work_struct. 2315 */ 2316 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2317 { 2318 struct list_head device_list; 2319 struct amdgpu_device *adev; 2320 int i, r; 2321 struct amdgpu_reset_context reset_context; 2322 2323 memset(&reset_context, 0, sizeof(reset_context)); 2324 2325 mutex_lock(&mgpu_info.mutex); 2326 if (mgpu_info.pending_reset == true) { 2327 mutex_unlock(&mgpu_info.mutex); 2328 return; 2329 } 2330 mgpu_info.pending_reset = true; 2331 mutex_unlock(&mgpu_info.mutex); 2332 2333 /* Use a common context, just need to make sure full reset is done */ 2334 reset_context.method = AMD_RESET_METHOD_NONE; 2335 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2336 2337 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2338 adev = mgpu_info.gpu_ins[i].adev; 2339 reset_context.reset_req_dev = adev; 2340 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2341 if (r) { 2342 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2343 r, adev_to_drm(adev)->unique); 2344 } 2345 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2346 r = -EALREADY; 2347 } 2348 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2349 adev = mgpu_info.gpu_ins[i].adev; 2350 flush_work(&adev->xgmi_reset_work); 2351 adev->gmc.xgmi.pending_reset = false; 2352 } 2353 2354 /* reset function will rebuild the xgmi hive info , clear it now */ 2355 for (i = 0; i < mgpu_info.num_dgpu; i++) 2356 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2357 2358 INIT_LIST_HEAD(&device_list); 2359 2360 for (i = 0; i < mgpu_info.num_dgpu; i++) 2361 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2362 2363 /* unregister the GPU first, reset function will add them back */ 2364 list_for_each_entry(adev, &device_list, reset_list) 2365 amdgpu_unregister_gpu_instance(adev); 2366 2367 /* Use a common context, just need to make sure full reset is done */ 2368 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2369 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2370 2371 if (r) { 2372 DRM_ERROR("reinit gpus failure"); 2373 return; 2374 } 2375 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2376 adev = mgpu_info.gpu_ins[i].adev; 2377 if (!adev->kfd.init_complete) 2378 amdgpu_amdkfd_device_init(adev); 2379 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2380 } 2381 return; 2382 } 2383 2384 static int amdgpu_pmops_prepare(struct device *dev) 2385 { 2386 struct drm_device *drm_dev = dev_get_drvdata(dev); 2387 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2388 2389 /* Return a positive number here so 2390 * DPM_FLAG_SMART_SUSPEND works properly 2391 */ 2392 if (amdgpu_device_supports_boco(drm_dev)) 2393 return pm_runtime_suspended(dev); 2394 2395 /* if we will not support s3 or s2i for the device 2396 * then skip suspend 2397 */ 2398 if (!amdgpu_acpi_is_s0ix_active(adev) && 2399 !amdgpu_acpi_is_s3_active(adev)) 2400 return 1; 2401 2402 return 0; 2403 } 2404 2405 static void amdgpu_pmops_complete(struct device *dev) 2406 { 2407 /* nothing to do */ 2408 } 2409 2410 static int amdgpu_pmops_suspend(struct device *dev) 2411 { 2412 struct drm_device *drm_dev = dev_get_drvdata(dev); 2413 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2414 2415 if (amdgpu_acpi_is_s0ix_active(adev)) 2416 adev->in_s0ix = true; 2417 else 2418 adev->in_s3 = true; 2419 return amdgpu_device_suspend(drm_dev, true); 2420 } 2421 2422 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2423 { 2424 struct drm_device *drm_dev = dev_get_drvdata(dev); 2425 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2426 2427 if (amdgpu_acpi_should_gpu_reset(adev)) 2428 return amdgpu_asic_reset(adev); 2429 2430 return 0; 2431 } 2432 2433 static int amdgpu_pmops_resume(struct device *dev) 2434 { 2435 struct drm_device *drm_dev = dev_get_drvdata(dev); 2436 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2437 int r; 2438 2439 /* Avoids registers access if device is physically gone */ 2440 if (!pci_device_is_present(adev->pdev)) 2441 adev->no_hw_access = true; 2442 2443 r = amdgpu_device_resume(drm_dev, true); 2444 if (amdgpu_acpi_is_s0ix_active(adev)) 2445 adev->in_s0ix = false; 2446 else 2447 adev->in_s3 = false; 2448 return r; 2449 } 2450 2451 static int amdgpu_pmops_freeze(struct device *dev) 2452 { 2453 struct drm_device *drm_dev = dev_get_drvdata(dev); 2454 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2455 int r; 2456 2457 adev->in_s4 = true; 2458 r = amdgpu_device_suspend(drm_dev, true); 2459 adev->in_s4 = false; 2460 if (r) 2461 return r; 2462 return amdgpu_asic_reset(adev); 2463 } 2464 2465 static int amdgpu_pmops_thaw(struct device *dev) 2466 { 2467 struct drm_device *drm_dev = dev_get_drvdata(dev); 2468 2469 return amdgpu_device_resume(drm_dev, true); 2470 } 2471 2472 static int amdgpu_pmops_poweroff(struct device *dev) 2473 { 2474 struct drm_device *drm_dev = dev_get_drvdata(dev); 2475 2476 return amdgpu_device_suspend(drm_dev, true); 2477 } 2478 2479 static int amdgpu_pmops_restore(struct device *dev) 2480 { 2481 struct drm_device *drm_dev = dev_get_drvdata(dev); 2482 2483 return amdgpu_device_resume(drm_dev, true); 2484 } 2485 2486 static int amdgpu_runtime_idle_check_display(struct device *dev) 2487 { 2488 struct pci_dev *pdev = to_pci_dev(dev); 2489 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2490 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2491 2492 if (adev->mode_info.num_crtc) { 2493 struct drm_connector *list_connector; 2494 struct drm_connector_list_iter iter; 2495 int ret = 0; 2496 2497 /* XXX: Return busy if any displays are connected to avoid 2498 * possible display wakeups after runtime resume due to 2499 * hotplug events in case any displays were connected while 2500 * the GPU was in suspend. Remove this once that is fixed. 2501 */ 2502 mutex_lock(&drm_dev->mode_config.mutex); 2503 drm_connector_list_iter_begin(drm_dev, &iter); 2504 drm_for_each_connector_iter(list_connector, &iter) { 2505 if (list_connector->status == connector_status_connected) { 2506 ret = -EBUSY; 2507 break; 2508 } 2509 } 2510 drm_connector_list_iter_end(&iter); 2511 mutex_unlock(&drm_dev->mode_config.mutex); 2512 2513 if (ret) 2514 return ret; 2515 2516 if (adev->dc_enabled) { 2517 struct drm_crtc *crtc; 2518 2519 drm_for_each_crtc(crtc, drm_dev) { 2520 drm_modeset_lock(&crtc->mutex, NULL); 2521 if (crtc->state->active) 2522 ret = -EBUSY; 2523 drm_modeset_unlock(&crtc->mutex); 2524 if (ret < 0) 2525 break; 2526 } 2527 } else { 2528 mutex_lock(&drm_dev->mode_config.mutex); 2529 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2530 2531 drm_connector_list_iter_begin(drm_dev, &iter); 2532 drm_for_each_connector_iter(list_connector, &iter) { 2533 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2534 ret = -EBUSY; 2535 break; 2536 } 2537 } 2538 2539 drm_connector_list_iter_end(&iter); 2540 2541 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2542 mutex_unlock(&drm_dev->mode_config.mutex); 2543 } 2544 if (ret) 2545 return ret; 2546 } 2547 2548 return 0; 2549 } 2550 2551 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2552 { 2553 struct pci_dev *pdev = to_pci_dev(dev); 2554 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2555 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2556 int ret, i; 2557 2558 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2559 pm_runtime_forbid(dev); 2560 return -EBUSY; 2561 } 2562 2563 ret = amdgpu_runtime_idle_check_display(dev); 2564 if (ret) 2565 return ret; 2566 2567 /* wait for all rings to drain before suspending */ 2568 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2569 struct amdgpu_ring *ring = adev->rings[i]; 2570 if (ring && ring->sched.ready) { 2571 ret = amdgpu_fence_wait_empty(ring); 2572 if (ret) 2573 return -EBUSY; 2574 } 2575 } 2576 2577 adev->in_runpm = true; 2578 if (amdgpu_device_supports_px(drm_dev)) 2579 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2580 2581 /* 2582 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2583 * proper cleanups and put itself into a state ready for PNP. That 2584 * can address some random resuming failure observed on BOCO capable 2585 * platforms. 2586 * TODO: this may be also needed for PX capable platform. 2587 */ 2588 if (amdgpu_device_supports_boco(drm_dev)) 2589 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2590 2591 ret = amdgpu_device_suspend(drm_dev, false); 2592 if (ret) { 2593 adev->in_runpm = false; 2594 if (amdgpu_device_supports_boco(drm_dev)) 2595 adev->mp1_state = PP_MP1_STATE_NONE; 2596 return ret; 2597 } 2598 2599 if (amdgpu_device_supports_boco(drm_dev)) 2600 adev->mp1_state = PP_MP1_STATE_NONE; 2601 2602 if (amdgpu_device_supports_px(drm_dev)) { 2603 /* Only need to handle PCI state in the driver for ATPX 2604 * PCI core handles it for _PR3. 2605 */ 2606 amdgpu_device_cache_pci_state(pdev); 2607 pci_disable_device(pdev); 2608 pci_ignore_hotplug(pdev); 2609 pci_set_power_state(pdev, PCI_D3cold); 2610 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2611 } else if (amdgpu_device_supports_boco(drm_dev)) { 2612 /* nothing to do */ 2613 } else if (amdgpu_device_supports_baco(drm_dev)) { 2614 amdgpu_device_baco_enter(drm_dev); 2615 } 2616 2617 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2618 2619 return 0; 2620 } 2621 2622 static int amdgpu_pmops_runtime_resume(struct device *dev) 2623 { 2624 struct pci_dev *pdev = to_pci_dev(dev); 2625 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2626 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2627 int ret; 2628 2629 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2630 return -EINVAL; 2631 2632 /* Avoids registers access if device is physically gone */ 2633 if (!pci_device_is_present(adev->pdev)) 2634 adev->no_hw_access = true; 2635 2636 if (amdgpu_device_supports_px(drm_dev)) { 2637 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2638 2639 /* Only need to handle PCI state in the driver for ATPX 2640 * PCI core handles it for _PR3. 2641 */ 2642 pci_set_power_state(pdev, PCI_D0); 2643 amdgpu_device_load_pci_state(pdev); 2644 ret = pci_enable_device(pdev); 2645 if (ret) 2646 return ret; 2647 pci_set_master(pdev); 2648 } else if (amdgpu_device_supports_boco(drm_dev)) { 2649 /* Only need to handle PCI state in the driver for ATPX 2650 * PCI core handles it for _PR3. 2651 */ 2652 pci_set_master(pdev); 2653 } else if (amdgpu_device_supports_baco(drm_dev)) { 2654 amdgpu_device_baco_exit(drm_dev); 2655 } 2656 ret = amdgpu_device_resume(drm_dev, false); 2657 if (ret) { 2658 if (amdgpu_device_supports_px(drm_dev)) 2659 pci_disable_device(pdev); 2660 return ret; 2661 } 2662 2663 if (amdgpu_device_supports_px(drm_dev)) 2664 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2665 adev->in_runpm = false; 2666 return 0; 2667 } 2668 2669 static int amdgpu_pmops_runtime_idle(struct device *dev) 2670 { 2671 struct drm_device *drm_dev = dev_get_drvdata(dev); 2672 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2673 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2674 int ret = 1; 2675 2676 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2677 pm_runtime_forbid(dev); 2678 return -EBUSY; 2679 } 2680 2681 ret = amdgpu_runtime_idle_check_display(dev); 2682 2683 pm_runtime_mark_last_busy(dev); 2684 pm_runtime_autosuspend(dev); 2685 return ret; 2686 } 2687 2688 long amdgpu_drm_ioctl(struct file *filp, 2689 unsigned int cmd, unsigned long arg) 2690 { 2691 struct drm_file *file_priv = filp->private_data; 2692 struct drm_device *dev; 2693 long ret; 2694 dev = file_priv->minor->dev; 2695 ret = pm_runtime_get_sync(dev->dev); 2696 if (ret < 0) 2697 goto out; 2698 2699 ret = drm_ioctl(filp, cmd, arg); 2700 2701 pm_runtime_mark_last_busy(dev->dev); 2702 out: 2703 pm_runtime_put_autosuspend(dev->dev); 2704 return ret; 2705 } 2706 2707 static const struct dev_pm_ops amdgpu_pm_ops = { 2708 .prepare = amdgpu_pmops_prepare, 2709 .complete = amdgpu_pmops_complete, 2710 .suspend = amdgpu_pmops_suspend, 2711 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2712 .resume = amdgpu_pmops_resume, 2713 .freeze = amdgpu_pmops_freeze, 2714 .thaw = amdgpu_pmops_thaw, 2715 .poweroff = amdgpu_pmops_poweroff, 2716 .restore = amdgpu_pmops_restore, 2717 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2718 .runtime_resume = amdgpu_pmops_runtime_resume, 2719 .runtime_idle = amdgpu_pmops_runtime_idle, 2720 }; 2721 2722 static int amdgpu_flush(struct file *f, fl_owner_t id) 2723 { 2724 struct drm_file *file_priv = f->private_data; 2725 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2726 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2727 2728 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2729 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2730 2731 return timeout >= 0 ? 0 : timeout; 2732 } 2733 2734 static const struct file_operations amdgpu_driver_kms_fops = { 2735 .owner = THIS_MODULE, 2736 .open = drm_open, 2737 .flush = amdgpu_flush, 2738 .release = drm_release, 2739 .unlocked_ioctl = amdgpu_drm_ioctl, 2740 .mmap = drm_gem_mmap, 2741 .poll = drm_poll, 2742 .read = drm_read, 2743 #ifdef CONFIG_COMPAT 2744 .compat_ioctl = amdgpu_kms_compat_ioctl, 2745 #endif 2746 #ifdef CONFIG_PROC_FS 2747 .show_fdinfo = amdgpu_show_fdinfo 2748 #endif 2749 }; 2750 2751 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2752 { 2753 struct drm_file *file; 2754 2755 if (!filp) 2756 return -EINVAL; 2757 2758 if (filp->f_op != &amdgpu_driver_kms_fops) { 2759 return -EINVAL; 2760 } 2761 2762 file = filp->private_data; 2763 *fpriv = file->driver_priv; 2764 return 0; 2765 } 2766 2767 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2768 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2769 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2770 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2771 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2772 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2773 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2774 /* KMS */ 2775 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2776 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2777 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2778 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2779 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2780 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2781 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2782 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2783 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2784 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2785 }; 2786 2787 static const struct drm_driver amdgpu_kms_driver = { 2788 .driver_features = 2789 DRIVER_ATOMIC | 2790 DRIVER_GEM | 2791 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2792 DRIVER_SYNCOBJ_TIMELINE, 2793 .open = amdgpu_driver_open_kms, 2794 .postclose = amdgpu_driver_postclose_kms, 2795 .lastclose = amdgpu_driver_lastclose_kms, 2796 .ioctls = amdgpu_ioctls_kms, 2797 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2798 .dumb_create = amdgpu_mode_dumb_create, 2799 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2800 .fops = &amdgpu_driver_kms_fops, 2801 .release = &amdgpu_driver_release_kms, 2802 2803 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2804 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2805 .gem_prime_import = amdgpu_gem_prime_import, 2806 .gem_prime_mmap = drm_gem_prime_mmap, 2807 2808 .name = DRIVER_NAME, 2809 .desc = DRIVER_DESC, 2810 .date = DRIVER_DATE, 2811 .major = KMS_DRIVER_MAJOR, 2812 .minor = KMS_DRIVER_MINOR, 2813 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2814 }; 2815 2816 static struct pci_error_handlers amdgpu_pci_err_handler = { 2817 .error_detected = amdgpu_pci_error_detected, 2818 .mmio_enabled = amdgpu_pci_mmio_enabled, 2819 .slot_reset = amdgpu_pci_slot_reset, 2820 .resume = amdgpu_pci_resume, 2821 }; 2822 2823 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2824 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2825 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2826 2827 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2828 &amdgpu_vram_mgr_attr_group, 2829 &amdgpu_gtt_mgr_attr_group, 2830 &amdgpu_vbios_version_attr_group, 2831 NULL, 2832 }; 2833 2834 2835 static struct pci_driver amdgpu_kms_pci_driver = { 2836 .name = DRIVER_NAME, 2837 .id_table = pciidlist, 2838 .probe = amdgpu_pci_probe, 2839 .remove = amdgpu_pci_remove, 2840 .shutdown = amdgpu_pci_shutdown, 2841 .driver.pm = &amdgpu_pm_ops, 2842 .err_handler = &amdgpu_pci_err_handler, 2843 .dev_groups = amdgpu_sysfs_groups, 2844 }; 2845 2846 static int __init amdgpu_init(void) 2847 { 2848 int r; 2849 2850 if (drm_firmware_drivers_only()) 2851 return -EINVAL; 2852 2853 r = amdgpu_sync_init(); 2854 if (r) 2855 goto error_sync; 2856 2857 r = amdgpu_fence_slab_init(); 2858 if (r) 2859 goto error_fence; 2860 2861 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2862 amdgpu_register_atpx_handler(); 2863 amdgpu_acpi_detect(); 2864 2865 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2866 amdgpu_amdkfd_init(); 2867 2868 /* let modprobe override vga console setting */ 2869 return pci_register_driver(&amdgpu_kms_pci_driver); 2870 2871 error_fence: 2872 amdgpu_sync_fini(); 2873 2874 error_sync: 2875 return r; 2876 } 2877 2878 static void __exit amdgpu_exit(void) 2879 { 2880 amdgpu_amdkfd_fini(); 2881 pci_unregister_driver(&amdgpu_kms_pci_driver); 2882 amdgpu_unregister_atpx_handler(); 2883 amdgpu_sync_fini(); 2884 amdgpu_fence_slab_fini(); 2885 mmu_notifier_synchronize(); 2886 } 2887 2888 module_init(amdgpu_init); 2889 module_exit(amdgpu_exit); 2890 2891 MODULE_AUTHOR(DRIVER_AUTHOR); 2892 MODULE_DESCRIPTION(DRIVER_DESC); 2893 MODULE_LICENSE("GPL and additional rights"); 2894