1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 */ 117 #define KMS_DRIVER_MAJOR 3 118 #define KMS_DRIVER_MINOR 54 119 #define KMS_DRIVER_PATCHLEVEL 0 120 121 unsigned int amdgpu_vram_limit = UINT_MAX; 122 int amdgpu_vis_vram_limit; 123 int amdgpu_gart_size = -1; /* auto */ 124 int amdgpu_gtt_size = -1; /* auto */ 125 int amdgpu_moverate = -1; /* auto */ 126 int amdgpu_audio = -1; 127 int amdgpu_disp_priority; 128 int amdgpu_hw_i2c; 129 int amdgpu_pcie_gen2 = -1; 130 int amdgpu_msi = -1; 131 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 132 int amdgpu_dpm = -1; 133 int amdgpu_fw_load_type = -1; 134 int amdgpu_aspm = -1; 135 int amdgpu_runtime_pm = -1; 136 uint amdgpu_ip_block_mask = 0xffffffff; 137 int amdgpu_bapm = -1; 138 int amdgpu_deep_color; 139 int amdgpu_vm_size = -1; 140 int amdgpu_vm_fragment_size = -1; 141 int amdgpu_vm_block_size = -1; 142 int amdgpu_vm_fault_stop; 143 int amdgpu_vm_debug; 144 int amdgpu_vm_update_mode = -1; 145 int amdgpu_exp_hw_support; 146 int amdgpu_dc = -1; 147 int amdgpu_sched_jobs = 32; 148 int amdgpu_sched_hw_submission = 2; 149 uint amdgpu_pcie_gen_cap; 150 uint amdgpu_pcie_lane_cap; 151 u64 amdgpu_cg_mask = 0xffffffffffffffff; 152 uint amdgpu_pg_mask = 0xffffffff; 153 uint amdgpu_sdma_phase_quantum = 32; 154 char *amdgpu_disable_cu; 155 char *amdgpu_virtual_display; 156 bool enforce_isolation; 157 /* 158 * OverDrive(bit 14) disabled by default 159 * GFX DCS(bit 19) disabled by default 160 */ 161 uint amdgpu_pp_feature_mask = 0xfff7bfff; 162 uint amdgpu_force_long_training; 163 int amdgpu_lbpw = -1; 164 int amdgpu_compute_multipipe = -1; 165 int amdgpu_gpu_recovery = -1; /* auto */ 166 int amdgpu_emu_mode; 167 uint amdgpu_smu_memory_pool_size; 168 int amdgpu_smu_pptable_id = -1; 169 /* 170 * FBC (bit 0) disabled by default 171 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 172 * - With this, for multiple monitors in sync(e.g. with the same model), 173 * mclk switching will be allowed. And the mclk will be not foced to the 174 * highest. That helps saving some idle power. 175 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 176 * PSR (bit 3) disabled by default 177 * EDP NO POWER SEQUENCING (bit 4) disabled by default 178 */ 179 uint amdgpu_dc_feature_mask = 2; 180 uint amdgpu_dc_debug_mask; 181 uint amdgpu_dc_visual_confirm; 182 int amdgpu_async_gfx_ring = 1; 183 int amdgpu_mcbp = -1; 184 int amdgpu_discovery = -1; 185 int amdgpu_mes; 186 int amdgpu_mes_kiq; 187 int amdgpu_noretry = -1; 188 int amdgpu_force_asic_type = -1; 189 int amdgpu_tmz = -1; /* auto */ 190 uint amdgpu_freesync_vid_mode; 191 int amdgpu_reset_method = -1; /* auto */ 192 int amdgpu_num_kcq = -1; 193 int amdgpu_smartshift_bias; 194 int amdgpu_use_xgmi_p2p = 1; 195 int amdgpu_vcnfw_log; 196 int amdgpu_sg_display = -1; /* auto */ 197 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 198 199 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 200 201 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 202 "DRM_UT_CORE", 203 "DRM_UT_DRIVER", 204 "DRM_UT_KMS", 205 "DRM_UT_PRIME", 206 "DRM_UT_ATOMIC", 207 "DRM_UT_VBL", 208 "DRM_UT_STATE", 209 "DRM_UT_LEASE", 210 "DRM_UT_DP", 211 "DRM_UT_DRMRES"); 212 213 struct amdgpu_mgpu_info mgpu_info = { 214 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 215 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 216 mgpu_info.delayed_reset_work, 217 amdgpu_drv_delayed_reset_work_handler, 0), 218 }; 219 int amdgpu_ras_enable = -1; 220 uint amdgpu_ras_mask = 0xffffffff; 221 int amdgpu_bad_page_threshold = -1; 222 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 223 .timeout_fatal_disable = false, 224 .period = 0x0, /* default to 0x0 (timeout disable) */ 225 }; 226 227 /** 228 * DOC: vramlimit (int) 229 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 230 */ 231 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 232 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 233 234 /** 235 * DOC: vis_vramlimit (int) 236 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 237 */ 238 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 239 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 240 241 /** 242 * DOC: gartsize (uint) 243 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 244 * The default is -1 (The size depends on asic). 245 */ 246 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 247 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 248 249 /** 250 * DOC: gttsize (int) 251 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 252 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 253 */ 254 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 255 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 256 257 /** 258 * DOC: moverate (int) 259 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 260 */ 261 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 262 module_param_named(moverate, amdgpu_moverate, int, 0600); 263 264 /** 265 * DOC: audio (int) 266 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 267 */ 268 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 269 module_param_named(audio, amdgpu_audio, int, 0444); 270 271 /** 272 * DOC: disp_priority (int) 273 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 274 */ 275 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 276 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 277 278 /** 279 * DOC: hw_i2c (int) 280 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 281 */ 282 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 283 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 284 285 /** 286 * DOC: pcie_gen2 (int) 287 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 288 */ 289 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 290 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 291 292 /** 293 * DOC: msi (int) 294 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 295 */ 296 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 297 module_param_named(msi, amdgpu_msi, int, 0444); 298 299 /** 300 * DOC: lockup_timeout (string) 301 * Set GPU scheduler timeout value in ms. 302 * 303 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 304 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 305 * to the default timeout. 306 * 307 * - With one value specified, the setting will apply to all non-compute jobs. 308 * - With multiple values specified, the first one will be for GFX. 309 * The second one is for Compute. The third and fourth ones are 310 * for SDMA and Video. 311 * 312 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 313 * jobs is 10000. The timeout for compute is 60000. 314 */ 315 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 316 "for passthrough or sriov, 10000 for all jobs." 317 " 0: keep default value. negative: infinity timeout), " 318 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 319 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 320 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 321 322 /** 323 * DOC: dpm (int) 324 * Override for dynamic power management setting 325 * (0 = disable, 1 = enable) 326 * The default is -1 (auto). 327 */ 328 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 329 module_param_named(dpm, amdgpu_dpm, int, 0444); 330 331 /** 332 * DOC: fw_load_type (int) 333 * Set different firmware loading type for debugging, if supported. 334 * Set to 0 to force direct loading if supported by the ASIC. Set 335 * to -1 to select the default loading mode for the ASIC, as defined 336 * by the driver. The default is -1 (auto). 337 */ 338 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 339 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 340 341 /** 342 * DOC: aspm (int) 343 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 344 */ 345 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 346 module_param_named(aspm, amdgpu_aspm, int, 0444); 347 348 /** 349 * DOC: runpm (int) 350 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 351 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 352 * Setting the value to 0 disables this functionality. 353 */ 354 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 355 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 356 357 /** 358 * DOC: ip_block_mask (uint) 359 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 360 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 361 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 362 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 363 */ 364 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 365 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 366 367 /** 368 * DOC: bapm (int) 369 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 370 * The default -1 (auto, enabled) 371 */ 372 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 373 module_param_named(bapm, amdgpu_bapm, int, 0444); 374 375 /** 376 * DOC: deep_color (int) 377 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 378 */ 379 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 380 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 381 382 /** 383 * DOC: vm_size (int) 384 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 385 */ 386 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 387 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 388 389 /** 390 * DOC: vm_fragment_size (int) 391 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 392 */ 393 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 394 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 395 396 /** 397 * DOC: vm_block_size (int) 398 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 399 */ 400 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 401 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 402 403 /** 404 * DOC: vm_fault_stop (int) 405 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 406 */ 407 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 408 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 409 410 /** 411 * DOC: vm_debug (int) 412 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 413 */ 414 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 415 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 416 417 /** 418 * DOC: vm_update_mode (int) 419 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 420 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 421 */ 422 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 423 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 424 425 /** 426 * DOC: exp_hw_support (int) 427 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 428 */ 429 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 430 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 431 432 /** 433 * DOC: dc (int) 434 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 435 */ 436 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 437 module_param_named(dc, amdgpu_dc, int, 0444); 438 439 /** 440 * DOC: sched_jobs (int) 441 * Override the max number of jobs supported in the sw queue. The default is 32. 442 */ 443 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 444 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 445 446 /** 447 * DOC: sched_hw_submission (int) 448 * Override the max number of HW submissions. The default is 2. 449 */ 450 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 451 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 452 453 /** 454 * DOC: ppfeaturemask (hexint) 455 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 456 * The default is the current set of stable power features. 457 */ 458 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 459 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 460 461 /** 462 * DOC: forcelongtraining (uint) 463 * Force long memory training in resume. 464 * The default is zero, indicates short training in resume. 465 */ 466 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 467 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 468 469 /** 470 * DOC: pcie_gen_cap (uint) 471 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 472 * The default is 0 (automatic for each asic). 473 */ 474 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 475 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 476 477 /** 478 * DOC: pcie_lane_cap (uint) 479 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 480 * The default is 0 (automatic for each asic). 481 */ 482 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 483 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 484 485 /** 486 * DOC: cg_mask (ullong) 487 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 488 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 489 */ 490 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 491 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 492 493 /** 494 * DOC: pg_mask (uint) 495 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 496 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 497 */ 498 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 499 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 500 501 /** 502 * DOC: sdma_phase_quantum (uint) 503 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 504 */ 505 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 506 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 507 508 /** 509 * DOC: disable_cu (charp) 510 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 511 */ 512 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 513 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 514 515 /** 516 * DOC: virtual_display (charp) 517 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 518 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 519 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 520 * device at 26:00.0. The default is NULL. 521 */ 522 MODULE_PARM_DESC(virtual_display, 523 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 524 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 525 526 /** 527 * DOC: lbpw (int) 528 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 529 */ 530 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 532 533 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 534 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 535 536 /** 537 * DOC: gpu_recovery (int) 538 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 539 */ 540 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 541 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 542 543 /** 544 * DOC: emu_mode (int) 545 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 546 */ 547 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 548 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 549 550 /** 551 * DOC: ras_enable (int) 552 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 553 */ 554 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 555 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 556 557 /** 558 * DOC: ras_mask (uint) 559 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 560 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 561 */ 562 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 563 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 564 565 /** 566 * DOC: timeout_fatal_disable (bool) 567 * Disable Watchdog timeout fatal error event 568 */ 569 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 570 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 571 572 /** 573 * DOC: timeout_period (uint) 574 * Modify the watchdog timeout max_cycles as (1 << period) 575 */ 576 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 577 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 578 579 /** 580 * DOC: si_support (int) 581 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 582 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 583 * otherwise using amdgpu driver. 584 */ 585 #ifdef CONFIG_DRM_AMDGPU_SI 586 587 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 588 int amdgpu_si_support = 0; 589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 590 #else 591 int amdgpu_si_support = 1; 592 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 593 #endif 594 595 module_param_named(si_support, amdgpu_si_support, int, 0444); 596 #endif 597 598 /** 599 * DOC: cik_support (int) 600 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 601 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 602 * otherwise using amdgpu driver. 603 */ 604 #ifdef CONFIG_DRM_AMDGPU_CIK 605 606 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 607 int amdgpu_cik_support = 0; 608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 609 #else 610 int amdgpu_cik_support = 1; 611 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 612 #endif 613 614 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 615 #endif 616 617 /** 618 * DOC: smu_memory_pool_size (uint) 619 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 620 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 621 */ 622 MODULE_PARM_DESC(smu_memory_pool_size, 623 "reserve gtt for smu debug usage, 0 = disable," 624 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 625 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 626 627 /** 628 * DOC: async_gfx_ring (int) 629 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 630 */ 631 MODULE_PARM_DESC(async_gfx_ring, 632 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 633 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 634 635 /** 636 * DOC: mcbp (int) 637 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 638 */ 639 MODULE_PARM_DESC(mcbp, 640 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 641 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 642 643 /** 644 * DOC: discovery (int) 645 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 646 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 647 */ 648 MODULE_PARM_DESC(discovery, 649 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 650 module_param_named(discovery, amdgpu_discovery, int, 0444); 651 652 /** 653 * DOC: mes (int) 654 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 655 * (0 = disabled (default), 1 = enabled) 656 */ 657 MODULE_PARM_DESC(mes, 658 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 659 module_param_named(mes, amdgpu_mes, int, 0444); 660 661 /** 662 * DOC: mes_kiq (int) 663 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 664 * (0 = disabled (default), 1 = enabled) 665 */ 666 MODULE_PARM_DESC(mes_kiq, 667 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 668 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 669 670 /** 671 * DOC: noretry (int) 672 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 673 * do not support per-process XNACK this also disables retry page faults. 674 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 675 */ 676 MODULE_PARM_DESC(noretry, 677 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 678 module_param_named(noretry, amdgpu_noretry, int, 0644); 679 680 /** 681 * DOC: force_asic_type (int) 682 * A non negative value used to specify the asic type for all supported GPUs. 683 */ 684 MODULE_PARM_DESC(force_asic_type, 685 "A non negative value used to specify the asic type for all supported GPUs"); 686 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 687 688 /** 689 * DOC: use_xgmi_p2p (int) 690 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 691 */ 692 MODULE_PARM_DESC(use_xgmi_p2p, 693 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 694 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 695 696 697 #ifdef CONFIG_HSA_AMD 698 /** 699 * DOC: sched_policy (int) 700 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 701 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 702 * assigns queues to HQDs. 703 */ 704 int sched_policy = KFD_SCHED_POLICY_HWS; 705 module_param(sched_policy, int, 0444); 706 MODULE_PARM_DESC(sched_policy, 707 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 708 709 /** 710 * DOC: hws_max_conc_proc (int) 711 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 712 * number of VMIDs assigned to the HWS, which is also the default. 713 */ 714 int hws_max_conc_proc = -1; 715 module_param(hws_max_conc_proc, int, 0444); 716 MODULE_PARM_DESC(hws_max_conc_proc, 717 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 718 719 /** 720 * DOC: cwsr_enable (int) 721 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 722 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 723 * disables it. 724 */ 725 int cwsr_enable = 1; 726 module_param(cwsr_enable, int, 0444); 727 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 728 729 /** 730 * DOC: max_num_of_queues_per_device (int) 731 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 732 * is 4096. 733 */ 734 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 735 module_param(max_num_of_queues_per_device, int, 0444); 736 MODULE_PARM_DESC(max_num_of_queues_per_device, 737 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 738 739 /** 740 * DOC: send_sigterm (int) 741 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 742 * but just print errors on dmesg. Setting 1 enables sending sigterm. 743 */ 744 int send_sigterm; 745 module_param(send_sigterm, int, 0444); 746 MODULE_PARM_DESC(send_sigterm, 747 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 748 749 /** 750 * DOC: debug_largebar (int) 751 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 752 * system. This limits the VRAM size reported to ROCm applications to the visible 753 * size, usually 256MB. 754 * Default value is 0, diabled. 755 */ 756 int debug_largebar; 757 module_param(debug_largebar, int, 0444); 758 MODULE_PARM_DESC(debug_largebar, 759 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 760 761 /** 762 * DOC: ignore_crat (int) 763 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 764 * table to get information about AMD APUs. This option can serve as a workaround on 765 * systems with a broken CRAT table. 766 * 767 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 768 * whether use CRAT) 769 */ 770 int ignore_crat; 771 module_param(ignore_crat, int, 0444); 772 MODULE_PARM_DESC(ignore_crat, 773 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 774 775 /** 776 * DOC: halt_if_hws_hang (int) 777 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 778 * Setting 1 enables halt on hang. 779 */ 780 int halt_if_hws_hang; 781 module_param(halt_if_hws_hang, int, 0644); 782 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 783 784 /** 785 * DOC: hws_gws_support(bool) 786 * Assume that HWS supports GWS barriers regardless of what firmware version 787 * check says. Default value: false (rely on MEC2 firmware version check). 788 */ 789 bool hws_gws_support; 790 module_param(hws_gws_support, bool, 0444); 791 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 792 793 /** 794 * DOC: queue_preemption_timeout_ms (int) 795 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 796 */ 797 int queue_preemption_timeout_ms = 9000; 798 module_param(queue_preemption_timeout_ms, int, 0644); 799 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 800 801 /** 802 * DOC: debug_evictions(bool) 803 * Enable extra debug messages to help determine the cause of evictions 804 */ 805 bool debug_evictions; 806 module_param(debug_evictions, bool, 0644); 807 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 808 809 /** 810 * DOC: no_system_mem_limit(bool) 811 * Disable system memory limit, to support multiple process shared memory 812 */ 813 bool no_system_mem_limit; 814 module_param(no_system_mem_limit, bool, 0644); 815 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 816 817 /** 818 * DOC: no_queue_eviction_on_vm_fault (int) 819 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 820 */ 821 int amdgpu_no_queue_eviction_on_vm_fault; 822 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 823 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 824 #endif 825 826 /** 827 * DOC: mtype_local (int) 828 */ 829 int amdgpu_mtype_local; 830 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 831 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 832 833 /** 834 * DOC: pcie_p2p (bool) 835 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 836 */ 837 #ifdef CONFIG_HSA_AMD_P2P 838 bool pcie_p2p = true; 839 module_param(pcie_p2p, bool, 0444); 840 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 841 #endif 842 843 /** 844 * DOC: dcfeaturemask (uint) 845 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 846 * The default is the current set of stable display features. 847 */ 848 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 849 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 850 851 /** 852 * DOC: dcdebugmask (uint) 853 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 854 */ 855 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 856 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 857 858 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 859 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 860 861 /** 862 * DOC: abmlevel (uint) 863 * Override the default ABM (Adaptive Backlight Management) level used for DC 864 * enabled hardware. Requires DMCU to be supported and loaded. 865 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 866 * default. Values 1-4 control the maximum allowable brightness reduction via 867 * the ABM algorithm, with 1 being the least reduction and 4 being the most 868 * reduction. 869 * 870 * Defaults to 0, or disabled. Userspace can still override this level later 871 * after boot. 872 */ 873 uint amdgpu_dm_abm_level; 874 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 875 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 876 877 int amdgpu_backlight = -1; 878 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 879 module_param_named(backlight, amdgpu_backlight, bint, 0444); 880 881 /** 882 * DOC: tmz (int) 883 * Trusted Memory Zone (TMZ) is a method to protect data being written 884 * to or read from memory. 885 * 886 * The default value: 0 (off). TODO: change to auto till it is completed. 887 */ 888 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 889 module_param_named(tmz, amdgpu_tmz, int, 0444); 890 891 /** 892 * DOC: freesync_video (uint) 893 * Enable the optimization to adjust front porch timing to achieve seamless 894 * mode change experience when setting a freesync supported mode for which full 895 * modeset is not needed. 896 * 897 * The Display Core will add a set of modes derived from the base FreeSync 898 * video mode into the corresponding connector's mode list based on commonly 899 * used refresh rates and VRR range of the connected display, when users enable 900 * this feature. From the userspace perspective, they can see a seamless mode 901 * change experience when the change between different refresh rates under the 902 * same resolution. Additionally, userspace applications such as Video playback 903 * can read this modeset list and change the refresh rate based on the video 904 * frame rate. Finally, the userspace can also derive an appropriate mode for a 905 * particular refresh rate based on the FreeSync Mode and add it to the 906 * connector's mode list. 907 * 908 * Note: This is an experimental feature. 909 * 910 * The default value: 0 (off). 911 */ 912 MODULE_PARM_DESC( 913 freesync_video, 914 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 915 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 916 917 /** 918 * DOC: reset_method (int) 919 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 920 */ 921 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 922 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 923 924 /** 925 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 926 * threshold value of faulty pages detected by RAS ECC, which may 927 * result in the GPU entering bad status when the number of total 928 * faulty pages by ECC exceeds the threshold value. 929 */ 930 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 931 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 932 933 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 934 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 935 936 /** 937 * DOC: vcnfw_log (int) 938 * Enable vcnfw log output for debugging, the default is disabled. 939 */ 940 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 941 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 942 943 /** 944 * DOC: sg_display (int) 945 * Disable S/G (scatter/gather) display (i.e., display from system memory). 946 * This option is only relevant on APUs. Set this option to 0 to disable 947 * S/G display if you experience flickering or other issues under memory 948 * pressure and report the issue. 949 */ 950 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 951 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 952 953 /** 954 * DOC: smu_pptable_id (int) 955 * Used to override pptable id. id = 0 use VBIOS pptable. 956 * id > 0 use the soft pptable with specicfied id. 957 */ 958 MODULE_PARM_DESC(smu_pptable_id, 959 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 960 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 961 962 /** 963 * DOC: partition_mode (int) 964 * Used to override the default SPX mode. 965 */ 966 MODULE_PARM_DESC( 967 user_partt_mode, 968 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 969 0 = AMDGPU_SPX_PARTITION_MODE, \ 970 1 = AMDGPU_DPX_PARTITION_MODE, \ 971 2 = AMDGPU_TPX_PARTITION_MODE, \ 972 3 = AMDGPU_QPX_PARTITION_MODE, \ 973 4 = AMDGPU_CPX_PARTITION_MODE)"); 974 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 975 976 977 /** 978 * DOC: enforce_isolation (bool) 979 * enforce process isolation between graphics and compute via using the same reserved vmid. 980 */ 981 module_param(enforce_isolation, bool, 0444); 982 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 983 984 /* These devices are not supported by amdgpu. 985 * They are supported by the mach64, r128, radeon drivers 986 */ 987 static const u16 amdgpu_unsupported_pciidlist[] = { 988 /* mach64 */ 989 0x4354, 990 0x4358, 991 0x4554, 992 0x4742, 993 0x4744, 994 0x4749, 995 0x474C, 996 0x474D, 997 0x474E, 998 0x474F, 999 0x4750, 1000 0x4751, 1001 0x4752, 1002 0x4753, 1003 0x4754, 1004 0x4755, 1005 0x4756, 1006 0x4757, 1007 0x4758, 1008 0x4759, 1009 0x475A, 1010 0x4C42, 1011 0x4C44, 1012 0x4C47, 1013 0x4C49, 1014 0x4C4D, 1015 0x4C4E, 1016 0x4C50, 1017 0x4C51, 1018 0x4C52, 1019 0x4C53, 1020 0x5654, 1021 0x5655, 1022 0x5656, 1023 /* r128 */ 1024 0x4c45, 1025 0x4c46, 1026 0x4d46, 1027 0x4d4c, 1028 0x5041, 1029 0x5042, 1030 0x5043, 1031 0x5044, 1032 0x5045, 1033 0x5046, 1034 0x5047, 1035 0x5048, 1036 0x5049, 1037 0x504A, 1038 0x504B, 1039 0x504C, 1040 0x504D, 1041 0x504E, 1042 0x504F, 1043 0x5050, 1044 0x5051, 1045 0x5052, 1046 0x5053, 1047 0x5054, 1048 0x5055, 1049 0x5056, 1050 0x5057, 1051 0x5058, 1052 0x5245, 1053 0x5246, 1054 0x5247, 1055 0x524b, 1056 0x524c, 1057 0x534d, 1058 0x5446, 1059 0x544C, 1060 0x5452, 1061 /* radeon */ 1062 0x3150, 1063 0x3151, 1064 0x3152, 1065 0x3154, 1066 0x3155, 1067 0x3E50, 1068 0x3E54, 1069 0x4136, 1070 0x4137, 1071 0x4144, 1072 0x4145, 1073 0x4146, 1074 0x4147, 1075 0x4148, 1076 0x4149, 1077 0x414A, 1078 0x414B, 1079 0x4150, 1080 0x4151, 1081 0x4152, 1082 0x4153, 1083 0x4154, 1084 0x4155, 1085 0x4156, 1086 0x4237, 1087 0x4242, 1088 0x4336, 1089 0x4337, 1090 0x4437, 1091 0x4966, 1092 0x4967, 1093 0x4A48, 1094 0x4A49, 1095 0x4A4A, 1096 0x4A4B, 1097 0x4A4C, 1098 0x4A4D, 1099 0x4A4E, 1100 0x4A4F, 1101 0x4A50, 1102 0x4A54, 1103 0x4B48, 1104 0x4B49, 1105 0x4B4A, 1106 0x4B4B, 1107 0x4B4C, 1108 0x4C57, 1109 0x4C58, 1110 0x4C59, 1111 0x4C5A, 1112 0x4C64, 1113 0x4C66, 1114 0x4C67, 1115 0x4E44, 1116 0x4E45, 1117 0x4E46, 1118 0x4E47, 1119 0x4E48, 1120 0x4E49, 1121 0x4E4A, 1122 0x4E4B, 1123 0x4E50, 1124 0x4E51, 1125 0x4E52, 1126 0x4E53, 1127 0x4E54, 1128 0x4E56, 1129 0x5144, 1130 0x5145, 1131 0x5146, 1132 0x5147, 1133 0x5148, 1134 0x514C, 1135 0x514D, 1136 0x5157, 1137 0x5158, 1138 0x5159, 1139 0x515A, 1140 0x515E, 1141 0x5460, 1142 0x5462, 1143 0x5464, 1144 0x5548, 1145 0x5549, 1146 0x554A, 1147 0x554B, 1148 0x554C, 1149 0x554D, 1150 0x554E, 1151 0x554F, 1152 0x5550, 1153 0x5551, 1154 0x5552, 1155 0x5554, 1156 0x564A, 1157 0x564B, 1158 0x564F, 1159 0x5652, 1160 0x5653, 1161 0x5657, 1162 0x5834, 1163 0x5835, 1164 0x5954, 1165 0x5955, 1166 0x5974, 1167 0x5975, 1168 0x5960, 1169 0x5961, 1170 0x5962, 1171 0x5964, 1172 0x5965, 1173 0x5969, 1174 0x5a41, 1175 0x5a42, 1176 0x5a61, 1177 0x5a62, 1178 0x5b60, 1179 0x5b62, 1180 0x5b63, 1181 0x5b64, 1182 0x5b65, 1183 0x5c61, 1184 0x5c63, 1185 0x5d48, 1186 0x5d49, 1187 0x5d4a, 1188 0x5d4c, 1189 0x5d4d, 1190 0x5d4e, 1191 0x5d4f, 1192 0x5d50, 1193 0x5d52, 1194 0x5d57, 1195 0x5e48, 1196 0x5e4a, 1197 0x5e4b, 1198 0x5e4c, 1199 0x5e4d, 1200 0x5e4f, 1201 0x6700, 1202 0x6701, 1203 0x6702, 1204 0x6703, 1205 0x6704, 1206 0x6705, 1207 0x6706, 1208 0x6707, 1209 0x6708, 1210 0x6709, 1211 0x6718, 1212 0x6719, 1213 0x671c, 1214 0x671d, 1215 0x671f, 1216 0x6720, 1217 0x6721, 1218 0x6722, 1219 0x6723, 1220 0x6724, 1221 0x6725, 1222 0x6726, 1223 0x6727, 1224 0x6728, 1225 0x6729, 1226 0x6738, 1227 0x6739, 1228 0x673e, 1229 0x6740, 1230 0x6741, 1231 0x6742, 1232 0x6743, 1233 0x6744, 1234 0x6745, 1235 0x6746, 1236 0x6747, 1237 0x6748, 1238 0x6749, 1239 0x674A, 1240 0x6750, 1241 0x6751, 1242 0x6758, 1243 0x6759, 1244 0x675B, 1245 0x675D, 1246 0x675F, 1247 0x6760, 1248 0x6761, 1249 0x6762, 1250 0x6763, 1251 0x6764, 1252 0x6765, 1253 0x6766, 1254 0x6767, 1255 0x6768, 1256 0x6770, 1257 0x6771, 1258 0x6772, 1259 0x6778, 1260 0x6779, 1261 0x677B, 1262 0x6840, 1263 0x6841, 1264 0x6842, 1265 0x6843, 1266 0x6849, 1267 0x684C, 1268 0x6850, 1269 0x6858, 1270 0x6859, 1271 0x6880, 1272 0x6888, 1273 0x6889, 1274 0x688A, 1275 0x688C, 1276 0x688D, 1277 0x6898, 1278 0x6899, 1279 0x689b, 1280 0x689c, 1281 0x689d, 1282 0x689e, 1283 0x68a0, 1284 0x68a1, 1285 0x68a8, 1286 0x68a9, 1287 0x68b0, 1288 0x68b8, 1289 0x68b9, 1290 0x68ba, 1291 0x68be, 1292 0x68bf, 1293 0x68c0, 1294 0x68c1, 1295 0x68c7, 1296 0x68c8, 1297 0x68c9, 1298 0x68d8, 1299 0x68d9, 1300 0x68da, 1301 0x68de, 1302 0x68e0, 1303 0x68e1, 1304 0x68e4, 1305 0x68e5, 1306 0x68e8, 1307 0x68e9, 1308 0x68f1, 1309 0x68f2, 1310 0x68f8, 1311 0x68f9, 1312 0x68fa, 1313 0x68fe, 1314 0x7100, 1315 0x7101, 1316 0x7102, 1317 0x7103, 1318 0x7104, 1319 0x7105, 1320 0x7106, 1321 0x7108, 1322 0x7109, 1323 0x710A, 1324 0x710B, 1325 0x710C, 1326 0x710E, 1327 0x710F, 1328 0x7140, 1329 0x7141, 1330 0x7142, 1331 0x7143, 1332 0x7144, 1333 0x7145, 1334 0x7146, 1335 0x7147, 1336 0x7149, 1337 0x714A, 1338 0x714B, 1339 0x714C, 1340 0x714D, 1341 0x714E, 1342 0x714F, 1343 0x7151, 1344 0x7152, 1345 0x7153, 1346 0x715E, 1347 0x715F, 1348 0x7180, 1349 0x7181, 1350 0x7183, 1351 0x7186, 1352 0x7187, 1353 0x7188, 1354 0x718A, 1355 0x718B, 1356 0x718C, 1357 0x718D, 1358 0x718F, 1359 0x7193, 1360 0x7196, 1361 0x719B, 1362 0x719F, 1363 0x71C0, 1364 0x71C1, 1365 0x71C2, 1366 0x71C3, 1367 0x71C4, 1368 0x71C5, 1369 0x71C6, 1370 0x71C7, 1371 0x71CD, 1372 0x71CE, 1373 0x71D2, 1374 0x71D4, 1375 0x71D5, 1376 0x71D6, 1377 0x71DA, 1378 0x71DE, 1379 0x7200, 1380 0x7210, 1381 0x7211, 1382 0x7240, 1383 0x7243, 1384 0x7244, 1385 0x7245, 1386 0x7246, 1387 0x7247, 1388 0x7248, 1389 0x7249, 1390 0x724A, 1391 0x724B, 1392 0x724C, 1393 0x724D, 1394 0x724E, 1395 0x724F, 1396 0x7280, 1397 0x7281, 1398 0x7283, 1399 0x7284, 1400 0x7287, 1401 0x7288, 1402 0x7289, 1403 0x728B, 1404 0x728C, 1405 0x7290, 1406 0x7291, 1407 0x7293, 1408 0x7297, 1409 0x7834, 1410 0x7835, 1411 0x791e, 1412 0x791f, 1413 0x793f, 1414 0x7941, 1415 0x7942, 1416 0x796c, 1417 0x796d, 1418 0x796e, 1419 0x796f, 1420 0x9400, 1421 0x9401, 1422 0x9402, 1423 0x9403, 1424 0x9405, 1425 0x940A, 1426 0x940B, 1427 0x940F, 1428 0x94A0, 1429 0x94A1, 1430 0x94A3, 1431 0x94B1, 1432 0x94B3, 1433 0x94B4, 1434 0x94B5, 1435 0x94B9, 1436 0x9440, 1437 0x9441, 1438 0x9442, 1439 0x9443, 1440 0x9444, 1441 0x9446, 1442 0x944A, 1443 0x944B, 1444 0x944C, 1445 0x944E, 1446 0x9450, 1447 0x9452, 1448 0x9456, 1449 0x945A, 1450 0x945B, 1451 0x945E, 1452 0x9460, 1453 0x9462, 1454 0x946A, 1455 0x946B, 1456 0x947A, 1457 0x947B, 1458 0x9480, 1459 0x9487, 1460 0x9488, 1461 0x9489, 1462 0x948A, 1463 0x948F, 1464 0x9490, 1465 0x9491, 1466 0x9495, 1467 0x9498, 1468 0x949C, 1469 0x949E, 1470 0x949F, 1471 0x94C0, 1472 0x94C1, 1473 0x94C3, 1474 0x94C4, 1475 0x94C5, 1476 0x94C6, 1477 0x94C7, 1478 0x94C8, 1479 0x94C9, 1480 0x94CB, 1481 0x94CC, 1482 0x94CD, 1483 0x9500, 1484 0x9501, 1485 0x9504, 1486 0x9505, 1487 0x9506, 1488 0x9507, 1489 0x9508, 1490 0x9509, 1491 0x950F, 1492 0x9511, 1493 0x9515, 1494 0x9517, 1495 0x9519, 1496 0x9540, 1497 0x9541, 1498 0x9542, 1499 0x954E, 1500 0x954F, 1501 0x9552, 1502 0x9553, 1503 0x9555, 1504 0x9557, 1505 0x955f, 1506 0x9580, 1507 0x9581, 1508 0x9583, 1509 0x9586, 1510 0x9587, 1511 0x9588, 1512 0x9589, 1513 0x958A, 1514 0x958B, 1515 0x958C, 1516 0x958D, 1517 0x958E, 1518 0x958F, 1519 0x9590, 1520 0x9591, 1521 0x9593, 1522 0x9595, 1523 0x9596, 1524 0x9597, 1525 0x9598, 1526 0x9599, 1527 0x959B, 1528 0x95C0, 1529 0x95C2, 1530 0x95C4, 1531 0x95C5, 1532 0x95C6, 1533 0x95C7, 1534 0x95C9, 1535 0x95CC, 1536 0x95CD, 1537 0x95CE, 1538 0x95CF, 1539 0x9610, 1540 0x9611, 1541 0x9612, 1542 0x9613, 1543 0x9614, 1544 0x9615, 1545 0x9616, 1546 0x9640, 1547 0x9641, 1548 0x9642, 1549 0x9643, 1550 0x9644, 1551 0x9645, 1552 0x9647, 1553 0x9648, 1554 0x9649, 1555 0x964a, 1556 0x964b, 1557 0x964c, 1558 0x964e, 1559 0x964f, 1560 0x9710, 1561 0x9711, 1562 0x9712, 1563 0x9713, 1564 0x9714, 1565 0x9715, 1566 0x9802, 1567 0x9803, 1568 0x9804, 1569 0x9805, 1570 0x9806, 1571 0x9807, 1572 0x9808, 1573 0x9809, 1574 0x980A, 1575 0x9900, 1576 0x9901, 1577 0x9903, 1578 0x9904, 1579 0x9905, 1580 0x9906, 1581 0x9907, 1582 0x9908, 1583 0x9909, 1584 0x990A, 1585 0x990B, 1586 0x990C, 1587 0x990D, 1588 0x990E, 1589 0x990F, 1590 0x9910, 1591 0x9913, 1592 0x9917, 1593 0x9918, 1594 0x9919, 1595 0x9990, 1596 0x9991, 1597 0x9992, 1598 0x9993, 1599 0x9994, 1600 0x9995, 1601 0x9996, 1602 0x9997, 1603 0x9998, 1604 0x9999, 1605 0x999A, 1606 0x999B, 1607 0x999C, 1608 0x999D, 1609 0x99A0, 1610 0x99A2, 1611 0x99A4, 1612 /* radeon secondary ids */ 1613 0x3171, 1614 0x3e70, 1615 0x4164, 1616 0x4165, 1617 0x4166, 1618 0x4168, 1619 0x4170, 1620 0x4171, 1621 0x4172, 1622 0x4173, 1623 0x496e, 1624 0x4a69, 1625 0x4a6a, 1626 0x4a6b, 1627 0x4a70, 1628 0x4a74, 1629 0x4b69, 1630 0x4b6b, 1631 0x4b6c, 1632 0x4c6e, 1633 0x4e64, 1634 0x4e65, 1635 0x4e66, 1636 0x4e67, 1637 0x4e68, 1638 0x4e69, 1639 0x4e6a, 1640 0x4e71, 1641 0x4f73, 1642 0x5569, 1643 0x556b, 1644 0x556d, 1645 0x556f, 1646 0x5571, 1647 0x5854, 1648 0x5874, 1649 0x5940, 1650 0x5941, 1651 0x5b70, 1652 0x5b72, 1653 0x5b73, 1654 0x5b74, 1655 0x5b75, 1656 0x5d44, 1657 0x5d45, 1658 0x5d6d, 1659 0x5d6f, 1660 0x5d72, 1661 0x5d77, 1662 0x5e6b, 1663 0x5e6d, 1664 0x7120, 1665 0x7124, 1666 0x7129, 1667 0x712e, 1668 0x712f, 1669 0x7162, 1670 0x7163, 1671 0x7166, 1672 0x7167, 1673 0x7172, 1674 0x7173, 1675 0x71a0, 1676 0x71a1, 1677 0x71a3, 1678 0x71a7, 1679 0x71bb, 1680 0x71e0, 1681 0x71e1, 1682 0x71e2, 1683 0x71e6, 1684 0x71e7, 1685 0x71f2, 1686 0x7269, 1687 0x726b, 1688 0x726e, 1689 0x72a0, 1690 0x72a8, 1691 0x72b1, 1692 0x72b3, 1693 0x793f, 1694 }; 1695 1696 static const struct pci_device_id pciidlist[] = { 1697 #ifdef CONFIG_DRM_AMDGPU_SI 1698 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1699 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1700 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1701 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1702 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1703 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1704 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1705 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1706 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1707 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1708 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1709 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1710 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1711 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1712 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1715 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1716 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1717 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1718 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1719 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1720 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1721 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1722 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1723 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1729 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1730 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1731 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1732 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1733 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1734 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1735 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1737 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1738 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1739 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1740 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1741 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1742 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1743 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1744 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1745 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1746 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1747 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1748 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1749 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1750 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1751 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1752 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1753 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1754 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1755 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1757 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1758 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1759 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1760 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1761 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1762 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1763 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1764 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1765 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1766 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1767 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1768 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1769 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1770 #endif 1771 #ifdef CONFIG_DRM_AMDGPU_CIK 1772 /* Kaveri */ 1773 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1774 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1775 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1776 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1777 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1778 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1779 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1783 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1784 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1785 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1786 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1787 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1788 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1789 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1790 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1791 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1792 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1793 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1794 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1795 /* Bonaire */ 1796 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1797 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1798 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1799 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1800 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1801 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1802 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1803 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1804 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1805 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1806 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1807 /* Hawaii */ 1808 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1809 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1810 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1811 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1812 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1813 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1814 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1815 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1816 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1817 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1818 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1819 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1820 /* Kabini */ 1821 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1822 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1823 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1824 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1825 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1826 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1827 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1828 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1829 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1831 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1832 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1833 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1834 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1835 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1836 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1837 /* mullins */ 1838 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1839 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1840 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1841 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1842 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1843 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1844 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1845 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1846 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1847 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1848 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1849 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1850 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1851 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1852 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1853 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1854 #endif 1855 /* topaz */ 1856 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1857 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1858 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1859 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1860 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1861 /* tonga */ 1862 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1863 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1864 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1865 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1866 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1867 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1868 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1869 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1870 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1871 /* fiji */ 1872 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1873 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1874 /* carrizo */ 1875 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1876 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1877 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1878 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1879 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1880 /* stoney */ 1881 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1882 /* Polaris11 */ 1883 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1884 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1885 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1886 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1887 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1888 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1889 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1890 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1891 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1892 /* Polaris10 */ 1893 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1894 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1895 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1896 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1897 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1898 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1899 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1900 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1901 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1902 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1903 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1904 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1905 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1906 /* Polaris12 */ 1907 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1908 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1909 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1910 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1911 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1912 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1913 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1914 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1915 /* VEGAM */ 1916 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1917 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1918 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1919 /* Vega 10 */ 1920 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1921 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1922 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1923 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1924 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1925 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1926 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1927 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1928 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1929 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1930 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1931 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1932 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1933 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1934 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1935 /* Vega 12 */ 1936 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1937 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1938 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1939 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1940 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1941 /* Vega 20 */ 1942 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1943 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1944 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1945 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1946 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1947 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1948 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1949 /* Raven */ 1950 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1951 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1952 /* Arcturus */ 1953 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1954 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1955 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1956 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1957 /* Navi10 */ 1958 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1959 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1960 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1961 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1962 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1963 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1964 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1965 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1966 /* Navi14 */ 1967 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1968 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1969 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1970 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1971 1972 /* Renoir */ 1973 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1974 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1975 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1976 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1977 1978 /* Navi12 */ 1979 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1980 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1981 1982 /* Sienna_Cichlid */ 1983 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1984 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1985 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1986 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1987 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1988 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1989 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1990 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1991 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1992 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1993 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1994 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1995 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1996 1997 /* Yellow Carp */ 1998 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1999 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2000 2001 /* Navy_Flounder */ 2002 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2003 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2004 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2005 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2006 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2007 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2008 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2009 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2010 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2011 2012 /* DIMGREY_CAVEFISH */ 2013 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2014 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2015 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2016 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2017 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2018 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2019 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2020 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2021 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2022 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2023 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2024 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2025 2026 /* Aldebaran */ 2027 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2028 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2029 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2030 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2031 2032 /* CYAN_SKILLFISH */ 2033 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2034 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2035 2036 /* BEIGE_GOBY */ 2037 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2038 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2039 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2040 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2041 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2042 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2043 2044 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2045 .class = PCI_CLASS_DISPLAY_VGA << 8, 2046 .class_mask = 0xffffff, 2047 .driver_data = CHIP_IP_DISCOVERY }, 2048 2049 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2050 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2051 .class_mask = 0xffffff, 2052 .driver_data = CHIP_IP_DISCOVERY }, 2053 2054 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2055 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2056 .class_mask = 0xffffff, 2057 .driver_data = CHIP_IP_DISCOVERY }, 2058 2059 {0, 0, 0} 2060 }; 2061 2062 MODULE_DEVICE_TABLE(pci, pciidlist); 2063 2064 static const struct drm_driver amdgpu_kms_driver; 2065 2066 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2067 { 2068 struct pci_dev *p = NULL; 2069 int i; 2070 2071 /* 0 - GPU 2072 * 1 - audio 2073 * 2 - USB 2074 * 3 - UCSI 2075 */ 2076 for (i = 1; i < 4; i++) { 2077 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2078 adev->pdev->bus->number, i); 2079 if (p) { 2080 pm_runtime_get_sync(&p->dev); 2081 pm_runtime_mark_last_busy(&p->dev); 2082 pm_runtime_put_autosuspend(&p->dev); 2083 pci_dev_put(p); 2084 } 2085 } 2086 } 2087 2088 static int amdgpu_pci_probe(struct pci_dev *pdev, 2089 const struct pci_device_id *ent) 2090 { 2091 struct drm_device *ddev; 2092 struct amdgpu_device *adev; 2093 unsigned long flags = ent->driver_data; 2094 int ret, retry = 0, i; 2095 bool supports_atomic = false; 2096 2097 /* skip devices which are owned by radeon */ 2098 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2099 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2100 return -ENODEV; 2101 } 2102 2103 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2104 amdgpu_aspm = 0; 2105 2106 if (amdgpu_virtual_display || 2107 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2108 supports_atomic = true; 2109 2110 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2111 DRM_INFO("This hardware requires experimental hardware support.\n" 2112 "See modparam exp_hw_support\n"); 2113 return -ENODEV; 2114 } 2115 /* differentiate between P10 and P11 asics with the same DID */ 2116 if (pdev->device == 0x67FF && 2117 (pdev->revision == 0xE3 || 2118 pdev->revision == 0xE7 || 2119 pdev->revision == 0xF3 || 2120 pdev->revision == 0xF7)) { 2121 flags &= ~AMD_ASIC_MASK; 2122 flags |= CHIP_POLARIS10; 2123 } 2124 2125 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2126 * however, SME requires an indirect IOMMU mapping because the encryption 2127 * bit is beyond the DMA mask of the chip. 2128 */ 2129 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2130 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2131 dev_info(&pdev->dev, 2132 "SME is not compatible with RAVEN\n"); 2133 return -ENOTSUPP; 2134 } 2135 2136 #ifdef CONFIG_DRM_AMDGPU_SI 2137 if (!amdgpu_si_support) { 2138 switch (flags & AMD_ASIC_MASK) { 2139 case CHIP_TAHITI: 2140 case CHIP_PITCAIRN: 2141 case CHIP_VERDE: 2142 case CHIP_OLAND: 2143 case CHIP_HAINAN: 2144 dev_info(&pdev->dev, 2145 "SI support provided by radeon.\n"); 2146 dev_info(&pdev->dev, 2147 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2148 ); 2149 return -ENODEV; 2150 } 2151 } 2152 #endif 2153 #ifdef CONFIG_DRM_AMDGPU_CIK 2154 if (!amdgpu_cik_support) { 2155 switch (flags & AMD_ASIC_MASK) { 2156 case CHIP_KAVERI: 2157 case CHIP_BONAIRE: 2158 case CHIP_HAWAII: 2159 case CHIP_KABINI: 2160 case CHIP_MULLINS: 2161 dev_info(&pdev->dev, 2162 "CIK support provided by radeon.\n"); 2163 dev_info(&pdev->dev, 2164 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2165 ); 2166 return -ENODEV; 2167 } 2168 } 2169 #endif 2170 2171 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2172 if (IS_ERR(adev)) 2173 return PTR_ERR(adev); 2174 2175 adev->dev = &pdev->dev; 2176 adev->pdev = pdev; 2177 ddev = adev_to_drm(adev); 2178 2179 if (!supports_atomic) 2180 ddev->driver_features &= ~DRIVER_ATOMIC; 2181 2182 ret = pci_enable_device(pdev); 2183 if (ret) 2184 return ret; 2185 2186 pci_set_drvdata(pdev, ddev); 2187 2188 ret = amdgpu_driver_load_kms(adev, flags); 2189 if (ret) 2190 goto err_pci; 2191 2192 retry_init: 2193 ret = drm_dev_register(ddev, flags); 2194 if (ret == -EAGAIN && ++retry <= 3) { 2195 DRM_INFO("retry init %d\n", retry); 2196 /* Don't request EX mode too frequently which is attacking */ 2197 msleep(5000); 2198 goto retry_init; 2199 } else if (ret) { 2200 goto err_pci; 2201 } 2202 2203 ret = amdgpu_xcp_dev_register(adev, ent); 2204 if (ret) 2205 goto err_pci; 2206 2207 /* 2208 * 1. don't init fbdev on hw without DCE 2209 * 2. don't init fbdev if there are no connectors 2210 */ 2211 if (adev->mode_info.mode_config_initialized && 2212 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2213 /* select 8 bpp console on low vram cards */ 2214 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2215 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2216 else 2217 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2218 } 2219 2220 ret = amdgpu_debugfs_init(adev); 2221 if (ret) 2222 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2223 2224 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2225 /* only need to skip on ATPX */ 2226 if (amdgpu_device_supports_px(ddev)) 2227 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2228 /* we want direct complete for BOCO */ 2229 if (amdgpu_device_supports_boco(ddev)) 2230 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2231 DPM_FLAG_SMART_SUSPEND | 2232 DPM_FLAG_MAY_SKIP_RESUME); 2233 pm_runtime_use_autosuspend(ddev->dev); 2234 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2235 2236 pm_runtime_allow(ddev->dev); 2237 2238 pm_runtime_mark_last_busy(ddev->dev); 2239 pm_runtime_put_autosuspend(ddev->dev); 2240 2241 /* 2242 * For runpm implemented via BACO, PMFW will handle the 2243 * timing for BACO in and out: 2244 * - put ASIC into BACO state only when both video and 2245 * audio functions are in D3 state. 2246 * - pull ASIC out of BACO state when either video or 2247 * audio function is in D0 state. 2248 * Also, at startup, PMFW assumes both functions are in 2249 * D0 state. 2250 * 2251 * So if snd driver was loaded prior to amdgpu driver 2252 * and audio function was put into D3 state, there will 2253 * be no PMFW-aware D-state transition(D0->D3) on runpm 2254 * suspend. Thus the BACO will be not correctly kicked in. 2255 * 2256 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2257 * into D0 state. Then there will be a PMFW-aware D-state 2258 * transition(D0->D3) on runpm suspend. 2259 */ 2260 if (amdgpu_device_supports_baco(ddev) && 2261 !(adev->flags & AMD_IS_APU) && 2262 (adev->asic_type >= CHIP_NAVI10)) 2263 amdgpu_get_secondary_funcs(adev); 2264 } 2265 2266 return 0; 2267 2268 err_pci: 2269 pci_disable_device(pdev); 2270 return ret; 2271 } 2272 2273 static void 2274 amdgpu_pci_remove(struct pci_dev *pdev) 2275 { 2276 struct drm_device *dev = pci_get_drvdata(pdev); 2277 struct amdgpu_device *adev = drm_to_adev(dev); 2278 2279 amdgpu_xcp_dev_unplug(adev); 2280 drm_dev_unplug(dev); 2281 2282 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2283 pm_runtime_get_sync(dev->dev); 2284 pm_runtime_forbid(dev->dev); 2285 } 2286 2287 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2288 !amdgpu_sriov_vf(adev)) { 2289 bool need_to_reset_gpu = false; 2290 2291 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2292 struct amdgpu_hive_info *hive; 2293 2294 hive = amdgpu_get_xgmi_hive(adev); 2295 if (hive->device_remove_count == 0) 2296 need_to_reset_gpu = true; 2297 hive->device_remove_count++; 2298 amdgpu_put_xgmi_hive(hive); 2299 } else { 2300 need_to_reset_gpu = true; 2301 } 2302 2303 /* Workaround for ASICs need to reset SMU. 2304 * Called only when the first device is removed. 2305 */ 2306 if (need_to_reset_gpu) { 2307 struct amdgpu_reset_context reset_context; 2308 2309 adev->shutdown = true; 2310 memset(&reset_context, 0, sizeof(reset_context)); 2311 reset_context.method = AMD_RESET_METHOD_NONE; 2312 reset_context.reset_req_dev = adev; 2313 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2314 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2315 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2316 } 2317 } 2318 2319 amdgpu_driver_unload_kms(dev); 2320 2321 /* 2322 * Flush any in flight DMA operations from device. 2323 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2324 * StatusTransactions Pending bit. 2325 */ 2326 pci_disable_device(pdev); 2327 pci_wait_for_pending_transaction(pdev); 2328 } 2329 2330 static void 2331 amdgpu_pci_shutdown(struct pci_dev *pdev) 2332 { 2333 struct drm_device *dev = pci_get_drvdata(pdev); 2334 struct amdgpu_device *adev = drm_to_adev(dev); 2335 2336 if (amdgpu_ras_intr_triggered()) 2337 return; 2338 2339 /* if we are running in a VM, make sure the device 2340 * torn down properly on reboot/shutdown. 2341 * unfortunately we can't detect certain 2342 * hypervisors so just do this all the time. 2343 */ 2344 if (!amdgpu_passthrough(adev)) 2345 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2346 amdgpu_device_ip_suspend(adev); 2347 adev->mp1_state = PP_MP1_STATE_NONE; 2348 } 2349 2350 /** 2351 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2352 * 2353 * @work: work_struct. 2354 */ 2355 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2356 { 2357 struct list_head device_list; 2358 struct amdgpu_device *adev; 2359 int i, r; 2360 struct amdgpu_reset_context reset_context; 2361 2362 memset(&reset_context, 0, sizeof(reset_context)); 2363 2364 mutex_lock(&mgpu_info.mutex); 2365 if (mgpu_info.pending_reset == true) { 2366 mutex_unlock(&mgpu_info.mutex); 2367 return; 2368 } 2369 mgpu_info.pending_reset = true; 2370 mutex_unlock(&mgpu_info.mutex); 2371 2372 /* Use a common context, just need to make sure full reset is done */ 2373 reset_context.method = AMD_RESET_METHOD_NONE; 2374 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2375 2376 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2377 adev = mgpu_info.gpu_ins[i].adev; 2378 reset_context.reset_req_dev = adev; 2379 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2380 if (r) { 2381 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2382 r, adev_to_drm(adev)->unique); 2383 } 2384 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2385 r = -EALREADY; 2386 } 2387 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2388 adev = mgpu_info.gpu_ins[i].adev; 2389 flush_work(&adev->xgmi_reset_work); 2390 adev->gmc.xgmi.pending_reset = false; 2391 } 2392 2393 /* reset function will rebuild the xgmi hive info , clear it now */ 2394 for (i = 0; i < mgpu_info.num_dgpu; i++) 2395 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2396 2397 INIT_LIST_HEAD(&device_list); 2398 2399 for (i = 0; i < mgpu_info.num_dgpu; i++) 2400 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2401 2402 /* unregister the GPU first, reset function will add them back */ 2403 list_for_each_entry(adev, &device_list, reset_list) 2404 amdgpu_unregister_gpu_instance(adev); 2405 2406 /* Use a common context, just need to make sure full reset is done */ 2407 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2408 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2409 2410 if (r) { 2411 DRM_ERROR("reinit gpus failure"); 2412 return; 2413 } 2414 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2415 adev = mgpu_info.gpu_ins[i].adev; 2416 if (!adev->kfd.init_complete) 2417 amdgpu_amdkfd_device_init(adev); 2418 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2419 } 2420 return; 2421 } 2422 2423 static int amdgpu_pmops_prepare(struct device *dev) 2424 { 2425 struct drm_device *drm_dev = dev_get_drvdata(dev); 2426 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2427 2428 /* Return a positive number here so 2429 * DPM_FLAG_SMART_SUSPEND works properly 2430 */ 2431 if (amdgpu_device_supports_boco(drm_dev)) 2432 return pm_runtime_suspended(dev); 2433 2434 /* if we will not support s3 or s2i for the device 2435 * then skip suspend 2436 */ 2437 if (!amdgpu_acpi_is_s0ix_active(adev) && 2438 !amdgpu_acpi_is_s3_active(adev)) 2439 return 1; 2440 2441 return 0; 2442 } 2443 2444 static void amdgpu_pmops_complete(struct device *dev) 2445 { 2446 /* nothing to do */ 2447 } 2448 2449 static int amdgpu_pmops_suspend(struct device *dev) 2450 { 2451 struct drm_device *drm_dev = dev_get_drvdata(dev); 2452 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2453 2454 if (amdgpu_acpi_is_s0ix_active(adev)) 2455 adev->in_s0ix = true; 2456 else if (amdgpu_acpi_is_s3_active(adev)) 2457 adev->in_s3 = true; 2458 if (!adev->in_s0ix && !adev->in_s3) 2459 return 0; 2460 return amdgpu_device_suspend(drm_dev, true); 2461 } 2462 2463 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2464 { 2465 struct drm_device *drm_dev = dev_get_drvdata(dev); 2466 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2467 2468 if (amdgpu_acpi_should_gpu_reset(adev)) 2469 return amdgpu_asic_reset(adev); 2470 2471 return 0; 2472 } 2473 2474 static int amdgpu_pmops_resume(struct device *dev) 2475 { 2476 struct drm_device *drm_dev = dev_get_drvdata(dev); 2477 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2478 int r; 2479 2480 if (!adev->in_s0ix && !adev->in_s3) 2481 return 0; 2482 2483 /* Avoids registers access if device is physically gone */ 2484 if (!pci_device_is_present(adev->pdev)) 2485 adev->no_hw_access = true; 2486 2487 r = amdgpu_device_resume(drm_dev, true); 2488 if (amdgpu_acpi_is_s0ix_active(adev)) 2489 adev->in_s0ix = false; 2490 else 2491 adev->in_s3 = false; 2492 return r; 2493 } 2494 2495 static int amdgpu_pmops_freeze(struct device *dev) 2496 { 2497 struct drm_device *drm_dev = dev_get_drvdata(dev); 2498 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2499 int r; 2500 2501 adev->in_s4 = true; 2502 r = amdgpu_device_suspend(drm_dev, true); 2503 adev->in_s4 = false; 2504 if (r) 2505 return r; 2506 2507 if (amdgpu_acpi_should_gpu_reset(adev)) 2508 return amdgpu_asic_reset(adev); 2509 return 0; 2510 } 2511 2512 static int amdgpu_pmops_thaw(struct device *dev) 2513 { 2514 struct drm_device *drm_dev = dev_get_drvdata(dev); 2515 2516 return amdgpu_device_resume(drm_dev, true); 2517 } 2518 2519 static int amdgpu_pmops_poweroff(struct device *dev) 2520 { 2521 struct drm_device *drm_dev = dev_get_drvdata(dev); 2522 2523 return amdgpu_device_suspend(drm_dev, true); 2524 } 2525 2526 static int amdgpu_pmops_restore(struct device *dev) 2527 { 2528 struct drm_device *drm_dev = dev_get_drvdata(dev); 2529 2530 return amdgpu_device_resume(drm_dev, true); 2531 } 2532 2533 static int amdgpu_runtime_idle_check_display(struct device *dev) 2534 { 2535 struct pci_dev *pdev = to_pci_dev(dev); 2536 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2537 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2538 2539 if (adev->mode_info.num_crtc) { 2540 struct drm_connector *list_connector; 2541 struct drm_connector_list_iter iter; 2542 int ret = 0; 2543 2544 /* XXX: Return busy if any displays are connected to avoid 2545 * possible display wakeups after runtime resume due to 2546 * hotplug events in case any displays were connected while 2547 * the GPU was in suspend. Remove this once that is fixed. 2548 */ 2549 mutex_lock(&drm_dev->mode_config.mutex); 2550 drm_connector_list_iter_begin(drm_dev, &iter); 2551 drm_for_each_connector_iter(list_connector, &iter) { 2552 if (list_connector->status == connector_status_connected) { 2553 ret = -EBUSY; 2554 break; 2555 } 2556 } 2557 drm_connector_list_iter_end(&iter); 2558 mutex_unlock(&drm_dev->mode_config.mutex); 2559 2560 if (ret) 2561 return ret; 2562 2563 if (adev->dc_enabled) { 2564 struct drm_crtc *crtc; 2565 2566 drm_for_each_crtc(crtc, drm_dev) { 2567 drm_modeset_lock(&crtc->mutex, NULL); 2568 if (crtc->state->active) 2569 ret = -EBUSY; 2570 drm_modeset_unlock(&crtc->mutex); 2571 if (ret < 0) 2572 break; 2573 } 2574 } else { 2575 mutex_lock(&drm_dev->mode_config.mutex); 2576 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2577 2578 drm_connector_list_iter_begin(drm_dev, &iter); 2579 drm_for_each_connector_iter(list_connector, &iter) { 2580 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2581 ret = -EBUSY; 2582 break; 2583 } 2584 } 2585 2586 drm_connector_list_iter_end(&iter); 2587 2588 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2589 mutex_unlock(&drm_dev->mode_config.mutex); 2590 } 2591 if (ret) 2592 return ret; 2593 } 2594 2595 return 0; 2596 } 2597 2598 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2599 { 2600 struct pci_dev *pdev = to_pci_dev(dev); 2601 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2602 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2603 int ret, i; 2604 2605 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2606 pm_runtime_forbid(dev); 2607 return -EBUSY; 2608 } 2609 2610 ret = amdgpu_runtime_idle_check_display(dev); 2611 if (ret) 2612 return ret; 2613 2614 /* wait for all rings to drain before suspending */ 2615 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2616 struct amdgpu_ring *ring = adev->rings[i]; 2617 if (ring && ring->sched.ready) { 2618 ret = amdgpu_fence_wait_empty(ring); 2619 if (ret) 2620 return -EBUSY; 2621 } 2622 } 2623 2624 adev->in_runpm = true; 2625 if (amdgpu_device_supports_px(drm_dev)) 2626 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2627 2628 /* 2629 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2630 * proper cleanups and put itself into a state ready for PNP. That 2631 * can address some random resuming failure observed on BOCO capable 2632 * platforms. 2633 * TODO: this may be also needed for PX capable platform. 2634 */ 2635 if (amdgpu_device_supports_boco(drm_dev)) 2636 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2637 2638 ret = amdgpu_device_suspend(drm_dev, false); 2639 if (ret) { 2640 adev->in_runpm = false; 2641 if (amdgpu_device_supports_boco(drm_dev)) 2642 adev->mp1_state = PP_MP1_STATE_NONE; 2643 return ret; 2644 } 2645 2646 if (amdgpu_device_supports_boco(drm_dev)) 2647 adev->mp1_state = PP_MP1_STATE_NONE; 2648 2649 if (amdgpu_device_supports_px(drm_dev)) { 2650 /* Only need to handle PCI state in the driver for ATPX 2651 * PCI core handles it for _PR3. 2652 */ 2653 amdgpu_device_cache_pci_state(pdev); 2654 pci_disable_device(pdev); 2655 pci_ignore_hotplug(pdev); 2656 pci_set_power_state(pdev, PCI_D3cold); 2657 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2658 } else if (amdgpu_device_supports_boco(drm_dev)) { 2659 /* nothing to do */ 2660 } else if (amdgpu_device_supports_baco(drm_dev)) { 2661 amdgpu_device_baco_enter(drm_dev); 2662 } 2663 2664 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2665 2666 return 0; 2667 } 2668 2669 static int amdgpu_pmops_runtime_resume(struct device *dev) 2670 { 2671 struct pci_dev *pdev = to_pci_dev(dev); 2672 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2673 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2674 int ret; 2675 2676 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2677 return -EINVAL; 2678 2679 /* Avoids registers access if device is physically gone */ 2680 if (!pci_device_is_present(adev->pdev)) 2681 adev->no_hw_access = true; 2682 2683 if (amdgpu_device_supports_px(drm_dev)) { 2684 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2685 2686 /* Only need to handle PCI state in the driver for ATPX 2687 * PCI core handles it for _PR3. 2688 */ 2689 pci_set_power_state(pdev, PCI_D0); 2690 amdgpu_device_load_pci_state(pdev); 2691 ret = pci_enable_device(pdev); 2692 if (ret) 2693 return ret; 2694 pci_set_master(pdev); 2695 } else if (amdgpu_device_supports_boco(drm_dev)) { 2696 /* Only need to handle PCI state in the driver for ATPX 2697 * PCI core handles it for _PR3. 2698 */ 2699 pci_set_master(pdev); 2700 } else if (amdgpu_device_supports_baco(drm_dev)) { 2701 amdgpu_device_baco_exit(drm_dev); 2702 } 2703 ret = amdgpu_device_resume(drm_dev, false); 2704 if (ret) { 2705 if (amdgpu_device_supports_px(drm_dev)) 2706 pci_disable_device(pdev); 2707 return ret; 2708 } 2709 2710 if (amdgpu_device_supports_px(drm_dev)) 2711 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2712 adev->in_runpm = false; 2713 return 0; 2714 } 2715 2716 static int amdgpu_pmops_runtime_idle(struct device *dev) 2717 { 2718 struct drm_device *drm_dev = dev_get_drvdata(dev); 2719 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2720 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2721 int ret = 1; 2722 2723 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2724 pm_runtime_forbid(dev); 2725 return -EBUSY; 2726 } 2727 2728 ret = amdgpu_runtime_idle_check_display(dev); 2729 2730 pm_runtime_mark_last_busy(dev); 2731 pm_runtime_autosuspend(dev); 2732 return ret; 2733 } 2734 2735 long amdgpu_drm_ioctl(struct file *filp, 2736 unsigned int cmd, unsigned long arg) 2737 { 2738 struct drm_file *file_priv = filp->private_data; 2739 struct drm_device *dev; 2740 long ret; 2741 dev = file_priv->minor->dev; 2742 ret = pm_runtime_get_sync(dev->dev); 2743 if (ret < 0) 2744 goto out; 2745 2746 ret = drm_ioctl(filp, cmd, arg); 2747 2748 pm_runtime_mark_last_busy(dev->dev); 2749 out: 2750 pm_runtime_put_autosuspend(dev->dev); 2751 return ret; 2752 } 2753 2754 static const struct dev_pm_ops amdgpu_pm_ops = { 2755 .prepare = amdgpu_pmops_prepare, 2756 .complete = amdgpu_pmops_complete, 2757 .suspend = amdgpu_pmops_suspend, 2758 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2759 .resume = amdgpu_pmops_resume, 2760 .freeze = amdgpu_pmops_freeze, 2761 .thaw = amdgpu_pmops_thaw, 2762 .poweroff = amdgpu_pmops_poweroff, 2763 .restore = amdgpu_pmops_restore, 2764 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2765 .runtime_resume = amdgpu_pmops_runtime_resume, 2766 .runtime_idle = amdgpu_pmops_runtime_idle, 2767 }; 2768 2769 static int amdgpu_flush(struct file *f, fl_owner_t id) 2770 { 2771 struct drm_file *file_priv = f->private_data; 2772 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2773 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2774 2775 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2776 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2777 2778 return timeout >= 0 ? 0 : timeout; 2779 } 2780 2781 static const struct file_operations amdgpu_driver_kms_fops = { 2782 .owner = THIS_MODULE, 2783 .open = drm_open, 2784 .flush = amdgpu_flush, 2785 .release = drm_release, 2786 .unlocked_ioctl = amdgpu_drm_ioctl, 2787 .mmap = drm_gem_mmap, 2788 .poll = drm_poll, 2789 .read = drm_read, 2790 #ifdef CONFIG_COMPAT 2791 .compat_ioctl = amdgpu_kms_compat_ioctl, 2792 #endif 2793 #ifdef CONFIG_PROC_FS 2794 .show_fdinfo = drm_show_fdinfo, 2795 #endif 2796 }; 2797 2798 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2799 { 2800 struct drm_file *file; 2801 2802 if (!filp) 2803 return -EINVAL; 2804 2805 if (filp->f_op != &amdgpu_driver_kms_fops) { 2806 return -EINVAL; 2807 } 2808 2809 file = filp->private_data; 2810 *fpriv = file->driver_priv; 2811 return 0; 2812 } 2813 2814 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2815 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2816 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2817 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2818 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2819 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2820 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2821 /* KMS */ 2822 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2823 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2824 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2825 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2826 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2827 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2828 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2829 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2830 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2831 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2832 }; 2833 2834 static const struct drm_driver amdgpu_kms_driver = { 2835 .driver_features = 2836 DRIVER_ATOMIC | 2837 DRIVER_GEM | 2838 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2839 DRIVER_SYNCOBJ_TIMELINE, 2840 .open = amdgpu_driver_open_kms, 2841 .postclose = amdgpu_driver_postclose_kms, 2842 .lastclose = amdgpu_driver_lastclose_kms, 2843 .ioctls = amdgpu_ioctls_kms, 2844 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2845 .dumb_create = amdgpu_mode_dumb_create, 2846 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2847 .fops = &amdgpu_driver_kms_fops, 2848 .release = &amdgpu_driver_release_kms, 2849 #ifdef CONFIG_PROC_FS 2850 .show_fdinfo = amdgpu_show_fdinfo, 2851 #endif 2852 2853 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2854 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2855 .gem_prime_import = amdgpu_gem_prime_import, 2856 .gem_prime_mmap = drm_gem_prime_mmap, 2857 2858 .name = DRIVER_NAME, 2859 .desc = DRIVER_DESC, 2860 .date = DRIVER_DATE, 2861 .major = KMS_DRIVER_MAJOR, 2862 .minor = KMS_DRIVER_MINOR, 2863 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2864 }; 2865 2866 const struct drm_driver amdgpu_partition_driver = { 2867 .driver_features = 2868 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2869 DRIVER_SYNCOBJ_TIMELINE, 2870 .open = amdgpu_driver_open_kms, 2871 .postclose = amdgpu_driver_postclose_kms, 2872 .lastclose = amdgpu_driver_lastclose_kms, 2873 .ioctls = amdgpu_ioctls_kms, 2874 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2875 .dumb_create = amdgpu_mode_dumb_create, 2876 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2877 .fops = &amdgpu_driver_kms_fops, 2878 .release = &amdgpu_driver_release_kms, 2879 2880 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2881 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2882 .gem_prime_import = amdgpu_gem_prime_import, 2883 .gem_prime_mmap = drm_gem_prime_mmap, 2884 2885 .name = DRIVER_NAME, 2886 .desc = DRIVER_DESC, 2887 .date = DRIVER_DATE, 2888 .major = KMS_DRIVER_MAJOR, 2889 .minor = KMS_DRIVER_MINOR, 2890 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2891 }; 2892 2893 static struct pci_error_handlers amdgpu_pci_err_handler = { 2894 .error_detected = amdgpu_pci_error_detected, 2895 .mmio_enabled = amdgpu_pci_mmio_enabled, 2896 .slot_reset = amdgpu_pci_slot_reset, 2897 .resume = amdgpu_pci_resume, 2898 }; 2899 2900 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2901 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2902 2903 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2904 &amdgpu_vram_mgr_attr_group, 2905 &amdgpu_gtt_mgr_attr_group, 2906 NULL, 2907 }; 2908 2909 2910 static struct pci_driver amdgpu_kms_pci_driver = { 2911 .name = DRIVER_NAME, 2912 .id_table = pciidlist, 2913 .probe = amdgpu_pci_probe, 2914 .remove = amdgpu_pci_remove, 2915 .shutdown = amdgpu_pci_shutdown, 2916 .driver.pm = &amdgpu_pm_ops, 2917 .err_handler = &amdgpu_pci_err_handler, 2918 .dev_groups = amdgpu_sysfs_groups, 2919 }; 2920 2921 static int __init amdgpu_init(void) 2922 { 2923 int r; 2924 2925 if (drm_firmware_drivers_only()) 2926 return -EINVAL; 2927 2928 r = amdgpu_sync_init(); 2929 if (r) 2930 goto error_sync; 2931 2932 r = amdgpu_fence_slab_init(); 2933 if (r) 2934 goto error_fence; 2935 2936 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2937 amdgpu_register_atpx_handler(); 2938 amdgpu_acpi_detect(); 2939 2940 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2941 amdgpu_amdkfd_init(); 2942 2943 /* let modprobe override vga console setting */ 2944 return pci_register_driver(&amdgpu_kms_pci_driver); 2945 2946 error_fence: 2947 amdgpu_sync_fini(); 2948 2949 error_sync: 2950 return r; 2951 } 2952 2953 static void __exit amdgpu_exit(void) 2954 { 2955 amdgpu_amdkfd_fini(); 2956 pci_unregister_driver(&amdgpu_kms_pci_driver); 2957 amdgpu_unregister_atpx_handler(); 2958 amdgpu_acpi_release(); 2959 amdgpu_sync_fini(); 2960 amdgpu_fence_slab_fini(); 2961 mmu_notifier_synchronize(); 2962 amdgpu_xcp_drv_release(); 2963 } 2964 2965 module_init(amdgpu_init); 2966 module_exit(amdgpu_exit); 2967 2968 MODULE_AUTHOR(DRIVER_AUTHOR); 2969 MODULE_DESCRIPTION(DRIVER_DESC); 2970 MODULE_LICENSE("GPL and additional rights"); 2971