1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_generic.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_vblank.h> 31 #include <drm/drm_managed.h> 32 #include "amdgpu_drv.h" 33 34 #include <drm/drm_pciids.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/cc_platform.h> 42 #include <linux/fb.h> 43 #include <linux/dynamic_debug.h> 44 45 #include "amdgpu.h" 46 #include "amdgpu_irq.h" 47 #include "amdgpu_dma_buf.h" 48 #include "amdgpu_sched.h" 49 #include "amdgpu_fdinfo.h" 50 #include "amdgpu_amdkfd.h" 51 52 #include "amdgpu_ras.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_reset.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * 3.49.0 - Add gang submit into CS IOCTL 109 */ 110 #define KMS_DRIVER_MAJOR 3 111 #define KMS_DRIVER_MINOR 49 112 #define KMS_DRIVER_PATCHLEVEL 0 113 114 int amdgpu_vram_limit; 115 int amdgpu_vis_vram_limit; 116 int amdgpu_gart_size = -1; /* auto */ 117 int amdgpu_gtt_size = -1; /* auto */ 118 int amdgpu_moverate = -1; /* auto */ 119 int amdgpu_audio = -1; 120 int amdgpu_disp_priority; 121 int amdgpu_hw_i2c; 122 int amdgpu_pcie_gen2 = -1; 123 int amdgpu_msi = -1; 124 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 125 int amdgpu_dpm = -1; 126 int amdgpu_fw_load_type = -1; 127 int amdgpu_aspm = -1; 128 int amdgpu_runtime_pm = -1; 129 uint amdgpu_ip_block_mask = 0xffffffff; 130 int amdgpu_bapm = -1; 131 int amdgpu_deep_color; 132 int amdgpu_vm_size = -1; 133 int amdgpu_vm_fragment_size = -1; 134 int amdgpu_vm_block_size = -1; 135 int amdgpu_vm_fault_stop; 136 int amdgpu_vm_debug; 137 int amdgpu_vm_update_mode = -1; 138 int amdgpu_exp_hw_support; 139 int amdgpu_dc = -1; 140 int amdgpu_sched_jobs = 32; 141 int amdgpu_sched_hw_submission = 2; 142 uint amdgpu_pcie_gen_cap; 143 uint amdgpu_pcie_lane_cap; 144 u64 amdgpu_cg_mask = 0xffffffffffffffff; 145 uint amdgpu_pg_mask = 0xffffffff; 146 uint amdgpu_sdma_phase_quantum = 32; 147 char *amdgpu_disable_cu = NULL; 148 char *amdgpu_virtual_display = NULL; 149 150 /* 151 * OverDrive(bit 14) disabled by default 152 * GFX DCS(bit 19) disabled by default 153 */ 154 uint amdgpu_pp_feature_mask = 0xfff7bfff; 155 uint amdgpu_force_long_training; 156 int amdgpu_job_hang_limit; 157 int amdgpu_lbpw = -1; 158 int amdgpu_compute_multipipe = -1; 159 int amdgpu_gpu_recovery = -1; /* auto */ 160 int amdgpu_emu_mode; 161 uint amdgpu_smu_memory_pool_size; 162 int amdgpu_smu_pptable_id = -1; 163 /* 164 * FBC (bit 0) disabled by default 165 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 166 * - With this, for multiple monitors in sync(e.g. with the same model), 167 * mclk switching will be allowed. And the mclk will be not foced to the 168 * highest. That helps saving some idle power. 169 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 170 * PSR (bit 3) disabled by default 171 * EDP NO POWER SEQUENCING (bit 4) disabled by default 172 */ 173 uint amdgpu_dc_feature_mask = 2; 174 uint amdgpu_dc_debug_mask; 175 uint amdgpu_dc_visual_confirm; 176 int amdgpu_async_gfx_ring = 1; 177 int amdgpu_mcbp; 178 int amdgpu_discovery = -1; 179 int amdgpu_mes; 180 int amdgpu_mes_kiq; 181 int amdgpu_noretry = -1; 182 int amdgpu_force_asic_type = -1; 183 int amdgpu_tmz = -1; /* auto */ 184 int amdgpu_reset_method = -1; /* auto */ 185 int amdgpu_num_kcq = -1; 186 int amdgpu_smartshift_bias; 187 int amdgpu_use_xgmi_p2p = 1; 188 int amdgpu_vcnfw_log; 189 190 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 191 192 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 193 "DRM_UT_CORE", 194 "DRM_UT_DRIVER", 195 "DRM_UT_KMS", 196 "DRM_UT_PRIME", 197 "DRM_UT_ATOMIC", 198 "DRM_UT_VBL", 199 "DRM_UT_STATE", 200 "DRM_UT_LEASE", 201 "DRM_UT_DP", 202 "DRM_UT_DRMRES"); 203 204 struct amdgpu_mgpu_info mgpu_info = { 205 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 206 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 207 mgpu_info.delayed_reset_work, 208 amdgpu_drv_delayed_reset_work_handler, 0), 209 }; 210 int amdgpu_ras_enable = -1; 211 uint amdgpu_ras_mask = 0xffffffff; 212 int amdgpu_bad_page_threshold = -1; 213 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 214 .timeout_fatal_disable = false, 215 .period = 0x0, /* default to 0x0 (timeout disable) */ 216 }; 217 218 /** 219 * DOC: vramlimit (int) 220 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 221 */ 222 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 223 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 224 225 /** 226 * DOC: vis_vramlimit (int) 227 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 228 */ 229 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 230 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 231 232 /** 233 * DOC: gartsize (uint) 234 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 235 * The default is -1 (The size depends on asic). 236 */ 237 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 238 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 239 240 /** 241 * DOC: gttsize (int) 242 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 243 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 244 */ 245 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 246 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 247 248 /** 249 * DOC: moverate (int) 250 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 251 */ 252 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 253 module_param_named(moverate, amdgpu_moverate, int, 0600); 254 255 /** 256 * DOC: audio (int) 257 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 258 */ 259 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 260 module_param_named(audio, amdgpu_audio, int, 0444); 261 262 /** 263 * DOC: disp_priority (int) 264 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 265 */ 266 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 267 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 268 269 /** 270 * DOC: hw_i2c (int) 271 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 272 */ 273 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 274 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 275 276 /** 277 * DOC: pcie_gen2 (int) 278 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 279 */ 280 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 281 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 282 283 /** 284 * DOC: msi (int) 285 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 286 */ 287 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 288 module_param_named(msi, amdgpu_msi, int, 0444); 289 290 /** 291 * DOC: lockup_timeout (string) 292 * Set GPU scheduler timeout value in ms. 293 * 294 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 295 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 296 * to the default timeout. 297 * 298 * - With one value specified, the setting will apply to all non-compute jobs. 299 * - With multiple values specified, the first one will be for GFX. 300 * The second one is for Compute. The third and fourth ones are 301 * for SDMA and Video. 302 * 303 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 304 * jobs is 10000. The timeout for compute is 60000. 305 */ 306 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 307 "for passthrough or sriov, 10000 for all jobs." 308 " 0: keep default value. negative: infinity timeout), " 309 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 310 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 311 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 312 313 /** 314 * DOC: dpm (int) 315 * Override for dynamic power management setting 316 * (0 = disable, 1 = enable) 317 * The default is -1 (auto). 318 */ 319 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 320 module_param_named(dpm, amdgpu_dpm, int, 0444); 321 322 /** 323 * DOC: fw_load_type (int) 324 * Set different firmware loading type for debugging, if supported. 325 * Set to 0 to force direct loading if supported by the ASIC. Set 326 * to -1 to select the default loading mode for the ASIC, as defined 327 * by the driver. The default is -1 (auto). 328 */ 329 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 330 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 331 332 /** 333 * DOC: aspm (int) 334 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 335 */ 336 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 337 module_param_named(aspm, amdgpu_aspm, int, 0444); 338 339 /** 340 * DOC: runpm (int) 341 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 342 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 343 * Setting the value to 0 disables this functionality. 344 */ 345 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 346 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 347 348 /** 349 * DOC: ip_block_mask (uint) 350 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 351 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 352 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 353 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 354 */ 355 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 356 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 357 358 /** 359 * DOC: bapm (int) 360 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 361 * The default -1 (auto, enabled) 362 */ 363 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 364 module_param_named(bapm, amdgpu_bapm, int, 0444); 365 366 /** 367 * DOC: deep_color (int) 368 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 369 */ 370 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 371 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 372 373 /** 374 * DOC: vm_size (int) 375 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 376 */ 377 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 378 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 379 380 /** 381 * DOC: vm_fragment_size (int) 382 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 383 */ 384 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 385 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 386 387 /** 388 * DOC: vm_block_size (int) 389 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 390 */ 391 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 392 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 393 394 /** 395 * DOC: vm_fault_stop (int) 396 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 397 */ 398 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 399 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 400 401 /** 402 * DOC: vm_debug (int) 403 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 404 */ 405 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 406 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 407 408 /** 409 * DOC: vm_update_mode (int) 410 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 411 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 412 */ 413 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 414 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 415 416 /** 417 * DOC: exp_hw_support (int) 418 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 419 */ 420 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 421 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 422 423 /** 424 * DOC: dc (int) 425 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 426 */ 427 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 428 module_param_named(dc, amdgpu_dc, int, 0444); 429 430 /** 431 * DOC: sched_jobs (int) 432 * Override the max number of jobs supported in the sw queue. The default is 32. 433 */ 434 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 435 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 436 437 /** 438 * DOC: sched_hw_submission (int) 439 * Override the max number of HW submissions. The default is 2. 440 */ 441 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 442 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 443 444 /** 445 * DOC: ppfeaturemask (hexint) 446 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 447 * The default is the current set of stable power features. 448 */ 449 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 450 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 451 452 /** 453 * DOC: forcelongtraining (uint) 454 * Force long memory training in resume. 455 * The default is zero, indicates short training in resume. 456 */ 457 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 458 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 459 460 /** 461 * DOC: pcie_gen_cap (uint) 462 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 463 * The default is 0 (automatic for each asic). 464 */ 465 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 466 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 467 468 /** 469 * DOC: pcie_lane_cap (uint) 470 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 471 * The default is 0 (automatic for each asic). 472 */ 473 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 474 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 475 476 /** 477 * DOC: cg_mask (ullong) 478 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 479 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 480 */ 481 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 482 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 483 484 /** 485 * DOC: pg_mask (uint) 486 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 487 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 488 */ 489 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 490 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 491 492 /** 493 * DOC: sdma_phase_quantum (uint) 494 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 495 */ 496 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 497 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 498 499 /** 500 * DOC: disable_cu (charp) 501 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 502 */ 503 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 504 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 505 506 /** 507 * DOC: virtual_display (charp) 508 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 509 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 510 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 511 * device at 26:00.0. The default is NULL. 512 */ 513 MODULE_PARM_DESC(virtual_display, 514 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 515 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 516 517 /** 518 * DOC: job_hang_limit (int) 519 * Set how much time allow a job hang and not drop it. The default is 0. 520 */ 521 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 522 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 523 524 /** 525 * DOC: lbpw (int) 526 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 527 */ 528 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 529 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 530 531 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 532 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 533 534 /** 535 * DOC: gpu_recovery (int) 536 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 537 */ 538 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 539 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 540 541 /** 542 * DOC: emu_mode (int) 543 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 544 */ 545 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 546 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 547 548 /** 549 * DOC: ras_enable (int) 550 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 551 */ 552 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 553 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 554 555 /** 556 * DOC: ras_mask (uint) 557 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 558 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 559 */ 560 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 561 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 562 563 /** 564 * DOC: timeout_fatal_disable (bool) 565 * Disable Watchdog timeout fatal error event 566 */ 567 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 568 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 569 570 /** 571 * DOC: timeout_period (uint) 572 * Modify the watchdog timeout max_cycles as (1 << period) 573 */ 574 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 575 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 576 577 /** 578 * DOC: si_support (int) 579 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 581 * otherwise using amdgpu driver. 582 */ 583 #ifdef CONFIG_DRM_AMDGPU_SI 584 585 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 586 int amdgpu_si_support = 0; 587 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 588 #else 589 int amdgpu_si_support = 1; 590 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 591 #endif 592 593 module_param_named(si_support, amdgpu_si_support, int, 0444); 594 #endif 595 596 /** 597 * DOC: cik_support (int) 598 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 599 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 600 * otherwise using amdgpu driver. 601 */ 602 #ifdef CONFIG_DRM_AMDGPU_CIK 603 604 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 605 int amdgpu_cik_support = 0; 606 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 607 #else 608 int amdgpu_cik_support = 1; 609 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 610 #endif 611 612 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 613 #endif 614 615 /** 616 * DOC: smu_memory_pool_size (uint) 617 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 618 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 619 */ 620 MODULE_PARM_DESC(smu_memory_pool_size, 621 "reserve gtt for smu debug usage, 0 = disable," 622 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 623 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 624 625 /** 626 * DOC: async_gfx_ring (int) 627 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 628 */ 629 MODULE_PARM_DESC(async_gfx_ring, 630 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 631 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 632 633 /** 634 * DOC: mcbp (int) 635 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 636 */ 637 MODULE_PARM_DESC(mcbp, 638 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 639 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 640 641 /** 642 * DOC: discovery (int) 643 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 644 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 645 */ 646 MODULE_PARM_DESC(discovery, 647 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 648 module_param_named(discovery, amdgpu_discovery, int, 0444); 649 650 /** 651 * DOC: mes (int) 652 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 653 * (0 = disabled (default), 1 = enabled) 654 */ 655 MODULE_PARM_DESC(mes, 656 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 657 module_param_named(mes, amdgpu_mes, int, 0444); 658 659 /** 660 * DOC: mes_kiq (int) 661 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 662 * (0 = disabled (default), 1 = enabled) 663 */ 664 MODULE_PARM_DESC(mes_kiq, 665 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 666 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 667 668 /** 669 * DOC: noretry (int) 670 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 671 * do not support per-process XNACK this also disables retry page faults. 672 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 673 */ 674 MODULE_PARM_DESC(noretry, 675 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 676 module_param_named(noretry, amdgpu_noretry, int, 0644); 677 678 /** 679 * DOC: force_asic_type (int) 680 * A non negative value used to specify the asic type for all supported GPUs. 681 */ 682 MODULE_PARM_DESC(force_asic_type, 683 "A non negative value used to specify the asic type for all supported GPUs"); 684 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 685 686 /** 687 * DOC: use_xgmi_p2p (int) 688 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 689 */ 690 MODULE_PARM_DESC(use_xgmi_p2p, 691 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 692 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 693 694 695 #ifdef CONFIG_HSA_AMD 696 /** 697 * DOC: sched_policy (int) 698 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 699 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 700 * assigns queues to HQDs. 701 */ 702 int sched_policy = KFD_SCHED_POLICY_HWS; 703 module_param(sched_policy, int, 0444); 704 MODULE_PARM_DESC(sched_policy, 705 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 706 707 /** 708 * DOC: hws_max_conc_proc (int) 709 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 710 * number of VMIDs assigned to the HWS, which is also the default. 711 */ 712 int hws_max_conc_proc = -1; 713 module_param(hws_max_conc_proc, int, 0444); 714 MODULE_PARM_DESC(hws_max_conc_proc, 715 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 716 717 /** 718 * DOC: cwsr_enable (int) 719 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 720 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 721 * disables it. 722 */ 723 int cwsr_enable = 1; 724 module_param(cwsr_enable, int, 0444); 725 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 726 727 /** 728 * DOC: max_num_of_queues_per_device (int) 729 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 730 * is 4096. 731 */ 732 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 733 module_param(max_num_of_queues_per_device, int, 0444); 734 MODULE_PARM_DESC(max_num_of_queues_per_device, 735 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 736 737 /** 738 * DOC: send_sigterm (int) 739 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 740 * but just print errors on dmesg. Setting 1 enables sending sigterm. 741 */ 742 int send_sigterm; 743 module_param(send_sigterm, int, 0444); 744 MODULE_PARM_DESC(send_sigterm, 745 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 746 747 /** 748 * DOC: debug_largebar (int) 749 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 750 * system. This limits the VRAM size reported to ROCm applications to the visible 751 * size, usually 256MB. 752 * Default value is 0, diabled. 753 */ 754 int debug_largebar; 755 module_param(debug_largebar, int, 0444); 756 MODULE_PARM_DESC(debug_largebar, 757 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 758 759 /** 760 * DOC: ignore_crat (int) 761 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 762 * table to get information about AMD APUs. This option can serve as a workaround on 763 * systems with a broken CRAT table. 764 * 765 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 766 * whether use CRAT) 767 */ 768 int ignore_crat; 769 module_param(ignore_crat, int, 0444); 770 MODULE_PARM_DESC(ignore_crat, 771 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 772 773 /** 774 * DOC: halt_if_hws_hang (int) 775 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 776 * Setting 1 enables halt on hang. 777 */ 778 int halt_if_hws_hang; 779 module_param(halt_if_hws_hang, int, 0644); 780 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 781 782 /** 783 * DOC: hws_gws_support(bool) 784 * Assume that HWS supports GWS barriers regardless of what firmware version 785 * check says. Default value: false (rely on MEC2 firmware version check). 786 */ 787 bool hws_gws_support; 788 module_param(hws_gws_support, bool, 0444); 789 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 790 791 /** 792 * DOC: queue_preemption_timeout_ms (int) 793 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 794 */ 795 int queue_preemption_timeout_ms = 9000; 796 module_param(queue_preemption_timeout_ms, int, 0644); 797 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 798 799 /** 800 * DOC: debug_evictions(bool) 801 * Enable extra debug messages to help determine the cause of evictions 802 */ 803 bool debug_evictions; 804 module_param(debug_evictions, bool, 0644); 805 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 806 807 /** 808 * DOC: no_system_mem_limit(bool) 809 * Disable system memory limit, to support multiple process shared memory 810 */ 811 bool no_system_mem_limit; 812 module_param(no_system_mem_limit, bool, 0644); 813 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 814 815 /** 816 * DOC: no_queue_eviction_on_vm_fault (int) 817 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 818 */ 819 int amdgpu_no_queue_eviction_on_vm_fault = 0; 820 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 821 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 822 #endif 823 824 /** 825 * DOC: pcie_p2p (bool) 826 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 827 */ 828 #ifdef CONFIG_HSA_AMD_P2P 829 bool pcie_p2p = true; 830 module_param(pcie_p2p, bool, 0444); 831 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 832 #endif 833 834 /** 835 * DOC: dcfeaturemask (uint) 836 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 837 * The default is the current set of stable display features. 838 */ 839 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 840 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 841 842 /** 843 * DOC: dcdebugmask (uint) 844 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 845 */ 846 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 847 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 848 849 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 850 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 851 852 /** 853 * DOC: abmlevel (uint) 854 * Override the default ABM (Adaptive Backlight Management) level used for DC 855 * enabled hardware. Requires DMCU to be supported and loaded. 856 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 857 * default. Values 1-4 control the maximum allowable brightness reduction via 858 * the ABM algorithm, with 1 being the least reduction and 4 being the most 859 * reduction. 860 * 861 * Defaults to 0, or disabled. Userspace can still override this level later 862 * after boot. 863 */ 864 uint amdgpu_dm_abm_level; 865 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 866 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 867 868 int amdgpu_backlight = -1; 869 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 870 module_param_named(backlight, amdgpu_backlight, bint, 0444); 871 872 /** 873 * DOC: tmz (int) 874 * Trusted Memory Zone (TMZ) is a method to protect data being written 875 * to or read from memory. 876 * 877 * The default value: 0 (off). TODO: change to auto till it is completed. 878 */ 879 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 880 module_param_named(tmz, amdgpu_tmz, int, 0444); 881 882 /** 883 * DOC: reset_method (int) 884 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 885 */ 886 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 887 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 888 889 /** 890 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 891 * threshold value of faulty pages detected by RAS ECC, which may 892 * result in the GPU entering bad status when the number of total 893 * faulty pages by ECC exceeds the threshold value. 894 */ 895 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 896 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 897 898 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 899 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 900 901 /** 902 * DOC: vcnfw_log (int) 903 * Enable vcnfw log output for debugging, the default is disabled. 904 */ 905 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 906 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 907 908 /** 909 * DOC: smu_pptable_id (int) 910 * Used to override pptable id. id = 0 use VBIOS pptable. 911 * id > 0 use the soft pptable with specicfied id. 912 */ 913 MODULE_PARM_DESC(smu_pptable_id, 914 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 915 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 916 917 /* These devices are not supported by amdgpu. 918 * They are supported by the mach64, r128, radeon drivers 919 */ 920 static const u16 amdgpu_unsupported_pciidlist[] = { 921 /* mach64 */ 922 0x4354, 923 0x4358, 924 0x4554, 925 0x4742, 926 0x4744, 927 0x4749, 928 0x474C, 929 0x474D, 930 0x474E, 931 0x474F, 932 0x4750, 933 0x4751, 934 0x4752, 935 0x4753, 936 0x4754, 937 0x4755, 938 0x4756, 939 0x4757, 940 0x4758, 941 0x4759, 942 0x475A, 943 0x4C42, 944 0x4C44, 945 0x4C47, 946 0x4C49, 947 0x4C4D, 948 0x4C4E, 949 0x4C50, 950 0x4C51, 951 0x4C52, 952 0x4C53, 953 0x5654, 954 0x5655, 955 0x5656, 956 /* r128 */ 957 0x4c45, 958 0x4c46, 959 0x4d46, 960 0x4d4c, 961 0x5041, 962 0x5042, 963 0x5043, 964 0x5044, 965 0x5045, 966 0x5046, 967 0x5047, 968 0x5048, 969 0x5049, 970 0x504A, 971 0x504B, 972 0x504C, 973 0x504D, 974 0x504E, 975 0x504F, 976 0x5050, 977 0x5051, 978 0x5052, 979 0x5053, 980 0x5054, 981 0x5055, 982 0x5056, 983 0x5057, 984 0x5058, 985 0x5245, 986 0x5246, 987 0x5247, 988 0x524b, 989 0x524c, 990 0x534d, 991 0x5446, 992 0x544C, 993 0x5452, 994 /* radeon */ 995 0x3150, 996 0x3151, 997 0x3152, 998 0x3154, 999 0x3155, 1000 0x3E50, 1001 0x3E54, 1002 0x4136, 1003 0x4137, 1004 0x4144, 1005 0x4145, 1006 0x4146, 1007 0x4147, 1008 0x4148, 1009 0x4149, 1010 0x414A, 1011 0x414B, 1012 0x4150, 1013 0x4151, 1014 0x4152, 1015 0x4153, 1016 0x4154, 1017 0x4155, 1018 0x4156, 1019 0x4237, 1020 0x4242, 1021 0x4336, 1022 0x4337, 1023 0x4437, 1024 0x4966, 1025 0x4967, 1026 0x4A48, 1027 0x4A49, 1028 0x4A4A, 1029 0x4A4B, 1030 0x4A4C, 1031 0x4A4D, 1032 0x4A4E, 1033 0x4A4F, 1034 0x4A50, 1035 0x4A54, 1036 0x4B48, 1037 0x4B49, 1038 0x4B4A, 1039 0x4B4B, 1040 0x4B4C, 1041 0x4C57, 1042 0x4C58, 1043 0x4C59, 1044 0x4C5A, 1045 0x4C64, 1046 0x4C66, 1047 0x4C67, 1048 0x4E44, 1049 0x4E45, 1050 0x4E46, 1051 0x4E47, 1052 0x4E48, 1053 0x4E49, 1054 0x4E4A, 1055 0x4E4B, 1056 0x4E50, 1057 0x4E51, 1058 0x4E52, 1059 0x4E53, 1060 0x4E54, 1061 0x4E56, 1062 0x5144, 1063 0x5145, 1064 0x5146, 1065 0x5147, 1066 0x5148, 1067 0x514C, 1068 0x514D, 1069 0x5157, 1070 0x5158, 1071 0x5159, 1072 0x515A, 1073 0x515E, 1074 0x5460, 1075 0x5462, 1076 0x5464, 1077 0x5548, 1078 0x5549, 1079 0x554A, 1080 0x554B, 1081 0x554C, 1082 0x554D, 1083 0x554E, 1084 0x554F, 1085 0x5550, 1086 0x5551, 1087 0x5552, 1088 0x5554, 1089 0x564A, 1090 0x564B, 1091 0x564F, 1092 0x5652, 1093 0x5653, 1094 0x5657, 1095 0x5834, 1096 0x5835, 1097 0x5954, 1098 0x5955, 1099 0x5974, 1100 0x5975, 1101 0x5960, 1102 0x5961, 1103 0x5962, 1104 0x5964, 1105 0x5965, 1106 0x5969, 1107 0x5a41, 1108 0x5a42, 1109 0x5a61, 1110 0x5a62, 1111 0x5b60, 1112 0x5b62, 1113 0x5b63, 1114 0x5b64, 1115 0x5b65, 1116 0x5c61, 1117 0x5c63, 1118 0x5d48, 1119 0x5d49, 1120 0x5d4a, 1121 0x5d4c, 1122 0x5d4d, 1123 0x5d4e, 1124 0x5d4f, 1125 0x5d50, 1126 0x5d52, 1127 0x5d57, 1128 0x5e48, 1129 0x5e4a, 1130 0x5e4b, 1131 0x5e4c, 1132 0x5e4d, 1133 0x5e4f, 1134 0x6700, 1135 0x6701, 1136 0x6702, 1137 0x6703, 1138 0x6704, 1139 0x6705, 1140 0x6706, 1141 0x6707, 1142 0x6708, 1143 0x6709, 1144 0x6718, 1145 0x6719, 1146 0x671c, 1147 0x671d, 1148 0x671f, 1149 0x6720, 1150 0x6721, 1151 0x6722, 1152 0x6723, 1153 0x6724, 1154 0x6725, 1155 0x6726, 1156 0x6727, 1157 0x6728, 1158 0x6729, 1159 0x6738, 1160 0x6739, 1161 0x673e, 1162 0x6740, 1163 0x6741, 1164 0x6742, 1165 0x6743, 1166 0x6744, 1167 0x6745, 1168 0x6746, 1169 0x6747, 1170 0x6748, 1171 0x6749, 1172 0x674A, 1173 0x6750, 1174 0x6751, 1175 0x6758, 1176 0x6759, 1177 0x675B, 1178 0x675D, 1179 0x675F, 1180 0x6760, 1181 0x6761, 1182 0x6762, 1183 0x6763, 1184 0x6764, 1185 0x6765, 1186 0x6766, 1187 0x6767, 1188 0x6768, 1189 0x6770, 1190 0x6771, 1191 0x6772, 1192 0x6778, 1193 0x6779, 1194 0x677B, 1195 0x6840, 1196 0x6841, 1197 0x6842, 1198 0x6843, 1199 0x6849, 1200 0x684C, 1201 0x6850, 1202 0x6858, 1203 0x6859, 1204 0x6880, 1205 0x6888, 1206 0x6889, 1207 0x688A, 1208 0x688C, 1209 0x688D, 1210 0x6898, 1211 0x6899, 1212 0x689b, 1213 0x689c, 1214 0x689d, 1215 0x689e, 1216 0x68a0, 1217 0x68a1, 1218 0x68a8, 1219 0x68a9, 1220 0x68b0, 1221 0x68b8, 1222 0x68b9, 1223 0x68ba, 1224 0x68be, 1225 0x68bf, 1226 0x68c0, 1227 0x68c1, 1228 0x68c7, 1229 0x68c8, 1230 0x68c9, 1231 0x68d8, 1232 0x68d9, 1233 0x68da, 1234 0x68de, 1235 0x68e0, 1236 0x68e1, 1237 0x68e4, 1238 0x68e5, 1239 0x68e8, 1240 0x68e9, 1241 0x68f1, 1242 0x68f2, 1243 0x68f8, 1244 0x68f9, 1245 0x68fa, 1246 0x68fe, 1247 0x7100, 1248 0x7101, 1249 0x7102, 1250 0x7103, 1251 0x7104, 1252 0x7105, 1253 0x7106, 1254 0x7108, 1255 0x7109, 1256 0x710A, 1257 0x710B, 1258 0x710C, 1259 0x710E, 1260 0x710F, 1261 0x7140, 1262 0x7141, 1263 0x7142, 1264 0x7143, 1265 0x7144, 1266 0x7145, 1267 0x7146, 1268 0x7147, 1269 0x7149, 1270 0x714A, 1271 0x714B, 1272 0x714C, 1273 0x714D, 1274 0x714E, 1275 0x714F, 1276 0x7151, 1277 0x7152, 1278 0x7153, 1279 0x715E, 1280 0x715F, 1281 0x7180, 1282 0x7181, 1283 0x7183, 1284 0x7186, 1285 0x7187, 1286 0x7188, 1287 0x718A, 1288 0x718B, 1289 0x718C, 1290 0x718D, 1291 0x718F, 1292 0x7193, 1293 0x7196, 1294 0x719B, 1295 0x719F, 1296 0x71C0, 1297 0x71C1, 1298 0x71C2, 1299 0x71C3, 1300 0x71C4, 1301 0x71C5, 1302 0x71C6, 1303 0x71C7, 1304 0x71CD, 1305 0x71CE, 1306 0x71D2, 1307 0x71D4, 1308 0x71D5, 1309 0x71D6, 1310 0x71DA, 1311 0x71DE, 1312 0x7200, 1313 0x7210, 1314 0x7211, 1315 0x7240, 1316 0x7243, 1317 0x7244, 1318 0x7245, 1319 0x7246, 1320 0x7247, 1321 0x7248, 1322 0x7249, 1323 0x724A, 1324 0x724B, 1325 0x724C, 1326 0x724D, 1327 0x724E, 1328 0x724F, 1329 0x7280, 1330 0x7281, 1331 0x7283, 1332 0x7284, 1333 0x7287, 1334 0x7288, 1335 0x7289, 1336 0x728B, 1337 0x728C, 1338 0x7290, 1339 0x7291, 1340 0x7293, 1341 0x7297, 1342 0x7834, 1343 0x7835, 1344 0x791e, 1345 0x791f, 1346 0x793f, 1347 0x7941, 1348 0x7942, 1349 0x796c, 1350 0x796d, 1351 0x796e, 1352 0x796f, 1353 0x9400, 1354 0x9401, 1355 0x9402, 1356 0x9403, 1357 0x9405, 1358 0x940A, 1359 0x940B, 1360 0x940F, 1361 0x94A0, 1362 0x94A1, 1363 0x94A3, 1364 0x94B1, 1365 0x94B3, 1366 0x94B4, 1367 0x94B5, 1368 0x94B9, 1369 0x9440, 1370 0x9441, 1371 0x9442, 1372 0x9443, 1373 0x9444, 1374 0x9446, 1375 0x944A, 1376 0x944B, 1377 0x944C, 1378 0x944E, 1379 0x9450, 1380 0x9452, 1381 0x9456, 1382 0x945A, 1383 0x945B, 1384 0x945E, 1385 0x9460, 1386 0x9462, 1387 0x946A, 1388 0x946B, 1389 0x947A, 1390 0x947B, 1391 0x9480, 1392 0x9487, 1393 0x9488, 1394 0x9489, 1395 0x948A, 1396 0x948F, 1397 0x9490, 1398 0x9491, 1399 0x9495, 1400 0x9498, 1401 0x949C, 1402 0x949E, 1403 0x949F, 1404 0x94C0, 1405 0x94C1, 1406 0x94C3, 1407 0x94C4, 1408 0x94C5, 1409 0x94C6, 1410 0x94C7, 1411 0x94C8, 1412 0x94C9, 1413 0x94CB, 1414 0x94CC, 1415 0x94CD, 1416 0x9500, 1417 0x9501, 1418 0x9504, 1419 0x9505, 1420 0x9506, 1421 0x9507, 1422 0x9508, 1423 0x9509, 1424 0x950F, 1425 0x9511, 1426 0x9515, 1427 0x9517, 1428 0x9519, 1429 0x9540, 1430 0x9541, 1431 0x9542, 1432 0x954E, 1433 0x954F, 1434 0x9552, 1435 0x9553, 1436 0x9555, 1437 0x9557, 1438 0x955f, 1439 0x9580, 1440 0x9581, 1441 0x9583, 1442 0x9586, 1443 0x9587, 1444 0x9588, 1445 0x9589, 1446 0x958A, 1447 0x958B, 1448 0x958C, 1449 0x958D, 1450 0x958E, 1451 0x958F, 1452 0x9590, 1453 0x9591, 1454 0x9593, 1455 0x9595, 1456 0x9596, 1457 0x9597, 1458 0x9598, 1459 0x9599, 1460 0x959B, 1461 0x95C0, 1462 0x95C2, 1463 0x95C4, 1464 0x95C5, 1465 0x95C6, 1466 0x95C7, 1467 0x95C9, 1468 0x95CC, 1469 0x95CD, 1470 0x95CE, 1471 0x95CF, 1472 0x9610, 1473 0x9611, 1474 0x9612, 1475 0x9613, 1476 0x9614, 1477 0x9615, 1478 0x9616, 1479 0x9640, 1480 0x9641, 1481 0x9642, 1482 0x9643, 1483 0x9644, 1484 0x9645, 1485 0x9647, 1486 0x9648, 1487 0x9649, 1488 0x964a, 1489 0x964b, 1490 0x964c, 1491 0x964e, 1492 0x964f, 1493 0x9710, 1494 0x9711, 1495 0x9712, 1496 0x9713, 1497 0x9714, 1498 0x9715, 1499 0x9802, 1500 0x9803, 1501 0x9804, 1502 0x9805, 1503 0x9806, 1504 0x9807, 1505 0x9808, 1506 0x9809, 1507 0x980A, 1508 0x9900, 1509 0x9901, 1510 0x9903, 1511 0x9904, 1512 0x9905, 1513 0x9906, 1514 0x9907, 1515 0x9908, 1516 0x9909, 1517 0x990A, 1518 0x990B, 1519 0x990C, 1520 0x990D, 1521 0x990E, 1522 0x990F, 1523 0x9910, 1524 0x9913, 1525 0x9917, 1526 0x9918, 1527 0x9919, 1528 0x9990, 1529 0x9991, 1530 0x9992, 1531 0x9993, 1532 0x9994, 1533 0x9995, 1534 0x9996, 1535 0x9997, 1536 0x9998, 1537 0x9999, 1538 0x999A, 1539 0x999B, 1540 0x999C, 1541 0x999D, 1542 0x99A0, 1543 0x99A2, 1544 0x99A4, 1545 /* radeon secondary ids */ 1546 0x3171, 1547 0x3e70, 1548 0x4164, 1549 0x4165, 1550 0x4166, 1551 0x4168, 1552 0x4170, 1553 0x4171, 1554 0x4172, 1555 0x4173, 1556 0x496e, 1557 0x4a69, 1558 0x4a6a, 1559 0x4a6b, 1560 0x4a70, 1561 0x4a74, 1562 0x4b69, 1563 0x4b6b, 1564 0x4b6c, 1565 0x4c6e, 1566 0x4e64, 1567 0x4e65, 1568 0x4e66, 1569 0x4e67, 1570 0x4e68, 1571 0x4e69, 1572 0x4e6a, 1573 0x4e71, 1574 0x4f73, 1575 0x5569, 1576 0x556b, 1577 0x556d, 1578 0x556f, 1579 0x5571, 1580 0x5854, 1581 0x5874, 1582 0x5940, 1583 0x5941, 1584 0x5b72, 1585 0x5b73, 1586 0x5b74, 1587 0x5b75, 1588 0x5d44, 1589 0x5d45, 1590 0x5d6d, 1591 0x5d6f, 1592 0x5d72, 1593 0x5d77, 1594 0x5e6b, 1595 0x5e6d, 1596 0x7120, 1597 0x7124, 1598 0x7129, 1599 0x712e, 1600 0x712f, 1601 0x7162, 1602 0x7163, 1603 0x7166, 1604 0x7167, 1605 0x7172, 1606 0x7173, 1607 0x71a0, 1608 0x71a1, 1609 0x71a3, 1610 0x71a7, 1611 0x71bb, 1612 0x71e0, 1613 0x71e1, 1614 0x71e2, 1615 0x71e6, 1616 0x71e7, 1617 0x71f2, 1618 0x7269, 1619 0x726b, 1620 0x726e, 1621 0x72a0, 1622 0x72a8, 1623 0x72b1, 1624 0x72b3, 1625 0x793f, 1626 }; 1627 1628 static const struct pci_device_id pciidlist[] = { 1629 #ifdef CONFIG_DRM_AMDGPU_SI 1630 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1631 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1632 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1633 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1634 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1635 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1636 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1637 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1638 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1639 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1640 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1641 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1642 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1643 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1644 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1647 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1648 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1649 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1650 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1651 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1652 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1653 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1654 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1655 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1658 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1659 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1660 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1661 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1662 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1663 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1664 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1665 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1666 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1667 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1668 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1669 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1670 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1671 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1672 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1674 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1675 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1676 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1677 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1678 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1679 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1680 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1681 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1682 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1683 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1684 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1685 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1686 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1689 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1690 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1691 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1692 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1693 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1694 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1695 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1696 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1700 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1701 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1702 #endif 1703 #ifdef CONFIG_DRM_AMDGPU_CIK 1704 /* Kaveri */ 1705 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1706 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1707 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1708 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1709 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1710 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1711 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1713 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1714 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1715 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1716 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1717 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1718 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1719 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1720 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1721 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1722 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1723 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1724 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1725 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1726 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1727 /* Bonaire */ 1728 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1729 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1730 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1731 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1732 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1733 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1734 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1735 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1736 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1737 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1738 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1739 /* Hawaii */ 1740 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1741 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1742 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1743 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1744 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1745 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1746 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1747 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1748 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1749 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1750 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1751 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1752 /* Kabini */ 1753 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1754 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1755 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1756 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1757 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1759 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1761 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1763 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1764 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1765 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1766 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1767 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1768 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1769 /* mullins */ 1770 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1772 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1774 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1775 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1776 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1777 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1778 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1779 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1783 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1784 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1785 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1786 #endif 1787 /* topaz */ 1788 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1789 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1790 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1791 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1792 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1793 /* tonga */ 1794 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1795 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1796 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1797 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1798 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1799 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1800 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1801 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1802 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1803 /* fiji */ 1804 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1805 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1806 /* carrizo */ 1807 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1808 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1809 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1810 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1811 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1812 /* stoney */ 1813 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1814 /* Polaris11 */ 1815 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1816 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1817 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1818 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1819 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1820 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1821 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1822 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1823 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1824 /* Polaris10 */ 1825 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1826 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1827 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1828 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1829 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1830 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1831 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1832 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1833 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1834 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1835 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1836 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1837 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1838 /* Polaris12 */ 1839 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1840 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1841 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1842 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1843 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1844 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1845 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1846 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1847 /* VEGAM */ 1848 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1849 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1850 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1851 /* Vega 10 */ 1852 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1853 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1854 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1855 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1856 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1857 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1858 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1859 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1860 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1861 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1862 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1863 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1864 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1865 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1866 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1867 /* Vega 12 */ 1868 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1869 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1870 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1871 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1872 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1873 /* Vega 20 */ 1874 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1875 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1876 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1877 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1878 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1879 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1880 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1881 /* Raven */ 1882 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1883 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1884 /* Arcturus */ 1885 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1886 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1887 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1888 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1889 /* Navi10 */ 1890 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1891 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1892 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1893 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1894 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1895 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1896 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1897 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1898 /* Navi14 */ 1899 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1900 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1901 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1902 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1903 1904 /* Renoir */ 1905 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1906 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1907 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1908 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1909 1910 /* Navi12 */ 1911 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1912 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1913 1914 /* Sienna_Cichlid */ 1915 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1916 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1917 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1918 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1919 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1920 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1921 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1922 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1923 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1924 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1925 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1926 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1927 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1928 1929 /* Yellow Carp */ 1930 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1931 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1932 1933 /* Navy_Flounder */ 1934 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1935 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1936 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1937 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1938 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1939 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1940 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1941 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1942 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1943 1944 /* DIMGREY_CAVEFISH */ 1945 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1946 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1947 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1948 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1949 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1950 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1951 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1952 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1953 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1954 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1955 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1956 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1957 1958 /* Aldebaran */ 1959 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1960 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1961 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1962 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1963 1964 /* CYAN_SKILLFISH */ 1965 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1966 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1967 1968 /* BEIGE_GOBY */ 1969 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1970 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1971 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1972 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1973 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1974 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1975 1976 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1977 .class = PCI_CLASS_DISPLAY_VGA << 8, 1978 .class_mask = 0xffffff, 1979 .driver_data = CHIP_IP_DISCOVERY }, 1980 1981 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1982 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1983 .class_mask = 0xffffff, 1984 .driver_data = CHIP_IP_DISCOVERY }, 1985 1986 {0, 0, 0} 1987 }; 1988 1989 MODULE_DEVICE_TABLE(pci, pciidlist); 1990 1991 static const struct drm_driver amdgpu_kms_driver; 1992 1993 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1994 { 1995 struct pci_dev *p = NULL; 1996 int i; 1997 1998 /* 0 - GPU 1999 * 1 - audio 2000 * 2 - USB 2001 * 3 - UCSI 2002 */ 2003 for (i = 1; i < 4; i++) { 2004 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2005 adev->pdev->bus->number, i); 2006 if (p) { 2007 pm_runtime_get_sync(&p->dev); 2008 pm_runtime_mark_last_busy(&p->dev); 2009 pm_runtime_put_autosuspend(&p->dev); 2010 pci_dev_put(p); 2011 } 2012 } 2013 } 2014 2015 static int amdgpu_pci_probe(struct pci_dev *pdev, 2016 const struct pci_device_id *ent) 2017 { 2018 struct drm_device *ddev; 2019 struct amdgpu_device *adev; 2020 unsigned long flags = ent->driver_data; 2021 int ret, retry = 0, i; 2022 bool supports_atomic = false; 2023 2024 /* skip devices which are owned by radeon */ 2025 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2026 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2027 return -ENODEV; 2028 } 2029 2030 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2031 amdgpu_aspm = 0; 2032 2033 if (amdgpu_virtual_display || 2034 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2035 supports_atomic = true; 2036 2037 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2038 DRM_INFO("This hardware requires experimental hardware support.\n" 2039 "See modparam exp_hw_support\n"); 2040 return -ENODEV; 2041 } 2042 /* differentiate between P10 and P11 asics with the same DID */ 2043 if (pdev->device == 0x67FF && 2044 (pdev->revision == 0xE3 || 2045 pdev->revision == 0xE7 || 2046 pdev->revision == 0xF3 || 2047 pdev->revision == 0xF7)) { 2048 flags &= ~AMD_ASIC_MASK; 2049 flags |= CHIP_POLARIS10; 2050 } 2051 2052 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2053 * however, SME requires an indirect IOMMU mapping because the encryption 2054 * bit is beyond the DMA mask of the chip. 2055 */ 2056 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2057 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2058 dev_info(&pdev->dev, 2059 "SME is not compatible with RAVEN\n"); 2060 return -ENOTSUPP; 2061 } 2062 2063 #ifdef CONFIG_DRM_AMDGPU_SI 2064 if (!amdgpu_si_support) { 2065 switch (flags & AMD_ASIC_MASK) { 2066 case CHIP_TAHITI: 2067 case CHIP_PITCAIRN: 2068 case CHIP_VERDE: 2069 case CHIP_OLAND: 2070 case CHIP_HAINAN: 2071 dev_info(&pdev->dev, 2072 "SI support provided by radeon.\n"); 2073 dev_info(&pdev->dev, 2074 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2075 ); 2076 return -ENODEV; 2077 } 2078 } 2079 #endif 2080 #ifdef CONFIG_DRM_AMDGPU_CIK 2081 if (!amdgpu_cik_support) { 2082 switch (flags & AMD_ASIC_MASK) { 2083 case CHIP_KAVERI: 2084 case CHIP_BONAIRE: 2085 case CHIP_HAWAII: 2086 case CHIP_KABINI: 2087 case CHIP_MULLINS: 2088 dev_info(&pdev->dev, 2089 "CIK support provided by radeon.\n"); 2090 dev_info(&pdev->dev, 2091 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2092 ); 2093 return -ENODEV; 2094 } 2095 } 2096 #endif 2097 2098 /* Get rid of things like offb */ 2099 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2100 if (ret) 2101 return ret; 2102 2103 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2104 if (IS_ERR(adev)) 2105 return PTR_ERR(adev); 2106 2107 adev->dev = &pdev->dev; 2108 adev->pdev = pdev; 2109 ddev = adev_to_drm(adev); 2110 2111 if (!supports_atomic) 2112 ddev->driver_features &= ~DRIVER_ATOMIC; 2113 2114 ret = pci_enable_device(pdev); 2115 if (ret) 2116 return ret; 2117 2118 pci_set_drvdata(pdev, ddev); 2119 2120 ret = amdgpu_driver_load_kms(adev, flags); 2121 if (ret) 2122 goto err_pci; 2123 2124 retry_init: 2125 ret = drm_dev_register(ddev, flags); 2126 if (ret == -EAGAIN && ++retry <= 3) { 2127 DRM_INFO("retry init %d\n", retry); 2128 /* Don't request EX mode too frequently which is attacking */ 2129 msleep(5000); 2130 goto retry_init; 2131 } else if (ret) { 2132 goto err_pci; 2133 } 2134 2135 /* 2136 * 1. don't init fbdev on hw without DCE 2137 * 2. don't init fbdev if there are no connectors 2138 */ 2139 if (adev->mode_info.mode_config_initialized && 2140 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2141 /* select 8 bpp console on low vram cards */ 2142 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2143 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2144 else 2145 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2146 } 2147 2148 ret = amdgpu_debugfs_init(adev); 2149 if (ret) 2150 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2151 2152 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2153 /* only need to skip on ATPX */ 2154 if (amdgpu_device_supports_px(ddev)) 2155 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2156 /* we want direct complete for BOCO */ 2157 if (amdgpu_device_supports_boco(ddev)) 2158 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2159 DPM_FLAG_SMART_SUSPEND | 2160 DPM_FLAG_MAY_SKIP_RESUME); 2161 pm_runtime_use_autosuspend(ddev->dev); 2162 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2163 2164 pm_runtime_allow(ddev->dev); 2165 2166 pm_runtime_mark_last_busy(ddev->dev); 2167 pm_runtime_put_autosuspend(ddev->dev); 2168 2169 /* 2170 * For runpm implemented via BACO, PMFW will handle the 2171 * timing for BACO in and out: 2172 * - put ASIC into BACO state only when both video and 2173 * audio functions are in D3 state. 2174 * - pull ASIC out of BACO state when either video or 2175 * audio function is in D0 state. 2176 * Also, at startup, PMFW assumes both functions are in 2177 * D0 state. 2178 * 2179 * So if snd driver was loaded prior to amdgpu driver 2180 * and audio function was put into D3 state, there will 2181 * be no PMFW-aware D-state transition(D0->D3) on runpm 2182 * suspend. Thus the BACO will be not correctly kicked in. 2183 * 2184 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2185 * into D0 state. Then there will be a PMFW-aware D-state 2186 * transition(D0->D3) on runpm suspend. 2187 */ 2188 if (amdgpu_device_supports_baco(ddev) && 2189 !(adev->flags & AMD_IS_APU) && 2190 (adev->asic_type >= CHIP_NAVI10)) 2191 amdgpu_get_secondary_funcs(adev); 2192 } 2193 2194 return 0; 2195 2196 err_pci: 2197 pci_disable_device(pdev); 2198 return ret; 2199 } 2200 2201 static void 2202 amdgpu_pci_remove(struct pci_dev *pdev) 2203 { 2204 struct drm_device *dev = pci_get_drvdata(pdev); 2205 struct amdgpu_device *adev = drm_to_adev(dev); 2206 2207 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2208 pm_runtime_get_sync(dev->dev); 2209 pm_runtime_forbid(dev->dev); 2210 } 2211 2212 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2213 !amdgpu_sriov_vf(adev)) { 2214 bool need_to_reset_gpu = false; 2215 2216 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2217 struct amdgpu_hive_info *hive; 2218 2219 hive = amdgpu_get_xgmi_hive(adev); 2220 if (hive->device_remove_count == 0) 2221 need_to_reset_gpu = true; 2222 hive->device_remove_count++; 2223 amdgpu_put_xgmi_hive(hive); 2224 } else { 2225 need_to_reset_gpu = true; 2226 } 2227 2228 /* Workaround for ASICs need to reset SMU. 2229 * Called only when the first device is removed. 2230 */ 2231 if (need_to_reset_gpu) { 2232 struct amdgpu_reset_context reset_context; 2233 2234 adev->shutdown = true; 2235 memset(&reset_context, 0, sizeof(reset_context)); 2236 reset_context.method = AMD_RESET_METHOD_NONE; 2237 reset_context.reset_req_dev = adev; 2238 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2239 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2240 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2241 } 2242 } 2243 2244 amdgpu_driver_unload_kms(dev); 2245 2246 drm_dev_unplug(dev); 2247 2248 /* 2249 * Flush any in flight DMA operations from device. 2250 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2251 * StatusTransactions Pending bit. 2252 */ 2253 pci_disable_device(pdev); 2254 pci_wait_for_pending_transaction(pdev); 2255 } 2256 2257 static void 2258 amdgpu_pci_shutdown(struct pci_dev *pdev) 2259 { 2260 struct drm_device *dev = pci_get_drvdata(pdev); 2261 struct amdgpu_device *adev = drm_to_adev(dev); 2262 2263 if (amdgpu_ras_intr_triggered()) 2264 return; 2265 2266 /* if we are running in a VM, make sure the device 2267 * torn down properly on reboot/shutdown. 2268 * unfortunately we can't detect certain 2269 * hypervisors so just do this all the time. 2270 */ 2271 if (!amdgpu_passthrough(adev)) 2272 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2273 amdgpu_device_ip_suspend(adev); 2274 adev->mp1_state = PP_MP1_STATE_NONE; 2275 } 2276 2277 /** 2278 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2279 * 2280 * @work: work_struct. 2281 */ 2282 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2283 { 2284 struct list_head device_list; 2285 struct amdgpu_device *adev; 2286 int i, r; 2287 struct amdgpu_reset_context reset_context; 2288 2289 memset(&reset_context, 0, sizeof(reset_context)); 2290 2291 mutex_lock(&mgpu_info.mutex); 2292 if (mgpu_info.pending_reset == true) { 2293 mutex_unlock(&mgpu_info.mutex); 2294 return; 2295 } 2296 mgpu_info.pending_reset = true; 2297 mutex_unlock(&mgpu_info.mutex); 2298 2299 /* Use a common context, just need to make sure full reset is done */ 2300 reset_context.method = AMD_RESET_METHOD_NONE; 2301 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2302 2303 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2304 adev = mgpu_info.gpu_ins[i].adev; 2305 reset_context.reset_req_dev = adev; 2306 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2307 if (r) { 2308 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2309 r, adev_to_drm(adev)->unique); 2310 } 2311 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2312 r = -EALREADY; 2313 } 2314 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2315 adev = mgpu_info.gpu_ins[i].adev; 2316 flush_work(&adev->xgmi_reset_work); 2317 adev->gmc.xgmi.pending_reset = false; 2318 } 2319 2320 /* reset function will rebuild the xgmi hive info , clear it now */ 2321 for (i = 0; i < mgpu_info.num_dgpu; i++) 2322 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2323 2324 INIT_LIST_HEAD(&device_list); 2325 2326 for (i = 0; i < mgpu_info.num_dgpu; i++) 2327 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2328 2329 /* unregister the GPU first, reset function will add them back */ 2330 list_for_each_entry(adev, &device_list, reset_list) 2331 amdgpu_unregister_gpu_instance(adev); 2332 2333 /* Use a common context, just need to make sure full reset is done */ 2334 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2335 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2336 2337 if (r) { 2338 DRM_ERROR("reinit gpus failure"); 2339 return; 2340 } 2341 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2342 adev = mgpu_info.gpu_ins[i].adev; 2343 if (!adev->kfd.init_complete) 2344 amdgpu_amdkfd_device_init(adev); 2345 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2346 } 2347 return; 2348 } 2349 2350 static int amdgpu_pmops_prepare(struct device *dev) 2351 { 2352 struct drm_device *drm_dev = dev_get_drvdata(dev); 2353 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2354 2355 /* Return a positive number here so 2356 * DPM_FLAG_SMART_SUSPEND works properly 2357 */ 2358 if (amdgpu_device_supports_boco(drm_dev)) 2359 return pm_runtime_suspended(dev); 2360 2361 /* if we will not support s3 or s2i for the device 2362 * then skip suspend 2363 */ 2364 if (!amdgpu_acpi_is_s0ix_active(adev) && 2365 !amdgpu_acpi_is_s3_active(adev)) 2366 return 1; 2367 2368 return 0; 2369 } 2370 2371 static void amdgpu_pmops_complete(struct device *dev) 2372 { 2373 /* nothing to do */ 2374 } 2375 2376 static int amdgpu_pmops_suspend(struct device *dev) 2377 { 2378 struct drm_device *drm_dev = dev_get_drvdata(dev); 2379 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2380 2381 if (amdgpu_acpi_is_s0ix_active(adev)) 2382 adev->in_s0ix = true; 2383 else 2384 adev->in_s3 = true; 2385 return amdgpu_device_suspend(drm_dev, true); 2386 } 2387 2388 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2389 { 2390 struct drm_device *drm_dev = dev_get_drvdata(dev); 2391 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2392 2393 if (amdgpu_acpi_should_gpu_reset(adev)) 2394 return amdgpu_asic_reset(adev); 2395 2396 return 0; 2397 } 2398 2399 static int amdgpu_pmops_resume(struct device *dev) 2400 { 2401 struct drm_device *drm_dev = dev_get_drvdata(dev); 2402 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2403 int r; 2404 2405 /* Avoids registers access if device is physically gone */ 2406 if (!pci_device_is_present(adev->pdev)) 2407 adev->no_hw_access = true; 2408 2409 r = amdgpu_device_resume(drm_dev, true); 2410 if (amdgpu_acpi_is_s0ix_active(adev)) 2411 adev->in_s0ix = false; 2412 else 2413 adev->in_s3 = false; 2414 return r; 2415 } 2416 2417 static int amdgpu_pmops_freeze(struct device *dev) 2418 { 2419 struct drm_device *drm_dev = dev_get_drvdata(dev); 2420 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2421 int r; 2422 2423 adev->in_s4 = true; 2424 r = amdgpu_device_suspend(drm_dev, true); 2425 adev->in_s4 = false; 2426 if (r) 2427 return r; 2428 return amdgpu_asic_reset(adev); 2429 } 2430 2431 static int amdgpu_pmops_thaw(struct device *dev) 2432 { 2433 struct drm_device *drm_dev = dev_get_drvdata(dev); 2434 2435 return amdgpu_device_resume(drm_dev, true); 2436 } 2437 2438 static int amdgpu_pmops_poweroff(struct device *dev) 2439 { 2440 struct drm_device *drm_dev = dev_get_drvdata(dev); 2441 2442 return amdgpu_device_suspend(drm_dev, true); 2443 } 2444 2445 static int amdgpu_pmops_restore(struct device *dev) 2446 { 2447 struct drm_device *drm_dev = dev_get_drvdata(dev); 2448 2449 return amdgpu_device_resume(drm_dev, true); 2450 } 2451 2452 static int amdgpu_runtime_idle_check_display(struct device *dev) 2453 { 2454 struct pci_dev *pdev = to_pci_dev(dev); 2455 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2456 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2457 2458 if (adev->mode_info.num_crtc) { 2459 struct drm_connector *list_connector; 2460 struct drm_connector_list_iter iter; 2461 int ret = 0; 2462 2463 /* XXX: Return busy if any displays are connected to avoid 2464 * possible display wakeups after runtime resume due to 2465 * hotplug events in case any displays were connected while 2466 * the GPU was in suspend. Remove this once that is fixed. 2467 */ 2468 mutex_lock(&drm_dev->mode_config.mutex); 2469 drm_connector_list_iter_begin(drm_dev, &iter); 2470 drm_for_each_connector_iter(list_connector, &iter) { 2471 if (list_connector->status == connector_status_connected) { 2472 ret = -EBUSY; 2473 break; 2474 } 2475 } 2476 drm_connector_list_iter_end(&iter); 2477 mutex_unlock(&drm_dev->mode_config.mutex); 2478 2479 if (ret) 2480 return ret; 2481 2482 if (adev->dc_enabled) { 2483 struct drm_crtc *crtc; 2484 2485 drm_for_each_crtc(crtc, drm_dev) { 2486 drm_modeset_lock(&crtc->mutex, NULL); 2487 if (crtc->state->active) 2488 ret = -EBUSY; 2489 drm_modeset_unlock(&crtc->mutex); 2490 if (ret < 0) 2491 break; 2492 } 2493 } else { 2494 mutex_lock(&drm_dev->mode_config.mutex); 2495 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2496 2497 drm_connector_list_iter_begin(drm_dev, &iter); 2498 drm_for_each_connector_iter(list_connector, &iter) { 2499 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2500 ret = -EBUSY; 2501 break; 2502 } 2503 } 2504 2505 drm_connector_list_iter_end(&iter); 2506 2507 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2508 mutex_unlock(&drm_dev->mode_config.mutex); 2509 } 2510 if (ret) 2511 return ret; 2512 } 2513 2514 return 0; 2515 } 2516 2517 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2518 { 2519 struct pci_dev *pdev = to_pci_dev(dev); 2520 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2521 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2522 int ret, i; 2523 2524 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2525 pm_runtime_forbid(dev); 2526 return -EBUSY; 2527 } 2528 2529 ret = amdgpu_runtime_idle_check_display(dev); 2530 if (ret) 2531 return ret; 2532 2533 /* wait for all rings to drain before suspending */ 2534 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2535 struct amdgpu_ring *ring = adev->rings[i]; 2536 if (ring && ring->sched.ready) { 2537 ret = amdgpu_fence_wait_empty(ring); 2538 if (ret) 2539 return -EBUSY; 2540 } 2541 } 2542 2543 adev->in_runpm = true; 2544 if (amdgpu_device_supports_px(drm_dev)) 2545 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2546 2547 /* 2548 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2549 * proper cleanups and put itself into a state ready for PNP. That 2550 * can address some random resuming failure observed on BOCO capable 2551 * platforms. 2552 * TODO: this may be also needed for PX capable platform. 2553 */ 2554 if (amdgpu_device_supports_boco(drm_dev)) 2555 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2556 2557 ret = amdgpu_device_suspend(drm_dev, false); 2558 if (ret) { 2559 adev->in_runpm = false; 2560 if (amdgpu_device_supports_boco(drm_dev)) 2561 adev->mp1_state = PP_MP1_STATE_NONE; 2562 return ret; 2563 } 2564 2565 if (amdgpu_device_supports_boco(drm_dev)) 2566 adev->mp1_state = PP_MP1_STATE_NONE; 2567 2568 if (amdgpu_device_supports_px(drm_dev)) { 2569 /* Only need to handle PCI state in the driver for ATPX 2570 * PCI core handles it for _PR3. 2571 */ 2572 amdgpu_device_cache_pci_state(pdev); 2573 pci_disable_device(pdev); 2574 pci_ignore_hotplug(pdev); 2575 pci_set_power_state(pdev, PCI_D3cold); 2576 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2577 } else if (amdgpu_device_supports_boco(drm_dev)) { 2578 /* nothing to do */ 2579 } else if (amdgpu_device_supports_baco(drm_dev)) { 2580 amdgpu_device_baco_enter(drm_dev); 2581 } 2582 2583 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2584 2585 return 0; 2586 } 2587 2588 static int amdgpu_pmops_runtime_resume(struct device *dev) 2589 { 2590 struct pci_dev *pdev = to_pci_dev(dev); 2591 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2592 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2593 int ret; 2594 2595 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2596 return -EINVAL; 2597 2598 /* Avoids registers access if device is physically gone */ 2599 if (!pci_device_is_present(adev->pdev)) 2600 adev->no_hw_access = true; 2601 2602 if (amdgpu_device_supports_px(drm_dev)) { 2603 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2604 2605 /* Only need to handle PCI state in the driver for ATPX 2606 * PCI core handles it for _PR3. 2607 */ 2608 pci_set_power_state(pdev, PCI_D0); 2609 amdgpu_device_load_pci_state(pdev); 2610 ret = pci_enable_device(pdev); 2611 if (ret) 2612 return ret; 2613 pci_set_master(pdev); 2614 } else if (amdgpu_device_supports_boco(drm_dev)) { 2615 /* Only need to handle PCI state in the driver for ATPX 2616 * PCI core handles it for _PR3. 2617 */ 2618 pci_set_master(pdev); 2619 } else if (amdgpu_device_supports_baco(drm_dev)) { 2620 amdgpu_device_baco_exit(drm_dev); 2621 } 2622 ret = amdgpu_device_resume(drm_dev, false); 2623 if (ret) { 2624 if (amdgpu_device_supports_px(drm_dev)) 2625 pci_disable_device(pdev); 2626 return ret; 2627 } 2628 2629 if (amdgpu_device_supports_px(drm_dev)) 2630 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2631 adev->in_runpm = false; 2632 return 0; 2633 } 2634 2635 static int amdgpu_pmops_runtime_idle(struct device *dev) 2636 { 2637 struct drm_device *drm_dev = dev_get_drvdata(dev); 2638 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2639 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2640 int ret = 1; 2641 2642 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2643 pm_runtime_forbid(dev); 2644 return -EBUSY; 2645 } 2646 2647 ret = amdgpu_runtime_idle_check_display(dev); 2648 2649 pm_runtime_mark_last_busy(dev); 2650 pm_runtime_autosuspend(dev); 2651 return ret; 2652 } 2653 2654 long amdgpu_drm_ioctl(struct file *filp, 2655 unsigned int cmd, unsigned long arg) 2656 { 2657 struct drm_file *file_priv = filp->private_data; 2658 struct drm_device *dev; 2659 long ret; 2660 dev = file_priv->minor->dev; 2661 ret = pm_runtime_get_sync(dev->dev); 2662 if (ret < 0) 2663 goto out; 2664 2665 ret = drm_ioctl(filp, cmd, arg); 2666 2667 pm_runtime_mark_last_busy(dev->dev); 2668 out: 2669 pm_runtime_put_autosuspend(dev->dev); 2670 return ret; 2671 } 2672 2673 static const struct dev_pm_ops amdgpu_pm_ops = { 2674 .prepare = amdgpu_pmops_prepare, 2675 .complete = amdgpu_pmops_complete, 2676 .suspend = amdgpu_pmops_suspend, 2677 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2678 .resume = amdgpu_pmops_resume, 2679 .freeze = amdgpu_pmops_freeze, 2680 .thaw = amdgpu_pmops_thaw, 2681 .poweroff = amdgpu_pmops_poweroff, 2682 .restore = amdgpu_pmops_restore, 2683 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2684 .runtime_resume = amdgpu_pmops_runtime_resume, 2685 .runtime_idle = amdgpu_pmops_runtime_idle, 2686 }; 2687 2688 static int amdgpu_flush(struct file *f, fl_owner_t id) 2689 { 2690 struct drm_file *file_priv = f->private_data; 2691 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2692 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2693 2694 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2695 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2696 2697 return timeout >= 0 ? 0 : timeout; 2698 } 2699 2700 static const struct file_operations amdgpu_driver_kms_fops = { 2701 .owner = THIS_MODULE, 2702 .open = drm_open, 2703 .flush = amdgpu_flush, 2704 .release = drm_release, 2705 .unlocked_ioctl = amdgpu_drm_ioctl, 2706 .mmap = drm_gem_mmap, 2707 .poll = drm_poll, 2708 .read = drm_read, 2709 #ifdef CONFIG_COMPAT 2710 .compat_ioctl = amdgpu_kms_compat_ioctl, 2711 #endif 2712 #ifdef CONFIG_PROC_FS 2713 .show_fdinfo = amdgpu_show_fdinfo 2714 #endif 2715 }; 2716 2717 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2718 { 2719 struct drm_file *file; 2720 2721 if (!filp) 2722 return -EINVAL; 2723 2724 if (filp->f_op != &amdgpu_driver_kms_fops) { 2725 return -EINVAL; 2726 } 2727 2728 file = filp->private_data; 2729 *fpriv = file->driver_priv; 2730 return 0; 2731 } 2732 2733 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2734 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2735 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2736 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2737 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2738 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2739 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2740 /* KMS */ 2741 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2742 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2743 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2744 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2745 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2746 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2747 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2748 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2749 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2750 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2751 }; 2752 2753 static const struct drm_driver amdgpu_kms_driver = { 2754 .driver_features = 2755 DRIVER_ATOMIC | 2756 DRIVER_GEM | 2757 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2758 DRIVER_SYNCOBJ_TIMELINE, 2759 .open = amdgpu_driver_open_kms, 2760 .postclose = amdgpu_driver_postclose_kms, 2761 .lastclose = amdgpu_driver_lastclose_kms, 2762 .ioctls = amdgpu_ioctls_kms, 2763 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2764 .dumb_create = amdgpu_mode_dumb_create, 2765 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2766 .fops = &amdgpu_driver_kms_fops, 2767 .release = &amdgpu_driver_release_kms, 2768 2769 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2770 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2771 .gem_prime_import = amdgpu_gem_prime_import, 2772 .gem_prime_mmap = drm_gem_prime_mmap, 2773 2774 .name = DRIVER_NAME, 2775 .desc = DRIVER_DESC, 2776 .date = DRIVER_DATE, 2777 .major = KMS_DRIVER_MAJOR, 2778 .minor = KMS_DRIVER_MINOR, 2779 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2780 }; 2781 2782 static struct pci_error_handlers amdgpu_pci_err_handler = { 2783 .error_detected = amdgpu_pci_error_detected, 2784 .mmio_enabled = amdgpu_pci_mmio_enabled, 2785 .slot_reset = amdgpu_pci_slot_reset, 2786 .resume = amdgpu_pci_resume, 2787 }; 2788 2789 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2790 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2791 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2792 2793 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2794 &amdgpu_vram_mgr_attr_group, 2795 &amdgpu_gtt_mgr_attr_group, 2796 &amdgpu_vbios_version_attr_group, 2797 NULL, 2798 }; 2799 2800 2801 static struct pci_driver amdgpu_kms_pci_driver = { 2802 .name = DRIVER_NAME, 2803 .id_table = pciidlist, 2804 .probe = amdgpu_pci_probe, 2805 .remove = amdgpu_pci_remove, 2806 .shutdown = amdgpu_pci_shutdown, 2807 .driver.pm = &amdgpu_pm_ops, 2808 .err_handler = &amdgpu_pci_err_handler, 2809 .dev_groups = amdgpu_sysfs_groups, 2810 }; 2811 2812 static int __init amdgpu_init(void) 2813 { 2814 int r; 2815 2816 if (drm_firmware_drivers_only()) 2817 return -EINVAL; 2818 2819 r = amdgpu_sync_init(); 2820 if (r) 2821 goto error_sync; 2822 2823 r = amdgpu_fence_slab_init(); 2824 if (r) 2825 goto error_fence; 2826 2827 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2828 amdgpu_register_atpx_handler(); 2829 amdgpu_acpi_detect(); 2830 2831 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2832 amdgpu_amdkfd_init(); 2833 2834 /* let modprobe override vga console setting */ 2835 return pci_register_driver(&amdgpu_kms_pci_driver); 2836 2837 error_fence: 2838 amdgpu_sync_fini(); 2839 2840 error_sync: 2841 return r; 2842 } 2843 2844 static void __exit amdgpu_exit(void) 2845 { 2846 amdgpu_amdkfd_fini(); 2847 pci_unregister_driver(&amdgpu_kms_pci_driver); 2848 amdgpu_unregister_atpx_handler(); 2849 amdgpu_sync_fini(); 2850 amdgpu_fence_slab_fini(); 2851 mmu_notifier_synchronize(); 2852 } 2853 2854 module_init(amdgpu_init); 2855 module_exit(amdgpu_exit); 2856 2857 MODULE_AUTHOR(DRIVER_AUTHOR); 2858 MODULE_DESCRIPTION(DRIVER_DESC); 2859 MODULE_LICENSE("GPL and additional rights"); 2860