1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/amdgpu_drm.h> 27 #include <drm/drm_gem.h> 28 #include "amdgpu_drv.h" 29 30 #include <drm/drm_pciids.h> 31 #include <linux/console.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/vga_switcheroo.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_irq.h" 39 #include "amdgpu_gem.h" 40 41 #include "amdgpu_amdkfd.h" 42 43 /* 44 * KMS wrapper. 45 * - 3.0.0 - initial driver 46 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 47 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 48 * at the end of IBs. 49 * - 3.3.0 - Add VM support for UVD on supported hardware. 50 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 51 * - 3.5.0 - Add support for new UVD_NO_OP register. 52 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 53 * - 3.7.0 - Add support for VCE clock list packet 54 * - 3.8.0 - Add support raster config init in the kernel 55 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 56 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 57 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 58 * - 3.12.0 - Add query for double offchip LDS buffers 59 * - 3.13.0 - Add PRT support 60 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 61 * - 3.15.0 - Export more gpu info for gfx9 62 * - 3.16.0 - Add reserved vmid support 63 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 64 * - 3.18.0 - Export gpu always on cu bitmap 65 * - 3.19.0 - Add support for UVD MJPEG decode 66 * - 3.20.0 - Add support for local BOs 67 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 68 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 69 * - 3.23.0 - Add query for VRAM lost counter 70 * - 3.24.0 - Add high priority compute support for gfx9 71 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 72 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 73 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 74 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 75 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 76 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 77 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 78 */ 79 #define KMS_DRIVER_MAJOR 3 80 #define KMS_DRIVER_MINOR 31 81 #define KMS_DRIVER_PATCHLEVEL 0 82 83 int amdgpu_vram_limit = 0; 84 int amdgpu_vis_vram_limit = 0; 85 int amdgpu_gart_size = -1; /* auto */ 86 int amdgpu_gtt_size = -1; /* auto */ 87 int amdgpu_moverate = -1; /* auto */ 88 int amdgpu_benchmarking = 0; 89 int amdgpu_testing = 0; 90 int amdgpu_audio = -1; 91 int amdgpu_disp_priority = 0; 92 int amdgpu_hw_i2c = 0; 93 int amdgpu_pcie_gen2 = -1; 94 int amdgpu_msi = -1; 95 int amdgpu_lockup_timeout = 10000; 96 int amdgpu_dpm = -1; 97 int amdgpu_fw_load_type = -1; 98 int amdgpu_aspm = -1; 99 int amdgpu_runtime_pm = -1; 100 uint amdgpu_ip_block_mask = 0xffffffff; 101 int amdgpu_bapm = -1; 102 int amdgpu_deep_color = 0; 103 int amdgpu_vm_size = -1; 104 int amdgpu_vm_fragment_size = -1; 105 int amdgpu_vm_block_size = -1; 106 int amdgpu_vm_fault_stop = 0; 107 int amdgpu_vm_debug = 0; 108 int amdgpu_vram_page_split = 512; 109 int amdgpu_vm_update_mode = -1; 110 int amdgpu_exp_hw_support = 0; 111 int amdgpu_dc = -1; 112 int amdgpu_sched_jobs = 32; 113 int amdgpu_sched_hw_submission = 2; 114 uint amdgpu_pcie_gen_cap = 0; 115 uint amdgpu_pcie_lane_cap = 0; 116 uint amdgpu_cg_mask = 0xffffffff; 117 uint amdgpu_pg_mask = 0xffffffff; 118 uint amdgpu_sdma_phase_quantum = 32; 119 char *amdgpu_disable_cu = NULL; 120 char *amdgpu_virtual_display = NULL; 121 /* OverDrive(bit 14) disabled by default*/ 122 uint amdgpu_pp_feature_mask = 0xffffbfff; 123 int amdgpu_ngg = 0; 124 int amdgpu_prim_buf_per_se = 0; 125 int amdgpu_pos_buf_per_se = 0; 126 int amdgpu_cntl_sb_buf_per_se = 0; 127 int amdgpu_param_buf_per_se = 0; 128 int amdgpu_job_hang_limit = 0; 129 int amdgpu_lbpw = -1; 130 int amdgpu_compute_multipipe = -1; 131 int amdgpu_gpu_recovery = -1; /* auto */ 132 int amdgpu_emu_mode = 0; 133 uint amdgpu_smu_memory_pool_size = 0; 134 /* FBC (bit 0) disabled by default*/ 135 uint amdgpu_dc_feature_mask = 0; 136 137 struct amdgpu_mgpu_info mgpu_info = { 138 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 139 }; 140 int amdgpu_ras_enable = -1; 141 uint amdgpu_ras_mask = 0xffffffff; 142 143 /** 144 * DOC: vramlimit (int) 145 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 146 */ 147 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 148 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 149 150 /** 151 * DOC: vis_vramlimit (int) 152 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 153 */ 154 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 155 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 156 157 /** 158 * DOC: gartsize (uint) 159 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 160 */ 161 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 162 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 163 164 /** 165 * DOC: gttsize (int) 166 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 167 * otherwise 3/4 RAM size). 168 */ 169 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 170 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 171 172 /** 173 * DOC: moverate (int) 174 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 175 */ 176 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 177 module_param_named(moverate, amdgpu_moverate, int, 0600); 178 179 /** 180 * DOC: benchmark (int) 181 * Run benchmarks. The default is 0 (Skip benchmarks). 182 */ 183 MODULE_PARM_DESC(benchmark, "Run benchmark"); 184 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 185 186 /** 187 * DOC: test (int) 188 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 189 */ 190 MODULE_PARM_DESC(test, "Run tests"); 191 module_param_named(test, amdgpu_testing, int, 0444); 192 193 /** 194 * DOC: audio (int) 195 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 196 */ 197 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 198 module_param_named(audio, amdgpu_audio, int, 0444); 199 200 /** 201 * DOC: disp_priority (int) 202 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 203 */ 204 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 205 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 206 207 /** 208 * DOC: hw_i2c (int) 209 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 210 */ 211 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 212 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 213 214 /** 215 * DOC: pcie_gen2 (int) 216 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 217 */ 218 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 219 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 220 221 /** 222 * DOC: msi (int) 223 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 224 */ 225 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 226 module_param_named(msi, amdgpu_msi, int, 0444); 227 228 /** 229 * DOC: lockup_timeout (int) 230 * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000. 231 * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000. 232 */ 233 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)"); 234 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 235 236 /** 237 * DOC: dpm (int) 238 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto). 239 */ 240 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 241 module_param_named(dpm, amdgpu_dpm, int, 0444); 242 243 /** 244 * DOC: fw_load_type (int) 245 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 246 */ 247 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 248 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 249 250 /** 251 * DOC: aspm (int) 252 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 253 */ 254 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 255 module_param_named(aspm, amdgpu_aspm, int, 0444); 256 257 /** 258 * DOC: runpm (int) 259 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 260 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 261 */ 262 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 263 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 264 265 /** 266 * DOC: ip_block_mask (uint) 267 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 268 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 269 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 270 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 271 */ 272 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 273 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 274 275 /** 276 * DOC: bapm (int) 277 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 278 * The default -1 (auto, enabled) 279 */ 280 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 281 module_param_named(bapm, amdgpu_bapm, int, 0444); 282 283 /** 284 * DOC: deep_color (int) 285 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 286 */ 287 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 288 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 289 290 /** 291 * DOC: vm_size (int) 292 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 293 */ 294 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 295 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 296 297 /** 298 * DOC: vm_fragment_size (int) 299 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 300 */ 301 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 302 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 303 304 /** 305 * DOC: vm_block_size (int) 306 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 307 */ 308 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 309 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 310 311 /** 312 * DOC: vm_fault_stop (int) 313 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 314 */ 315 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 316 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 317 318 /** 319 * DOC: vm_debug (int) 320 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 321 */ 322 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 323 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 324 325 /** 326 * DOC: vm_update_mode (int) 327 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 328 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 329 */ 330 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 331 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 332 333 /** 334 * DOC: vram_page_split (int) 335 * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512. 336 */ 337 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); 338 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 339 340 /** 341 * DOC: exp_hw_support (int) 342 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 343 */ 344 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 345 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 346 347 /** 348 * DOC: dc (int) 349 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 350 */ 351 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 352 module_param_named(dc, amdgpu_dc, int, 0444); 353 354 /** 355 * DOC: sched_jobs (int) 356 * Override the max number of jobs supported in the sw queue. The default is 32. 357 */ 358 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 359 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 360 361 /** 362 * DOC: sched_hw_submission (int) 363 * Override the max number of HW submissions. The default is 2. 364 */ 365 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 366 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 367 368 /** 369 * DOC: ppfeaturemask (uint) 370 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 371 * The default is the current set of stable power features. 372 */ 373 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 374 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 375 376 /** 377 * DOC: pcie_gen_cap (uint) 378 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 379 * The default is 0 (automatic for each asic). 380 */ 381 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 382 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 383 384 /** 385 * DOC: pcie_lane_cap (uint) 386 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 387 * The default is 0 (automatic for each asic). 388 */ 389 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 390 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 391 392 /** 393 * DOC: cg_mask (uint) 394 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 395 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 396 */ 397 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 398 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 399 400 /** 401 * DOC: pg_mask (uint) 402 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 403 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 404 */ 405 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 406 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 407 408 /** 409 * DOC: sdma_phase_quantum (uint) 410 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 411 */ 412 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 413 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 414 415 /** 416 * DOC: disable_cu (charp) 417 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 418 */ 419 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 420 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 421 422 /** 423 * DOC: virtual_display (charp) 424 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 425 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 426 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 427 * device at 26:00.0. The default is NULL. 428 */ 429 MODULE_PARM_DESC(virtual_display, 430 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 431 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 432 433 /** 434 * DOC: ngg (int) 435 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 436 */ 437 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 438 module_param_named(ngg, amdgpu_ngg, int, 0444); 439 440 /** 441 * DOC: prim_buf_per_se (int) 442 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 443 */ 444 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 445 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 446 447 /** 448 * DOC: pos_buf_per_se (int) 449 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 450 */ 451 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 452 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 453 454 /** 455 * DOC: cntl_sb_buf_per_se (int) 456 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 457 */ 458 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 459 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 460 461 /** 462 * DOC: param_buf_per_se (int) 463 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 464 * The default is 0 (depending on gfx). 465 */ 466 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 467 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 468 469 /** 470 * DOC: job_hang_limit (int) 471 * Set how much time allow a job hang and not drop it. The default is 0. 472 */ 473 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 474 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 475 476 /** 477 * DOC: lbpw (int) 478 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 479 */ 480 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 481 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 482 483 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 484 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 485 486 /** 487 * DOC: gpu_recovery (int) 488 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 489 */ 490 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 491 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 492 493 /** 494 * DOC: emu_mode (int) 495 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 496 */ 497 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 498 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 499 500 /** 501 * DOC: ras_enable (int) 502 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 503 */ 504 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 505 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 506 507 /** 508 * DOC: ras_mask (uint) 509 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 510 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 511 */ 512 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 513 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 514 515 /** 516 * DOC: si_support (int) 517 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 518 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 519 * otherwise using amdgpu driver. 520 */ 521 #ifdef CONFIG_DRM_AMDGPU_SI 522 523 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 524 int amdgpu_si_support = 0; 525 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 526 #else 527 int amdgpu_si_support = 1; 528 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 529 #endif 530 531 module_param_named(si_support, amdgpu_si_support, int, 0444); 532 #endif 533 534 /** 535 * DOC: cik_support (int) 536 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 537 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 538 * otherwise using amdgpu driver. 539 */ 540 #ifdef CONFIG_DRM_AMDGPU_CIK 541 542 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 543 int amdgpu_cik_support = 0; 544 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 545 #else 546 int amdgpu_cik_support = 1; 547 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 548 #endif 549 550 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 551 #endif 552 553 /** 554 * DOC: smu_memory_pool_size (uint) 555 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 556 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 557 */ 558 MODULE_PARM_DESC(smu_memory_pool_size, 559 "reserve gtt for smu debug usage, 0 = disable," 560 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 561 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 562 563 #ifdef CONFIG_HSA_AMD 564 /** 565 * DOC: sched_policy (int) 566 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 567 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 568 * assigns queues to HQDs. 569 */ 570 int sched_policy = KFD_SCHED_POLICY_HWS; 571 module_param(sched_policy, int, 0444); 572 MODULE_PARM_DESC(sched_policy, 573 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 574 575 /** 576 * DOC: hws_max_conc_proc (int) 577 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 578 * number of VMIDs assigned to the HWS, which is also the default. 579 */ 580 int hws_max_conc_proc = 8; 581 module_param(hws_max_conc_proc, int, 0444); 582 MODULE_PARM_DESC(hws_max_conc_proc, 583 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 584 585 /** 586 * DOC: cwsr_enable (int) 587 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 588 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 589 * disables it. 590 */ 591 int cwsr_enable = 1; 592 module_param(cwsr_enable, int, 0444); 593 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 594 595 /** 596 * DOC: max_num_of_queues_per_device (int) 597 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 598 * is 4096. 599 */ 600 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 601 module_param(max_num_of_queues_per_device, int, 0444); 602 MODULE_PARM_DESC(max_num_of_queues_per_device, 603 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 604 605 /** 606 * DOC: send_sigterm (int) 607 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 608 * but just print errors on dmesg. Setting 1 enables sending sigterm. 609 */ 610 int send_sigterm; 611 module_param(send_sigterm, int, 0444); 612 MODULE_PARM_DESC(send_sigterm, 613 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 614 615 /** 616 * DOC: debug_largebar (int) 617 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 618 * system. This limits the VRAM size reported to ROCm applications to the visible 619 * size, usually 256MB. 620 * Default value is 0, diabled. 621 */ 622 int debug_largebar; 623 module_param(debug_largebar, int, 0444); 624 MODULE_PARM_DESC(debug_largebar, 625 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 626 627 /** 628 * DOC: ignore_crat (int) 629 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 630 * table to get information about AMD APUs. This option can serve as a workaround on 631 * systems with a broken CRAT table. 632 */ 633 int ignore_crat; 634 module_param(ignore_crat, int, 0444); 635 MODULE_PARM_DESC(ignore_crat, 636 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 637 638 /** 639 * DOC: noretry (int) 640 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry. 641 * Setting 1 disables retry. 642 * Retry is needed for recoverable page faults. 643 */ 644 int noretry; 645 module_param(noretry, int, 0644); 646 MODULE_PARM_DESC(noretry, 647 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); 648 649 /** 650 * DOC: halt_if_hws_hang (int) 651 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 652 * Setting 1 enables halt on hang. 653 */ 654 int halt_if_hws_hang; 655 module_param(halt_if_hws_hang, int, 0644); 656 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 657 #endif 658 659 /** 660 * DOC: dcfeaturemask (uint) 661 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 662 * The default is the current set of stable display features. 663 */ 664 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 665 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 666 667 static const struct pci_device_id pciidlist[] = { 668 #ifdef CONFIG_DRM_AMDGPU_SI 669 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 670 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 671 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 672 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 673 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 674 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 675 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 676 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 677 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 678 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 679 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 680 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 681 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 682 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 683 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 684 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 685 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 686 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 687 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 688 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 689 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 690 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 691 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 692 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 693 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 694 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 695 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 696 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 697 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 698 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 699 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 700 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 701 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 702 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 703 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 704 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 705 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 706 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 707 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 708 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 709 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 710 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 711 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 712 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 713 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 714 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 715 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 716 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 717 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 718 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 719 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 720 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 721 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 722 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 723 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 724 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 725 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 726 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 727 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 728 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 729 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 730 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 731 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 732 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 733 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 734 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 735 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 736 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 737 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 738 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 739 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 740 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 741 #endif 742 #ifdef CONFIG_DRM_AMDGPU_CIK 743 /* Kaveri */ 744 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 745 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 746 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 747 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 748 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 749 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 750 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 751 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 752 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 753 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 754 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 755 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 756 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 757 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 758 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 759 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 760 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 761 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 762 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 763 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 764 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 765 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 766 /* Bonaire */ 767 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 768 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 769 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 770 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 771 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 772 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 773 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 774 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 775 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 776 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 777 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 778 /* Hawaii */ 779 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 780 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 781 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 782 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 783 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 784 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 785 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 786 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 787 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 788 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 789 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 790 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 791 /* Kabini */ 792 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 793 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 794 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 795 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 796 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 797 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 798 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 799 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 800 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 801 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 802 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 803 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 804 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 805 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 806 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 807 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 808 /* mullins */ 809 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 810 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 811 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 812 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 813 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 814 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 815 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 816 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 817 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 818 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 819 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 820 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 821 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 822 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 823 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 824 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 825 #endif 826 /* topaz */ 827 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 828 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 829 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 830 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 831 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 832 /* tonga */ 833 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 834 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 835 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 836 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 837 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 838 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 839 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 840 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 841 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 842 /* fiji */ 843 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 844 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 845 /* carrizo */ 846 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 847 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 848 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 849 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 850 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 851 /* stoney */ 852 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 853 /* Polaris11 */ 854 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 855 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 856 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 857 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 858 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 859 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 860 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 861 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 862 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 863 /* Polaris10 */ 864 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 865 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 866 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 867 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 868 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 869 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 870 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 871 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 872 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 873 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 874 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 875 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 876 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 877 /* Polaris12 */ 878 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 879 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 880 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 881 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 882 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 883 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 884 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 885 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 886 /* VEGAM */ 887 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 888 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 889 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 890 /* Vega 10 */ 891 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 892 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 893 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 894 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 895 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 896 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 897 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 898 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 899 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 900 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 901 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 902 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 903 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 904 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 905 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 906 /* Vega 12 */ 907 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 908 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 909 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 910 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 911 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 912 /* Vega 20 */ 913 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 914 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 915 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 916 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 917 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 918 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 919 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 920 /* Raven */ 921 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 922 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 923 924 {0, 0, 0} 925 }; 926 927 MODULE_DEVICE_TABLE(pci, pciidlist); 928 929 static struct drm_driver kms_driver; 930 931 static int amdgpu_pci_probe(struct pci_dev *pdev, 932 const struct pci_device_id *ent) 933 { 934 struct drm_device *dev; 935 unsigned long flags = ent->driver_data; 936 int ret, retry = 0; 937 bool supports_atomic = false; 938 939 if (!amdgpu_virtual_display && 940 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 941 supports_atomic = true; 942 943 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 944 DRM_INFO("This hardware requires experimental hardware support.\n" 945 "See modparam exp_hw_support\n"); 946 return -ENODEV; 947 } 948 949 /* Get rid of things like offb */ 950 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 951 if (ret) 952 return ret; 953 954 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 955 if (IS_ERR(dev)) 956 return PTR_ERR(dev); 957 958 if (!supports_atomic) 959 dev->driver_features &= ~DRIVER_ATOMIC; 960 961 ret = pci_enable_device(pdev); 962 if (ret) 963 goto err_free; 964 965 dev->pdev = pdev; 966 967 pci_set_drvdata(pdev, dev); 968 969 retry_init: 970 ret = drm_dev_register(dev, ent->driver_data); 971 if (ret == -EAGAIN && ++retry <= 3) { 972 DRM_INFO("retry init %d\n", retry); 973 /* Don't request EX mode too frequently which is attacking */ 974 msleep(5000); 975 goto retry_init; 976 } else if (ret) 977 goto err_pci; 978 979 return 0; 980 981 err_pci: 982 pci_disable_device(pdev); 983 err_free: 984 drm_dev_put(dev); 985 return ret; 986 } 987 988 static void 989 amdgpu_pci_remove(struct pci_dev *pdev) 990 { 991 struct drm_device *dev = pci_get_drvdata(pdev); 992 993 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 994 drm_dev_unplug(dev); 995 drm_dev_put(dev); 996 pci_disable_device(pdev); 997 pci_set_drvdata(pdev, NULL); 998 } 999 1000 static void 1001 amdgpu_pci_shutdown(struct pci_dev *pdev) 1002 { 1003 struct drm_device *dev = pci_get_drvdata(pdev); 1004 struct amdgpu_device *adev = dev->dev_private; 1005 1006 /* if we are running in a VM, make sure the device 1007 * torn down properly on reboot/shutdown. 1008 * unfortunately we can't detect certain 1009 * hypervisors so just do this all the time. 1010 */ 1011 amdgpu_device_ip_suspend(adev); 1012 } 1013 1014 static int amdgpu_pmops_suspend(struct device *dev) 1015 { 1016 struct pci_dev *pdev = to_pci_dev(dev); 1017 1018 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1019 return amdgpu_device_suspend(drm_dev, true, true); 1020 } 1021 1022 static int amdgpu_pmops_resume(struct device *dev) 1023 { 1024 struct pci_dev *pdev = to_pci_dev(dev); 1025 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1026 1027 /* GPU comes up enabled by the bios on resume */ 1028 if (amdgpu_device_is_px(drm_dev)) { 1029 pm_runtime_disable(dev); 1030 pm_runtime_set_active(dev); 1031 pm_runtime_enable(dev); 1032 } 1033 1034 return amdgpu_device_resume(drm_dev, true, true); 1035 } 1036 1037 static int amdgpu_pmops_freeze(struct device *dev) 1038 { 1039 struct pci_dev *pdev = to_pci_dev(dev); 1040 1041 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1042 return amdgpu_device_suspend(drm_dev, false, true); 1043 } 1044 1045 static int amdgpu_pmops_thaw(struct device *dev) 1046 { 1047 struct pci_dev *pdev = to_pci_dev(dev); 1048 1049 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1050 return amdgpu_device_resume(drm_dev, false, true); 1051 } 1052 1053 static int amdgpu_pmops_poweroff(struct device *dev) 1054 { 1055 struct pci_dev *pdev = to_pci_dev(dev); 1056 1057 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1058 return amdgpu_device_suspend(drm_dev, true, true); 1059 } 1060 1061 static int amdgpu_pmops_restore(struct device *dev) 1062 { 1063 struct pci_dev *pdev = to_pci_dev(dev); 1064 1065 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1066 return amdgpu_device_resume(drm_dev, false, true); 1067 } 1068 1069 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1070 { 1071 struct pci_dev *pdev = to_pci_dev(dev); 1072 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1073 int ret; 1074 1075 if (!amdgpu_device_is_px(drm_dev)) { 1076 pm_runtime_forbid(dev); 1077 return -EBUSY; 1078 } 1079 1080 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1081 drm_kms_helper_poll_disable(drm_dev); 1082 1083 ret = amdgpu_device_suspend(drm_dev, false, false); 1084 pci_save_state(pdev); 1085 pci_disable_device(pdev); 1086 pci_ignore_hotplug(pdev); 1087 if (amdgpu_is_atpx_hybrid()) 1088 pci_set_power_state(pdev, PCI_D3cold); 1089 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1090 pci_set_power_state(pdev, PCI_D3hot); 1091 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1092 1093 return 0; 1094 } 1095 1096 static int amdgpu_pmops_runtime_resume(struct device *dev) 1097 { 1098 struct pci_dev *pdev = to_pci_dev(dev); 1099 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1100 int ret; 1101 1102 if (!amdgpu_device_is_px(drm_dev)) 1103 return -EINVAL; 1104 1105 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1106 1107 if (amdgpu_is_atpx_hybrid() || 1108 !amdgpu_has_atpx_dgpu_power_cntl()) 1109 pci_set_power_state(pdev, PCI_D0); 1110 pci_restore_state(pdev); 1111 ret = pci_enable_device(pdev); 1112 if (ret) 1113 return ret; 1114 pci_set_master(pdev); 1115 1116 ret = amdgpu_device_resume(drm_dev, false, false); 1117 drm_kms_helper_poll_enable(drm_dev); 1118 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1119 return 0; 1120 } 1121 1122 static int amdgpu_pmops_runtime_idle(struct device *dev) 1123 { 1124 struct pci_dev *pdev = to_pci_dev(dev); 1125 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1126 struct drm_crtc *crtc; 1127 1128 if (!amdgpu_device_is_px(drm_dev)) { 1129 pm_runtime_forbid(dev); 1130 return -EBUSY; 1131 } 1132 1133 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1134 if (crtc->enabled) { 1135 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1136 return -EBUSY; 1137 } 1138 } 1139 1140 pm_runtime_mark_last_busy(dev); 1141 pm_runtime_autosuspend(dev); 1142 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1143 return 1; 1144 } 1145 1146 long amdgpu_drm_ioctl(struct file *filp, 1147 unsigned int cmd, unsigned long arg) 1148 { 1149 struct drm_file *file_priv = filp->private_data; 1150 struct drm_device *dev; 1151 long ret; 1152 dev = file_priv->minor->dev; 1153 ret = pm_runtime_get_sync(dev->dev); 1154 if (ret < 0) 1155 return ret; 1156 1157 ret = drm_ioctl(filp, cmd, arg); 1158 1159 pm_runtime_mark_last_busy(dev->dev); 1160 pm_runtime_put_autosuspend(dev->dev); 1161 return ret; 1162 } 1163 1164 static const struct dev_pm_ops amdgpu_pm_ops = { 1165 .suspend = amdgpu_pmops_suspend, 1166 .resume = amdgpu_pmops_resume, 1167 .freeze = amdgpu_pmops_freeze, 1168 .thaw = amdgpu_pmops_thaw, 1169 .poweroff = amdgpu_pmops_poweroff, 1170 .restore = amdgpu_pmops_restore, 1171 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1172 .runtime_resume = amdgpu_pmops_runtime_resume, 1173 .runtime_idle = amdgpu_pmops_runtime_idle, 1174 }; 1175 1176 static int amdgpu_flush(struct file *f, fl_owner_t id) 1177 { 1178 struct drm_file *file_priv = f->private_data; 1179 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1180 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1181 1182 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1183 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1184 1185 return timeout >= 0 ? 0 : timeout; 1186 } 1187 1188 static const struct file_operations amdgpu_driver_kms_fops = { 1189 .owner = THIS_MODULE, 1190 .open = drm_open, 1191 .flush = amdgpu_flush, 1192 .release = drm_release, 1193 .unlocked_ioctl = amdgpu_drm_ioctl, 1194 .mmap = amdgpu_mmap, 1195 .poll = drm_poll, 1196 .read = drm_read, 1197 #ifdef CONFIG_COMPAT 1198 .compat_ioctl = amdgpu_kms_compat_ioctl, 1199 #endif 1200 }; 1201 1202 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1203 { 1204 struct drm_file *file; 1205 1206 if (!filp) 1207 return -EINVAL; 1208 1209 if (filp->f_op != &amdgpu_driver_kms_fops) { 1210 return -EINVAL; 1211 } 1212 1213 file = filp->private_data; 1214 *fpriv = file->driver_priv; 1215 return 0; 1216 } 1217 1218 static bool 1219 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1220 bool in_vblank_irq, int *vpos, int *hpos, 1221 ktime_t *stime, ktime_t *etime, 1222 const struct drm_display_mode *mode) 1223 { 1224 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1225 stime, etime, mode); 1226 } 1227 1228 static struct drm_driver kms_driver = { 1229 .driver_features = 1230 DRIVER_USE_AGP | DRIVER_ATOMIC | 1231 DRIVER_GEM | 1232 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1233 .load = amdgpu_driver_load_kms, 1234 .open = amdgpu_driver_open_kms, 1235 .postclose = amdgpu_driver_postclose_kms, 1236 .lastclose = amdgpu_driver_lastclose_kms, 1237 .unload = amdgpu_driver_unload_kms, 1238 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1239 .enable_vblank = amdgpu_enable_vblank_kms, 1240 .disable_vblank = amdgpu_disable_vblank_kms, 1241 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1242 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1243 .irq_handler = amdgpu_irq_handler, 1244 .ioctls = amdgpu_ioctls_kms, 1245 .gem_free_object_unlocked = amdgpu_gem_object_free, 1246 .gem_open_object = amdgpu_gem_object_open, 1247 .gem_close_object = amdgpu_gem_object_close, 1248 .dumb_create = amdgpu_mode_dumb_create, 1249 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1250 .fops = &amdgpu_driver_kms_fops, 1251 1252 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1253 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1254 .gem_prime_export = amdgpu_gem_prime_export, 1255 .gem_prime_import = amdgpu_gem_prime_import, 1256 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1257 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1258 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1259 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1260 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1261 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1262 1263 .name = DRIVER_NAME, 1264 .desc = DRIVER_DESC, 1265 .date = DRIVER_DATE, 1266 .major = KMS_DRIVER_MAJOR, 1267 .minor = KMS_DRIVER_MINOR, 1268 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1269 }; 1270 1271 static struct pci_driver amdgpu_kms_pci_driver = { 1272 .name = DRIVER_NAME, 1273 .id_table = pciidlist, 1274 .probe = amdgpu_pci_probe, 1275 .remove = amdgpu_pci_remove, 1276 .shutdown = amdgpu_pci_shutdown, 1277 .driver.pm = &amdgpu_pm_ops, 1278 }; 1279 1280 1281 1282 static int __init amdgpu_init(void) 1283 { 1284 int r; 1285 1286 if (vgacon_text_force()) { 1287 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1288 return -EINVAL; 1289 } 1290 1291 r = amdgpu_sync_init(); 1292 if (r) 1293 goto error_sync; 1294 1295 r = amdgpu_fence_slab_init(); 1296 if (r) 1297 goto error_fence; 1298 1299 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1300 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1301 amdgpu_register_atpx_handler(); 1302 1303 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1304 amdgpu_amdkfd_init(); 1305 1306 /* let modprobe override vga console setting */ 1307 return pci_register_driver(&amdgpu_kms_pci_driver); 1308 1309 error_fence: 1310 amdgpu_sync_fini(); 1311 1312 error_sync: 1313 return r; 1314 } 1315 1316 static void __exit amdgpu_exit(void) 1317 { 1318 amdgpu_amdkfd_fini(); 1319 pci_unregister_driver(&amdgpu_kms_pci_driver); 1320 amdgpu_unregister_atpx_handler(); 1321 amdgpu_sync_fini(); 1322 amdgpu_fence_slab_fini(); 1323 } 1324 1325 module_init(amdgpu_init); 1326 module_exit(amdgpu_exit); 1327 1328 MODULE_AUTHOR(DRIVER_AUTHOR); 1329 MODULE_DESCRIPTION(DRIVER_DESC); 1330 MODULE_LICENSE("GPL and additional rights"); 1331