1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 105 * - 3.48.0 - Add IP discovery version info to HW INFO 106 * - 3.49.0 - Add gang submit into CS IOCTL 107 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 108 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 109 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 110 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 111 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 112 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 113 * 3.53.0 - Support for GFX11 CP GFX shadowing 114 */ 115 #define KMS_DRIVER_MAJOR 3 116 #define KMS_DRIVER_MINOR 53 117 #define KMS_DRIVER_PATCHLEVEL 0 118 119 unsigned int amdgpu_vram_limit = UINT_MAX; 120 int amdgpu_vis_vram_limit; 121 int amdgpu_gart_size = -1; /* auto */ 122 int amdgpu_gtt_size = -1; /* auto */ 123 int amdgpu_moverate = -1; /* auto */ 124 int amdgpu_audio = -1; 125 int amdgpu_disp_priority; 126 int amdgpu_hw_i2c; 127 int amdgpu_pcie_gen2 = -1; 128 int amdgpu_msi = -1; 129 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 130 int amdgpu_dpm = -1; 131 int amdgpu_fw_load_type = -1; 132 int amdgpu_aspm = -1; 133 int amdgpu_runtime_pm = -1; 134 uint amdgpu_ip_block_mask = 0xffffffff; 135 int amdgpu_bapm = -1; 136 int amdgpu_deep_color; 137 int amdgpu_vm_size = -1; 138 int amdgpu_vm_fragment_size = -1; 139 int amdgpu_vm_block_size = -1; 140 int amdgpu_vm_fault_stop; 141 int amdgpu_vm_debug; 142 int amdgpu_vm_update_mode = -1; 143 int amdgpu_exp_hw_support; 144 int amdgpu_dc = -1; 145 int amdgpu_sched_jobs = 32; 146 int amdgpu_sched_hw_submission = 2; 147 uint amdgpu_pcie_gen_cap; 148 uint amdgpu_pcie_lane_cap; 149 u64 amdgpu_cg_mask = 0xffffffffffffffff; 150 uint amdgpu_pg_mask = 0xffffffff; 151 uint amdgpu_sdma_phase_quantum = 32; 152 char *amdgpu_disable_cu; 153 char *amdgpu_virtual_display; 154 155 /* 156 * OverDrive(bit 14) disabled by default 157 * GFX DCS(bit 19) disabled by default 158 */ 159 uint amdgpu_pp_feature_mask = 0xfff7bfff; 160 uint amdgpu_force_long_training; 161 int amdgpu_lbpw = -1; 162 int amdgpu_compute_multipipe = -1; 163 int amdgpu_gpu_recovery = -1; /* auto */ 164 int amdgpu_emu_mode; 165 uint amdgpu_smu_memory_pool_size; 166 int amdgpu_smu_pptable_id = -1; 167 /* 168 * FBC (bit 0) disabled by default 169 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 170 * - With this, for multiple monitors in sync(e.g. with the same model), 171 * mclk switching will be allowed. And the mclk will be not foced to the 172 * highest. That helps saving some idle power. 173 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 174 * PSR (bit 3) disabled by default 175 * EDP NO POWER SEQUENCING (bit 4) disabled by default 176 */ 177 uint amdgpu_dc_feature_mask = 2; 178 uint amdgpu_dc_debug_mask; 179 uint amdgpu_dc_visual_confirm; 180 int amdgpu_async_gfx_ring = 1; 181 int amdgpu_mcbp; 182 int amdgpu_discovery = -1; 183 int amdgpu_mes; 184 int amdgpu_mes_kiq; 185 int amdgpu_noretry = -1; 186 int amdgpu_force_asic_type = -1; 187 int amdgpu_tmz = -1; /* auto */ 188 uint amdgpu_freesync_vid_mode; 189 int amdgpu_reset_method = -1; /* auto */ 190 int amdgpu_num_kcq = -1; 191 int amdgpu_smartshift_bias; 192 int amdgpu_use_xgmi_p2p = 1; 193 int amdgpu_vcnfw_log; 194 int amdgpu_sg_display = -1; /* auto */ 195 196 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 197 198 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 199 "DRM_UT_CORE", 200 "DRM_UT_DRIVER", 201 "DRM_UT_KMS", 202 "DRM_UT_PRIME", 203 "DRM_UT_ATOMIC", 204 "DRM_UT_VBL", 205 "DRM_UT_STATE", 206 "DRM_UT_LEASE", 207 "DRM_UT_DP", 208 "DRM_UT_DRMRES"); 209 210 struct amdgpu_mgpu_info mgpu_info = { 211 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 212 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 213 mgpu_info.delayed_reset_work, 214 amdgpu_drv_delayed_reset_work_handler, 0), 215 }; 216 int amdgpu_ras_enable = -1; 217 uint amdgpu_ras_mask = 0xffffffff; 218 int amdgpu_bad_page_threshold = -1; 219 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 220 .timeout_fatal_disable = false, 221 .period = 0x0, /* default to 0x0 (timeout disable) */ 222 }; 223 224 /** 225 * DOC: vramlimit (int) 226 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 227 */ 228 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 229 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 230 231 /** 232 * DOC: vis_vramlimit (int) 233 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 234 */ 235 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 236 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 237 238 /** 239 * DOC: gartsize (uint) 240 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 241 * The default is -1 (The size depends on asic). 242 */ 243 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 244 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 245 246 /** 247 * DOC: gttsize (int) 248 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 249 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 250 */ 251 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 252 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 253 254 /** 255 * DOC: moverate (int) 256 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 257 */ 258 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 259 module_param_named(moverate, amdgpu_moverate, int, 0600); 260 261 /** 262 * DOC: audio (int) 263 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 264 */ 265 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 266 module_param_named(audio, amdgpu_audio, int, 0444); 267 268 /** 269 * DOC: disp_priority (int) 270 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 271 */ 272 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 273 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 274 275 /** 276 * DOC: hw_i2c (int) 277 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 278 */ 279 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 280 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 281 282 /** 283 * DOC: pcie_gen2 (int) 284 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 285 */ 286 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 287 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 288 289 /** 290 * DOC: msi (int) 291 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 292 */ 293 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 294 module_param_named(msi, amdgpu_msi, int, 0444); 295 296 /** 297 * DOC: lockup_timeout (string) 298 * Set GPU scheduler timeout value in ms. 299 * 300 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 301 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 302 * to the default timeout. 303 * 304 * - With one value specified, the setting will apply to all non-compute jobs. 305 * - With multiple values specified, the first one will be for GFX. 306 * The second one is for Compute. The third and fourth ones are 307 * for SDMA and Video. 308 * 309 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 310 * jobs is 10000. The timeout for compute is 60000. 311 */ 312 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 313 "for passthrough or sriov, 10000 for all jobs." 314 " 0: keep default value. negative: infinity timeout), " 315 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 316 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 317 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 318 319 /** 320 * DOC: dpm (int) 321 * Override for dynamic power management setting 322 * (0 = disable, 1 = enable) 323 * The default is -1 (auto). 324 */ 325 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 326 module_param_named(dpm, amdgpu_dpm, int, 0444); 327 328 /** 329 * DOC: fw_load_type (int) 330 * Set different firmware loading type for debugging, if supported. 331 * Set to 0 to force direct loading if supported by the ASIC. Set 332 * to -1 to select the default loading mode for the ASIC, as defined 333 * by the driver. The default is -1 (auto). 334 */ 335 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 336 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 337 338 /** 339 * DOC: aspm (int) 340 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 341 */ 342 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 343 module_param_named(aspm, amdgpu_aspm, int, 0444); 344 345 /** 346 * DOC: runpm (int) 347 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 348 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 349 * Setting the value to 0 disables this functionality. 350 */ 351 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 352 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 353 354 /** 355 * DOC: ip_block_mask (uint) 356 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 357 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 358 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 359 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 360 */ 361 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 362 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 363 364 /** 365 * DOC: bapm (int) 366 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 367 * The default -1 (auto, enabled) 368 */ 369 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 370 module_param_named(bapm, amdgpu_bapm, int, 0444); 371 372 /** 373 * DOC: deep_color (int) 374 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 375 */ 376 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 377 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 378 379 /** 380 * DOC: vm_size (int) 381 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 382 */ 383 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 384 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 385 386 /** 387 * DOC: vm_fragment_size (int) 388 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 389 */ 390 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 391 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 392 393 /** 394 * DOC: vm_block_size (int) 395 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 396 */ 397 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 398 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 399 400 /** 401 * DOC: vm_fault_stop (int) 402 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 403 */ 404 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 405 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 406 407 /** 408 * DOC: vm_debug (int) 409 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 410 */ 411 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 412 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 413 414 /** 415 * DOC: vm_update_mode (int) 416 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 417 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 418 */ 419 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 420 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 421 422 /** 423 * DOC: exp_hw_support (int) 424 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 425 */ 426 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 427 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 428 429 /** 430 * DOC: dc (int) 431 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 432 */ 433 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 434 module_param_named(dc, amdgpu_dc, int, 0444); 435 436 /** 437 * DOC: sched_jobs (int) 438 * Override the max number of jobs supported in the sw queue. The default is 32. 439 */ 440 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 441 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 442 443 /** 444 * DOC: sched_hw_submission (int) 445 * Override the max number of HW submissions. The default is 2. 446 */ 447 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 448 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 449 450 /** 451 * DOC: ppfeaturemask (hexint) 452 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 453 * The default is the current set of stable power features. 454 */ 455 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 456 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 457 458 /** 459 * DOC: forcelongtraining (uint) 460 * Force long memory training in resume. 461 * The default is zero, indicates short training in resume. 462 */ 463 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 464 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 465 466 /** 467 * DOC: pcie_gen_cap (uint) 468 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 469 * The default is 0 (automatic for each asic). 470 */ 471 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 472 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 473 474 /** 475 * DOC: pcie_lane_cap (uint) 476 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 477 * The default is 0 (automatic for each asic). 478 */ 479 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 480 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 481 482 /** 483 * DOC: cg_mask (ullong) 484 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 485 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 486 */ 487 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 488 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 489 490 /** 491 * DOC: pg_mask (uint) 492 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 493 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 494 */ 495 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 496 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 497 498 /** 499 * DOC: sdma_phase_quantum (uint) 500 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 501 */ 502 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 503 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 504 505 /** 506 * DOC: disable_cu (charp) 507 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 508 */ 509 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 510 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 511 512 /** 513 * DOC: virtual_display (charp) 514 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 515 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 516 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 517 * device at 26:00.0. The default is NULL. 518 */ 519 MODULE_PARM_DESC(virtual_display, 520 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 521 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 522 523 /** 524 * DOC: lbpw (int) 525 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 526 */ 527 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 528 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 529 530 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 532 533 /** 534 * DOC: gpu_recovery (int) 535 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 536 */ 537 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 538 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 539 540 /** 541 * DOC: emu_mode (int) 542 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 543 */ 544 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 545 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 546 547 /** 548 * DOC: ras_enable (int) 549 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 550 */ 551 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 552 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 553 554 /** 555 * DOC: ras_mask (uint) 556 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 557 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 558 */ 559 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 560 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 561 562 /** 563 * DOC: timeout_fatal_disable (bool) 564 * Disable Watchdog timeout fatal error event 565 */ 566 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 567 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 568 569 /** 570 * DOC: timeout_period (uint) 571 * Modify the watchdog timeout max_cycles as (1 << period) 572 */ 573 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 574 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 575 576 /** 577 * DOC: si_support (int) 578 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 580 * otherwise using amdgpu driver. 581 */ 582 #ifdef CONFIG_DRM_AMDGPU_SI 583 584 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 585 int amdgpu_si_support = 0; 586 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 587 #else 588 int amdgpu_si_support = 1; 589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 590 #endif 591 592 module_param_named(si_support, amdgpu_si_support, int, 0444); 593 #endif 594 595 /** 596 * DOC: cik_support (int) 597 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 598 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 599 * otherwise using amdgpu driver. 600 */ 601 #ifdef CONFIG_DRM_AMDGPU_CIK 602 603 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 604 int amdgpu_cik_support = 0; 605 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 606 #else 607 int amdgpu_cik_support = 1; 608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 609 #endif 610 611 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 612 #endif 613 614 /** 615 * DOC: smu_memory_pool_size (uint) 616 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 617 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 618 */ 619 MODULE_PARM_DESC(smu_memory_pool_size, 620 "reserve gtt for smu debug usage, 0 = disable," 621 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 622 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 623 624 /** 625 * DOC: async_gfx_ring (int) 626 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 627 */ 628 MODULE_PARM_DESC(async_gfx_ring, 629 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 630 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 631 632 /** 633 * DOC: mcbp (int) 634 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 635 */ 636 MODULE_PARM_DESC(mcbp, 637 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 638 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 639 640 /** 641 * DOC: discovery (int) 642 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 643 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 644 */ 645 MODULE_PARM_DESC(discovery, 646 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 647 module_param_named(discovery, amdgpu_discovery, int, 0444); 648 649 /** 650 * DOC: mes (int) 651 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 652 * (0 = disabled (default), 1 = enabled) 653 */ 654 MODULE_PARM_DESC(mes, 655 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 656 module_param_named(mes, amdgpu_mes, int, 0444); 657 658 /** 659 * DOC: mes_kiq (int) 660 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 661 * (0 = disabled (default), 1 = enabled) 662 */ 663 MODULE_PARM_DESC(mes_kiq, 664 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 665 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 666 667 /** 668 * DOC: noretry (int) 669 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 670 * do not support per-process XNACK this also disables retry page faults. 671 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 672 */ 673 MODULE_PARM_DESC(noretry, 674 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 675 module_param_named(noretry, amdgpu_noretry, int, 0644); 676 677 /** 678 * DOC: force_asic_type (int) 679 * A non negative value used to specify the asic type for all supported GPUs. 680 */ 681 MODULE_PARM_DESC(force_asic_type, 682 "A non negative value used to specify the asic type for all supported GPUs"); 683 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 684 685 /** 686 * DOC: use_xgmi_p2p (int) 687 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 688 */ 689 MODULE_PARM_DESC(use_xgmi_p2p, 690 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 691 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 692 693 694 #ifdef CONFIG_HSA_AMD 695 /** 696 * DOC: sched_policy (int) 697 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 698 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 699 * assigns queues to HQDs. 700 */ 701 int sched_policy = KFD_SCHED_POLICY_HWS; 702 module_param(sched_policy, int, 0444); 703 MODULE_PARM_DESC(sched_policy, 704 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 705 706 /** 707 * DOC: hws_max_conc_proc (int) 708 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 709 * number of VMIDs assigned to the HWS, which is also the default. 710 */ 711 int hws_max_conc_proc = -1; 712 module_param(hws_max_conc_proc, int, 0444); 713 MODULE_PARM_DESC(hws_max_conc_proc, 714 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 715 716 /** 717 * DOC: cwsr_enable (int) 718 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 719 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 720 * disables it. 721 */ 722 int cwsr_enable = 1; 723 module_param(cwsr_enable, int, 0444); 724 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 725 726 /** 727 * DOC: max_num_of_queues_per_device (int) 728 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 729 * is 4096. 730 */ 731 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 732 module_param(max_num_of_queues_per_device, int, 0444); 733 MODULE_PARM_DESC(max_num_of_queues_per_device, 734 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 735 736 /** 737 * DOC: send_sigterm (int) 738 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 739 * but just print errors on dmesg. Setting 1 enables sending sigterm. 740 */ 741 int send_sigterm; 742 module_param(send_sigterm, int, 0444); 743 MODULE_PARM_DESC(send_sigterm, 744 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 745 746 /** 747 * DOC: debug_largebar (int) 748 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 749 * system. This limits the VRAM size reported to ROCm applications to the visible 750 * size, usually 256MB. 751 * Default value is 0, diabled. 752 */ 753 int debug_largebar; 754 module_param(debug_largebar, int, 0444); 755 MODULE_PARM_DESC(debug_largebar, 756 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 757 758 /** 759 * DOC: ignore_crat (int) 760 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 761 * table to get information about AMD APUs. This option can serve as a workaround on 762 * systems with a broken CRAT table. 763 * 764 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 765 * whether use CRAT) 766 */ 767 int ignore_crat; 768 module_param(ignore_crat, int, 0444); 769 MODULE_PARM_DESC(ignore_crat, 770 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 771 772 /** 773 * DOC: halt_if_hws_hang (int) 774 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 775 * Setting 1 enables halt on hang. 776 */ 777 int halt_if_hws_hang; 778 module_param(halt_if_hws_hang, int, 0644); 779 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 780 781 /** 782 * DOC: hws_gws_support(bool) 783 * Assume that HWS supports GWS barriers regardless of what firmware version 784 * check says. Default value: false (rely on MEC2 firmware version check). 785 */ 786 bool hws_gws_support; 787 module_param(hws_gws_support, bool, 0444); 788 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 789 790 /** 791 * DOC: queue_preemption_timeout_ms (int) 792 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 793 */ 794 int queue_preemption_timeout_ms = 9000; 795 module_param(queue_preemption_timeout_ms, int, 0644); 796 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 797 798 /** 799 * DOC: debug_evictions(bool) 800 * Enable extra debug messages to help determine the cause of evictions 801 */ 802 bool debug_evictions; 803 module_param(debug_evictions, bool, 0644); 804 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 805 806 /** 807 * DOC: no_system_mem_limit(bool) 808 * Disable system memory limit, to support multiple process shared memory 809 */ 810 bool no_system_mem_limit; 811 module_param(no_system_mem_limit, bool, 0644); 812 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 813 814 /** 815 * DOC: no_queue_eviction_on_vm_fault (int) 816 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 817 */ 818 int amdgpu_no_queue_eviction_on_vm_fault; 819 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 820 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 821 #endif 822 823 /** 824 * DOC: pcie_p2p (bool) 825 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 826 */ 827 #ifdef CONFIG_HSA_AMD_P2P 828 bool pcie_p2p = true; 829 module_param(pcie_p2p, bool, 0444); 830 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 831 #endif 832 833 /** 834 * DOC: dcfeaturemask (uint) 835 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 836 * The default is the current set of stable display features. 837 */ 838 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 839 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 840 841 /** 842 * DOC: dcdebugmask (uint) 843 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 844 */ 845 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 846 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 847 848 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 849 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 850 851 /** 852 * DOC: abmlevel (uint) 853 * Override the default ABM (Adaptive Backlight Management) level used for DC 854 * enabled hardware. Requires DMCU to be supported and loaded. 855 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 856 * default. Values 1-4 control the maximum allowable brightness reduction via 857 * the ABM algorithm, with 1 being the least reduction and 4 being the most 858 * reduction. 859 * 860 * Defaults to 0, or disabled. Userspace can still override this level later 861 * after boot. 862 */ 863 uint amdgpu_dm_abm_level; 864 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 865 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 866 867 int amdgpu_backlight = -1; 868 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 869 module_param_named(backlight, amdgpu_backlight, bint, 0444); 870 871 /** 872 * DOC: tmz (int) 873 * Trusted Memory Zone (TMZ) is a method to protect data being written 874 * to or read from memory. 875 * 876 * The default value: 0 (off). TODO: change to auto till it is completed. 877 */ 878 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 879 module_param_named(tmz, amdgpu_tmz, int, 0444); 880 881 /** 882 * DOC: freesync_video (uint) 883 * Enable the optimization to adjust front porch timing to achieve seamless 884 * mode change experience when setting a freesync supported mode for which full 885 * modeset is not needed. 886 * 887 * The Display Core will add a set of modes derived from the base FreeSync 888 * video mode into the corresponding connector's mode list based on commonly 889 * used refresh rates and VRR range of the connected display, when users enable 890 * this feature. From the userspace perspective, they can see a seamless mode 891 * change experience when the change between different refresh rates under the 892 * same resolution. Additionally, userspace applications such as Video playback 893 * can read this modeset list and change the refresh rate based on the video 894 * frame rate. Finally, the userspace can also derive an appropriate mode for a 895 * particular refresh rate based on the FreeSync Mode and add it to the 896 * connector's mode list. 897 * 898 * Note: This is an experimental feature. 899 * 900 * The default value: 0 (off). 901 */ 902 MODULE_PARM_DESC( 903 freesync_video, 904 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 905 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 906 907 /** 908 * DOC: reset_method (int) 909 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 910 */ 911 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 912 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 913 914 /** 915 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 916 * threshold value of faulty pages detected by RAS ECC, which may 917 * result in the GPU entering bad status when the number of total 918 * faulty pages by ECC exceeds the threshold value. 919 */ 920 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 921 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 922 923 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 924 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 925 926 /** 927 * DOC: vcnfw_log (int) 928 * Enable vcnfw log output for debugging, the default is disabled. 929 */ 930 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 931 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 932 933 /** 934 * DOC: sg_display (int) 935 * Disable S/G (scatter/gather) display (i.e., display from system memory). 936 * This option is only relevant on APUs. Set this option to 0 to disable 937 * S/G display if you experience flickering or other issues under memory 938 * pressure and report the issue. 939 */ 940 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 941 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 942 943 /** 944 * DOC: smu_pptable_id (int) 945 * Used to override pptable id. id = 0 use VBIOS pptable. 946 * id > 0 use the soft pptable with specicfied id. 947 */ 948 MODULE_PARM_DESC(smu_pptable_id, 949 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 950 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 951 952 /* These devices are not supported by amdgpu. 953 * They are supported by the mach64, r128, radeon drivers 954 */ 955 static const u16 amdgpu_unsupported_pciidlist[] = { 956 /* mach64 */ 957 0x4354, 958 0x4358, 959 0x4554, 960 0x4742, 961 0x4744, 962 0x4749, 963 0x474C, 964 0x474D, 965 0x474E, 966 0x474F, 967 0x4750, 968 0x4751, 969 0x4752, 970 0x4753, 971 0x4754, 972 0x4755, 973 0x4756, 974 0x4757, 975 0x4758, 976 0x4759, 977 0x475A, 978 0x4C42, 979 0x4C44, 980 0x4C47, 981 0x4C49, 982 0x4C4D, 983 0x4C4E, 984 0x4C50, 985 0x4C51, 986 0x4C52, 987 0x4C53, 988 0x5654, 989 0x5655, 990 0x5656, 991 /* r128 */ 992 0x4c45, 993 0x4c46, 994 0x4d46, 995 0x4d4c, 996 0x5041, 997 0x5042, 998 0x5043, 999 0x5044, 1000 0x5045, 1001 0x5046, 1002 0x5047, 1003 0x5048, 1004 0x5049, 1005 0x504A, 1006 0x504B, 1007 0x504C, 1008 0x504D, 1009 0x504E, 1010 0x504F, 1011 0x5050, 1012 0x5051, 1013 0x5052, 1014 0x5053, 1015 0x5054, 1016 0x5055, 1017 0x5056, 1018 0x5057, 1019 0x5058, 1020 0x5245, 1021 0x5246, 1022 0x5247, 1023 0x524b, 1024 0x524c, 1025 0x534d, 1026 0x5446, 1027 0x544C, 1028 0x5452, 1029 /* radeon */ 1030 0x3150, 1031 0x3151, 1032 0x3152, 1033 0x3154, 1034 0x3155, 1035 0x3E50, 1036 0x3E54, 1037 0x4136, 1038 0x4137, 1039 0x4144, 1040 0x4145, 1041 0x4146, 1042 0x4147, 1043 0x4148, 1044 0x4149, 1045 0x414A, 1046 0x414B, 1047 0x4150, 1048 0x4151, 1049 0x4152, 1050 0x4153, 1051 0x4154, 1052 0x4155, 1053 0x4156, 1054 0x4237, 1055 0x4242, 1056 0x4336, 1057 0x4337, 1058 0x4437, 1059 0x4966, 1060 0x4967, 1061 0x4A48, 1062 0x4A49, 1063 0x4A4A, 1064 0x4A4B, 1065 0x4A4C, 1066 0x4A4D, 1067 0x4A4E, 1068 0x4A4F, 1069 0x4A50, 1070 0x4A54, 1071 0x4B48, 1072 0x4B49, 1073 0x4B4A, 1074 0x4B4B, 1075 0x4B4C, 1076 0x4C57, 1077 0x4C58, 1078 0x4C59, 1079 0x4C5A, 1080 0x4C64, 1081 0x4C66, 1082 0x4C67, 1083 0x4E44, 1084 0x4E45, 1085 0x4E46, 1086 0x4E47, 1087 0x4E48, 1088 0x4E49, 1089 0x4E4A, 1090 0x4E4B, 1091 0x4E50, 1092 0x4E51, 1093 0x4E52, 1094 0x4E53, 1095 0x4E54, 1096 0x4E56, 1097 0x5144, 1098 0x5145, 1099 0x5146, 1100 0x5147, 1101 0x5148, 1102 0x514C, 1103 0x514D, 1104 0x5157, 1105 0x5158, 1106 0x5159, 1107 0x515A, 1108 0x515E, 1109 0x5460, 1110 0x5462, 1111 0x5464, 1112 0x5548, 1113 0x5549, 1114 0x554A, 1115 0x554B, 1116 0x554C, 1117 0x554D, 1118 0x554E, 1119 0x554F, 1120 0x5550, 1121 0x5551, 1122 0x5552, 1123 0x5554, 1124 0x564A, 1125 0x564B, 1126 0x564F, 1127 0x5652, 1128 0x5653, 1129 0x5657, 1130 0x5834, 1131 0x5835, 1132 0x5954, 1133 0x5955, 1134 0x5974, 1135 0x5975, 1136 0x5960, 1137 0x5961, 1138 0x5962, 1139 0x5964, 1140 0x5965, 1141 0x5969, 1142 0x5a41, 1143 0x5a42, 1144 0x5a61, 1145 0x5a62, 1146 0x5b60, 1147 0x5b62, 1148 0x5b63, 1149 0x5b64, 1150 0x5b65, 1151 0x5c61, 1152 0x5c63, 1153 0x5d48, 1154 0x5d49, 1155 0x5d4a, 1156 0x5d4c, 1157 0x5d4d, 1158 0x5d4e, 1159 0x5d4f, 1160 0x5d50, 1161 0x5d52, 1162 0x5d57, 1163 0x5e48, 1164 0x5e4a, 1165 0x5e4b, 1166 0x5e4c, 1167 0x5e4d, 1168 0x5e4f, 1169 0x6700, 1170 0x6701, 1171 0x6702, 1172 0x6703, 1173 0x6704, 1174 0x6705, 1175 0x6706, 1176 0x6707, 1177 0x6708, 1178 0x6709, 1179 0x6718, 1180 0x6719, 1181 0x671c, 1182 0x671d, 1183 0x671f, 1184 0x6720, 1185 0x6721, 1186 0x6722, 1187 0x6723, 1188 0x6724, 1189 0x6725, 1190 0x6726, 1191 0x6727, 1192 0x6728, 1193 0x6729, 1194 0x6738, 1195 0x6739, 1196 0x673e, 1197 0x6740, 1198 0x6741, 1199 0x6742, 1200 0x6743, 1201 0x6744, 1202 0x6745, 1203 0x6746, 1204 0x6747, 1205 0x6748, 1206 0x6749, 1207 0x674A, 1208 0x6750, 1209 0x6751, 1210 0x6758, 1211 0x6759, 1212 0x675B, 1213 0x675D, 1214 0x675F, 1215 0x6760, 1216 0x6761, 1217 0x6762, 1218 0x6763, 1219 0x6764, 1220 0x6765, 1221 0x6766, 1222 0x6767, 1223 0x6768, 1224 0x6770, 1225 0x6771, 1226 0x6772, 1227 0x6778, 1228 0x6779, 1229 0x677B, 1230 0x6840, 1231 0x6841, 1232 0x6842, 1233 0x6843, 1234 0x6849, 1235 0x684C, 1236 0x6850, 1237 0x6858, 1238 0x6859, 1239 0x6880, 1240 0x6888, 1241 0x6889, 1242 0x688A, 1243 0x688C, 1244 0x688D, 1245 0x6898, 1246 0x6899, 1247 0x689b, 1248 0x689c, 1249 0x689d, 1250 0x689e, 1251 0x68a0, 1252 0x68a1, 1253 0x68a8, 1254 0x68a9, 1255 0x68b0, 1256 0x68b8, 1257 0x68b9, 1258 0x68ba, 1259 0x68be, 1260 0x68bf, 1261 0x68c0, 1262 0x68c1, 1263 0x68c7, 1264 0x68c8, 1265 0x68c9, 1266 0x68d8, 1267 0x68d9, 1268 0x68da, 1269 0x68de, 1270 0x68e0, 1271 0x68e1, 1272 0x68e4, 1273 0x68e5, 1274 0x68e8, 1275 0x68e9, 1276 0x68f1, 1277 0x68f2, 1278 0x68f8, 1279 0x68f9, 1280 0x68fa, 1281 0x68fe, 1282 0x7100, 1283 0x7101, 1284 0x7102, 1285 0x7103, 1286 0x7104, 1287 0x7105, 1288 0x7106, 1289 0x7108, 1290 0x7109, 1291 0x710A, 1292 0x710B, 1293 0x710C, 1294 0x710E, 1295 0x710F, 1296 0x7140, 1297 0x7141, 1298 0x7142, 1299 0x7143, 1300 0x7144, 1301 0x7145, 1302 0x7146, 1303 0x7147, 1304 0x7149, 1305 0x714A, 1306 0x714B, 1307 0x714C, 1308 0x714D, 1309 0x714E, 1310 0x714F, 1311 0x7151, 1312 0x7152, 1313 0x7153, 1314 0x715E, 1315 0x715F, 1316 0x7180, 1317 0x7181, 1318 0x7183, 1319 0x7186, 1320 0x7187, 1321 0x7188, 1322 0x718A, 1323 0x718B, 1324 0x718C, 1325 0x718D, 1326 0x718F, 1327 0x7193, 1328 0x7196, 1329 0x719B, 1330 0x719F, 1331 0x71C0, 1332 0x71C1, 1333 0x71C2, 1334 0x71C3, 1335 0x71C4, 1336 0x71C5, 1337 0x71C6, 1338 0x71C7, 1339 0x71CD, 1340 0x71CE, 1341 0x71D2, 1342 0x71D4, 1343 0x71D5, 1344 0x71D6, 1345 0x71DA, 1346 0x71DE, 1347 0x7200, 1348 0x7210, 1349 0x7211, 1350 0x7240, 1351 0x7243, 1352 0x7244, 1353 0x7245, 1354 0x7246, 1355 0x7247, 1356 0x7248, 1357 0x7249, 1358 0x724A, 1359 0x724B, 1360 0x724C, 1361 0x724D, 1362 0x724E, 1363 0x724F, 1364 0x7280, 1365 0x7281, 1366 0x7283, 1367 0x7284, 1368 0x7287, 1369 0x7288, 1370 0x7289, 1371 0x728B, 1372 0x728C, 1373 0x7290, 1374 0x7291, 1375 0x7293, 1376 0x7297, 1377 0x7834, 1378 0x7835, 1379 0x791e, 1380 0x791f, 1381 0x793f, 1382 0x7941, 1383 0x7942, 1384 0x796c, 1385 0x796d, 1386 0x796e, 1387 0x796f, 1388 0x9400, 1389 0x9401, 1390 0x9402, 1391 0x9403, 1392 0x9405, 1393 0x940A, 1394 0x940B, 1395 0x940F, 1396 0x94A0, 1397 0x94A1, 1398 0x94A3, 1399 0x94B1, 1400 0x94B3, 1401 0x94B4, 1402 0x94B5, 1403 0x94B9, 1404 0x9440, 1405 0x9441, 1406 0x9442, 1407 0x9443, 1408 0x9444, 1409 0x9446, 1410 0x944A, 1411 0x944B, 1412 0x944C, 1413 0x944E, 1414 0x9450, 1415 0x9452, 1416 0x9456, 1417 0x945A, 1418 0x945B, 1419 0x945E, 1420 0x9460, 1421 0x9462, 1422 0x946A, 1423 0x946B, 1424 0x947A, 1425 0x947B, 1426 0x9480, 1427 0x9487, 1428 0x9488, 1429 0x9489, 1430 0x948A, 1431 0x948F, 1432 0x9490, 1433 0x9491, 1434 0x9495, 1435 0x9498, 1436 0x949C, 1437 0x949E, 1438 0x949F, 1439 0x94C0, 1440 0x94C1, 1441 0x94C3, 1442 0x94C4, 1443 0x94C5, 1444 0x94C6, 1445 0x94C7, 1446 0x94C8, 1447 0x94C9, 1448 0x94CB, 1449 0x94CC, 1450 0x94CD, 1451 0x9500, 1452 0x9501, 1453 0x9504, 1454 0x9505, 1455 0x9506, 1456 0x9507, 1457 0x9508, 1458 0x9509, 1459 0x950F, 1460 0x9511, 1461 0x9515, 1462 0x9517, 1463 0x9519, 1464 0x9540, 1465 0x9541, 1466 0x9542, 1467 0x954E, 1468 0x954F, 1469 0x9552, 1470 0x9553, 1471 0x9555, 1472 0x9557, 1473 0x955f, 1474 0x9580, 1475 0x9581, 1476 0x9583, 1477 0x9586, 1478 0x9587, 1479 0x9588, 1480 0x9589, 1481 0x958A, 1482 0x958B, 1483 0x958C, 1484 0x958D, 1485 0x958E, 1486 0x958F, 1487 0x9590, 1488 0x9591, 1489 0x9593, 1490 0x9595, 1491 0x9596, 1492 0x9597, 1493 0x9598, 1494 0x9599, 1495 0x959B, 1496 0x95C0, 1497 0x95C2, 1498 0x95C4, 1499 0x95C5, 1500 0x95C6, 1501 0x95C7, 1502 0x95C9, 1503 0x95CC, 1504 0x95CD, 1505 0x95CE, 1506 0x95CF, 1507 0x9610, 1508 0x9611, 1509 0x9612, 1510 0x9613, 1511 0x9614, 1512 0x9615, 1513 0x9616, 1514 0x9640, 1515 0x9641, 1516 0x9642, 1517 0x9643, 1518 0x9644, 1519 0x9645, 1520 0x9647, 1521 0x9648, 1522 0x9649, 1523 0x964a, 1524 0x964b, 1525 0x964c, 1526 0x964e, 1527 0x964f, 1528 0x9710, 1529 0x9711, 1530 0x9712, 1531 0x9713, 1532 0x9714, 1533 0x9715, 1534 0x9802, 1535 0x9803, 1536 0x9804, 1537 0x9805, 1538 0x9806, 1539 0x9807, 1540 0x9808, 1541 0x9809, 1542 0x980A, 1543 0x9900, 1544 0x9901, 1545 0x9903, 1546 0x9904, 1547 0x9905, 1548 0x9906, 1549 0x9907, 1550 0x9908, 1551 0x9909, 1552 0x990A, 1553 0x990B, 1554 0x990C, 1555 0x990D, 1556 0x990E, 1557 0x990F, 1558 0x9910, 1559 0x9913, 1560 0x9917, 1561 0x9918, 1562 0x9919, 1563 0x9990, 1564 0x9991, 1565 0x9992, 1566 0x9993, 1567 0x9994, 1568 0x9995, 1569 0x9996, 1570 0x9997, 1571 0x9998, 1572 0x9999, 1573 0x999A, 1574 0x999B, 1575 0x999C, 1576 0x999D, 1577 0x99A0, 1578 0x99A2, 1579 0x99A4, 1580 /* radeon secondary ids */ 1581 0x3171, 1582 0x3e70, 1583 0x4164, 1584 0x4165, 1585 0x4166, 1586 0x4168, 1587 0x4170, 1588 0x4171, 1589 0x4172, 1590 0x4173, 1591 0x496e, 1592 0x4a69, 1593 0x4a6a, 1594 0x4a6b, 1595 0x4a70, 1596 0x4a74, 1597 0x4b69, 1598 0x4b6b, 1599 0x4b6c, 1600 0x4c6e, 1601 0x4e64, 1602 0x4e65, 1603 0x4e66, 1604 0x4e67, 1605 0x4e68, 1606 0x4e69, 1607 0x4e6a, 1608 0x4e71, 1609 0x4f73, 1610 0x5569, 1611 0x556b, 1612 0x556d, 1613 0x556f, 1614 0x5571, 1615 0x5854, 1616 0x5874, 1617 0x5940, 1618 0x5941, 1619 0x5b72, 1620 0x5b73, 1621 0x5b74, 1622 0x5b75, 1623 0x5d44, 1624 0x5d45, 1625 0x5d6d, 1626 0x5d6f, 1627 0x5d72, 1628 0x5d77, 1629 0x5e6b, 1630 0x5e6d, 1631 0x7120, 1632 0x7124, 1633 0x7129, 1634 0x712e, 1635 0x712f, 1636 0x7162, 1637 0x7163, 1638 0x7166, 1639 0x7167, 1640 0x7172, 1641 0x7173, 1642 0x71a0, 1643 0x71a1, 1644 0x71a3, 1645 0x71a7, 1646 0x71bb, 1647 0x71e0, 1648 0x71e1, 1649 0x71e2, 1650 0x71e6, 1651 0x71e7, 1652 0x71f2, 1653 0x7269, 1654 0x726b, 1655 0x726e, 1656 0x72a0, 1657 0x72a8, 1658 0x72b1, 1659 0x72b3, 1660 0x793f, 1661 }; 1662 1663 static const struct pci_device_id pciidlist[] = { 1664 #ifdef CONFIG_DRM_AMDGPU_SI 1665 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1666 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1668 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1669 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1670 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1671 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1672 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1673 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1674 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1675 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1676 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1677 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1678 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1679 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1680 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1681 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1682 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1683 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1684 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1685 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1686 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1687 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1688 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1689 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1690 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1691 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1692 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1693 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1694 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1699 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1700 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1701 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1702 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1707 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1708 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1710 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1711 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1716 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1717 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1718 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1719 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1720 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1721 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1722 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1725 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1726 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1727 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1728 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1729 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1730 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1731 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1732 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1736 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1737 #endif 1738 #ifdef CONFIG_DRM_AMDGPU_CIK 1739 /* Kaveri */ 1740 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1742 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1743 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1744 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1745 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1746 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1747 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1748 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1751 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1752 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1753 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1754 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1755 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1756 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1757 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1760 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1761 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1762 /* Bonaire */ 1763 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1764 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1765 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1766 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1767 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1768 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1769 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1770 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1771 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1772 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1773 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1774 /* Hawaii */ 1775 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1776 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1777 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1778 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1779 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1780 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1781 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1782 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1783 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1784 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1785 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1786 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1787 /* Kabini */ 1788 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1789 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1790 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1791 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1792 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1793 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1794 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1795 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1796 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1797 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1798 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1799 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1800 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1801 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1802 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1803 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1804 /* mullins */ 1805 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1806 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1814 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1815 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1816 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1817 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1818 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 #endif 1822 /* topaz */ 1823 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1824 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1825 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1826 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1827 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1828 /* tonga */ 1829 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1830 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1831 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1832 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1833 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1834 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1835 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1836 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1837 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1838 /* fiji */ 1839 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1840 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1841 /* carrizo */ 1842 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1843 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1844 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1845 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1846 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1847 /* stoney */ 1848 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1849 /* Polaris11 */ 1850 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1851 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1852 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1853 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1854 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1855 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1856 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1857 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1858 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1859 /* Polaris10 */ 1860 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1861 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1863 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1864 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1865 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1866 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1867 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1868 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1869 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1870 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1871 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1872 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1873 /* Polaris12 */ 1874 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1875 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1876 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1877 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1878 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1879 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1880 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1881 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1882 /* VEGAM */ 1883 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1884 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1885 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1886 /* Vega 10 */ 1887 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1888 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1893 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1894 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1895 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1896 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1897 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1898 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1899 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1900 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1901 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1902 /* Vega 12 */ 1903 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1904 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1905 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1906 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1907 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1908 /* Vega 20 */ 1909 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1910 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1911 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1912 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1913 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1914 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1915 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1916 /* Raven */ 1917 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1918 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1919 /* Arcturus */ 1920 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1921 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1922 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1923 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1924 /* Navi10 */ 1925 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1926 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1927 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1928 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1929 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1930 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1931 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1932 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1933 /* Navi14 */ 1934 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1935 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1936 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1937 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1938 1939 /* Renoir */ 1940 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1941 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1942 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1943 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1944 1945 /* Navi12 */ 1946 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1947 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1948 1949 /* Sienna_Cichlid */ 1950 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1951 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1953 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1954 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1955 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1956 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1957 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1958 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1959 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1960 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1961 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1962 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1963 1964 /* Yellow Carp */ 1965 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1966 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1967 1968 /* Navy_Flounder */ 1969 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1970 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1971 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1972 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1973 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1974 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1975 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1976 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1977 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1978 1979 /* DIMGREY_CAVEFISH */ 1980 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1981 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1982 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1983 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1984 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1985 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1986 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1987 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1988 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1989 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1990 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1991 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1992 1993 /* Aldebaran */ 1994 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1995 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1996 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1997 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1998 1999 /* CYAN_SKILLFISH */ 2000 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2001 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2002 2003 /* BEIGE_GOBY */ 2004 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2005 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2006 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2007 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2008 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2009 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2010 2011 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2012 .class = PCI_CLASS_DISPLAY_VGA << 8, 2013 .class_mask = 0xffffff, 2014 .driver_data = CHIP_IP_DISCOVERY }, 2015 2016 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2017 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2018 .class_mask = 0xffffff, 2019 .driver_data = CHIP_IP_DISCOVERY }, 2020 2021 {0, 0, 0} 2022 }; 2023 2024 MODULE_DEVICE_TABLE(pci, pciidlist); 2025 2026 static const struct drm_driver amdgpu_kms_driver; 2027 2028 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2029 { 2030 struct pci_dev *p = NULL; 2031 int i; 2032 2033 /* 0 - GPU 2034 * 1 - audio 2035 * 2 - USB 2036 * 3 - UCSI 2037 */ 2038 for (i = 1; i < 4; i++) { 2039 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2040 adev->pdev->bus->number, i); 2041 if (p) { 2042 pm_runtime_get_sync(&p->dev); 2043 pm_runtime_mark_last_busy(&p->dev); 2044 pm_runtime_put_autosuspend(&p->dev); 2045 pci_dev_put(p); 2046 } 2047 } 2048 } 2049 2050 static int amdgpu_pci_probe(struct pci_dev *pdev, 2051 const struct pci_device_id *ent) 2052 { 2053 struct drm_device *ddev; 2054 struct amdgpu_device *adev; 2055 unsigned long flags = ent->driver_data; 2056 int ret, retry = 0, i; 2057 bool supports_atomic = false; 2058 2059 /* skip devices which are owned by radeon */ 2060 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2061 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2062 return -ENODEV; 2063 } 2064 2065 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2066 amdgpu_aspm = 0; 2067 2068 if (amdgpu_virtual_display || 2069 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2070 supports_atomic = true; 2071 2072 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2073 DRM_INFO("This hardware requires experimental hardware support.\n" 2074 "See modparam exp_hw_support\n"); 2075 return -ENODEV; 2076 } 2077 /* differentiate between P10 and P11 asics with the same DID */ 2078 if (pdev->device == 0x67FF && 2079 (pdev->revision == 0xE3 || 2080 pdev->revision == 0xE7 || 2081 pdev->revision == 0xF3 || 2082 pdev->revision == 0xF7)) { 2083 flags &= ~AMD_ASIC_MASK; 2084 flags |= CHIP_POLARIS10; 2085 } 2086 2087 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2088 * however, SME requires an indirect IOMMU mapping because the encryption 2089 * bit is beyond the DMA mask of the chip. 2090 */ 2091 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2092 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2093 dev_info(&pdev->dev, 2094 "SME is not compatible with RAVEN\n"); 2095 return -ENOTSUPP; 2096 } 2097 2098 #ifdef CONFIG_DRM_AMDGPU_SI 2099 if (!amdgpu_si_support) { 2100 switch (flags & AMD_ASIC_MASK) { 2101 case CHIP_TAHITI: 2102 case CHIP_PITCAIRN: 2103 case CHIP_VERDE: 2104 case CHIP_OLAND: 2105 case CHIP_HAINAN: 2106 dev_info(&pdev->dev, 2107 "SI support provided by radeon.\n"); 2108 dev_info(&pdev->dev, 2109 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2110 ); 2111 return -ENODEV; 2112 } 2113 } 2114 #endif 2115 #ifdef CONFIG_DRM_AMDGPU_CIK 2116 if (!amdgpu_cik_support) { 2117 switch (flags & AMD_ASIC_MASK) { 2118 case CHIP_KAVERI: 2119 case CHIP_BONAIRE: 2120 case CHIP_HAWAII: 2121 case CHIP_KABINI: 2122 case CHIP_MULLINS: 2123 dev_info(&pdev->dev, 2124 "CIK support provided by radeon.\n"); 2125 dev_info(&pdev->dev, 2126 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2127 ); 2128 return -ENODEV; 2129 } 2130 } 2131 #endif 2132 2133 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2134 if (IS_ERR(adev)) 2135 return PTR_ERR(adev); 2136 2137 adev->dev = &pdev->dev; 2138 adev->pdev = pdev; 2139 ddev = adev_to_drm(adev); 2140 2141 if (!supports_atomic) 2142 ddev->driver_features &= ~DRIVER_ATOMIC; 2143 2144 ret = pci_enable_device(pdev); 2145 if (ret) 2146 return ret; 2147 2148 pci_set_drvdata(pdev, ddev); 2149 2150 ret = amdgpu_driver_load_kms(adev, flags); 2151 if (ret) 2152 goto err_pci; 2153 2154 retry_init: 2155 ret = drm_dev_register(ddev, flags); 2156 if (ret == -EAGAIN && ++retry <= 3) { 2157 DRM_INFO("retry init %d\n", retry); 2158 /* Don't request EX mode too frequently which is attacking */ 2159 msleep(5000); 2160 goto retry_init; 2161 } else if (ret) { 2162 goto err_pci; 2163 } 2164 2165 /* 2166 * 1. don't init fbdev on hw without DCE 2167 * 2. don't init fbdev if there are no connectors 2168 */ 2169 if (adev->mode_info.mode_config_initialized && 2170 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2171 /* select 8 bpp console on low vram cards */ 2172 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2173 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2174 else 2175 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2176 } 2177 2178 ret = amdgpu_debugfs_init(adev); 2179 if (ret) 2180 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2181 2182 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2183 /* only need to skip on ATPX */ 2184 if (amdgpu_device_supports_px(ddev)) 2185 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2186 /* we want direct complete for BOCO */ 2187 if (amdgpu_device_supports_boco(ddev)) 2188 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2189 DPM_FLAG_SMART_SUSPEND | 2190 DPM_FLAG_MAY_SKIP_RESUME); 2191 pm_runtime_use_autosuspend(ddev->dev); 2192 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2193 2194 pm_runtime_allow(ddev->dev); 2195 2196 pm_runtime_mark_last_busy(ddev->dev); 2197 pm_runtime_put_autosuspend(ddev->dev); 2198 2199 /* 2200 * For runpm implemented via BACO, PMFW will handle the 2201 * timing for BACO in and out: 2202 * - put ASIC into BACO state only when both video and 2203 * audio functions are in D3 state. 2204 * - pull ASIC out of BACO state when either video or 2205 * audio function is in D0 state. 2206 * Also, at startup, PMFW assumes both functions are in 2207 * D0 state. 2208 * 2209 * So if snd driver was loaded prior to amdgpu driver 2210 * and audio function was put into D3 state, there will 2211 * be no PMFW-aware D-state transition(D0->D3) on runpm 2212 * suspend. Thus the BACO will be not correctly kicked in. 2213 * 2214 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2215 * into D0 state. Then there will be a PMFW-aware D-state 2216 * transition(D0->D3) on runpm suspend. 2217 */ 2218 if (amdgpu_device_supports_baco(ddev) && 2219 !(adev->flags & AMD_IS_APU) && 2220 (adev->asic_type >= CHIP_NAVI10)) 2221 amdgpu_get_secondary_funcs(adev); 2222 } 2223 2224 return 0; 2225 2226 err_pci: 2227 pci_disable_device(pdev); 2228 return ret; 2229 } 2230 2231 static void 2232 amdgpu_pci_remove(struct pci_dev *pdev) 2233 { 2234 struct drm_device *dev = pci_get_drvdata(pdev); 2235 struct amdgpu_device *adev = drm_to_adev(dev); 2236 2237 drm_dev_unplug(dev); 2238 2239 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2240 pm_runtime_get_sync(dev->dev); 2241 pm_runtime_forbid(dev->dev); 2242 } 2243 2244 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2245 !amdgpu_sriov_vf(adev)) { 2246 bool need_to_reset_gpu = false; 2247 2248 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2249 struct amdgpu_hive_info *hive; 2250 2251 hive = amdgpu_get_xgmi_hive(adev); 2252 if (hive->device_remove_count == 0) 2253 need_to_reset_gpu = true; 2254 hive->device_remove_count++; 2255 amdgpu_put_xgmi_hive(hive); 2256 } else { 2257 need_to_reset_gpu = true; 2258 } 2259 2260 /* Workaround for ASICs need to reset SMU. 2261 * Called only when the first device is removed. 2262 */ 2263 if (need_to_reset_gpu) { 2264 struct amdgpu_reset_context reset_context; 2265 2266 adev->shutdown = true; 2267 memset(&reset_context, 0, sizeof(reset_context)); 2268 reset_context.method = AMD_RESET_METHOD_NONE; 2269 reset_context.reset_req_dev = adev; 2270 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2271 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2272 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2273 } 2274 } 2275 2276 amdgpu_driver_unload_kms(dev); 2277 2278 /* 2279 * Flush any in flight DMA operations from device. 2280 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2281 * StatusTransactions Pending bit. 2282 */ 2283 pci_disable_device(pdev); 2284 pci_wait_for_pending_transaction(pdev); 2285 } 2286 2287 static void 2288 amdgpu_pci_shutdown(struct pci_dev *pdev) 2289 { 2290 struct drm_device *dev = pci_get_drvdata(pdev); 2291 struct amdgpu_device *adev = drm_to_adev(dev); 2292 2293 if (amdgpu_ras_intr_triggered()) 2294 return; 2295 2296 /* if we are running in a VM, make sure the device 2297 * torn down properly on reboot/shutdown. 2298 * unfortunately we can't detect certain 2299 * hypervisors so just do this all the time. 2300 */ 2301 if (!amdgpu_passthrough(adev)) 2302 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2303 amdgpu_device_ip_suspend(adev); 2304 adev->mp1_state = PP_MP1_STATE_NONE; 2305 } 2306 2307 /** 2308 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2309 * 2310 * @work: work_struct. 2311 */ 2312 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2313 { 2314 struct list_head device_list; 2315 struct amdgpu_device *adev; 2316 int i, r; 2317 struct amdgpu_reset_context reset_context; 2318 2319 memset(&reset_context, 0, sizeof(reset_context)); 2320 2321 mutex_lock(&mgpu_info.mutex); 2322 if (mgpu_info.pending_reset == true) { 2323 mutex_unlock(&mgpu_info.mutex); 2324 return; 2325 } 2326 mgpu_info.pending_reset = true; 2327 mutex_unlock(&mgpu_info.mutex); 2328 2329 /* Use a common context, just need to make sure full reset is done */ 2330 reset_context.method = AMD_RESET_METHOD_NONE; 2331 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2332 2333 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2334 adev = mgpu_info.gpu_ins[i].adev; 2335 reset_context.reset_req_dev = adev; 2336 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2337 if (r) { 2338 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2339 r, adev_to_drm(adev)->unique); 2340 } 2341 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2342 r = -EALREADY; 2343 } 2344 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2345 adev = mgpu_info.gpu_ins[i].adev; 2346 flush_work(&adev->xgmi_reset_work); 2347 adev->gmc.xgmi.pending_reset = false; 2348 } 2349 2350 /* reset function will rebuild the xgmi hive info , clear it now */ 2351 for (i = 0; i < mgpu_info.num_dgpu; i++) 2352 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2353 2354 INIT_LIST_HEAD(&device_list); 2355 2356 for (i = 0; i < mgpu_info.num_dgpu; i++) 2357 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2358 2359 /* unregister the GPU first, reset function will add them back */ 2360 list_for_each_entry(adev, &device_list, reset_list) 2361 amdgpu_unregister_gpu_instance(adev); 2362 2363 /* Use a common context, just need to make sure full reset is done */ 2364 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2365 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2366 2367 if (r) { 2368 DRM_ERROR("reinit gpus failure"); 2369 return; 2370 } 2371 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2372 adev = mgpu_info.gpu_ins[i].adev; 2373 if (!adev->kfd.init_complete) 2374 amdgpu_amdkfd_device_init(adev); 2375 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2376 } 2377 return; 2378 } 2379 2380 static int amdgpu_pmops_prepare(struct device *dev) 2381 { 2382 struct drm_device *drm_dev = dev_get_drvdata(dev); 2383 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2384 2385 /* Return a positive number here so 2386 * DPM_FLAG_SMART_SUSPEND works properly 2387 */ 2388 if (amdgpu_device_supports_boco(drm_dev)) 2389 return pm_runtime_suspended(dev); 2390 2391 /* if we will not support s3 or s2i for the device 2392 * then skip suspend 2393 */ 2394 if (!amdgpu_acpi_is_s0ix_active(adev) && 2395 !amdgpu_acpi_is_s3_active(adev)) 2396 return 1; 2397 2398 return 0; 2399 } 2400 2401 static void amdgpu_pmops_complete(struct device *dev) 2402 { 2403 /* nothing to do */ 2404 } 2405 2406 static int amdgpu_pmops_suspend(struct device *dev) 2407 { 2408 struct drm_device *drm_dev = dev_get_drvdata(dev); 2409 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2410 2411 if (amdgpu_acpi_is_s0ix_active(adev)) 2412 adev->in_s0ix = true; 2413 else if (amdgpu_acpi_is_s3_active(adev)) 2414 adev->in_s3 = true; 2415 if (!adev->in_s0ix && !adev->in_s3) 2416 return 0; 2417 return amdgpu_device_suspend(drm_dev, true); 2418 } 2419 2420 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2421 { 2422 struct drm_device *drm_dev = dev_get_drvdata(dev); 2423 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2424 2425 if (amdgpu_acpi_should_gpu_reset(adev)) 2426 return amdgpu_asic_reset(adev); 2427 2428 return 0; 2429 } 2430 2431 static int amdgpu_pmops_resume(struct device *dev) 2432 { 2433 struct drm_device *drm_dev = dev_get_drvdata(dev); 2434 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2435 int r; 2436 2437 if (!adev->in_s0ix && !adev->in_s3) 2438 return 0; 2439 2440 /* Avoids registers access if device is physically gone */ 2441 if (!pci_device_is_present(adev->pdev)) 2442 adev->no_hw_access = true; 2443 2444 r = amdgpu_device_resume(drm_dev, true); 2445 if (amdgpu_acpi_is_s0ix_active(adev)) 2446 adev->in_s0ix = false; 2447 else 2448 adev->in_s3 = false; 2449 return r; 2450 } 2451 2452 static int amdgpu_pmops_freeze(struct device *dev) 2453 { 2454 struct drm_device *drm_dev = dev_get_drvdata(dev); 2455 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2456 int r; 2457 2458 adev->in_s4 = true; 2459 r = amdgpu_device_suspend(drm_dev, true); 2460 adev->in_s4 = false; 2461 if (r) 2462 return r; 2463 2464 if (amdgpu_acpi_should_gpu_reset(adev)) 2465 return amdgpu_asic_reset(adev); 2466 return 0; 2467 } 2468 2469 static int amdgpu_pmops_thaw(struct device *dev) 2470 { 2471 struct drm_device *drm_dev = dev_get_drvdata(dev); 2472 2473 return amdgpu_device_resume(drm_dev, true); 2474 } 2475 2476 static int amdgpu_pmops_poweroff(struct device *dev) 2477 { 2478 struct drm_device *drm_dev = dev_get_drvdata(dev); 2479 2480 return amdgpu_device_suspend(drm_dev, true); 2481 } 2482 2483 static int amdgpu_pmops_restore(struct device *dev) 2484 { 2485 struct drm_device *drm_dev = dev_get_drvdata(dev); 2486 2487 return amdgpu_device_resume(drm_dev, true); 2488 } 2489 2490 static int amdgpu_runtime_idle_check_display(struct device *dev) 2491 { 2492 struct pci_dev *pdev = to_pci_dev(dev); 2493 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2494 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2495 2496 if (adev->mode_info.num_crtc) { 2497 struct drm_connector *list_connector; 2498 struct drm_connector_list_iter iter; 2499 int ret = 0; 2500 2501 /* XXX: Return busy if any displays are connected to avoid 2502 * possible display wakeups after runtime resume due to 2503 * hotplug events in case any displays were connected while 2504 * the GPU was in suspend. Remove this once that is fixed. 2505 */ 2506 mutex_lock(&drm_dev->mode_config.mutex); 2507 drm_connector_list_iter_begin(drm_dev, &iter); 2508 drm_for_each_connector_iter(list_connector, &iter) { 2509 if (list_connector->status == connector_status_connected) { 2510 ret = -EBUSY; 2511 break; 2512 } 2513 } 2514 drm_connector_list_iter_end(&iter); 2515 mutex_unlock(&drm_dev->mode_config.mutex); 2516 2517 if (ret) 2518 return ret; 2519 2520 if (adev->dc_enabled) { 2521 struct drm_crtc *crtc; 2522 2523 drm_for_each_crtc(crtc, drm_dev) { 2524 drm_modeset_lock(&crtc->mutex, NULL); 2525 if (crtc->state->active) 2526 ret = -EBUSY; 2527 drm_modeset_unlock(&crtc->mutex); 2528 if (ret < 0) 2529 break; 2530 } 2531 } else { 2532 mutex_lock(&drm_dev->mode_config.mutex); 2533 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2534 2535 drm_connector_list_iter_begin(drm_dev, &iter); 2536 drm_for_each_connector_iter(list_connector, &iter) { 2537 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2538 ret = -EBUSY; 2539 break; 2540 } 2541 } 2542 2543 drm_connector_list_iter_end(&iter); 2544 2545 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2546 mutex_unlock(&drm_dev->mode_config.mutex); 2547 } 2548 if (ret) 2549 return ret; 2550 } 2551 2552 return 0; 2553 } 2554 2555 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2556 { 2557 struct pci_dev *pdev = to_pci_dev(dev); 2558 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2559 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2560 int ret, i; 2561 2562 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2563 pm_runtime_forbid(dev); 2564 return -EBUSY; 2565 } 2566 2567 ret = amdgpu_runtime_idle_check_display(dev); 2568 if (ret) 2569 return ret; 2570 2571 /* wait for all rings to drain before suspending */ 2572 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2573 struct amdgpu_ring *ring = adev->rings[i]; 2574 if (ring && ring->sched.ready) { 2575 ret = amdgpu_fence_wait_empty(ring); 2576 if (ret) 2577 return -EBUSY; 2578 } 2579 } 2580 2581 adev->in_runpm = true; 2582 if (amdgpu_device_supports_px(drm_dev)) 2583 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2584 2585 /* 2586 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2587 * proper cleanups and put itself into a state ready for PNP. That 2588 * can address some random resuming failure observed on BOCO capable 2589 * platforms. 2590 * TODO: this may be also needed for PX capable platform. 2591 */ 2592 if (amdgpu_device_supports_boco(drm_dev)) 2593 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2594 2595 ret = amdgpu_device_suspend(drm_dev, false); 2596 if (ret) { 2597 adev->in_runpm = false; 2598 if (amdgpu_device_supports_boco(drm_dev)) 2599 adev->mp1_state = PP_MP1_STATE_NONE; 2600 return ret; 2601 } 2602 2603 if (amdgpu_device_supports_boco(drm_dev)) 2604 adev->mp1_state = PP_MP1_STATE_NONE; 2605 2606 if (amdgpu_device_supports_px(drm_dev)) { 2607 /* Only need to handle PCI state in the driver for ATPX 2608 * PCI core handles it for _PR3. 2609 */ 2610 amdgpu_device_cache_pci_state(pdev); 2611 pci_disable_device(pdev); 2612 pci_ignore_hotplug(pdev); 2613 pci_set_power_state(pdev, PCI_D3cold); 2614 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2615 } else if (amdgpu_device_supports_boco(drm_dev)) { 2616 /* nothing to do */ 2617 } else if (amdgpu_device_supports_baco(drm_dev)) { 2618 amdgpu_device_baco_enter(drm_dev); 2619 } 2620 2621 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2622 2623 return 0; 2624 } 2625 2626 static int amdgpu_pmops_runtime_resume(struct device *dev) 2627 { 2628 struct pci_dev *pdev = to_pci_dev(dev); 2629 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2630 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2631 int ret; 2632 2633 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2634 return -EINVAL; 2635 2636 /* Avoids registers access if device is physically gone */ 2637 if (!pci_device_is_present(adev->pdev)) 2638 adev->no_hw_access = true; 2639 2640 if (amdgpu_device_supports_px(drm_dev)) { 2641 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2642 2643 /* Only need to handle PCI state in the driver for ATPX 2644 * PCI core handles it for _PR3. 2645 */ 2646 pci_set_power_state(pdev, PCI_D0); 2647 amdgpu_device_load_pci_state(pdev); 2648 ret = pci_enable_device(pdev); 2649 if (ret) 2650 return ret; 2651 pci_set_master(pdev); 2652 } else if (amdgpu_device_supports_boco(drm_dev)) { 2653 /* Only need to handle PCI state in the driver for ATPX 2654 * PCI core handles it for _PR3. 2655 */ 2656 pci_set_master(pdev); 2657 } else if (amdgpu_device_supports_baco(drm_dev)) { 2658 amdgpu_device_baco_exit(drm_dev); 2659 } 2660 ret = amdgpu_device_resume(drm_dev, false); 2661 if (ret) { 2662 if (amdgpu_device_supports_px(drm_dev)) 2663 pci_disable_device(pdev); 2664 return ret; 2665 } 2666 2667 if (amdgpu_device_supports_px(drm_dev)) 2668 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2669 adev->in_runpm = false; 2670 return 0; 2671 } 2672 2673 static int amdgpu_pmops_runtime_idle(struct device *dev) 2674 { 2675 struct drm_device *drm_dev = dev_get_drvdata(dev); 2676 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2677 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2678 int ret = 1; 2679 2680 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2681 pm_runtime_forbid(dev); 2682 return -EBUSY; 2683 } 2684 2685 ret = amdgpu_runtime_idle_check_display(dev); 2686 2687 pm_runtime_mark_last_busy(dev); 2688 pm_runtime_autosuspend(dev); 2689 return ret; 2690 } 2691 2692 long amdgpu_drm_ioctl(struct file *filp, 2693 unsigned int cmd, unsigned long arg) 2694 { 2695 struct drm_file *file_priv = filp->private_data; 2696 struct drm_device *dev; 2697 long ret; 2698 dev = file_priv->minor->dev; 2699 ret = pm_runtime_get_sync(dev->dev); 2700 if (ret < 0) 2701 goto out; 2702 2703 ret = drm_ioctl(filp, cmd, arg); 2704 2705 pm_runtime_mark_last_busy(dev->dev); 2706 out: 2707 pm_runtime_put_autosuspend(dev->dev); 2708 return ret; 2709 } 2710 2711 static const struct dev_pm_ops amdgpu_pm_ops = { 2712 .prepare = amdgpu_pmops_prepare, 2713 .complete = amdgpu_pmops_complete, 2714 .suspend = amdgpu_pmops_suspend, 2715 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2716 .resume = amdgpu_pmops_resume, 2717 .freeze = amdgpu_pmops_freeze, 2718 .thaw = amdgpu_pmops_thaw, 2719 .poweroff = amdgpu_pmops_poweroff, 2720 .restore = amdgpu_pmops_restore, 2721 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2722 .runtime_resume = amdgpu_pmops_runtime_resume, 2723 .runtime_idle = amdgpu_pmops_runtime_idle, 2724 }; 2725 2726 static int amdgpu_flush(struct file *f, fl_owner_t id) 2727 { 2728 struct drm_file *file_priv = f->private_data; 2729 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2730 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2731 2732 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2733 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2734 2735 return timeout >= 0 ? 0 : timeout; 2736 } 2737 2738 static const struct file_operations amdgpu_driver_kms_fops = { 2739 .owner = THIS_MODULE, 2740 .open = drm_open, 2741 .flush = amdgpu_flush, 2742 .release = drm_release, 2743 .unlocked_ioctl = amdgpu_drm_ioctl, 2744 .mmap = drm_gem_mmap, 2745 .poll = drm_poll, 2746 .read = drm_read, 2747 #ifdef CONFIG_COMPAT 2748 .compat_ioctl = amdgpu_kms_compat_ioctl, 2749 #endif 2750 #ifdef CONFIG_PROC_FS 2751 .show_fdinfo = amdgpu_show_fdinfo 2752 #endif 2753 }; 2754 2755 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2756 { 2757 struct drm_file *file; 2758 2759 if (!filp) 2760 return -EINVAL; 2761 2762 if (filp->f_op != &amdgpu_driver_kms_fops) { 2763 return -EINVAL; 2764 } 2765 2766 file = filp->private_data; 2767 *fpriv = file->driver_priv; 2768 return 0; 2769 } 2770 2771 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2772 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2773 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2774 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2775 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2776 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2777 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2778 /* KMS */ 2779 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2780 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2781 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2782 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2783 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2784 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2785 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2786 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2787 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2788 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2789 }; 2790 2791 static const struct drm_driver amdgpu_kms_driver = { 2792 .driver_features = 2793 DRIVER_ATOMIC | 2794 DRIVER_GEM | 2795 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2796 DRIVER_SYNCOBJ_TIMELINE, 2797 .open = amdgpu_driver_open_kms, 2798 .postclose = amdgpu_driver_postclose_kms, 2799 .lastclose = amdgpu_driver_lastclose_kms, 2800 .ioctls = amdgpu_ioctls_kms, 2801 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2802 .dumb_create = amdgpu_mode_dumb_create, 2803 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2804 .fops = &amdgpu_driver_kms_fops, 2805 .release = &amdgpu_driver_release_kms, 2806 2807 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2808 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2809 .gem_prime_import = amdgpu_gem_prime_import, 2810 .gem_prime_mmap = drm_gem_prime_mmap, 2811 2812 .name = DRIVER_NAME, 2813 .desc = DRIVER_DESC, 2814 .date = DRIVER_DATE, 2815 .major = KMS_DRIVER_MAJOR, 2816 .minor = KMS_DRIVER_MINOR, 2817 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2818 }; 2819 2820 static struct pci_error_handlers amdgpu_pci_err_handler = { 2821 .error_detected = amdgpu_pci_error_detected, 2822 .mmio_enabled = amdgpu_pci_mmio_enabled, 2823 .slot_reset = amdgpu_pci_slot_reset, 2824 .resume = amdgpu_pci_resume, 2825 }; 2826 2827 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2828 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2829 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2830 2831 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2832 &amdgpu_vram_mgr_attr_group, 2833 &amdgpu_gtt_mgr_attr_group, 2834 &amdgpu_vbios_version_attr_group, 2835 NULL, 2836 }; 2837 2838 2839 static struct pci_driver amdgpu_kms_pci_driver = { 2840 .name = DRIVER_NAME, 2841 .id_table = pciidlist, 2842 .probe = amdgpu_pci_probe, 2843 .remove = amdgpu_pci_remove, 2844 .shutdown = amdgpu_pci_shutdown, 2845 .driver.pm = &amdgpu_pm_ops, 2846 .err_handler = &amdgpu_pci_err_handler, 2847 .dev_groups = amdgpu_sysfs_groups, 2848 }; 2849 2850 static int __init amdgpu_init(void) 2851 { 2852 int r; 2853 2854 if (drm_firmware_drivers_only()) 2855 return -EINVAL; 2856 2857 r = amdgpu_sync_init(); 2858 if (r) 2859 goto error_sync; 2860 2861 r = amdgpu_fence_slab_init(); 2862 if (r) 2863 goto error_fence; 2864 2865 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2866 amdgpu_register_atpx_handler(); 2867 amdgpu_acpi_detect(); 2868 2869 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2870 amdgpu_amdkfd_init(); 2871 2872 /* let modprobe override vga console setting */ 2873 return pci_register_driver(&amdgpu_kms_pci_driver); 2874 2875 error_fence: 2876 amdgpu_sync_fini(); 2877 2878 error_sync: 2879 return r; 2880 } 2881 2882 static void __exit amdgpu_exit(void) 2883 { 2884 amdgpu_amdkfd_fini(); 2885 pci_unregister_driver(&amdgpu_kms_pci_driver); 2886 amdgpu_unregister_atpx_handler(); 2887 amdgpu_sync_fini(); 2888 amdgpu_fence_slab_fini(); 2889 mmu_notifier_synchronize(); 2890 } 2891 2892 module_init(amdgpu_init); 2893 module_exit(amdgpu_exit); 2894 2895 MODULE_AUTHOR(DRIVER_AUTHOR); 2896 MODULE_DESCRIPTION(DRIVER_DESC); 2897 MODULE_LICENSE("GPL and additional rights"); 2898