1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/console.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 40 #include "amdgpu.h" 41 #include "amdgpu_irq.h" 42 #include "amdgpu_dma_buf.h" 43 #include "amdgpu_sched.h" 44 45 #include "amdgpu_amdkfd.h" 46 47 #include "amdgpu_ras.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 * - 3.16.0 - Add reserved vmid support 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 70 * - 3.18.0 - Export gpu always on cu bitmap 71 * - 3.19.0 - Add support for UVD MJPEG decode 72 * - 3.20.0 - Add support for local BOs 73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 75 * - 3.23.0 - Add query for VRAM lost counter 76 * - 3.24.0 - Add high priority compute support for gfx9 77 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 78 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 79 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 80 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 81 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 82 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 83 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 84 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 85 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 86 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 87 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 88 * - 3.36.0 - Allow reading more status registers on si/cik 89 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 90 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 91 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 92 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 93 * - 3.41.0 - Add video codec query 94 */ 95 #define KMS_DRIVER_MAJOR 3 96 #define KMS_DRIVER_MINOR 41 97 #define KMS_DRIVER_PATCHLEVEL 0 98 99 int amdgpu_vram_limit; 100 int amdgpu_vis_vram_limit; 101 int amdgpu_gart_size = -1; /* auto */ 102 int amdgpu_gtt_size = -1; /* auto */ 103 int amdgpu_moverate = -1; /* auto */ 104 int amdgpu_benchmarking; 105 int amdgpu_testing; 106 int amdgpu_audio = -1; 107 int amdgpu_disp_priority; 108 int amdgpu_hw_i2c; 109 int amdgpu_pcie_gen2 = -1; 110 int amdgpu_msi = -1; 111 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 112 int amdgpu_dpm = -1; 113 int amdgpu_fw_load_type = -1; 114 int amdgpu_aspm = -1; 115 int amdgpu_runtime_pm = -1; 116 uint amdgpu_ip_block_mask = 0xffffffff; 117 int amdgpu_bapm = -1; 118 int amdgpu_deep_color; 119 int amdgpu_vm_size = -1; 120 int amdgpu_vm_fragment_size = -1; 121 int amdgpu_vm_block_size = -1; 122 int amdgpu_vm_fault_stop; 123 int amdgpu_vm_debug; 124 int amdgpu_vm_update_mode = -1; 125 int amdgpu_exp_hw_support; 126 int amdgpu_dc = -1; 127 int amdgpu_sched_jobs = 32; 128 int amdgpu_sched_hw_submission = 2; 129 uint amdgpu_pcie_gen_cap; 130 uint amdgpu_pcie_lane_cap; 131 uint amdgpu_cg_mask = 0xffffffff; 132 uint amdgpu_pg_mask = 0xffffffff; 133 uint amdgpu_sdma_phase_quantum = 32; 134 char *amdgpu_disable_cu = NULL; 135 char *amdgpu_virtual_display = NULL; 136 137 /* 138 * OverDrive(bit 14) disabled by default 139 * GFX DCS(bit 19) disabled by default 140 */ 141 uint amdgpu_pp_feature_mask = 0xfff7bfff; 142 uint amdgpu_force_long_training; 143 int amdgpu_job_hang_limit; 144 int amdgpu_lbpw = -1; 145 int amdgpu_compute_multipipe = -1; 146 int amdgpu_gpu_recovery = -1; /* auto */ 147 int amdgpu_emu_mode; 148 uint amdgpu_smu_memory_pool_size; 149 /* 150 * FBC (bit 0) disabled by default 151 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 152 * - With this, for multiple monitors in sync(e.g. with the same model), 153 * mclk switching will be allowed. And the mclk will be not foced to the 154 * highest. That helps saving some idle power. 155 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 156 * PSR (bit 3) disabled by default 157 */ 158 uint amdgpu_dc_feature_mask = 2; 159 uint amdgpu_dc_debug_mask; 160 int amdgpu_async_gfx_ring = 1; 161 int amdgpu_mcbp; 162 int amdgpu_discovery = -1; 163 int amdgpu_mes; 164 int amdgpu_noretry = -1; 165 int amdgpu_force_asic_type = -1; 166 int amdgpu_tmz; 167 uint amdgpu_freesync_vid_mode; 168 int amdgpu_reset_method = -1; /* auto */ 169 int amdgpu_num_kcq = -1; 170 171 struct amdgpu_mgpu_info mgpu_info = { 172 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 173 }; 174 int amdgpu_ras_enable = -1; 175 uint amdgpu_ras_mask = 0xffffffff; 176 int amdgpu_bad_page_threshold = 100; 177 178 /** 179 * DOC: vramlimit (int) 180 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 181 */ 182 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 183 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 184 185 /** 186 * DOC: vis_vramlimit (int) 187 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 188 */ 189 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 190 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 191 192 /** 193 * DOC: gartsize (uint) 194 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 195 */ 196 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 197 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 198 199 /** 200 * DOC: gttsize (int) 201 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 202 * otherwise 3/4 RAM size). 203 */ 204 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 205 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 206 207 /** 208 * DOC: moverate (int) 209 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 210 */ 211 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 212 module_param_named(moverate, amdgpu_moverate, int, 0600); 213 214 /** 215 * DOC: benchmark (int) 216 * Run benchmarks. The default is 0 (Skip benchmarks). 217 */ 218 MODULE_PARM_DESC(benchmark, "Run benchmark"); 219 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 220 221 /** 222 * DOC: test (int) 223 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 224 */ 225 MODULE_PARM_DESC(test, "Run tests"); 226 module_param_named(test, amdgpu_testing, int, 0444); 227 228 /** 229 * DOC: audio (int) 230 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 231 */ 232 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 233 module_param_named(audio, amdgpu_audio, int, 0444); 234 235 /** 236 * DOC: disp_priority (int) 237 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 238 */ 239 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 240 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 241 242 /** 243 * DOC: hw_i2c (int) 244 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 245 */ 246 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 247 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 248 249 /** 250 * DOC: pcie_gen2 (int) 251 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 252 */ 253 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 254 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 255 256 /** 257 * DOC: msi (int) 258 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 259 */ 260 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 261 module_param_named(msi, amdgpu_msi, int, 0444); 262 263 /** 264 * DOC: lockup_timeout (string) 265 * Set GPU scheduler timeout value in ms. 266 * 267 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 268 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 269 * to the default timeout. 270 * 271 * - With one value specified, the setting will apply to all non-compute jobs. 272 * - With multiple values specified, the first one will be for GFX. 273 * The second one is for Compute. The third and fourth ones are 274 * for SDMA and Video. 275 * 276 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 277 * jobs is 10000. And there is no timeout enforced on compute jobs. 278 */ 279 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 280 "for passthrough or sriov, 10000 for all jobs." 281 " 0: keep default value. negative: infinity timeout), " 282 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 283 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 284 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 285 286 /** 287 * DOC: dpm (int) 288 * Override for dynamic power management setting 289 * (0 = disable, 1 = enable) 290 * The default is -1 (auto). 291 */ 292 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 293 module_param_named(dpm, amdgpu_dpm, int, 0444); 294 295 /** 296 * DOC: fw_load_type (int) 297 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 298 */ 299 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 300 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 301 302 /** 303 * DOC: aspm (int) 304 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 305 */ 306 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 307 module_param_named(aspm, amdgpu_aspm, int, 0444); 308 309 /** 310 * DOC: runpm (int) 311 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 312 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 313 */ 314 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 315 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 316 317 /** 318 * DOC: ip_block_mask (uint) 319 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 320 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 321 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 322 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 323 */ 324 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 325 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 326 327 /** 328 * DOC: bapm (int) 329 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 330 * The default -1 (auto, enabled) 331 */ 332 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 333 module_param_named(bapm, amdgpu_bapm, int, 0444); 334 335 /** 336 * DOC: deep_color (int) 337 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 338 */ 339 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 340 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 341 342 /** 343 * DOC: vm_size (int) 344 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 345 */ 346 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 347 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 348 349 /** 350 * DOC: vm_fragment_size (int) 351 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 352 */ 353 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 354 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 355 356 /** 357 * DOC: vm_block_size (int) 358 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 359 */ 360 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 361 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 362 363 /** 364 * DOC: vm_fault_stop (int) 365 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 366 */ 367 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 368 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 369 370 /** 371 * DOC: vm_debug (int) 372 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 373 */ 374 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 375 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 376 377 /** 378 * DOC: vm_update_mode (int) 379 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 380 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 381 */ 382 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 383 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 384 385 /** 386 * DOC: exp_hw_support (int) 387 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 388 */ 389 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 390 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 391 392 /** 393 * DOC: dc (int) 394 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 395 */ 396 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 397 module_param_named(dc, amdgpu_dc, int, 0444); 398 399 /** 400 * DOC: sched_jobs (int) 401 * Override the max number of jobs supported in the sw queue. The default is 32. 402 */ 403 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 404 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 405 406 /** 407 * DOC: sched_hw_submission (int) 408 * Override the max number of HW submissions. The default is 2. 409 */ 410 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 411 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 412 413 /** 414 * DOC: ppfeaturemask (hexint) 415 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 416 * The default is the current set of stable power features. 417 */ 418 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 419 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 420 421 /** 422 * DOC: forcelongtraining (uint) 423 * Force long memory training in resume. 424 * The default is zero, indicates short training in resume. 425 */ 426 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 427 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 428 429 /** 430 * DOC: pcie_gen_cap (uint) 431 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 432 * The default is 0 (automatic for each asic). 433 */ 434 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 435 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 436 437 /** 438 * DOC: pcie_lane_cap (uint) 439 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 440 * The default is 0 (automatic for each asic). 441 */ 442 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 443 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 444 445 /** 446 * DOC: cg_mask (uint) 447 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 448 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 449 */ 450 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 451 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 452 453 /** 454 * DOC: pg_mask (uint) 455 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 456 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 457 */ 458 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 459 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 460 461 /** 462 * DOC: sdma_phase_quantum (uint) 463 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 464 */ 465 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 466 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 467 468 /** 469 * DOC: disable_cu (charp) 470 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 471 */ 472 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 473 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 474 475 /** 476 * DOC: virtual_display (charp) 477 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 478 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 479 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 480 * device at 26:00.0. The default is NULL. 481 */ 482 MODULE_PARM_DESC(virtual_display, 483 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 484 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 485 486 /** 487 * DOC: job_hang_limit (int) 488 * Set how much time allow a job hang and not drop it. The default is 0. 489 */ 490 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 491 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 492 493 /** 494 * DOC: lbpw (int) 495 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 496 */ 497 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 498 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 499 500 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 501 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 502 503 /** 504 * DOC: gpu_recovery (int) 505 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 506 */ 507 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 508 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 509 510 /** 511 * DOC: emu_mode (int) 512 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 513 */ 514 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 515 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 516 517 /** 518 * DOC: ras_enable (int) 519 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 520 */ 521 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 522 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 523 524 /** 525 * DOC: ras_mask (uint) 526 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 527 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 528 */ 529 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 530 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 531 532 /** 533 * DOC: si_support (int) 534 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 535 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 536 * otherwise using amdgpu driver. 537 */ 538 #ifdef CONFIG_DRM_AMDGPU_SI 539 540 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 541 int amdgpu_si_support = 0; 542 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 543 #else 544 int amdgpu_si_support = 1; 545 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 546 #endif 547 548 module_param_named(si_support, amdgpu_si_support, int, 0444); 549 #endif 550 551 /** 552 * DOC: cik_support (int) 553 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 554 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 555 * otherwise using amdgpu driver. 556 */ 557 #ifdef CONFIG_DRM_AMDGPU_CIK 558 559 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 560 int amdgpu_cik_support = 0; 561 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 562 #else 563 int amdgpu_cik_support = 1; 564 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 565 #endif 566 567 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 568 #endif 569 570 /** 571 * DOC: smu_memory_pool_size (uint) 572 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 573 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 574 */ 575 MODULE_PARM_DESC(smu_memory_pool_size, 576 "reserve gtt for smu debug usage, 0 = disable," 577 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 578 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 579 580 /** 581 * DOC: async_gfx_ring (int) 582 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 583 */ 584 MODULE_PARM_DESC(async_gfx_ring, 585 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 586 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 587 588 /** 589 * DOC: mcbp (int) 590 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 591 */ 592 MODULE_PARM_DESC(mcbp, 593 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 594 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 595 596 /** 597 * DOC: discovery (int) 598 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 599 * (-1 = auto (default), 0 = disabled, 1 = enabled) 600 */ 601 MODULE_PARM_DESC(discovery, 602 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 603 module_param_named(discovery, amdgpu_discovery, int, 0444); 604 605 /** 606 * DOC: mes (int) 607 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 608 * (0 = disabled (default), 1 = enabled) 609 */ 610 MODULE_PARM_DESC(mes, 611 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 612 module_param_named(mes, amdgpu_mes, int, 0444); 613 614 /** 615 * DOC: noretry (int) 616 * Disable retry faults in the GPU memory controller. 617 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 618 */ 619 MODULE_PARM_DESC(noretry, 620 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 621 module_param_named(noretry, amdgpu_noretry, int, 0644); 622 623 /** 624 * DOC: force_asic_type (int) 625 * A non negative value used to specify the asic type for all supported GPUs. 626 */ 627 MODULE_PARM_DESC(force_asic_type, 628 "A non negative value used to specify the asic type for all supported GPUs"); 629 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 630 631 632 633 #ifdef CONFIG_HSA_AMD 634 /** 635 * DOC: sched_policy (int) 636 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 637 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 638 * assigns queues to HQDs. 639 */ 640 int sched_policy = KFD_SCHED_POLICY_HWS; 641 module_param(sched_policy, int, 0444); 642 MODULE_PARM_DESC(sched_policy, 643 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 644 645 /** 646 * DOC: hws_max_conc_proc (int) 647 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 648 * number of VMIDs assigned to the HWS, which is also the default. 649 */ 650 int hws_max_conc_proc = 8; 651 module_param(hws_max_conc_proc, int, 0444); 652 MODULE_PARM_DESC(hws_max_conc_proc, 653 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 654 655 /** 656 * DOC: cwsr_enable (int) 657 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 658 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 659 * disables it. 660 */ 661 int cwsr_enable = 1; 662 module_param(cwsr_enable, int, 0444); 663 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 664 665 /** 666 * DOC: max_num_of_queues_per_device (int) 667 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 668 * is 4096. 669 */ 670 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 671 module_param(max_num_of_queues_per_device, int, 0444); 672 MODULE_PARM_DESC(max_num_of_queues_per_device, 673 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 674 675 /** 676 * DOC: send_sigterm (int) 677 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 678 * but just print errors on dmesg. Setting 1 enables sending sigterm. 679 */ 680 int send_sigterm; 681 module_param(send_sigterm, int, 0444); 682 MODULE_PARM_DESC(send_sigterm, 683 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 684 685 /** 686 * DOC: debug_largebar (int) 687 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 688 * system. This limits the VRAM size reported to ROCm applications to the visible 689 * size, usually 256MB. 690 * Default value is 0, diabled. 691 */ 692 int debug_largebar; 693 module_param(debug_largebar, int, 0444); 694 MODULE_PARM_DESC(debug_largebar, 695 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 696 697 /** 698 * DOC: ignore_crat (int) 699 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 700 * table to get information about AMD APUs. This option can serve as a workaround on 701 * systems with a broken CRAT table. 702 * 703 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 704 * whehter use CRAT) 705 */ 706 int ignore_crat; 707 module_param(ignore_crat, int, 0444); 708 MODULE_PARM_DESC(ignore_crat, 709 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 710 711 /** 712 * DOC: halt_if_hws_hang (int) 713 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 714 * Setting 1 enables halt on hang. 715 */ 716 int halt_if_hws_hang; 717 module_param(halt_if_hws_hang, int, 0644); 718 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 719 720 /** 721 * DOC: hws_gws_support(bool) 722 * Assume that HWS supports GWS barriers regardless of what firmware version 723 * check says. Default value: false (rely on MEC2 firmware version check). 724 */ 725 bool hws_gws_support; 726 module_param(hws_gws_support, bool, 0444); 727 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 728 729 /** 730 * DOC: queue_preemption_timeout_ms (int) 731 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 732 */ 733 int queue_preemption_timeout_ms = 9000; 734 module_param(queue_preemption_timeout_ms, int, 0644); 735 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 736 737 /** 738 * DOC: debug_evictions(bool) 739 * Enable extra debug messages to help determine the cause of evictions 740 */ 741 bool debug_evictions; 742 module_param(debug_evictions, bool, 0644); 743 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 744 745 /** 746 * DOC: no_system_mem_limit(bool) 747 * Disable system memory limit, to support multiple process shared memory 748 */ 749 bool no_system_mem_limit; 750 module_param(no_system_mem_limit, bool, 0644); 751 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 752 753 #endif 754 755 /** 756 * DOC: dcfeaturemask (uint) 757 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 758 * The default is the current set of stable display features. 759 */ 760 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 761 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 762 763 /** 764 * DOC: dcdebugmask (uint) 765 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 766 */ 767 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 768 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 769 770 /** 771 * DOC: abmlevel (uint) 772 * Override the default ABM (Adaptive Backlight Management) level used for DC 773 * enabled hardware. Requires DMCU to be supported and loaded. 774 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 775 * default. Values 1-4 control the maximum allowable brightness reduction via 776 * the ABM algorithm, with 1 being the least reduction and 4 being the most 777 * reduction. 778 * 779 * Defaults to 0, or disabled. Userspace can still override this level later 780 * after boot. 781 */ 782 uint amdgpu_dm_abm_level; 783 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 784 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 785 786 /** 787 * DOC: tmz (int) 788 * Trusted Memory Zone (TMZ) is a method to protect data being written 789 * to or read from memory. 790 * 791 * The default value: 0 (off). TODO: change to auto till it is completed. 792 */ 793 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); 794 module_param_named(tmz, amdgpu_tmz, int, 0444); 795 796 /** 797 * DOC: freesync_video (uint) 798 * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience 799 * when setting a freesync supported mode for which full modeset is not needed. 800 * The default value: 0 (off). 801 */ 802 MODULE_PARM_DESC( 803 freesync_video, 804 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 805 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 806 807 /** 808 * DOC: reset_method (int) 809 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 810 */ 811 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 812 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 813 814 /** 815 * DOC: bad_page_threshold (int) 816 * Bad page threshold is to specify the threshold value of faulty pages 817 * detected by RAS ECC, that may result in GPU entering bad status if total 818 * faulty pages by ECC exceed threshold value and leave it for user's further 819 * check. 820 */ 821 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto, 0 = disable bad page retirement, 100 = default value"); 822 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 823 824 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 825 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 826 827 static const struct pci_device_id pciidlist[] = { 828 #ifdef CONFIG_DRM_AMDGPU_SI 829 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 830 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 831 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 832 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 833 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 834 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 835 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 836 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 837 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 838 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 839 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 840 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 841 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 842 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 843 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 844 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 845 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 846 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 847 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 848 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 849 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 850 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 851 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 852 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 853 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 854 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 855 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 856 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 857 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 858 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 859 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 860 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 861 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 862 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 863 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 864 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 865 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 866 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 867 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 868 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 869 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 870 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 871 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 872 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 873 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 874 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 875 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 876 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 877 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 878 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 879 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 880 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 881 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 882 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 883 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 884 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 885 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 886 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 887 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 888 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 889 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 890 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 891 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 892 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 893 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 894 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 895 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 896 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 897 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 898 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 899 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 900 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 901 #endif 902 #ifdef CONFIG_DRM_AMDGPU_CIK 903 /* Kaveri */ 904 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 905 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 906 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 907 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 908 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 909 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 910 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 911 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 912 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 913 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 914 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 915 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 916 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 917 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 918 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 919 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 920 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 921 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 922 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 923 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 924 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 925 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 926 /* Bonaire */ 927 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 928 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 929 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 930 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 931 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 932 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 933 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 934 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 935 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 936 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 937 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 938 /* Hawaii */ 939 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 940 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 941 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 942 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 943 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 944 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 945 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 946 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 947 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 948 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 949 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 950 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 951 /* Kabini */ 952 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 953 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 954 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 955 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 956 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 957 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 958 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 959 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 960 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 961 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 962 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 963 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 964 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 965 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 966 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 967 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 968 /* mullins */ 969 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 970 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 971 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 972 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 973 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 974 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 975 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 976 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 977 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 978 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 979 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 980 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 981 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 982 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 983 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 984 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 985 #endif 986 /* topaz */ 987 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 988 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 989 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 990 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 991 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 992 /* tonga */ 993 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 994 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 995 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 996 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 997 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 998 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 999 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1000 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1001 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1002 /* fiji */ 1003 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1004 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1005 /* carrizo */ 1006 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1007 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1008 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1009 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1010 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1011 /* stoney */ 1012 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1013 /* Polaris11 */ 1014 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1015 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1016 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1017 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1018 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1019 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1020 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1021 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1022 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1023 /* Polaris10 */ 1024 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1025 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1026 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1027 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1028 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1029 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1030 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1031 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1032 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1033 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1034 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1035 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1036 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1037 /* Polaris12 */ 1038 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1039 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1040 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1041 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1042 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1043 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1044 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1045 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1046 /* VEGAM */ 1047 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1048 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1049 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1050 /* Vega 10 */ 1051 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1052 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1053 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1054 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1055 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1056 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1057 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1058 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1059 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1060 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1061 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1062 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1063 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1064 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1065 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1066 /* Vega 12 */ 1067 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1068 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1069 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1070 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1071 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1072 /* Vega 20 */ 1073 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1074 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1075 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1076 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1077 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1078 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1079 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1080 /* Raven */ 1081 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1082 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1083 /* Arcturus */ 1084 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1085 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1086 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1087 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1088 /* Navi10 */ 1089 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1090 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1091 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1092 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1093 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1094 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1095 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1096 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1097 /* Navi14 */ 1098 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1099 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1100 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1101 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1102 1103 /* Renoir */ 1104 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1105 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1106 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1107 1108 /* Navi12 */ 1109 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1110 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1111 1112 /* Sienna_Cichlid */ 1113 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1114 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1115 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1116 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1117 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1118 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1119 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1120 1121 /* Van Gogh */ 1122 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1123 1124 /* Navy_Flounder */ 1125 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1126 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1127 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1128 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1129 1130 /* DIMGREY_CAVEFISH */ 1131 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1132 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1133 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1134 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1135 1136 {0, 0, 0} 1137 }; 1138 1139 MODULE_DEVICE_TABLE(pci, pciidlist); 1140 1141 static const struct drm_driver amdgpu_kms_driver; 1142 1143 static int amdgpu_pci_probe(struct pci_dev *pdev, 1144 const struct pci_device_id *ent) 1145 { 1146 struct drm_device *ddev; 1147 struct amdgpu_device *adev; 1148 unsigned long flags = ent->driver_data; 1149 int ret, retry = 0; 1150 bool supports_atomic = false; 1151 1152 if (!amdgpu_virtual_display && 1153 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1154 supports_atomic = true; 1155 1156 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1157 DRM_INFO("This hardware requires experimental hardware support.\n" 1158 "See modparam exp_hw_support\n"); 1159 return -ENODEV; 1160 } 1161 1162 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1163 * however, SME requires an indirect IOMMU mapping because the encryption 1164 * bit is beyond the DMA mask of the chip. 1165 */ 1166 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1167 dev_info(&pdev->dev, 1168 "SME is not compatible with RAVEN\n"); 1169 return -ENOTSUPP; 1170 } 1171 1172 #ifdef CONFIG_DRM_AMDGPU_SI 1173 if (!amdgpu_si_support) { 1174 switch (flags & AMD_ASIC_MASK) { 1175 case CHIP_TAHITI: 1176 case CHIP_PITCAIRN: 1177 case CHIP_VERDE: 1178 case CHIP_OLAND: 1179 case CHIP_HAINAN: 1180 dev_info(&pdev->dev, 1181 "SI support provided by radeon.\n"); 1182 dev_info(&pdev->dev, 1183 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1184 ); 1185 return -ENODEV; 1186 } 1187 } 1188 #endif 1189 #ifdef CONFIG_DRM_AMDGPU_CIK 1190 if (!amdgpu_cik_support) { 1191 switch (flags & AMD_ASIC_MASK) { 1192 case CHIP_KAVERI: 1193 case CHIP_BONAIRE: 1194 case CHIP_HAWAII: 1195 case CHIP_KABINI: 1196 case CHIP_MULLINS: 1197 dev_info(&pdev->dev, 1198 "CIK support provided by radeon.\n"); 1199 dev_info(&pdev->dev, 1200 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1201 ); 1202 return -ENODEV; 1203 } 1204 } 1205 #endif 1206 1207 /* Get rid of things like offb */ 1208 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1209 if (ret) 1210 return ret; 1211 1212 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1213 if (IS_ERR(adev)) 1214 return PTR_ERR(adev); 1215 1216 adev->dev = &pdev->dev; 1217 adev->pdev = pdev; 1218 ddev = adev_to_drm(adev); 1219 1220 if (!supports_atomic) 1221 ddev->driver_features &= ~DRIVER_ATOMIC; 1222 1223 ret = pci_enable_device(pdev); 1224 if (ret) 1225 return ret; 1226 1227 pci_set_drvdata(pdev, ddev); 1228 1229 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1230 if (ret) 1231 goto err_pci; 1232 1233 retry_init: 1234 ret = drm_dev_register(ddev, ent->driver_data); 1235 if (ret == -EAGAIN && ++retry <= 3) { 1236 DRM_INFO("retry init %d\n", retry); 1237 /* Don't request EX mode too frequently which is attacking */ 1238 msleep(5000); 1239 goto retry_init; 1240 } else if (ret) { 1241 goto err_pci; 1242 } 1243 1244 ret = amdgpu_debugfs_init(adev); 1245 if (ret) 1246 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1247 1248 return 0; 1249 1250 err_pci: 1251 pci_disable_device(pdev); 1252 return ret; 1253 } 1254 1255 static void 1256 amdgpu_pci_remove(struct pci_dev *pdev) 1257 { 1258 struct drm_device *dev = pci_get_drvdata(pdev); 1259 1260 #ifdef MODULE 1261 if (THIS_MODULE->state != MODULE_STATE_GOING) 1262 #endif 1263 DRM_ERROR("Hotplug removal is not supported\n"); 1264 drm_dev_unplug(dev); 1265 amdgpu_driver_unload_kms(dev); 1266 pci_disable_device(pdev); 1267 pci_set_drvdata(pdev, NULL); 1268 } 1269 1270 static void 1271 amdgpu_pci_shutdown(struct pci_dev *pdev) 1272 { 1273 struct drm_device *dev = pci_get_drvdata(pdev); 1274 struct amdgpu_device *adev = drm_to_adev(dev); 1275 1276 if (amdgpu_ras_intr_triggered()) 1277 return; 1278 1279 /* if we are running in a VM, make sure the device 1280 * torn down properly on reboot/shutdown. 1281 * unfortunately we can't detect certain 1282 * hypervisors so just do this all the time. 1283 */ 1284 if (!amdgpu_passthrough(adev)) 1285 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1286 adev->in_poweroff_reboot_com = true; 1287 amdgpu_device_ip_suspend(adev); 1288 adev->in_poweroff_reboot_com = false; 1289 adev->mp1_state = PP_MP1_STATE_NONE; 1290 } 1291 1292 static int amdgpu_pmops_suspend(struct device *dev) 1293 { 1294 struct drm_device *drm_dev = dev_get_drvdata(dev); 1295 1296 return amdgpu_device_suspend(drm_dev, true); 1297 } 1298 1299 static int amdgpu_pmops_resume(struct device *dev) 1300 { 1301 struct drm_device *drm_dev = dev_get_drvdata(dev); 1302 1303 return amdgpu_device_resume(drm_dev, true); 1304 } 1305 1306 static int amdgpu_pmops_freeze(struct device *dev) 1307 { 1308 struct drm_device *drm_dev = dev_get_drvdata(dev); 1309 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1310 int r; 1311 1312 adev->in_hibernate = true; 1313 r = amdgpu_device_suspend(drm_dev, true); 1314 adev->in_hibernate = false; 1315 if (r) 1316 return r; 1317 return amdgpu_asic_reset(adev); 1318 } 1319 1320 static int amdgpu_pmops_thaw(struct device *dev) 1321 { 1322 struct drm_device *drm_dev = dev_get_drvdata(dev); 1323 1324 return amdgpu_device_resume(drm_dev, true); 1325 } 1326 1327 static int amdgpu_pmops_poweroff(struct device *dev) 1328 { 1329 struct drm_device *drm_dev = dev_get_drvdata(dev); 1330 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1331 int r; 1332 1333 adev->in_poweroff_reboot_com = true; 1334 r = amdgpu_device_suspend(drm_dev, true); 1335 adev->in_poweroff_reboot_com = false; 1336 return r; 1337 } 1338 1339 static int amdgpu_pmops_restore(struct device *dev) 1340 { 1341 struct drm_device *drm_dev = dev_get_drvdata(dev); 1342 1343 return amdgpu_device_resume(drm_dev, true); 1344 } 1345 1346 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1347 { 1348 struct pci_dev *pdev = to_pci_dev(dev); 1349 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1350 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1351 int ret, i; 1352 1353 if (!adev->runpm) { 1354 pm_runtime_forbid(dev); 1355 return -EBUSY; 1356 } 1357 1358 /* wait for all rings to drain before suspending */ 1359 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1360 struct amdgpu_ring *ring = adev->rings[i]; 1361 if (ring && ring->sched.ready) { 1362 ret = amdgpu_fence_wait_empty(ring); 1363 if (ret) 1364 return -EBUSY; 1365 } 1366 } 1367 1368 adev->in_runpm = true; 1369 if (amdgpu_device_supports_atpx(drm_dev)) 1370 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1371 1372 ret = amdgpu_device_suspend(drm_dev, false); 1373 if (ret) { 1374 adev->in_runpm = false; 1375 return ret; 1376 } 1377 1378 if (amdgpu_device_supports_atpx(drm_dev)) { 1379 /* Only need to handle PCI state in the driver for ATPX 1380 * PCI core handles it for _PR3. 1381 */ 1382 if (!amdgpu_is_atpx_hybrid()) { 1383 amdgpu_device_cache_pci_state(pdev); 1384 pci_disable_device(pdev); 1385 pci_ignore_hotplug(pdev); 1386 pci_set_power_state(pdev, PCI_D3cold); 1387 } 1388 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1389 } else if (amdgpu_device_supports_baco(drm_dev)) { 1390 amdgpu_device_baco_enter(drm_dev); 1391 } 1392 1393 return 0; 1394 } 1395 1396 static int amdgpu_pmops_runtime_resume(struct device *dev) 1397 { 1398 struct pci_dev *pdev = to_pci_dev(dev); 1399 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1400 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1401 int ret; 1402 1403 if (!adev->runpm) 1404 return -EINVAL; 1405 1406 if (amdgpu_device_supports_atpx(drm_dev)) { 1407 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1408 1409 /* Only need to handle PCI state in the driver for ATPX 1410 * PCI core handles it for _PR3. 1411 */ 1412 if (!amdgpu_is_atpx_hybrid()) { 1413 pci_set_power_state(pdev, PCI_D0); 1414 amdgpu_device_load_pci_state(pdev); 1415 ret = pci_enable_device(pdev); 1416 if (ret) 1417 return ret; 1418 } 1419 pci_set_master(pdev); 1420 } else if (amdgpu_device_supports_boco(drm_dev)) { 1421 /* Only need to handle PCI state in the driver for ATPX 1422 * PCI core handles it for _PR3. 1423 */ 1424 pci_set_master(pdev); 1425 } else if (amdgpu_device_supports_baco(drm_dev)) { 1426 amdgpu_device_baco_exit(drm_dev); 1427 } 1428 ret = amdgpu_device_resume(drm_dev, false); 1429 if (amdgpu_device_supports_atpx(drm_dev)) 1430 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1431 adev->in_runpm = false; 1432 return 0; 1433 } 1434 1435 static int amdgpu_pmops_runtime_idle(struct device *dev) 1436 { 1437 struct drm_device *drm_dev = dev_get_drvdata(dev); 1438 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1439 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1440 int ret = 1; 1441 1442 if (!adev->runpm) { 1443 pm_runtime_forbid(dev); 1444 return -EBUSY; 1445 } 1446 1447 if (amdgpu_device_has_dc_support(adev)) { 1448 struct drm_crtc *crtc; 1449 1450 drm_modeset_lock_all(drm_dev); 1451 1452 drm_for_each_crtc(crtc, drm_dev) { 1453 if (crtc->state->active) { 1454 ret = -EBUSY; 1455 break; 1456 } 1457 } 1458 1459 drm_modeset_unlock_all(drm_dev); 1460 1461 } else { 1462 struct drm_connector *list_connector; 1463 struct drm_connector_list_iter iter; 1464 1465 mutex_lock(&drm_dev->mode_config.mutex); 1466 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1467 1468 drm_connector_list_iter_begin(drm_dev, &iter); 1469 drm_for_each_connector_iter(list_connector, &iter) { 1470 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1471 ret = -EBUSY; 1472 break; 1473 } 1474 } 1475 1476 drm_connector_list_iter_end(&iter); 1477 1478 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1479 mutex_unlock(&drm_dev->mode_config.mutex); 1480 } 1481 1482 if (ret == -EBUSY) 1483 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1484 1485 pm_runtime_mark_last_busy(dev); 1486 pm_runtime_autosuspend(dev); 1487 return ret; 1488 } 1489 1490 long amdgpu_drm_ioctl(struct file *filp, 1491 unsigned int cmd, unsigned long arg) 1492 { 1493 struct drm_file *file_priv = filp->private_data; 1494 struct drm_device *dev; 1495 long ret; 1496 dev = file_priv->minor->dev; 1497 ret = pm_runtime_get_sync(dev->dev); 1498 if (ret < 0) 1499 goto out; 1500 1501 ret = drm_ioctl(filp, cmd, arg); 1502 1503 pm_runtime_mark_last_busy(dev->dev); 1504 out: 1505 pm_runtime_put_autosuspend(dev->dev); 1506 return ret; 1507 } 1508 1509 static const struct dev_pm_ops amdgpu_pm_ops = { 1510 .suspend = amdgpu_pmops_suspend, 1511 .resume = amdgpu_pmops_resume, 1512 .freeze = amdgpu_pmops_freeze, 1513 .thaw = amdgpu_pmops_thaw, 1514 .poweroff = amdgpu_pmops_poweroff, 1515 .restore = amdgpu_pmops_restore, 1516 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1517 .runtime_resume = amdgpu_pmops_runtime_resume, 1518 .runtime_idle = amdgpu_pmops_runtime_idle, 1519 }; 1520 1521 static int amdgpu_flush(struct file *f, fl_owner_t id) 1522 { 1523 struct drm_file *file_priv = f->private_data; 1524 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1525 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1526 1527 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1528 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1529 1530 return timeout >= 0 ? 0 : timeout; 1531 } 1532 1533 static const struct file_operations amdgpu_driver_kms_fops = { 1534 .owner = THIS_MODULE, 1535 .open = drm_open, 1536 .flush = amdgpu_flush, 1537 .release = drm_release, 1538 .unlocked_ioctl = amdgpu_drm_ioctl, 1539 .mmap = amdgpu_mmap, 1540 .poll = drm_poll, 1541 .read = drm_read, 1542 #ifdef CONFIG_COMPAT 1543 .compat_ioctl = amdgpu_kms_compat_ioctl, 1544 #endif 1545 }; 1546 1547 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1548 { 1549 struct drm_file *file; 1550 1551 if (!filp) 1552 return -EINVAL; 1553 1554 if (filp->f_op != &amdgpu_driver_kms_fops) { 1555 return -EINVAL; 1556 } 1557 1558 file = filp->private_data; 1559 *fpriv = file->driver_priv; 1560 return 0; 1561 } 1562 1563 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1564 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1565 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1566 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1567 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1568 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1569 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1570 /* KMS */ 1571 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1572 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1573 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1574 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1575 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1576 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1577 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1578 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1579 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1580 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1581 }; 1582 1583 static const struct drm_driver amdgpu_kms_driver = { 1584 .driver_features = 1585 DRIVER_ATOMIC | 1586 DRIVER_GEM | 1587 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1588 DRIVER_SYNCOBJ_TIMELINE, 1589 .open = amdgpu_driver_open_kms, 1590 .postclose = amdgpu_driver_postclose_kms, 1591 .lastclose = amdgpu_driver_lastclose_kms, 1592 .irq_handler = amdgpu_irq_handler, 1593 .ioctls = amdgpu_ioctls_kms, 1594 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1595 .dumb_create = amdgpu_mode_dumb_create, 1596 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1597 .fops = &amdgpu_driver_kms_fops, 1598 1599 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1600 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1601 .gem_prime_import = amdgpu_gem_prime_import, 1602 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1603 1604 .name = DRIVER_NAME, 1605 .desc = DRIVER_DESC, 1606 .date = DRIVER_DATE, 1607 .major = KMS_DRIVER_MAJOR, 1608 .minor = KMS_DRIVER_MINOR, 1609 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1610 }; 1611 1612 static struct pci_error_handlers amdgpu_pci_err_handler = { 1613 .error_detected = amdgpu_pci_error_detected, 1614 .mmio_enabled = amdgpu_pci_mmio_enabled, 1615 .slot_reset = amdgpu_pci_slot_reset, 1616 .resume = amdgpu_pci_resume, 1617 }; 1618 1619 static struct pci_driver amdgpu_kms_pci_driver = { 1620 .name = DRIVER_NAME, 1621 .id_table = pciidlist, 1622 .probe = amdgpu_pci_probe, 1623 .remove = amdgpu_pci_remove, 1624 .shutdown = amdgpu_pci_shutdown, 1625 .driver.pm = &amdgpu_pm_ops, 1626 .err_handler = &amdgpu_pci_err_handler, 1627 }; 1628 1629 static int __init amdgpu_init(void) 1630 { 1631 int r; 1632 1633 if (vgacon_text_force()) { 1634 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1635 return -EINVAL; 1636 } 1637 1638 r = amdgpu_sync_init(); 1639 if (r) 1640 goto error_sync; 1641 1642 r = amdgpu_fence_slab_init(); 1643 if (r) 1644 goto error_fence; 1645 1646 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1647 amdgpu_register_atpx_handler(); 1648 1649 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1650 amdgpu_amdkfd_init(); 1651 1652 /* let modprobe override vga console setting */ 1653 return pci_register_driver(&amdgpu_kms_pci_driver); 1654 1655 error_fence: 1656 amdgpu_sync_fini(); 1657 1658 error_sync: 1659 return r; 1660 } 1661 1662 static void __exit amdgpu_exit(void) 1663 { 1664 amdgpu_amdkfd_fini(); 1665 pci_unregister_driver(&amdgpu_kms_pci_driver); 1666 amdgpu_unregister_atpx_handler(); 1667 amdgpu_sync_fini(); 1668 amdgpu_fence_slab_fini(); 1669 mmu_notifier_synchronize(); 1670 } 1671 1672 module_init(amdgpu_init); 1673 module_exit(amdgpu_exit); 1674 1675 MODULE_AUTHOR(DRIVER_AUTHOR); 1676 MODULE_DESCRIPTION(DRIVER_DESC); 1677 MODULE_LICENSE("GPL and additional rights"); 1678