1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/amdgpu_drm.h> 27 #include <drm/drm_gem.h> 28 #include "amdgpu_drv.h" 29 30 #include <drm/drm_pciids.h> 31 #include <linux/console.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/vga_switcheroo.h> 35 #include <drm/drm_crtc_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_irq.h" 39 #include "amdgpu_gem.h" 40 41 #include "amdgpu_amdkfd.h" 42 43 /* 44 * KMS wrapper. 45 * - 3.0.0 - initial driver 46 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 47 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 48 * at the end of IBs. 49 * - 3.3.0 - Add VM support for UVD on supported hardware. 50 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 51 * - 3.5.0 - Add support for new UVD_NO_OP register. 52 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 53 * - 3.7.0 - Add support for VCE clock list packet 54 * - 3.8.0 - Add support raster config init in the kernel 55 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 56 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 57 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 58 * - 3.12.0 - Add query for double offchip LDS buffers 59 * - 3.13.0 - Add PRT support 60 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 61 * - 3.15.0 - Export more gpu info for gfx9 62 * - 3.16.0 - Add reserved vmid support 63 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 64 * - 3.18.0 - Export gpu always on cu bitmap 65 * - 3.19.0 - Add support for UVD MJPEG decode 66 * - 3.20.0 - Add support for local BOs 67 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 68 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 69 * - 3.23.0 - Add query for VRAM lost counter 70 * - 3.24.0 - Add high priority compute support for gfx9 71 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 72 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 73 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 74 */ 75 #define KMS_DRIVER_MAJOR 3 76 #define KMS_DRIVER_MINOR 27 77 #define KMS_DRIVER_PATCHLEVEL 0 78 79 int amdgpu_vram_limit = 0; 80 int amdgpu_vis_vram_limit = 0; 81 int amdgpu_gart_size = -1; /* auto */ 82 int amdgpu_gtt_size = -1; /* auto */ 83 int amdgpu_moverate = -1; /* auto */ 84 int amdgpu_benchmarking = 0; 85 int amdgpu_testing = 0; 86 int amdgpu_audio = -1; 87 int amdgpu_disp_priority = 0; 88 int amdgpu_hw_i2c = 0; 89 int amdgpu_pcie_gen2 = -1; 90 int amdgpu_msi = -1; 91 int amdgpu_lockup_timeout = 10000; 92 int amdgpu_dpm = -1; 93 int amdgpu_fw_load_type = -1; 94 int amdgpu_aspm = -1; 95 int amdgpu_runtime_pm = -1; 96 uint amdgpu_ip_block_mask = 0xffffffff; 97 int amdgpu_bapm = -1; 98 int amdgpu_deep_color = 0; 99 int amdgpu_vm_size = -1; 100 int amdgpu_vm_fragment_size = -1; 101 int amdgpu_vm_block_size = -1; 102 int amdgpu_vm_fault_stop = 0; 103 int amdgpu_vm_debug = 0; 104 int amdgpu_vram_page_split = 512; 105 int amdgpu_vm_update_mode = -1; 106 int amdgpu_exp_hw_support = 0; 107 int amdgpu_dc = -1; 108 int amdgpu_sched_jobs = 32; 109 int amdgpu_sched_hw_submission = 2; 110 uint amdgpu_pcie_gen_cap = 0; 111 uint amdgpu_pcie_lane_cap = 0; 112 uint amdgpu_cg_mask = 0xffffffff; 113 uint amdgpu_pg_mask = 0xffffffff; 114 uint amdgpu_sdma_phase_quantum = 32; 115 char *amdgpu_disable_cu = NULL; 116 char *amdgpu_virtual_display = NULL; 117 /* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/ 118 uint amdgpu_pp_feature_mask = 0xfffd3fff; 119 int amdgpu_ngg = 0; 120 int amdgpu_prim_buf_per_se = 0; 121 int amdgpu_pos_buf_per_se = 0; 122 int amdgpu_cntl_sb_buf_per_se = 0; 123 int amdgpu_param_buf_per_se = 0; 124 int amdgpu_job_hang_limit = 0; 125 int amdgpu_lbpw = -1; 126 int amdgpu_compute_multipipe = -1; 127 int amdgpu_gpu_recovery = -1; /* auto */ 128 int amdgpu_emu_mode = 0; 129 uint amdgpu_smu_memory_pool_size = 0; 130 131 /** 132 * DOC: vramlimit (int) 133 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 134 */ 135 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 136 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 137 138 /** 139 * DOC: vis_vramlimit (int) 140 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 141 */ 142 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 143 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 144 145 /** 146 * DOC: gartsize (uint) 147 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 148 */ 149 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 150 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 151 152 /** 153 * DOC: gttsize (int) 154 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 155 * otherwise 3/4 RAM size). 156 */ 157 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 158 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 159 160 /** 161 * DOC: moverate (int) 162 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 163 */ 164 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 165 module_param_named(moverate, amdgpu_moverate, int, 0600); 166 167 /** 168 * DOC: benchmark (int) 169 * Run benchmarks. The default is 0 (Skip benchmarks). 170 */ 171 MODULE_PARM_DESC(benchmark, "Run benchmark"); 172 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 173 174 /** 175 * DOC: test (int) 176 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 177 */ 178 MODULE_PARM_DESC(test, "Run tests"); 179 module_param_named(test, amdgpu_testing, int, 0444); 180 181 /** 182 * DOC: audio (int) 183 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 184 */ 185 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 186 module_param_named(audio, amdgpu_audio, int, 0444); 187 188 /** 189 * DOC: disp_priority (int) 190 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 191 */ 192 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 193 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 194 195 /** 196 * DOC: hw_i2c (int) 197 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 198 */ 199 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 200 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 201 202 /** 203 * DOC: pcie_gen2 (int) 204 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 205 */ 206 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 207 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 208 209 /** 210 * DOC: msi (int) 211 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 212 */ 213 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 214 module_param_named(msi, amdgpu_msi, int, 0444); 215 216 /** 217 * DOC: lockup_timeout (int) 218 * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000. 219 * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000. 220 */ 221 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)"); 222 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 223 224 /** 225 * DOC: dpm (int) 226 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto). 227 */ 228 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 229 module_param_named(dpm, amdgpu_dpm, int, 0444); 230 231 /** 232 * DOC: fw_load_type (int) 233 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 234 */ 235 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 236 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 237 238 /** 239 * DOC: aspm (int) 240 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 241 */ 242 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 243 module_param_named(aspm, amdgpu_aspm, int, 0444); 244 245 /** 246 * DOC: runpm (int) 247 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 248 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 249 */ 250 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 251 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 252 253 /** 254 * DOC: ip_block_mask (uint) 255 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 256 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 257 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 258 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 259 */ 260 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 261 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 262 263 /** 264 * DOC: bapm (int) 265 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 266 * The default -1 (auto, enabled) 267 */ 268 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 269 module_param_named(bapm, amdgpu_bapm, int, 0444); 270 271 /** 272 * DOC: deep_color (int) 273 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 274 */ 275 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 276 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 277 278 /** 279 * DOC: vm_size (int) 280 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 281 */ 282 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 283 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 284 285 /** 286 * DOC: vm_fragment_size (int) 287 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 288 */ 289 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 290 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 291 292 /** 293 * DOC: vm_block_size (int) 294 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 295 */ 296 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 297 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 298 299 /** 300 * DOC: vm_fault_stop (int) 301 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 302 */ 303 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 304 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 305 306 /** 307 * DOC: vm_debug (int) 308 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 309 */ 310 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 311 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 312 313 /** 314 * DOC: vm_update_mode (int) 315 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 316 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 317 */ 318 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 319 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 320 321 /** 322 * DOC: vram_page_split (int) 323 * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512. 324 */ 325 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); 326 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 327 328 /** 329 * DOC: exp_hw_support (int) 330 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 331 */ 332 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 333 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 334 335 /** 336 * DOC: dc (int) 337 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 338 */ 339 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 340 module_param_named(dc, amdgpu_dc, int, 0444); 341 342 /** 343 * DOC: sched_jobs (int) 344 * Override the max number of jobs supported in the sw queue. The default is 32. 345 */ 346 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 347 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 348 349 /** 350 * DOC: sched_hw_submission (int) 351 * Override the max number of HW submissions. The default is 2. 352 */ 353 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 354 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 355 356 /** 357 * DOC: ppfeaturemask (uint) 358 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 359 * The default is the current set of stable power features. 360 */ 361 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 362 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 363 364 /** 365 * DOC: pcie_gen_cap (uint) 366 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 367 * The default is 0 (automatic for each asic). 368 */ 369 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 370 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 371 372 /** 373 * DOC: pcie_lane_cap (uint) 374 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 375 * The default is 0 (automatic for each asic). 376 */ 377 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 378 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 379 380 /** 381 * DOC: cg_mask (uint) 382 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 383 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 384 */ 385 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 386 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 387 388 /** 389 * DOC: pg_mask (uint) 390 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 391 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 392 */ 393 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 394 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 395 396 /** 397 * DOC: sdma_phase_quantum (uint) 398 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 399 */ 400 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 401 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 402 403 /** 404 * DOC: disable_cu (charp) 405 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 406 */ 407 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 408 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 409 410 /** 411 * DOC: virtual_display (charp) 412 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 413 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 414 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 415 * device at 26:00.0. The default is NULL. 416 */ 417 MODULE_PARM_DESC(virtual_display, 418 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 419 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 420 421 /** 422 * DOC: ngg (int) 423 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 424 */ 425 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 426 module_param_named(ngg, amdgpu_ngg, int, 0444); 427 428 /** 429 * DOC: prim_buf_per_se (int) 430 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 431 */ 432 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 433 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 434 435 /** 436 * DOC: pos_buf_per_se (int) 437 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 438 */ 439 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 440 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 441 442 /** 443 * DOC: cntl_sb_buf_per_se (int) 444 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 445 */ 446 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 447 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 448 449 /** 450 * DOC: param_buf_per_se (int) 451 * Override the size of Off-Chip Pramater Cache per Shader Engine in Byte. The default is 0 (depending on gfx). 452 */ 453 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); 454 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 455 456 /** 457 * DOC: job_hang_limit (int) 458 * Set how much time allow a job hang and not drop it. The default is 0. 459 */ 460 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 461 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 462 463 /** 464 * DOC: lbpw (int) 465 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 466 */ 467 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 468 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 469 470 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 471 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 472 473 /** 474 * DOC: gpu_recovery (int) 475 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 476 */ 477 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 478 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 479 480 /** 481 * DOC: emu_mode (int) 482 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 483 */ 484 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 485 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 486 487 /** 488 * DOC: si_support (int) 489 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 490 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 491 * otherwise using amdgpu driver. 492 */ 493 #ifdef CONFIG_DRM_AMDGPU_SI 494 495 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 496 int amdgpu_si_support = 0; 497 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 498 #else 499 int amdgpu_si_support = 1; 500 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 501 #endif 502 503 module_param_named(si_support, amdgpu_si_support, int, 0444); 504 #endif 505 506 /** 507 * DOC: cik_support (int) 508 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 509 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 510 * otherwise using amdgpu driver. 511 */ 512 #ifdef CONFIG_DRM_AMDGPU_CIK 513 514 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 515 int amdgpu_cik_support = 0; 516 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 517 #else 518 int amdgpu_cik_support = 1; 519 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 520 #endif 521 522 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 523 #endif 524 525 /** 526 * DOC: smu_memory_pool_size (uint) 527 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 528 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 529 */ 530 MODULE_PARM_DESC(smu_memory_pool_size, 531 "reserve gtt for smu debug usage, 0 = disable," 532 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 533 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 534 535 static const struct pci_device_id pciidlist[] = { 536 #ifdef CONFIG_DRM_AMDGPU_SI 537 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 538 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 539 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 540 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 541 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 542 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 543 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 544 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 545 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 546 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 547 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 548 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 549 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 550 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 551 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 552 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 553 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 554 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 555 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 556 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 557 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 558 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 559 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 560 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 561 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 562 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 563 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 564 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 565 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 566 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 567 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 568 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 569 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 570 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 571 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 572 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 573 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 574 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 575 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 576 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 577 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 578 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 579 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 580 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 581 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 582 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 583 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 584 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 585 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 586 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 587 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 588 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 589 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 590 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 591 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 592 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 593 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 594 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 595 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 596 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 597 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 598 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 599 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 600 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 601 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 602 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 603 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 604 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 605 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 606 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 607 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 608 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 609 #endif 610 #ifdef CONFIG_DRM_AMDGPU_CIK 611 /* Kaveri */ 612 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 613 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 614 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 615 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 616 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 617 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 618 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 619 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 620 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 621 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 622 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 623 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 624 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 625 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 626 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 627 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 628 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 629 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 630 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 631 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 632 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 633 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 634 /* Bonaire */ 635 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 636 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 637 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 638 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 639 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 640 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 641 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 642 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 643 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 644 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 645 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 646 /* Hawaii */ 647 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 648 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 649 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 650 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 651 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 652 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 653 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 654 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 655 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 656 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 657 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 658 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 659 /* Kabini */ 660 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 661 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 662 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 663 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 664 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 665 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 666 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 667 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 668 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 669 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 670 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 671 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 672 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 673 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 674 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 675 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 676 /* mullins */ 677 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 678 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 679 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 680 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 681 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 682 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 683 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 684 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 685 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 686 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 687 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 688 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 689 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 690 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 691 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 692 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 693 #endif 694 /* topaz */ 695 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 696 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 697 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 698 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 699 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 700 /* tonga */ 701 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 702 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 703 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 704 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 705 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 706 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 707 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 708 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 709 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 710 /* fiji */ 711 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 712 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 713 /* carrizo */ 714 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 715 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 716 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 717 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 718 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 719 /* stoney */ 720 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 721 /* Polaris11 */ 722 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 723 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 724 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 725 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 726 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 727 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 728 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 729 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 730 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 731 /* Polaris10 */ 732 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 733 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 734 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 735 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 736 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 737 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 738 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 739 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 740 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 741 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 742 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 743 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 744 /* Polaris12 */ 745 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 746 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 747 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 748 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 749 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 750 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 751 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 752 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 753 /* VEGAM */ 754 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 755 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 756 /* Vega 10 */ 757 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 758 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 759 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 760 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 761 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 762 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 763 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 764 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 765 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 766 /* Vega 12 */ 767 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 768 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 769 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 770 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 771 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 772 /* Vega 20 */ 773 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 774 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 775 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 776 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 777 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 778 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 779 /* Raven */ 780 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 781 782 {0, 0, 0} 783 }; 784 785 MODULE_DEVICE_TABLE(pci, pciidlist); 786 787 static struct drm_driver kms_driver; 788 789 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 790 { 791 struct apertures_struct *ap; 792 bool primary = false; 793 794 ap = alloc_apertures(1); 795 if (!ap) 796 return -ENOMEM; 797 798 ap->ranges[0].base = pci_resource_start(pdev, 0); 799 ap->ranges[0].size = pci_resource_len(pdev, 0); 800 801 #ifdef CONFIG_X86 802 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 803 #endif 804 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 805 kfree(ap); 806 807 return 0; 808 } 809 810 811 static int amdgpu_pci_probe(struct pci_dev *pdev, 812 const struct pci_device_id *ent) 813 { 814 struct drm_device *dev; 815 unsigned long flags = ent->driver_data; 816 int ret, retry = 0; 817 bool supports_atomic = false; 818 819 if (!amdgpu_virtual_display && 820 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 821 supports_atomic = true; 822 823 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 824 DRM_INFO("This hardware requires experimental hardware support.\n" 825 "See modparam exp_hw_support\n"); 826 return -ENODEV; 827 } 828 829 /* 830 * Initialize amdkfd before starting radeon. If it was not loaded yet, 831 * defer radeon probing 832 */ 833 ret = amdgpu_amdkfd_init(); 834 if (ret == -EPROBE_DEFER) 835 return ret; 836 837 /* Get rid of things like offb */ 838 ret = amdgpu_kick_out_firmware_fb(pdev); 839 if (ret) 840 return ret; 841 842 /* warn the user if they mix atomic and non-atomic capable GPUs */ 843 if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) 844 DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); 845 /* support atomic early so the atomic debugfs stuff gets created */ 846 if (supports_atomic) 847 kms_driver.driver_features |= DRIVER_ATOMIC; 848 849 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 850 if (IS_ERR(dev)) 851 return PTR_ERR(dev); 852 853 ret = pci_enable_device(pdev); 854 if (ret) 855 goto err_free; 856 857 dev->pdev = pdev; 858 859 pci_set_drvdata(pdev, dev); 860 861 retry_init: 862 ret = drm_dev_register(dev, ent->driver_data); 863 if (ret == -EAGAIN && ++retry <= 3) { 864 DRM_INFO("retry init %d\n", retry); 865 /* Don't request EX mode too frequently which is attacking */ 866 msleep(5000); 867 goto retry_init; 868 } else if (ret) 869 goto err_pci; 870 871 return 0; 872 873 err_pci: 874 pci_disable_device(pdev); 875 err_free: 876 drm_dev_put(dev); 877 return ret; 878 } 879 880 static void 881 amdgpu_pci_remove(struct pci_dev *pdev) 882 { 883 struct drm_device *dev = pci_get_drvdata(pdev); 884 885 drm_dev_unregister(dev); 886 drm_dev_put(dev); 887 pci_disable_device(pdev); 888 pci_set_drvdata(pdev, NULL); 889 } 890 891 static void 892 amdgpu_pci_shutdown(struct pci_dev *pdev) 893 { 894 struct drm_device *dev = pci_get_drvdata(pdev); 895 struct amdgpu_device *adev = dev->dev_private; 896 897 /* if we are running in a VM, make sure the device 898 * torn down properly on reboot/shutdown. 899 * unfortunately we can't detect certain 900 * hypervisors so just do this all the time. 901 */ 902 amdgpu_device_ip_suspend(adev); 903 } 904 905 static int amdgpu_pmops_suspend(struct device *dev) 906 { 907 struct pci_dev *pdev = to_pci_dev(dev); 908 909 struct drm_device *drm_dev = pci_get_drvdata(pdev); 910 return amdgpu_device_suspend(drm_dev, true, true); 911 } 912 913 static int amdgpu_pmops_resume(struct device *dev) 914 { 915 struct pci_dev *pdev = to_pci_dev(dev); 916 struct drm_device *drm_dev = pci_get_drvdata(pdev); 917 918 /* GPU comes up enabled by the bios on resume */ 919 if (amdgpu_device_is_px(drm_dev)) { 920 pm_runtime_disable(dev); 921 pm_runtime_set_active(dev); 922 pm_runtime_enable(dev); 923 } 924 925 return amdgpu_device_resume(drm_dev, true, true); 926 } 927 928 static int amdgpu_pmops_freeze(struct device *dev) 929 { 930 struct pci_dev *pdev = to_pci_dev(dev); 931 932 struct drm_device *drm_dev = pci_get_drvdata(pdev); 933 return amdgpu_device_suspend(drm_dev, false, true); 934 } 935 936 static int amdgpu_pmops_thaw(struct device *dev) 937 { 938 struct pci_dev *pdev = to_pci_dev(dev); 939 940 struct drm_device *drm_dev = pci_get_drvdata(pdev); 941 return amdgpu_device_resume(drm_dev, false, true); 942 } 943 944 static int amdgpu_pmops_poweroff(struct device *dev) 945 { 946 struct pci_dev *pdev = to_pci_dev(dev); 947 948 struct drm_device *drm_dev = pci_get_drvdata(pdev); 949 return amdgpu_device_suspend(drm_dev, true, true); 950 } 951 952 static int amdgpu_pmops_restore(struct device *dev) 953 { 954 struct pci_dev *pdev = to_pci_dev(dev); 955 956 struct drm_device *drm_dev = pci_get_drvdata(pdev); 957 return amdgpu_device_resume(drm_dev, false, true); 958 } 959 960 static int amdgpu_pmops_runtime_suspend(struct device *dev) 961 { 962 struct pci_dev *pdev = to_pci_dev(dev); 963 struct drm_device *drm_dev = pci_get_drvdata(pdev); 964 int ret; 965 966 if (!amdgpu_device_is_px(drm_dev)) { 967 pm_runtime_forbid(dev); 968 return -EBUSY; 969 } 970 971 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 972 drm_kms_helper_poll_disable(drm_dev); 973 974 ret = amdgpu_device_suspend(drm_dev, false, false); 975 pci_save_state(pdev); 976 pci_disable_device(pdev); 977 pci_ignore_hotplug(pdev); 978 if (amdgpu_is_atpx_hybrid()) 979 pci_set_power_state(pdev, PCI_D3cold); 980 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 981 pci_set_power_state(pdev, PCI_D3hot); 982 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 983 984 return 0; 985 } 986 987 static int amdgpu_pmops_runtime_resume(struct device *dev) 988 { 989 struct pci_dev *pdev = to_pci_dev(dev); 990 struct drm_device *drm_dev = pci_get_drvdata(pdev); 991 int ret; 992 993 if (!amdgpu_device_is_px(drm_dev)) 994 return -EINVAL; 995 996 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 997 998 if (amdgpu_is_atpx_hybrid() || 999 !amdgpu_has_atpx_dgpu_power_cntl()) 1000 pci_set_power_state(pdev, PCI_D0); 1001 pci_restore_state(pdev); 1002 ret = pci_enable_device(pdev); 1003 if (ret) 1004 return ret; 1005 pci_set_master(pdev); 1006 1007 ret = amdgpu_device_resume(drm_dev, false, false); 1008 drm_kms_helper_poll_enable(drm_dev); 1009 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1010 return 0; 1011 } 1012 1013 static int amdgpu_pmops_runtime_idle(struct device *dev) 1014 { 1015 struct pci_dev *pdev = to_pci_dev(dev); 1016 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1017 struct drm_crtc *crtc; 1018 1019 if (!amdgpu_device_is_px(drm_dev)) { 1020 pm_runtime_forbid(dev); 1021 return -EBUSY; 1022 } 1023 1024 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1025 if (crtc->enabled) { 1026 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1027 return -EBUSY; 1028 } 1029 } 1030 1031 pm_runtime_mark_last_busy(dev); 1032 pm_runtime_autosuspend(dev); 1033 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1034 return 1; 1035 } 1036 1037 long amdgpu_drm_ioctl(struct file *filp, 1038 unsigned int cmd, unsigned long arg) 1039 { 1040 struct drm_file *file_priv = filp->private_data; 1041 struct drm_device *dev; 1042 long ret; 1043 dev = file_priv->minor->dev; 1044 ret = pm_runtime_get_sync(dev->dev); 1045 if (ret < 0) 1046 return ret; 1047 1048 ret = drm_ioctl(filp, cmd, arg); 1049 1050 pm_runtime_mark_last_busy(dev->dev); 1051 pm_runtime_put_autosuspend(dev->dev); 1052 return ret; 1053 } 1054 1055 static const struct dev_pm_ops amdgpu_pm_ops = { 1056 .suspend = amdgpu_pmops_suspend, 1057 .resume = amdgpu_pmops_resume, 1058 .freeze = amdgpu_pmops_freeze, 1059 .thaw = amdgpu_pmops_thaw, 1060 .poweroff = amdgpu_pmops_poweroff, 1061 .restore = amdgpu_pmops_restore, 1062 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1063 .runtime_resume = amdgpu_pmops_runtime_resume, 1064 .runtime_idle = amdgpu_pmops_runtime_idle, 1065 }; 1066 1067 static int amdgpu_flush(struct file *f, fl_owner_t id) 1068 { 1069 struct drm_file *file_priv = f->private_data; 1070 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1071 1072 amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr); 1073 1074 return 0; 1075 } 1076 1077 1078 static const struct file_operations amdgpu_driver_kms_fops = { 1079 .owner = THIS_MODULE, 1080 .open = drm_open, 1081 .flush = amdgpu_flush, 1082 .release = drm_release, 1083 .unlocked_ioctl = amdgpu_drm_ioctl, 1084 .mmap = amdgpu_mmap, 1085 .poll = drm_poll, 1086 .read = drm_read, 1087 #ifdef CONFIG_COMPAT 1088 .compat_ioctl = amdgpu_kms_compat_ioctl, 1089 #endif 1090 }; 1091 1092 static bool 1093 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1094 bool in_vblank_irq, int *vpos, int *hpos, 1095 ktime_t *stime, ktime_t *etime, 1096 const struct drm_display_mode *mode) 1097 { 1098 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1099 stime, etime, mode); 1100 } 1101 1102 static struct drm_driver kms_driver = { 1103 .driver_features = 1104 DRIVER_USE_AGP | 1105 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 1106 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1107 .load = amdgpu_driver_load_kms, 1108 .open = amdgpu_driver_open_kms, 1109 .postclose = amdgpu_driver_postclose_kms, 1110 .lastclose = amdgpu_driver_lastclose_kms, 1111 .unload = amdgpu_driver_unload_kms, 1112 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1113 .enable_vblank = amdgpu_enable_vblank_kms, 1114 .disable_vblank = amdgpu_disable_vblank_kms, 1115 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1116 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1117 .irq_handler = amdgpu_irq_handler, 1118 .ioctls = amdgpu_ioctls_kms, 1119 .gem_free_object_unlocked = amdgpu_gem_object_free, 1120 .gem_open_object = amdgpu_gem_object_open, 1121 .gem_close_object = amdgpu_gem_object_close, 1122 .dumb_create = amdgpu_mode_dumb_create, 1123 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1124 .fops = &amdgpu_driver_kms_fops, 1125 1126 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1127 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1128 .gem_prime_export = amdgpu_gem_prime_export, 1129 .gem_prime_import = amdgpu_gem_prime_import, 1130 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1131 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1132 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1133 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1134 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1135 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1136 1137 .name = DRIVER_NAME, 1138 .desc = DRIVER_DESC, 1139 .date = DRIVER_DATE, 1140 .major = KMS_DRIVER_MAJOR, 1141 .minor = KMS_DRIVER_MINOR, 1142 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1143 }; 1144 1145 static struct drm_driver *driver; 1146 static struct pci_driver *pdriver; 1147 1148 static struct pci_driver amdgpu_kms_pci_driver = { 1149 .name = DRIVER_NAME, 1150 .id_table = pciidlist, 1151 .probe = amdgpu_pci_probe, 1152 .remove = amdgpu_pci_remove, 1153 .shutdown = amdgpu_pci_shutdown, 1154 .driver.pm = &amdgpu_pm_ops, 1155 }; 1156 1157 1158 1159 static int __init amdgpu_init(void) 1160 { 1161 int r; 1162 1163 if (vgacon_text_force()) { 1164 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1165 return -EINVAL; 1166 } 1167 1168 r = amdgpu_sync_init(); 1169 if (r) 1170 goto error_sync; 1171 1172 r = amdgpu_fence_slab_init(); 1173 if (r) 1174 goto error_fence; 1175 1176 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1177 driver = &kms_driver; 1178 pdriver = &amdgpu_kms_pci_driver; 1179 driver->num_ioctls = amdgpu_max_kms_ioctl; 1180 amdgpu_register_atpx_handler(); 1181 /* let modprobe override vga console setting */ 1182 return pci_register_driver(pdriver); 1183 1184 error_fence: 1185 amdgpu_sync_fini(); 1186 1187 error_sync: 1188 return r; 1189 } 1190 1191 static void __exit amdgpu_exit(void) 1192 { 1193 amdgpu_amdkfd_fini(); 1194 pci_unregister_driver(pdriver); 1195 amdgpu_unregister_atpx_handler(); 1196 amdgpu_sync_fini(); 1197 amdgpu_fence_slab_fini(); 1198 } 1199 1200 module_init(amdgpu_init); 1201 module_exit(amdgpu_exit); 1202 1203 MODULE_AUTHOR(DRIVER_AUTHOR); 1204 MODULE_DESCRIPTION(DRIVER_DESC); 1205 MODULE_LICENSE("GPL and additional rights"); 1206