1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 /* 48 * KMS wrapper. 49 * - 3.0.0 - initial driver 50 */ 51 #define KMS_DRIVER_MAJOR 3 52 #define KMS_DRIVER_MINOR 0 53 #define KMS_DRIVER_PATCHLEVEL 0 54 55 int amdgpu_vram_limit = 0; 56 int amdgpu_gart_size = -1; /* auto */ 57 int amdgpu_benchmarking = 0; 58 int amdgpu_testing = 0; 59 int amdgpu_audio = -1; 60 int amdgpu_disp_priority = 0; 61 int amdgpu_hw_i2c = 0; 62 int amdgpu_pcie_gen2 = -1; 63 int amdgpu_msi = -1; 64 int amdgpu_lockup_timeout = 10000; 65 int amdgpu_dpm = -1; 66 int amdgpu_smc_load_fw = 1; 67 int amdgpu_aspm = -1; 68 int amdgpu_runtime_pm = -1; 69 int amdgpu_hard_reset = 0; 70 unsigned amdgpu_ip_block_mask = 0xffffffff; 71 int amdgpu_bapm = -1; 72 int amdgpu_deep_color = 0; 73 int amdgpu_vm_size = 8; 74 int amdgpu_vm_block_size = -1; 75 int amdgpu_exp_hw_support = 0; 76 77 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 78 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 79 80 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 81 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 82 83 MODULE_PARM_DESC(benchmark, "Run benchmark"); 84 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 85 86 MODULE_PARM_DESC(test, "Run tests"); 87 module_param_named(test, amdgpu_testing, int, 0444); 88 89 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 90 module_param_named(audio, amdgpu_audio, int, 0444); 91 92 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 93 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 94 95 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 96 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 97 98 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 99 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 100 101 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 102 module_param_named(msi, amdgpu_msi, int, 0444); 103 104 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 105 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 106 107 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 108 module_param_named(dpm, amdgpu_dpm, int, 0444); 109 110 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 111 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 112 113 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 114 module_param_named(aspm, amdgpu_aspm, int, 0444); 115 116 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 117 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 118 119 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 120 module_param_named(hard_reset, amdgpu_hard_reset, int, 0444); 121 122 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 123 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 124 125 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 126 module_param_named(bapm, amdgpu_bapm, int, 0444); 127 128 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 129 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 130 131 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)"); 132 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 133 134 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 135 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 136 137 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 138 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 139 140 static struct pci_device_id pciidlist[] = { 141 #ifdef CONFIG_DRM_AMDGPU_CIK 142 /* Kaveri */ 143 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 144 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 145 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 146 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 147 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 148 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 149 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 150 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 151 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 152 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 153 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 154 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 155 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 156 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 157 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 158 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 159 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 160 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 161 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 162 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 163 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 164 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 165 /* Bonaire */ 166 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 167 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 168 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 169 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 170 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 171 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 172 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 173 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 174 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 175 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 176 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 177 /* Hawaii */ 178 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 179 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 180 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 181 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 182 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 183 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 184 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 185 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 186 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 187 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 188 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 189 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 190 /* Kabini */ 191 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 192 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 193 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 194 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 195 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 196 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 197 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 198 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 199 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 200 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 201 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 202 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 203 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 204 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 205 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 206 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 207 /* mullins */ 208 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 209 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 210 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 211 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 212 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 213 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 214 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 215 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 216 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 217 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 218 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 219 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 220 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 221 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 222 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 223 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 224 #endif 225 /* topaz */ 226 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 227 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 228 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 229 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 230 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 231 /* tonga */ 232 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 233 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 234 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 235 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 236 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 237 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 238 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 239 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 240 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 241 /* carrizo */ 242 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 243 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 244 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 245 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 246 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 247 248 {0, 0, 0} 249 }; 250 251 MODULE_DEVICE_TABLE(pci, pciidlist); 252 253 static struct drm_driver kms_driver; 254 255 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 256 { 257 struct apertures_struct *ap; 258 bool primary = false; 259 260 ap = alloc_apertures(1); 261 if (!ap) 262 return -ENOMEM; 263 264 ap->ranges[0].base = pci_resource_start(pdev, 0); 265 ap->ranges[0].size = pci_resource_len(pdev, 0); 266 267 #ifdef CONFIG_X86 268 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 269 #endif 270 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 271 kfree(ap); 272 273 return 0; 274 } 275 276 static int amdgpu_pci_probe(struct pci_dev *pdev, 277 const struct pci_device_id *ent) 278 { 279 unsigned long flags = ent->driver_data; 280 int ret; 281 282 if ((flags & AMDGPU_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 283 DRM_INFO("This hardware requires experimental hardware support.\n" 284 "See modparam exp_hw_support\n"); 285 return -ENODEV; 286 } 287 288 /* Get rid of things like offb */ 289 ret = amdgpu_kick_out_firmware_fb(pdev); 290 if (ret) 291 return ret; 292 293 return drm_get_pci_dev(pdev, ent, &kms_driver); 294 } 295 296 static void 297 amdgpu_pci_remove(struct pci_dev *pdev) 298 { 299 struct drm_device *dev = pci_get_drvdata(pdev); 300 301 drm_put_dev(dev); 302 } 303 304 static int amdgpu_pmops_suspend(struct device *dev) 305 { 306 struct pci_dev *pdev = to_pci_dev(dev); 307 struct drm_device *drm_dev = pci_get_drvdata(pdev); 308 return amdgpu_suspend_kms(drm_dev, true, true); 309 } 310 311 static int amdgpu_pmops_resume(struct device *dev) 312 { 313 struct pci_dev *pdev = to_pci_dev(dev); 314 struct drm_device *drm_dev = pci_get_drvdata(pdev); 315 return amdgpu_resume_kms(drm_dev, true, true); 316 } 317 318 static int amdgpu_pmops_freeze(struct device *dev) 319 { 320 struct pci_dev *pdev = to_pci_dev(dev); 321 struct drm_device *drm_dev = pci_get_drvdata(pdev); 322 return amdgpu_suspend_kms(drm_dev, false, true); 323 } 324 325 static int amdgpu_pmops_thaw(struct device *dev) 326 { 327 struct pci_dev *pdev = to_pci_dev(dev); 328 struct drm_device *drm_dev = pci_get_drvdata(pdev); 329 return amdgpu_resume_kms(drm_dev, false, true); 330 } 331 332 static int amdgpu_pmops_runtime_suspend(struct device *dev) 333 { 334 struct pci_dev *pdev = to_pci_dev(dev); 335 struct drm_device *drm_dev = pci_get_drvdata(pdev); 336 int ret; 337 338 if (!amdgpu_device_is_px(drm_dev)) { 339 pm_runtime_forbid(dev); 340 return -EBUSY; 341 } 342 343 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 344 drm_kms_helper_poll_disable(drm_dev); 345 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 346 347 ret = amdgpu_suspend_kms(drm_dev, false, false); 348 pci_save_state(pdev); 349 pci_disable_device(pdev); 350 pci_ignore_hotplug(pdev); 351 pci_set_power_state(pdev, PCI_D3cold); 352 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 353 354 return 0; 355 } 356 357 static int amdgpu_pmops_runtime_resume(struct device *dev) 358 { 359 struct pci_dev *pdev = to_pci_dev(dev); 360 struct drm_device *drm_dev = pci_get_drvdata(pdev); 361 int ret; 362 363 if (!amdgpu_device_is_px(drm_dev)) 364 return -EINVAL; 365 366 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 367 368 pci_set_power_state(pdev, PCI_D0); 369 pci_restore_state(pdev); 370 ret = pci_enable_device(pdev); 371 if (ret) 372 return ret; 373 pci_set_master(pdev); 374 375 ret = amdgpu_resume_kms(drm_dev, false, false); 376 drm_kms_helper_poll_enable(drm_dev); 377 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 378 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 379 return 0; 380 } 381 382 static int amdgpu_pmops_runtime_idle(struct device *dev) 383 { 384 struct pci_dev *pdev = to_pci_dev(dev); 385 struct drm_device *drm_dev = pci_get_drvdata(pdev); 386 struct drm_crtc *crtc; 387 388 if (!amdgpu_device_is_px(drm_dev)) { 389 pm_runtime_forbid(dev); 390 return -EBUSY; 391 } 392 393 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 394 if (crtc->enabled) { 395 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 396 return -EBUSY; 397 } 398 } 399 400 pm_runtime_mark_last_busy(dev); 401 pm_runtime_autosuspend(dev); 402 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 403 return 1; 404 } 405 406 long amdgpu_drm_ioctl(struct file *filp, 407 unsigned int cmd, unsigned long arg) 408 { 409 struct drm_file *file_priv = filp->private_data; 410 struct drm_device *dev; 411 long ret; 412 dev = file_priv->minor->dev; 413 ret = pm_runtime_get_sync(dev->dev); 414 if (ret < 0) 415 return ret; 416 417 ret = drm_ioctl(filp, cmd, arg); 418 419 pm_runtime_mark_last_busy(dev->dev); 420 pm_runtime_put_autosuspend(dev->dev); 421 return ret; 422 } 423 424 static const struct dev_pm_ops amdgpu_pm_ops = { 425 .suspend = amdgpu_pmops_suspend, 426 .resume = amdgpu_pmops_resume, 427 .freeze = amdgpu_pmops_freeze, 428 .thaw = amdgpu_pmops_thaw, 429 .poweroff = amdgpu_pmops_freeze, 430 .restore = amdgpu_pmops_resume, 431 .runtime_suspend = amdgpu_pmops_runtime_suspend, 432 .runtime_resume = amdgpu_pmops_runtime_resume, 433 .runtime_idle = amdgpu_pmops_runtime_idle, 434 }; 435 436 static const struct file_operations amdgpu_driver_kms_fops = { 437 .owner = THIS_MODULE, 438 .open = drm_open, 439 .release = drm_release, 440 .unlocked_ioctl = amdgpu_drm_ioctl, 441 .mmap = amdgpu_mmap, 442 .poll = drm_poll, 443 .read = drm_read, 444 #ifdef CONFIG_COMPAT 445 .compat_ioctl = amdgpu_kms_compat_ioctl, 446 #endif 447 }; 448 449 static struct drm_driver kms_driver = { 450 .driver_features = 451 DRIVER_USE_AGP | 452 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 453 DRIVER_PRIME | DRIVER_RENDER, 454 .dev_priv_size = 0, 455 .load = amdgpu_driver_load_kms, 456 .open = amdgpu_driver_open_kms, 457 .preclose = amdgpu_driver_preclose_kms, 458 .postclose = amdgpu_driver_postclose_kms, 459 .lastclose = amdgpu_driver_lastclose_kms, 460 .set_busid = drm_pci_set_busid, 461 .unload = amdgpu_driver_unload_kms, 462 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 463 .enable_vblank = amdgpu_enable_vblank_kms, 464 .disable_vblank = amdgpu_disable_vblank_kms, 465 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 466 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 467 #if defined(CONFIG_DEBUG_FS) 468 .debugfs_init = amdgpu_debugfs_init, 469 .debugfs_cleanup = amdgpu_debugfs_cleanup, 470 #endif 471 .irq_preinstall = amdgpu_irq_preinstall, 472 .irq_postinstall = amdgpu_irq_postinstall, 473 .irq_uninstall = amdgpu_irq_uninstall, 474 .irq_handler = amdgpu_irq_handler, 475 .ioctls = amdgpu_ioctls_kms, 476 .gem_free_object = amdgpu_gem_object_free, 477 .gem_open_object = amdgpu_gem_object_open, 478 .gem_close_object = amdgpu_gem_object_close, 479 .dumb_create = amdgpu_mode_dumb_create, 480 .dumb_map_offset = amdgpu_mode_dumb_mmap, 481 .dumb_destroy = drm_gem_dumb_destroy, 482 .fops = &amdgpu_driver_kms_fops, 483 484 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 485 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 486 .gem_prime_export = amdgpu_gem_prime_export, 487 .gem_prime_import = drm_gem_prime_import, 488 .gem_prime_pin = amdgpu_gem_prime_pin, 489 .gem_prime_unpin = amdgpu_gem_prime_unpin, 490 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 491 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 492 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 493 .gem_prime_vmap = amdgpu_gem_prime_vmap, 494 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 495 496 .name = DRIVER_NAME, 497 .desc = DRIVER_DESC, 498 .date = DRIVER_DATE, 499 .major = KMS_DRIVER_MAJOR, 500 .minor = KMS_DRIVER_MINOR, 501 .patchlevel = KMS_DRIVER_PATCHLEVEL, 502 }; 503 504 static struct drm_driver *driver; 505 static struct pci_driver *pdriver; 506 507 static struct pci_driver amdgpu_kms_pci_driver = { 508 .name = DRIVER_NAME, 509 .id_table = pciidlist, 510 .probe = amdgpu_pci_probe, 511 .remove = amdgpu_pci_remove, 512 .driver.pm = &amdgpu_pm_ops, 513 }; 514 515 static int __init amdgpu_init(void) 516 { 517 #ifdef CONFIG_VGA_CONSOLE 518 if (vgacon_text_force()) { 519 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 520 return -EINVAL; 521 } 522 #endif 523 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 524 driver = &kms_driver; 525 pdriver = &amdgpu_kms_pci_driver; 526 driver->driver_features |= DRIVER_MODESET; 527 driver->num_ioctls = amdgpu_max_kms_ioctl; 528 amdgpu_register_atpx_handler(); 529 530 /* let modprobe override vga console setting */ 531 return drm_pci_init(driver, pdriver); 532 } 533 534 static void __exit amdgpu_exit(void) 535 { 536 drm_pci_exit(driver, pdriver); 537 amdgpu_unregister_atpx_handler(); 538 } 539 540 module_init(amdgpu_init); 541 module_exit(amdgpu_exit); 542 543 MODULE_AUTHOR(DRIVER_AUTHOR); 544 MODULE_DESCRIPTION(DRIVER_DESC); 545 MODULE_LICENSE("GPL and additional rights"); 546