1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/fb.h> 42 #include <linux/dynamic_debug.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 #include "amdgpu_dma_buf.h" 47 #include "amdgpu_sched.h" 48 #include "amdgpu_fdinfo.h" 49 #include "amdgpu_amdkfd.h" 50 51 #include "amdgpu_ras.h" 52 #include "amdgpu_xgmi.h" 53 #include "amdgpu_reset.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 */ 111 #define KMS_DRIVER_MAJOR 3 112 #define KMS_DRIVER_MINOR 50 113 #define KMS_DRIVER_PATCHLEVEL 0 114 115 unsigned int amdgpu_vram_limit = UINT_MAX; 116 int amdgpu_vis_vram_limit; 117 int amdgpu_gart_size = -1; /* auto */ 118 int amdgpu_gtt_size = -1; /* auto */ 119 int amdgpu_moverate = -1; /* auto */ 120 int amdgpu_audio = -1; 121 int amdgpu_disp_priority; 122 int amdgpu_hw_i2c; 123 int amdgpu_pcie_gen2 = -1; 124 int amdgpu_msi = -1; 125 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 126 int amdgpu_dpm = -1; 127 int amdgpu_fw_load_type = -1; 128 int amdgpu_aspm = -1; 129 int amdgpu_runtime_pm = -1; 130 uint amdgpu_ip_block_mask = 0xffffffff; 131 int amdgpu_bapm = -1; 132 int amdgpu_deep_color; 133 int amdgpu_vm_size = -1; 134 int amdgpu_vm_fragment_size = -1; 135 int amdgpu_vm_block_size = -1; 136 int amdgpu_vm_fault_stop; 137 int amdgpu_vm_debug; 138 int amdgpu_vm_update_mode = -1; 139 int amdgpu_exp_hw_support; 140 int amdgpu_dc = -1; 141 int amdgpu_sched_jobs = 32; 142 int amdgpu_sched_hw_submission = 2; 143 uint amdgpu_pcie_gen_cap; 144 uint amdgpu_pcie_lane_cap; 145 u64 amdgpu_cg_mask = 0xffffffffffffffff; 146 uint amdgpu_pg_mask = 0xffffffff; 147 uint amdgpu_sdma_phase_quantum = 32; 148 char *amdgpu_disable_cu = NULL; 149 char *amdgpu_virtual_display = NULL; 150 151 /* 152 * OverDrive(bit 14) disabled by default 153 * GFX DCS(bit 19) disabled by default 154 */ 155 uint amdgpu_pp_feature_mask = 0xfff7bfff; 156 uint amdgpu_force_long_training; 157 int amdgpu_job_hang_limit; 158 int amdgpu_lbpw = -1; 159 int amdgpu_compute_multipipe = -1; 160 int amdgpu_gpu_recovery = -1; /* auto */ 161 int amdgpu_emu_mode; 162 uint amdgpu_smu_memory_pool_size; 163 int amdgpu_smu_pptable_id = -1; 164 /* 165 * FBC (bit 0) disabled by default 166 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 167 * - With this, for multiple monitors in sync(e.g. with the same model), 168 * mclk switching will be allowed. And the mclk will be not foced to the 169 * highest. That helps saving some idle power. 170 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 171 * PSR (bit 3) disabled by default 172 * EDP NO POWER SEQUENCING (bit 4) disabled by default 173 */ 174 uint amdgpu_dc_feature_mask = 2; 175 uint amdgpu_dc_debug_mask; 176 uint amdgpu_dc_visual_confirm; 177 int amdgpu_async_gfx_ring = 1; 178 int amdgpu_mcbp; 179 int amdgpu_discovery = -1; 180 int amdgpu_mes; 181 int amdgpu_mes_kiq; 182 int amdgpu_noretry = -1; 183 int amdgpu_force_asic_type = -1; 184 int amdgpu_tmz = -1; /* auto */ 185 uint amdgpu_freesync_vid_mode; 186 int amdgpu_reset_method = -1; /* auto */ 187 int amdgpu_num_kcq = -1; 188 int amdgpu_smartshift_bias; 189 int amdgpu_use_xgmi_p2p = 1; 190 int amdgpu_vcnfw_log; 191 192 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 193 194 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 195 "DRM_UT_CORE", 196 "DRM_UT_DRIVER", 197 "DRM_UT_KMS", 198 "DRM_UT_PRIME", 199 "DRM_UT_ATOMIC", 200 "DRM_UT_VBL", 201 "DRM_UT_STATE", 202 "DRM_UT_LEASE", 203 "DRM_UT_DP", 204 "DRM_UT_DRMRES"); 205 206 struct amdgpu_mgpu_info mgpu_info = { 207 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 208 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 209 mgpu_info.delayed_reset_work, 210 amdgpu_drv_delayed_reset_work_handler, 0), 211 }; 212 int amdgpu_ras_enable = -1; 213 uint amdgpu_ras_mask = 0xffffffff; 214 int amdgpu_bad_page_threshold = -1; 215 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 216 .timeout_fatal_disable = false, 217 .period = 0x0, /* default to 0x0 (timeout disable) */ 218 }; 219 220 /** 221 * DOC: vramlimit (int) 222 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 223 */ 224 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 225 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 226 227 /** 228 * DOC: vis_vramlimit (int) 229 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 230 */ 231 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 232 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 233 234 /** 235 * DOC: gartsize (uint) 236 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 237 * The default is -1 (The size depends on asic). 238 */ 239 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 240 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 241 242 /** 243 * DOC: gttsize (int) 244 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 245 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 246 */ 247 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 248 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 249 250 /** 251 * DOC: moverate (int) 252 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 253 */ 254 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 255 module_param_named(moverate, amdgpu_moverate, int, 0600); 256 257 /** 258 * DOC: audio (int) 259 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 260 */ 261 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 262 module_param_named(audio, amdgpu_audio, int, 0444); 263 264 /** 265 * DOC: disp_priority (int) 266 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 267 */ 268 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 269 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 270 271 /** 272 * DOC: hw_i2c (int) 273 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 274 */ 275 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 276 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 277 278 /** 279 * DOC: pcie_gen2 (int) 280 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 281 */ 282 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 283 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 284 285 /** 286 * DOC: msi (int) 287 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 288 */ 289 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 290 module_param_named(msi, amdgpu_msi, int, 0444); 291 292 /** 293 * DOC: lockup_timeout (string) 294 * Set GPU scheduler timeout value in ms. 295 * 296 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 297 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 298 * to the default timeout. 299 * 300 * - With one value specified, the setting will apply to all non-compute jobs. 301 * - With multiple values specified, the first one will be for GFX. 302 * The second one is for Compute. The third and fourth ones are 303 * for SDMA and Video. 304 * 305 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 306 * jobs is 10000. The timeout for compute is 60000. 307 */ 308 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 309 "for passthrough or sriov, 10000 for all jobs." 310 " 0: keep default value. negative: infinity timeout), " 311 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 312 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 313 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 314 315 /** 316 * DOC: dpm (int) 317 * Override for dynamic power management setting 318 * (0 = disable, 1 = enable) 319 * The default is -1 (auto). 320 */ 321 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 322 module_param_named(dpm, amdgpu_dpm, int, 0444); 323 324 /** 325 * DOC: fw_load_type (int) 326 * Set different firmware loading type for debugging, if supported. 327 * Set to 0 to force direct loading if supported by the ASIC. Set 328 * to -1 to select the default loading mode for the ASIC, as defined 329 * by the driver. The default is -1 (auto). 330 */ 331 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 332 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 333 334 /** 335 * DOC: aspm (int) 336 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 337 */ 338 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 339 module_param_named(aspm, amdgpu_aspm, int, 0444); 340 341 /** 342 * DOC: runpm (int) 343 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 344 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 345 * Setting the value to 0 disables this functionality. 346 */ 347 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 348 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 349 350 /** 351 * DOC: ip_block_mask (uint) 352 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 353 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 354 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 355 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 356 */ 357 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 358 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 359 360 /** 361 * DOC: bapm (int) 362 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 363 * The default -1 (auto, enabled) 364 */ 365 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 366 module_param_named(bapm, amdgpu_bapm, int, 0444); 367 368 /** 369 * DOC: deep_color (int) 370 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 371 */ 372 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 373 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 374 375 /** 376 * DOC: vm_size (int) 377 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 378 */ 379 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 380 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 381 382 /** 383 * DOC: vm_fragment_size (int) 384 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 385 */ 386 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 387 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 388 389 /** 390 * DOC: vm_block_size (int) 391 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 392 */ 393 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 394 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 395 396 /** 397 * DOC: vm_fault_stop (int) 398 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 399 */ 400 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 401 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 402 403 /** 404 * DOC: vm_debug (int) 405 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 406 */ 407 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 408 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 409 410 /** 411 * DOC: vm_update_mode (int) 412 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 413 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 414 */ 415 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 416 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 417 418 /** 419 * DOC: exp_hw_support (int) 420 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 421 */ 422 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 423 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 424 425 /** 426 * DOC: dc (int) 427 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 428 */ 429 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 430 module_param_named(dc, amdgpu_dc, int, 0444); 431 432 /** 433 * DOC: sched_jobs (int) 434 * Override the max number of jobs supported in the sw queue. The default is 32. 435 */ 436 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 437 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 438 439 /** 440 * DOC: sched_hw_submission (int) 441 * Override the max number of HW submissions. The default is 2. 442 */ 443 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 444 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 445 446 /** 447 * DOC: ppfeaturemask (hexint) 448 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 449 * The default is the current set of stable power features. 450 */ 451 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 452 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 453 454 /** 455 * DOC: forcelongtraining (uint) 456 * Force long memory training in resume. 457 * The default is zero, indicates short training in resume. 458 */ 459 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 460 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 461 462 /** 463 * DOC: pcie_gen_cap (uint) 464 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 465 * The default is 0 (automatic for each asic). 466 */ 467 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 468 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 469 470 /** 471 * DOC: pcie_lane_cap (uint) 472 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 473 * The default is 0 (automatic for each asic). 474 */ 475 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 476 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 477 478 /** 479 * DOC: cg_mask (ullong) 480 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 481 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 482 */ 483 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 484 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 485 486 /** 487 * DOC: pg_mask (uint) 488 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 489 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 490 */ 491 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 492 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 493 494 /** 495 * DOC: sdma_phase_quantum (uint) 496 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 497 */ 498 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 499 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 500 501 /** 502 * DOC: disable_cu (charp) 503 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 504 */ 505 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 506 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 507 508 /** 509 * DOC: virtual_display (charp) 510 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 511 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 512 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 513 * device at 26:00.0. The default is NULL. 514 */ 515 MODULE_PARM_DESC(virtual_display, 516 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 517 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 518 519 /** 520 * DOC: job_hang_limit (int) 521 * Set how much time allow a job hang and not drop it. The default is 0. 522 */ 523 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 524 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 525 526 /** 527 * DOC: lbpw (int) 528 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 529 */ 530 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 532 533 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 534 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 535 536 /** 537 * DOC: gpu_recovery (int) 538 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 539 */ 540 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 541 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 542 543 /** 544 * DOC: emu_mode (int) 545 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 546 */ 547 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 548 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 549 550 /** 551 * DOC: ras_enable (int) 552 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 553 */ 554 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 555 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 556 557 /** 558 * DOC: ras_mask (uint) 559 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 560 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 561 */ 562 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 563 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 564 565 /** 566 * DOC: timeout_fatal_disable (bool) 567 * Disable Watchdog timeout fatal error event 568 */ 569 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 570 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 571 572 /** 573 * DOC: timeout_period (uint) 574 * Modify the watchdog timeout max_cycles as (1 << period) 575 */ 576 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 577 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 578 579 /** 580 * DOC: si_support (int) 581 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 582 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 583 * otherwise using amdgpu driver. 584 */ 585 #ifdef CONFIG_DRM_AMDGPU_SI 586 587 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 588 int amdgpu_si_support = 0; 589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 590 #else 591 int amdgpu_si_support = 1; 592 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 593 #endif 594 595 module_param_named(si_support, amdgpu_si_support, int, 0444); 596 #endif 597 598 /** 599 * DOC: cik_support (int) 600 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 601 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 602 * otherwise using amdgpu driver. 603 */ 604 #ifdef CONFIG_DRM_AMDGPU_CIK 605 606 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 607 int amdgpu_cik_support = 0; 608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 609 #else 610 int amdgpu_cik_support = 1; 611 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 612 #endif 613 614 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 615 #endif 616 617 /** 618 * DOC: smu_memory_pool_size (uint) 619 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 620 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 621 */ 622 MODULE_PARM_DESC(smu_memory_pool_size, 623 "reserve gtt for smu debug usage, 0 = disable," 624 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 625 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 626 627 /** 628 * DOC: async_gfx_ring (int) 629 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 630 */ 631 MODULE_PARM_DESC(async_gfx_ring, 632 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 633 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 634 635 /** 636 * DOC: mcbp (int) 637 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 638 */ 639 MODULE_PARM_DESC(mcbp, 640 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 641 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 642 643 /** 644 * DOC: discovery (int) 645 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 646 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 647 */ 648 MODULE_PARM_DESC(discovery, 649 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 650 module_param_named(discovery, amdgpu_discovery, int, 0444); 651 652 /** 653 * DOC: mes (int) 654 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 655 * (0 = disabled (default), 1 = enabled) 656 */ 657 MODULE_PARM_DESC(mes, 658 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 659 module_param_named(mes, amdgpu_mes, int, 0444); 660 661 /** 662 * DOC: mes_kiq (int) 663 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 664 * (0 = disabled (default), 1 = enabled) 665 */ 666 MODULE_PARM_DESC(mes_kiq, 667 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 668 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 669 670 /** 671 * DOC: noretry (int) 672 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 673 * do not support per-process XNACK this also disables retry page faults. 674 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 675 */ 676 MODULE_PARM_DESC(noretry, 677 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 678 module_param_named(noretry, amdgpu_noretry, int, 0644); 679 680 /** 681 * DOC: force_asic_type (int) 682 * A non negative value used to specify the asic type for all supported GPUs. 683 */ 684 MODULE_PARM_DESC(force_asic_type, 685 "A non negative value used to specify the asic type for all supported GPUs"); 686 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 687 688 /** 689 * DOC: use_xgmi_p2p (int) 690 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 691 */ 692 MODULE_PARM_DESC(use_xgmi_p2p, 693 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 694 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 695 696 697 #ifdef CONFIG_HSA_AMD 698 /** 699 * DOC: sched_policy (int) 700 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 701 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 702 * assigns queues to HQDs. 703 */ 704 int sched_policy = KFD_SCHED_POLICY_HWS; 705 module_param(sched_policy, int, 0444); 706 MODULE_PARM_DESC(sched_policy, 707 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 708 709 /** 710 * DOC: hws_max_conc_proc (int) 711 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 712 * number of VMIDs assigned to the HWS, which is also the default. 713 */ 714 int hws_max_conc_proc = -1; 715 module_param(hws_max_conc_proc, int, 0444); 716 MODULE_PARM_DESC(hws_max_conc_proc, 717 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 718 719 /** 720 * DOC: cwsr_enable (int) 721 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 722 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 723 * disables it. 724 */ 725 int cwsr_enable = 1; 726 module_param(cwsr_enable, int, 0444); 727 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 728 729 /** 730 * DOC: max_num_of_queues_per_device (int) 731 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 732 * is 4096. 733 */ 734 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 735 module_param(max_num_of_queues_per_device, int, 0444); 736 MODULE_PARM_DESC(max_num_of_queues_per_device, 737 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 738 739 /** 740 * DOC: send_sigterm (int) 741 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 742 * but just print errors on dmesg. Setting 1 enables sending sigterm. 743 */ 744 int send_sigterm; 745 module_param(send_sigterm, int, 0444); 746 MODULE_PARM_DESC(send_sigterm, 747 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 748 749 /** 750 * DOC: debug_largebar (int) 751 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 752 * system. This limits the VRAM size reported to ROCm applications to the visible 753 * size, usually 256MB. 754 * Default value is 0, diabled. 755 */ 756 int debug_largebar; 757 module_param(debug_largebar, int, 0444); 758 MODULE_PARM_DESC(debug_largebar, 759 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 760 761 /** 762 * DOC: ignore_crat (int) 763 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 764 * table to get information about AMD APUs. This option can serve as a workaround on 765 * systems with a broken CRAT table. 766 * 767 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 768 * whether use CRAT) 769 */ 770 int ignore_crat; 771 module_param(ignore_crat, int, 0444); 772 MODULE_PARM_DESC(ignore_crat, 773 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 774 775 /** 776 * DOC: halt_if_hws_hang (int) 777 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 778 * Setting 1 enables halt on hang. 779 */ 780 int halt_if_hws_hang; 781 module_param(halt_if_hws_hang, int, 0644); 782 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 783 784 /** 785 * DOC: hws_gws_support(bool) 786 * Assume that HWS supports GWS barriers regardless of what firmware version 787 * check says. Default value: false (rely on MEC2 firmware version check). 788 */ 789 bool hws_gws_support; 790 module_param(hws_gws_support, bool, 0444); 791 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 792 793 /** 794 * DOC: queue_preemption_timeout_ms (int) 795 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 796 */ 797 int queue_preemption_timeout_ms = 9000; 798 module_param(queue_preemption_timeout_ms, int, 0644); 799 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 800 801 /** 802 * DOC: debug_evictions(bool) 803 * Enable extra debug messages to help determine the cause of evictions 804 */ 805 bool debug_evictions; 806 module_param(debug_evictions, bool, 0644); 807 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 808 809 /** 810 * DOC: no_system_mem_limit(bool) 811 * Disable system memory limit, to support multiple process shared memory 812 */ 813 bool no_system_mem_limit; 814 module_param(no_system_mem_limit, bool, 0644); 815 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 816 817 /** 818 * DOC: no_queue_eviction_on_vm_fault (int) 819 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 820 */ 821 int amdgpu_no_queue_eviction_on_vm_fault = 0; 822 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 823 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 824 #endif 825 826 /** 827 * DOC: pcie_p2p (bool) 828 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 829 */ 830 #ifdef CONFIG_HSA_AMD_P2P 831 bool pcie_p2p = true; 832 module_param(pcie_p2p, bool, 0444); 833 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 834 #endif 835 836 /** 837 * DOC: dcfeaturemask (uint) 838 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 839 * The default is the current set of stable display features. 840 */ 841 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 842 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 843 844 /** 845 * DOC: dcdebugmask (uint) 846 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 847 */ 848 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 849 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 850 851 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 852 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 853 854 /** 855 * DOC: abmlevel (uint) 856 * Override the default ABM (Adaptive Backlight Management) level used for DC 857 * enabled hardware. Requires DMCU to be supported and loaded. 858 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 859 * default. Values 1-4 control the maximum allowable brightness reduction via 860 * the ABM algorithm, with 1 being the least reduction and 4 being the most 861 * reduction. 862 * 863 * Defaults to 0, or disabled. Userspace can still override this level later 864 * after boot. 865 */ 866 uint amdgpu_dm_abm_level; 867 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 868 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 869 870 int amdgpu_backlight = -1; 871 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 872 module_param_named(backlight, amdgpu_backlight, bint, 0444); 873 874 /** 875 * DOC: tmz (int) 876 * Trusted Memory Zone (TMZ) is a method to protect data being written 877 * to or read from memory. 878 * 879 * The default value: 0 (off). TODO: change to auto till it is completed. 880 */ 881 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 882 module_param_named(tmz, amdgpu_tmz, int, 0444); 883 884 /** 885 * DOC: freesync_video (uint) 886 * Enable the optimization to adjust front porch timing to achieve seamless 887 * mode change experience when setting a freesync supported mode for which full 888 * modeset is not needed. 889 * 890 * The Display Core will add a set of modes derived from the base FreeSync 891 * video mode into the corresponding connector's mode list based on commonly 892 * used refresh rates and VRR range of the connected display, when users enable 893 * this feature. From the userspace perspective, they can see a seamless mode 894 * change experience when the change between different refresh rates under the 895 * same resolution. Additionally, userspace applications such as Video playback 896 * can read this modeset list and change the refresh rate based on the video 897 * frame rate. Finally, the userspace can also derive an appropriate mode for a 898 * particular refresh rate based on the FreeSync Mode and add it to the 899 * connector's mode list. 900 * 901 * Note: This is an experimental feature. 902 * 903 * The default value: 0 (off). 904 */ 905 MODULE_PARM_DESC( 906 freesync_video, 907 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 908 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 909 910 /** 911 * DOC: reset_method (int) 912 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 913 */ 914 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 915 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 916 917 /** 918 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 919 * threshold value of faulty pages detected by RAS ECC, which may 920 * result in the GPU entering bad status when the number of total 921 * faulty pages by ECC exceeds the threshold value. 922 */ 923 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 924 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 925 926 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 927 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 928 929 /** 930 * DOC: vcnfw_log (int) 931 * Enable vcnfw log output for debugging, the default is disabled. 932 */ 933 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 934 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 935 936 /** 937 * DOC: smu_pptable_id (int) 938 * Used to override pptable id. id = 0 use VBIOS pptable. 939 * id > 0 use the soft pptable with specicfied id. 940 */ 941 MODULE_PARM_DESC(smu_pptable_id, 942 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 943 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 944 945 /* These devices are not supported by amdgpu. 946 * They are supported by the mach64, r128, radeon drivers 947 */ 948 static const u16 amdgpu_unsupported_pciidlist[] = { 949 /* mach64 */ 950 0x4354, 951 0x4358, 952 0x4554, 953 0x4742, 954 0x4744, 955 0x4749, 956 0x474C, 957 0x474D, 958 0x474E, 959 0x474F, 960 0x4750, 961 0x4751, 962 0x4752, 963 0x4753, 964 0x4754, 965 0x4755, 966 0x4756, 967 0x4757, 968 0x4758, 969 0x4759, 970 0x475A, 971 0x4C42, 972 0x4C44, 973 0x4C47, 974 0x4C49, 975 0x4C4D, 976 0x4C4E, 977 0x4C50, 978 0x4C51, 979 0x4C52, 980 0x4C53, 981 0x5654, 982 0x5655, 983 0x5656, 984 /* r128 */ 985 0x4c45, 986 0x4c46, 987 0x4d46, 988 0x4d4c, 989 0x5041, 990 0x5042, 991 0x5043, 992 0x5044, 993 0x5045, 994 0x5046, 995 0x5047, 996 0x5048, 997 0x5049, 998 0x504A, 999 0x504B, 1000 0x504C, 1001 0x504D, 1002 0x504E, 1003 0x504F, 1004 0x5050, 1005 0x5051, 1006 0x5052, 1007 0x5053, 1008 0x5054, 1009 0x5055, 1010 0x5056, 1011 0x5057, 1012 0x5058, 1013 0x5245, 1014 0x5246, 1015 0x5247, 1016 0x524b, 1017 0x524c, 1018 0x534d, 1019 0x5446, 1020 0x544C, 1021 0x5452, 1022 /* radeon */ 1023 0x3150, 1024 0x3151, 1025 0x3152, 1026 0x3154, 1027 0x3155, 1028 0x3E50, 1029 0x3E54, 1030 0x4136, 1031 0x4137, 1032 0x4144, 1033 0x4145, 1034 0x4146, 1035 0x4147, 1036 0x4148, 1037 0x4149, 1038 0x414A, 1039 0x414B, 1040 0x4150, 1041 0x4151, 1042 0x4152, 1043 0x4153, 1044 0x4154, 1045 0x4155, 1046 0x4156, 1047 0x4237, 1048 0x4242, 1049 0x4336, 1050 0x4337, 1051 0x4437, 1052 0x4966, 1053 0x4967, 1054 0x4A48, 1055 0x4A49, 1056 0x4A4A, 1057 0x4A4B, 1058 0x4A4C, 1059 0x4A4D, 1060 0x4A4E, 1061 0x4A4F, 1062 0x4A50, 1063 0x4A54, 1064 0x4B48, 1065 0x4B49, 1066 0x4B4A, 1067 0x4B4B, 1068 0x4B4C, 1069 0x4C57, 1070 0x4C58, 1071 0x4C59, 1072 0x4C5A, 1073 0x4C64, 1074 0x4C66, 1075 0x4C67, 1076 0x4E44, 1077 0x4E45, 1078 0x4E46, 1079 0x4E47, 1080 0x4E48, 1081 0x4E49, 1082 0x4E4A, 1083 0x4E4B, 1084 0x4E50, 1085 0x4E51, 1086 0x4E52, 1087 0x4E53, 1088 0x4E54, 1089 0x4E56, 1090 0x5144, 1091 0x5145, 1092 0x5146, 1093 0x5147, 1094 0x5148, 1095 0x514C, 1096 0x514D, 1097 0x5157, 1098 0x5158, 1099 0x5159, 1100 0x515A, 1101 0x515E, 1102 0x5460, 1103 0x5462, 1104 0x5464, 1105 0x5548, 1106 0x5549, 1107 0x554A, 1108 0x554B, 1109 0x554C, 1110 0x554D, 1111 0x554E, 1112 0x554F, 1113 0x5550, 1114 0x5551, 1115 0x5552, 1116 0x5554, 1117 0x564A, 1118 0x564B, 1119 0x564F, 1120 0x5652, 1121 0x5653, 1122 0x5657, 1123 0x5834, 1124 0x5835, 1125 0x5954, 1126 0x5955, 1127 0x5974, 1128 0x5975, 1129 0x5960, 1130 0x5961, 1131 0x5962, 1132 0x5964, 1133 0x5965, 1134 0x5969, 1135 0x5a41, 1136 0x5a42, 1137 0x5a61, 1138 0x5a62, 1139 0x5b60, 1140 0x5b62, 1141 0x5b63, 1142 0x5b64, 1143 0x5b65, 1144 0x5c61, 1145 0x5c63, 1146 0x5d48, 1147 0x5d49, 1148 0x5d4a, 1149 0x5d4c, 1150 0x5d4d, 1151 0x5d4e, 1152 0x5d4f, 1153 0x5d50, 1154 0x5d52, 1155 0x5d57, 1156 0x5e48, 1157 0x5e4a, 1158 0x5e4b, 1159 0x5e4c, 1160 0x5e4d, 1161 0x5e4f, 1162 0x6700, 1163 0x6701, 1164 0x6702, 1165 0x6703, 1166 0x6704, 1167 0x6705, 1168 0x6706, 1169 0x6707, 1170 0x6708, 1171 0x6709, 1172 0x6718, 1173 0x6719, 1174 0x671c, 1175 0x671d, 1176 0x671f, 1177 0x6720, 1178 0x6721, 1179 0x6722, 1180 0x6723, 1181 0x6724, 1182 0x6725, 1183 0x6726, 1184 0x6727, 1185 0x6728, 1186 0x6729, 1187 0x6738, 1188 0x6739, 1189 0x673e, 1190 0x6740, 1191 0x6741, 1192 0x6742, 1193 0x6743, 1194 0x6744, 1195 0x6745, 1196 0x6746, 1197 0x6747, 1198 0x6748, 1199 0x6749, 1200 0x674A, 1201 0x6750, 1202 0x6751, 1203 0x6758, 1204 0x6759, 1205 0x675B, 1206 0x675D, 1207 0x675F, 1208 0x6760, 1209 0x6761, 1210 0x6762, 1211 0x6763, 1212 0x6764, 1213 0x6765, 1214 0x6766, 1215 0x6767, 1216 0x6768, 1217 0x6770, 1218 0x6771, 1219 0x6772, 1220 0x6778, 1221 0x6779, 1222 0x677B, 1223 0x6840, 1224 0x6841, 1225 0x6842, 1226 0x6843, 1227 0x6849, 1228 0x684C, 1229 0x6850, 1230 0x6858, 1231 0x6859, 1232 0x6880, 1233 0x6888, 1234 0x6889, 1235 0x688A, 1236 0x688C, 1237 0x688D, 1238 0x6898, 1239 0x6899, 1240 0x689b, 1241 0x689c, 1242 0x689d, 1243 0x689e, 1244 0x68a0, 1245 0x68a1, 1246 0x68a8, 1247 0x68a9, 1248 0x68b0, 1249 0x68b8, 1250 0x68b9, 1251 0x68ba, 1252 0x68be, 1253 0x68bf, 1254 0x68c0, 1255 0x68c1, 1256 0x68c7, 1257 0x68c8, 1258 0x68c9, 1259 0x68d8, 1260 0x68d9, 1261 0x68da, 1262 0x68de, 1263 0x68e0, 1264 0x68e1, 1265 0x68e4, 1266 0x68e5, 1267 0x68e8, 1268 0x68e9, 1269 0x68f1, 1270 0x68f2, 1271 0x68f8, 1272 0x68f9, 1273 0x68fa, 1274 0x68fe, 1275 0x7100, 1276 0x7101, 1277 0x7102, 1278 0x7103, 1279 0x7104, 1280 0x7105, 1281 0x7106, 1282 0x7108, 1283 0x7109, 1284 0x710A, 1285 0x710B, 1286 0x710C, 1287 0x710E, 1288 0x710F, 1289 0x7140, 1290 0x7141, 1291 0x7142, 1292 0x7143, 1293 0x7144, 1294 0x7145, 1295 0x7146, 1296 0x7147, 1297 0x7149, 1298 0x714A, 1299 0x714B, 1300 0x714C, 1301 0x714D, 1302 0x714E, 1303 0x714F, 1304 0x7151, 1305 0x7152, 1306 0x7153, 1307 0x715E, 1308 0x715F, 1309 0x7180, 1310 0x7181, 1311 0x7183, 1312 0x7186, 1313 0x7187, 1314 0x7188, 1315 0x718A, 1316 0x718B, 1317 0x718C, 1318 0x718D, 1319 0x718F, 1320 0x7193, 1321 0x7196, 1322 0x719B, 1323 0x719F, 1324 0x71C0, 1325 0x71C1, 1326 0x71C2, 1327 0x71C3, 1328 0x71C4, 1329 0x71C5, 1330 0x71C6, 1331 0x71C7, 1332 0x71CD, 1333 0x71CE, 1334 0x71D2, 1335 0x71D4, 1336 0x71D5, 1337 0x71D6, 1338 0x71DA, 1339 0x71DE, 1340 0x7200, 1341 0x7210, 1342 0x7211, 1343 0x7240, 1344 0x7243, 1345 0x7244, 1346 0x7245, 1347 0x7246, 1348 0x7247, 1349 0x7248, 1350 0x7249, 1351 0x724A, 1352 0x724B, 1353 0x724C, 1354 0x724D, 1355 0x724E, 1356 0x724F, 1357 0x7280, 1358 0x7281, 1359 0x7283, 1360 0x7284, 1361 0x7287, 1362 0x7288, 1363 0x7289, 1364 0x728B, 1365 0x728C, 1366 0x7290, 1367 0x7291, 1368 0x7293, 1369 0x7297, 1370 0x7834, 1371 0x7835, 1372 0x791e, 1373 0x791f, 1374 0x793f, 1375 0x7941, 1376 0x7942, 1377 0x796c, 1378 0x796d, 1379 0x796e, 1380 0x796f, 1381 0x9400, 1382 0x9401, 1383 0x9402, 1384 0x9403, 1385 0x9405, 1386 0x940A, 1387 0x940B, 1388 0x940F, 1389 0x94A0, 1390 0x94A1, 1391 0x94A3, 1392 0x94B1, 1393 0x94B3, 1394 0x94B4, 1395 0x94B5, 1396 0x94B9, 1397 0x9440, 1398 0x9441, 1399 0x9442, 1400 0x9443, 1401 0x9444, 1402 0x9446, 1403 0x944A, 1404 0x944B, 1405 0x944C, 1406 0x944E, 1407 0x9450, 1408 0x9452, 1409 0x9456, 1410 0x945A, 1411 0x945B, 1412 0x945E, 1413 0x9460, 1414 0x9462, 1415 0x946A, 1416 0x946B, 1417 0x947A, 1418 0x947B, 1419 0x9480, 1420 0x9487, 1421 0x9488, 1422 0x9489, 1423 0x948A, 1424 0x948F, 1425 0x9490, 1426 0x9491, 1427 0x9495, 1428 0x9498, 1429 0x949C, 1430 0x949E, 1431 0x949F, 1432 0x94C0, 1433 0x94C1, 1434 0x94C3, 1435 0x94C4, 1436 0x94C5, 1437 0x94C6, 1438 0x94C7, 1439 0x94C8, 1440 0x94C9, 1441 0x94CB, 1442 0x94CC, 1443 0x94CD, 1444 0x9500, 1445 0x9501, 1446 0x9504, 1447 0x9505, 1448 0x9506, 1449 0x9507, 1450 0x9508, 1451 0x9509, 1452 0x950F, 1453 0x9511, 1454 0x9515, 1455 0x9517, 1456 0x9519, 1457 0x9540, 1458 0x9541, 1459 0x9542, 1460 0x954E, 1461 0x954F, 1462 0x9552, 1463 0x9553, 1464 0x9555, 1465 0x9557, 1466 0x955f, 1467 0x9580, 1468 0x9581, 1469 0x9583, 1470 0x9586, 1471 0x9587, 1472 0x9588, 1473 0x9589, 1474 0x958A, 1475 0x958B, 1476 0x958C, 1477 0x958D, 1478 0x958E, 1479 0x958F, 1480 0x9590, 1481 0x9591, 1482 0x9593, 1483 0x9595, 1484 0x9596, 1485 0x9597, 1486 0x9598, 1487 0x9599, 1488 0x959B, 1489 0x95C0, 1490 0x95C2, 1491 0x95C4, 1492 0x95C5, 1493 0x95C6, 1494 0x95C7, 1495 0x95C9, 1496 0x95CC, 1497 0x95CD, 1498 0x95CE, 1499 0x95CF, 1500 0x9610, 1501 0x9611, 1502 0x9612, 1503 0x9613, 1504 0x9614, 1505 0x9615, 1506 0x9616, 1507 0x9640, 1508 0x9641, 1509 0x9642, 1510 0x9643, 1511 0x9644, 1512 0x9645, 1513 0x9647, 1514 0x9648, 1515 0x9649, 1516 0x964a, 1517 0x964b, 1518 0x964c, 1519 0x964e, 1520 0x964f, 1521 0x9710, 1522 0x9711, 1523 0x9712, 1524 0x9713, 1525 0x9714, 1526 0x9715, 1527 0x9802, 1528 0x9803, 1529 0x9804, 1530 0x9805, 1531 0x9806, 1532 0x9807, 1533 0x9808, 1534 0x9809, 1535 0x980A, 1536 0x9900, 1537 0x9901, 1538 0x9903, 1539 0x9904, 1540 0x9905, 1541 0x9906, 1542 0x9907, 1543 0x9908, 1544 0x9909, 1545 0x990A, 1546 0x990B, 1547 0x990C, 1548 0x990D, 1549 0x990E, 1550 0x990F, 1551 0x9910, 1552 0x9913, 1553 0x9917, 1554 0x9918, 1555 0x9919, 1556 0x9990, 1557 0x9991, 1558 0x9992, 1559 0x9993, 1560 0x9994, 1561 0x9995, 1562 0x9996, 1563 0x9997, 1564 0x9998, 1565 0x9999, 1566 0x999A, 1567 0x999B, 1568 0x999C, 1569 0x999D, 1570 0x99A0, 1571 0x99A2, 1572 0x99A4, 1573 /* radeon secondary ids */ 1574 0x3171, 1575 0x3e70, 1576 0x4164, 1577 0x4165, 1578 0x4166, 1579 0x4168, 1580 0x4170, 1581 0x4171, 1582 0x4172, 1583 0x4173, 1584 0x496e, 1585 0x4a69, 1586 0x4a6a, 1587 0x4a6b, 1588 0x4a70, 1589 0x4a74, 1590 0x4b69, 1591 0x4b6b, 1592 0x4b6c, 1593 0x4c6e, 1594 0x4e64, 1595 0x4e65, 1596 0x4e66, 1597 0x4e67, 1598 0x4e68, 1599 0x4e69, 1600 0x4e6a, 1601 0x4e71, 1602 0x4f73, 1603 0x5569, 1604 0x556b, 1605 0x556d, 1606 0x556f, 1607 0x5571, 1608 0x5854, 1609 0x5874, 1610 0x5940, 1611 0x5941, 1612 0x5b72, 1613 0x5b73, 1614 0x5b74, 1615 0x5b75, 1616 0x5d44, 1617 0x5d45, 1618 0x5d6d, 1619 0x5d6f, 1620 0x5d72, 1621 0x5d77, 1622 0x5e6b, 1623 0x5e6d, 1624 0x7120, 1625 0x7124, 1626 0x7129, 1627 0x712e, 1628 0x712f, 1629 0x7162, 1630 0x7163, 1631 0x7166, 1632 0x7167, 1633 0x7172, 1634 0x7173, 1635 0x71a0, 1636 0x71a1, 1637 0x71a3, 1638 0x71a7, 1639 0x71bb, 1640 0x71e0, 1641 0x71e1, 1642 0x71e2, 1643 0x71e6, 1644 0x71e7, 1645 0x71f2, 1646 0x7269, 1647 0x726b, 1648 0x726e, 1649 0x72a0, 1650 0x72a8, 1651 0x72b1, 1652 0x72b3, 1653 0x793f, 1654 }; 1655 1656 static const struct pci_device_id pciidlist[] = { 1657 #ifdef CONFIG_DRM_AMDGPU_SI 1658 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1659 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1660 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1661 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1662 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1663 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1664 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1665 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1666 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1668 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1669 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1670 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1671 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1674 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1675 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1676 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1677 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1678 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1679 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1680 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1681 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1682 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1683 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1684 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1685 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1689 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1690 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1691 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1692 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1693 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1694 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1695 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1700 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1701 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1708 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1709 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1710 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1711 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1713 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1717 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1718 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1719 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1720 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1721 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1722 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1723 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1724 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1729 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1730 #endif 1731 #ifdef CONFIG_DRM_AMDGPU_CIK 1732 /* Kaveri */ 1733 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1735 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1736 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1737 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1743 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1744 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1745 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1746 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1747 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1748 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1749 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1750 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1752 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1753 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1754 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1755 /* Bonaire */ 1756 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1757 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1758 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1759 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1760 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1761 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1762 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1763 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1764 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1765 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1766 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1767 /* Hawaii */ 1768 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1769 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1770 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1771 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1772 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1773 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1774 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1775 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1776 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1777 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1778 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1779 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1780 /* Kabini */ 1781 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1783 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1784 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1785 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1786 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1787 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1788 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1789 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1790 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1791 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1792 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1793 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1794 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1795 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1796 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1797 /* mullins */ 1798 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1800 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1801 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1802 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1803 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1804 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1805 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1806 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1814 #endif 1815 /* topaz */ 1816 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1817 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1818 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1819 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1820 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1821 /* tonga */ 1822 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1823 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1824 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1825 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1826 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1827 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1828 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1829 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1830 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1831 /* fiji */ 1832 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1833 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1834 /* carrizo */ 1835 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1836 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1837 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1838 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1839 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1840 /* stoney */ 1841 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1842 /* Polaris11 */ 1843 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1844 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1845 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1846 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1847 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1848 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1849 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1850 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1851 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1852 /* Polaris10 */ 1853 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1854 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1855 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1856 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1857 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1858 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1859 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1860 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1861 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1863 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1864 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1865 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1866 /* Polaris12 */ 1867 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1868 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1869 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1870 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1871 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1872 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1873 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1874 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1875 /* VEGAM */ 1876 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1877 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1878 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1879 /* Vega 10 */ 1880 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1881 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1882 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1883 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1884 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1885 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1886 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1887 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1888 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1893 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1894 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1895 /* Vega 12 */ 1896 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1897 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1898 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1899 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1900 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1901 /* Vega 20 */ 1902 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1903 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1904 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1905 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1906 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1907 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1908 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1909 /* Raven */ 1910 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1911 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1912 /* Arcturus */ 1913 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1914 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1915 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1916 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1917 /* Navi10 */ 1918 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1919 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1920 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1921 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1922 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1923 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1924 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1925 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1926 /* Navi14 */ 1927 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1928 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1929 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1930 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1931 1932 /* Renoir */ 1933 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1934 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1935 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1936 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1937 1938 /* Navi12 */ 1939 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1940 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1941 1942 /* Sienna_Cichlid */ 1943 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1944 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1945 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1946 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1947 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1948 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1949 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1950 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1951 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1953 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1954 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1955 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1956 1957 /* Yellow Carp */ 1958 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1959 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1960 1961 /* Navy_Flounder */ 1962 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1963 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1964 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1965 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1966 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1967 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1968 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1969 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1970 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1971 1972 /* DIMGREY_CAVEFISH */ 1973 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1974 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1975 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1976 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1977 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1978 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1979 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1980 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1981 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1982 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1983 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1984 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1985 1986 /* Aldebaran */ 1987 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1988 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1989 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1990 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1991 1992 /* CYAN_SKILLFISH */ 1993 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1994 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1995 1996 /* BEIGE_GOBY */ 1997 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1998 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1999 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2000 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2001 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2002 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2003 2004 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2005 .class = PCI_CLASS_DISPLAY_VGA << 8, 2006 .class_mask = 0xffffff, 2007 .driver_data = CHIP_IP_DISCOVERY }, 2008 2009 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2010 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2011 .class_mask = 0xffffff, 2012 .driver_data = CHIP_IP_DISCOVERY }, 2013 2014 {0, 0, 0} 2015 }; 2016 2017 MODULE_DEVICE_TABLE(pci, pciidlist); 2018 2019 static const struct drm_driver amdgpu_kms_driver; 2020 2021 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2022 { 2023 struct pci_dev *p = NULL; 2024 int i; 2025 2026 /* 0 - GPU 2027 * 1 - audio 2028 * 2 - USB 2029 * 3 - UCSI 2030 */ 2031 for (i = 1; i < 4; i++) { 2032 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2033 adev->pdev->bus->number, i); 2034 if (p) { 2035 pm_runtime_get_sync(&p->dev); 2036 pm_runtime_mark_last_busy(&p->dev); 2037 pm_runtime_put_autosuspend(&p->dev); 2038 pci_dev_put(p); 2039 } 2040 } 2041 } 2042 2043 static int amdgpu_pci_probe(struct pci_dev *pdev, 2044 const struct pci_device_id *ent) 2045 { 2046 struct drm_device *ddev; 2047 struct amdgpu_device *adev; 2048 unsigned long flags = ent->driver_data; 2049 int ret, retry = 0, i; 2050 bool supports_atomic = false; 2051 2052 /* skip devices which are owned by radeon */ 2053 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2054 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2055 return -ENODEV; 2056 } 2057 2058 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2059 amdgpu_aspm = 0; 2060 2061 if (amdgpu_virtual_display || 2062 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2063 supports_atomic = true; 2064 2065 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2066 DRM_INFO("This hardware requires experimental hardware support.\n" 2067 "See modparam exp_hw_support\n"); 2068 return -ENODEV; 2069 } 2070 /* differentiate between P10 and P11 asics with the same DID */ 2071 if (pdev->device == 0x67FF && 2072 (pdev->revision == 0xE3 || 2073 pdev->revision == 0xE7 || 2074 pdev->revision == 0xF3 || 2075 pdev->revision == 0xF7)) { 2076 flags &= ~AMD_ASIC_MASK; 2077 flags |= CHIP_POLARIS10; 2078 } 2079 2080 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2081 * however, SME requires an indirect IOMMU mapping because the encryption 2082 * bit is beyond the DMA mask of the chip. 2083 */ 2084 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2085 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2086 dev_info(&pdev->dev, 2087 "SME is not compatible with RAVEN\n"); 2088 return -ENOTSUPP; 2089 } 2090 2091 #ifdef CONFIG_DRM_AMDGPU_SI 2092 if (!amdgpu_si_support) { 2093 switch (flags & AMD_ASIC_MASK) { 2094 case CHIP_TAHITI: 2095 case CHIP_PITCAIRN: 2096 case CHIP_VERDE: 2097 case CHIP_OLAND: 2098 case CHIP_HAINAN: 2099 dev_info(&pdev->dev, 2100 "SI support provided by radeon.\n"); 2101 dev_info(&pdev->dev, 2102 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2103 ); 2104 return -ENODEV; 2105 } 2106 } 2107 #endif 2108 #ifdef CONFIG_DRM_AMDGPU_CIK 2109 if (!amdgpu_cik_support) { 2110 switch (flags & AMD_ASIC_MASK) { 2111 case CHIP_KAVERI: 2112 case CHIP_BONAIRE: 2113 case CHIP_HAWAII: 2114 case CHIP_KABINI: 2115 case CHIP_MULLINS: 2116 dev_info(&pdev->dev, 2117 "CIK support provided by radeon.\n"); 2118 dev_info(&pdev->dev, 2119 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2120 ); 2121 return -ENODEV; 2122 } 2123 } 2124 #endif 2125 2126 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2127 if (IS_ERR(adev)) 2128 return PTR_ERR(adev); 2129 2130 adev->dev = &pdev->dev; 2131 adev->pdev = pdev; 2132 ddev = adev_to_drm(adev); 2133 2134 if (!supports_atomic) 2135 ddev->driver_features &= ~DRIVER_ATOMIC; 2136 2137 ret = pci_enable_device(pdev); 2138 if (ret) 2139 return ret; 2140 2141 pci_set_drvdata(pdev, ddev); 2142 2143 ret = amdgpu_driver_load_kms(adev, flags); 2144 if (ret) 2145 goto err_pci; 2146 2147 retry_init: 2148 ret = drm_dev_register(ddev, flags); 2149 if (ret == -EAGAIN && ++retry <= 3) { 2150 DRM_INFO("retry init %d\n", retry); 2151 /* Don't request EX mode too frequently which is attacking */ 2152 msleep(5000); 2153 goto retry_init; 2154 } else if (ret) { 2155 goto err_pci; 2156 } 2157 2158 /* 2159 * 1. don't init fbdev on hw without DCE 2160 * 2. don't init fbdev if there are no connectors 2161 */ 2162 if (adev->mode_info.mode_config_initialized && 2163 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2164 /* select 8 bpp console on low vram cards */ 2165 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2166 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2167 else 2168 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2169 } 2170 2171 ret = amdgpu_debugfs_init(adev); 2172 if (ret) 2173 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2174 2175 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2176 /* only need to skip on ATPX */ 2177 if (amdgpu_device_supports_px(ddev)) 2178 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2179 /* we want direct complete for BOCO */ 2180 if (amdgpu_device_supports_boco(ddev)) 2181 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2182 DPM_FLAG_SMART_SUSPEND | 2183 DPM_FLAG_MAY_SKIP_RESUME); 2184 pm_runtime_use_autosuspend(ddev->dev); 2185 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2186 2187 pm_runtime_allow(ddev->dev); 2188 2189 pm_runtime_mark_last_busy(ddev->dev); 2190 pm_runtime_put_autosuspend(ddev->dev); 2191 2192 /* 2193 * For runpm implemented via BACO, PMFW will handle the 2194 * timing for BACO in and out: 2195 * - put ASIC into BACO state only when both video and 2196 * audio functions are in D3 state. 2197 * - pull ASIC out of BACO state when either video or 2198 * audio function is in D0 state. 2199 * Also, at startup, PMFW assumes both functions are in 2200 * D0 state. 2201 * 2202 * So if snd driver was loaded prior to amdgpu driver 2203 * and audio function was put into D3 state, there will 2204 * be no PMFW-aware D-state transition(D0->D3) on runpm 2205 * suspend. Thus the BACO will be not correctly kicked in. 2206 * 2207 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2208 * into D0 state. Then there will be a PMFW-aware D-state 2209 * transition(D0->D3) on runpm suspend. 2210 */ 2211 if (amdgpu_device_supports_baco(ddev) && 2212 !(adev->flags & AMD_IS_APU) && 2213 (adev->asic_type >= CHIP_NAVI10)) 2214 amdgpu_get_secondary_funcs(adev); 2215 } 2216 2217 return 0; 2218 2219 err_pci: 2220 pci_disable_device(pdev); 2221 return ret; 2222 } 2223 2224 static void 2225 amdgpu_pci_remove(struct pci_dev *pdev) 2226 { 2227 struct drm_device *dev = pci_get_drvdata(pdev); 2228 struct amdgpu_device *adev = drm_to_adev(dev); 2229 2230 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2231 pm_runtime_get_sync(dev->dev); 2232 pm_runtime_forbid(dev->dev); 2233 } 2234 2235 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2236 !amdgpu_sriov_vf(adev)) { 2237 bool need_to_reset_gpu = false; 2238 2239 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2240 struct amdgpu_hive_info *hive; 2241 2242 hive = amdgpu_get_xgmi_hive(adev); 2243 if (hive->device_remove_count == 0) 2244 need_to_reset_gpu = true; 2245 hive->device_remove_count++; 2246 amdgpu_put_xgmi_hive(hive); 2247 } else { 2248 need_to_reset_gpu = true; 2249 } 2250 2251 /* Workaround for ASICs need to reset SMU. 2252 * Called only when the first device is removed. 2253 */ 2254 if (need_to_reset_gpu) { 2255 struct amdgpu_reset_context reset_context; 2256 2257 adev->shutdown = true; 2258 memset(&reset_context, 0, sizeof(reset_context)); 2259 reset_context.method = AMD_RESET_METHOD_NONE; 2260 reset_context.reset_req_dev = adev; 2261 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2262 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2263 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2264 } 2265 } 2266 2267 amdgpu_driver_unload_kms(dev); 2268 2269 drm_dev_unplug(dev); 2270 2271 /* 2272 * Flush any in flight DMA operations from device. 2273 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2274 * StatusTransactions Pending bit. 2275 */ 2276 pci_disable_device(pdev); 2277 pci_wait_for_pending_transaction(pdev); 2278 } 2279 2280 static void 2281 amdgpu_pci_shutdown(struct pci_dev *pdev) 2282 { 2283 struct drm_device *dev = pci_get_drvdata(pdev); 2284 struct amdgpu_device *adev = drm_to_adev(dev); 2285 2286 if (amdgpu_ras_intr_triggered()) 2287 return; 2288 2289 /* if we are running in a VM, make sure the device 2290 * torn down properly on reboot/shutdown. 2291 * unfortunately we can't detect certain 2292 * hypervisors so just do this all the time. 2293 */ 2294 if (!amdgpu_passthrough(adev)) 2295 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2296 amdgpu_device_ip_suspend(adev); 2297 adev->mp1_state = PP_MP1_STATE_NONE; 2298 } 2299 2300 /** 2301 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2302 * 2303 * @work: work_struct. 2304 */ 2305 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2306 { 2307 struct list_head device_list; 2308 struct amdgpu_device *adev; 2309 int i, r; 2310 struct amdgpu_reset_context reset_context; 2311 2312 memset(&reset_context, 0, sizeof(reset_context)); 2313 2314 mutex_lock(&mgpu_info.mutex); 2315 if (mgpu_info.pending_reset == true) { 2316 mutex_unlock(&mgpu_info.mutex); 2317 return; 2318 } 2319 mgpu_info.pending_reset = true; 2320 mutex_unlock(&mgpu_info.mutex); 2321 2322 /* Use a common context, just need to make sure full reset is done */ 2323 reset_context.method = AMD_RESET_METHOD_NONE; 2324 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2325 2326 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2327 adev = mgpu_info.gpu_ins[i].adev; 2328 reset_context.reset_req_dev = adev; 2329 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2330 if (r) { 2331 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2332 r, adev_to_drm(adev)->unique); 2333 } 2334 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2335 r = -EALREADY; 2336 } 2337 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2338 adev = mgpu_info.gpu_ins[i].adev; 2339 flush_work(&adev->xgmi_reset_work); 2340 adev->gmc.xgmi.pending_reset = false; 2341 } 2342 2343 /* reset function will rebuild the xgmi hive info , clear it now */ 2344 for (i = 0; i < mgpu_info.num_dgpu; i++) 2345 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2346 2347 INIT_LIST_HEAD(&device_list); 2348 2349 for (i = 0; i < mgpu_info.num_dgpu; i++) 2350 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2351 2352 /* unregister the GPU first, reset function will add them back */ 2353 list_for_each_entry(adev, &device_list, reset_list) 2354 amdgpu_unregister_gpu_instance(adev); 2355 2356 /* Use a common context, just need to make sure full reset is done */ 2357 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2358 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2359 2360 if (r) { 2361 DRM_ERROR("reinit gpus failure"); 2362 return; 2363 } 2364 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2365 adev = mgpu_info.gpu_ins[i].adev; 2366 if (!adev->kfd.init_complete) 2367 amdgpu_amdkfd_device_init(adev); 2368 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2369 } 2370 return; 2371 } 2372 2373 static int amdgpu_pmops_prepare(struct device *dev) 2374 { 2375 struct drm_device *drm_dev = dev_get_drvdata(dev); 2376 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2377 2378 /* Return a positive number here so 2379 * DPM_FLAG_SMART_SUSPEND works properly 2380 */ 2381 if (amdgpu_device_supports_boco(drm_dev)) 2382 return pm_runtime_suspended(dev); 2383 2384 /* if we will not support s3 or s2i for the device 2385 * then skip suspend 2386 */ 2387 if (!amdgpu_acpi_is_s0ix_active(adev) && 2388 !amdgpu_acpi_is_s3_active(adev)) 2389 return 1; 2390 2391 return 0; 2392 } 2393 2394 static void amdgpu_pmops_complete(struct device *dev) 2395 { 2396 /* nothing to do */ 2397 } 2398 2399 static int amdgpu_pmops_suspend(struct device *dev) 2400 { 2401 struct drm_device *drm_dev = dev_get_drvdata(dev); 2402 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2403 2404 if (amdgpu_acpi_is_s0ix_active(adev)) 2405 adev->in_s0ix = true; 2406 else 2407 adev->in_s3 = true; 2408 return amdgpu_device_suspend(drm_dev, true); 2409 } 2410 2411 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2412 { 2413 struct drm_device *drm_dev = dev_get_drvdata(dev); 2414 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2415 2416 if (amdgpu_acpi_should_gpu_reset(adev)) 2417 return amdgpu_asic_reset(adev); 2418 2419 return 0; 2420 } 2421 2422 static int amdgpu_pmops_resume(struct device *dev) 2423 { 2424 struct drm_device *drm_dev = dev_get_drvdata(dev); 2425 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2426 int r; 2427 2428 /* Avoids registers access if device is physically gone */ 2429 if (!pci_device_is_present(adev->pdev)) 2430 adev->no_hw_access = true; 2431 2432 r = amdgpu_device_resume(drm_dev, true); 2433 if (amdgpu_acpi_is_s0ix_active(adev)) 2434 adev->in_s0ix = false; 2435 else 2436 adev->in_s3 = false; 2437 return r; 2438 } 2439 2440 static int amdgpu_pmops_freeze(struct device *dev) 2441 { 2442 struct drm_device *drm_dev = dev_get_drvdata(dev); 2443 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2444 int r; 2445 2446 adev->in_s4 = true; 2447 r = amdgpu_device_suspend(drm_dev, true); 2448 adev->in_s4 = false; 2449 if (r) 2450 return r; 2451 return amdgpu_asic_reset(adev); 2452 } 2453 2454 static int amdgpu_pmops_thaw(struct device *dev) 2455 { 2456 struct drm_device *drm_dev = dev_get_drvdata(dev); 2457 2458 return amdgpu_device_resume(drm_dev, true); 2459 } 2460 2461 static int amdgpu_pmops_poweroff(struct device *dev) 2462 { 2463 struct drm_device *drm_dev = dev_get_drvdata(dev); 2464 2465 return amdgpu_device_suspend(drm_dev, true); 2466 } 2467 2468 static int amdgpu_pmops_restore(struct device *dev) 2469 { 2470 struct drm_device *drm_dev = dev_get_drvdata(dev); 2471 2472 return amdgpu_device_resume(drm_dev, true); 2473 } 2474 2475 static int amdgpu_runtime_idle_check_display(struct device *dev) 2476 { 2477 struct pci_dev *pdev = to_pci_dev(dev); 2478 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2479 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2480 2481 if (adev->mode_info.num_crtc) { 2482 struct drm_connector *list_connector; 2483 struct drm_connector_list_iter iter; 2484 int ret = 0; 2485 2486 /* XXX: Return busy if any displays are connected to avoid 2487 * possible display wakeups after runtime resume due to 2488 * hotplug events in case any displays were connected while 2489 * the GPU was in suspend. Remove this once that is fixed. 2490 */ 2491 mutex_lock(&drm_dev->mode_config.mutex); 2492 drm_connector_list_iter_begin(drm_dev, &iter); 2493 drm_for_each_connector_iter(list_connector, &iter) { 2494 if (list_connector->status == connector_status_connected) { 2495 ret = -EBUSY; 2496 break; 2497 } 2498 } 2499 drm_connector_list_iter_end(&iter); 2500 mutex_unlock(&drm_dev->mode_config.mutex); 2501 2502 if (ret) 2503 return ret; 2504 2505 if (adev->dc_enabled) { 2506 struct drm_crtc *crtc; 2507 2508 drm_for_each_crtc(crtc, drm_dev) { 2509 drm_modeset_lock(&crtc->mutex, NULL); 2510 if (crtc->state->active) 2511 ret = -EBUSY; 2512 drm_modeset_unlock(&crtc->mutex); 2513 if (ret < 0) 2514 break; 2515 } 2516 } else { 2517 mutex_lock(&drm_dev->mode_config.mutex); 2518 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2519 2520 drm_connector_list_iter_begin(drm_dev, &iter); 2521 drm_for_each_connector_iter(list_connector, &iter) { 2522 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2523 ret = -EBUSY; 2524 break; 2525 } 2526 } 2527 2528 drm_connector_list_iter_end(&iter); 2529 2530 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2531 mutex_unlock(&drm_dev->mode_config.mutex); 2532 } 2533 if (ret) 2534 return ret; 2535 } 2536 2537 return 0; 2538 } 2539 2540 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2541 { 2542 struct pci_dev *pdev = to_pci_dev(dev); 2543 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2544 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2545 int ret, i; 2546 2547 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2548 pm_runtime_forbid(dev); 2549 return -EBUSY; 2550 } 2551 2552 ret = amdgpu_runtime_idle_check_display(dev); 2553 if (ret) 2554 return ret; 2555 2556 /* wait for all rings to drain before suspending */ 2557 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2558 struct amdgpu_ring *ring = adev->rings[i]; 2559 if (ring && ring->sched.ready) { 2560 ret = amdgpu_fence_wait_empty(ring); 2561 if (ret) 2562 return -EBUSY; 2563 } 2564 } 2565 2566 adev->in_runpm = true; 2567 if (amdgpu_device_supports_px(drm_dev)) 2568 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2569 2570 /* 2571 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2572 * proper cleanups and put itself into a state ready for PNP. That 2573 * can address some random resuming failure observed on BOCO capable 2574 * platforms. 2575 * TODO: this may be also needed for PX capable platform. 2576 */ 2577 if (amdgpu_device_supports_boco(drm_dev)) 2578 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2579 2580 ret = amdgpu_device_suspend(drm_dev, false); 2581 if (ret) { 2582 adev->in_runpm = false; 2583 if (amdgpu_device_supports_boco(drm_dev)) 2584 adev->mp1_state = PP_MP1_STATE_NONE; 2585 return ret; 2586 } 2587 2588 if (amdgpu_device_supports_boco(drm_dev)) 2589 adev->mp1_state = PP_MP1_STATE_NONE; 2590 2591 if (amdgpu_device_supports_px(drm_dev)) { 2592 /* Only need to handle PCI state in the driver for ATPX 2593 * PCI core handles it for _PR3. 2594 */ 2595 amdgpu_device_cache_pci_state(pdev); 2596 pci_disable_device(pdev); 2597 pci_ignore_hotplug(pdev); 2598 pci_set_power_state(pdev, PCI_D3cold); 2599 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2600 } else if (amdgpu_device_supports_boco(drm_dev)) { 2601 /* nothing to do */ 2602 } else if (amdgpu_device_supports_baco(drm_dev)) { 2603 amdgpu_device_baco_enter(drm_dev); 2604 } 2605 2606 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2607 2608 return 0; 2609 } 2610 2611 static int amdgpu_pmops_runtime_resume(struct device *dev) 2612 { 2613 struct pci_dev *pdev = to_pci_dev(dev); 2614 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2615 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2616 int ret; 2617 2618 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2619 return -EINVAL; 2620 2621 /* Avoids registers access if device is physically gone */ 2622 if (!pci_device_is_present(adev->pdev)) 2623 adev->no_hw_access = true; 2624 2625 if (amdgpu_device_supports_px(drm_dev)) { 2626 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2627 2628 /* Only need to handle PCI state in the driver for ATPX 2629 * PCI core handles it for _PR3. 2630 */ 2631 pci_set_power_state(pdev, PCI_D0); 2632 amdgpu_device_load_pci_state(pdev); 2633 ret = pci_enable_device(pdev); 2634 if (ret) 2635 return ret; 2636 pci_set_master(pdev); 2637 } else if (amdgpu_device_supports_boco(drm_dev)) { 2638 /* Only need to handle PCI state in the driver for ATPX 2639 * PCI core handles it for _PR3. 2640 */ 2641 pci_set_master(pdev); 2642 } else if (amdgpu_device_supports_baco(drm_dev)) { 2643 amdgpu_device_baco_exit(drm_dev); 2644 } 2645 ret = amdgpu_device_resume(drm_dev, false); 2646 if (ret) { 2647 if (amdgpu_device_supports_px(drm_dev)) 2648 pci_disable_device(pdev); 2649 return ret; 2650 } 2651 2652 if (amdgpu_device_supports_px(drm_dev)) 2653 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2654 adev->in_runpm = false; 2655 return 0; 2656 } 2657 2658 static int amdgpu_pmops_runtime_idle(struct device *dev) 2659 { 2660 struct drm_device *drm_dev = dev_get_drvdata(dev); 2661 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2662 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2663 int ret = 1; 2664 2665 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2666 pm_runtime_forbid(dev); 2667 return -EBUSY; 2668 } 2669 2670 ret = amdgpu_runtime_idle_check_display(dev); 2671 2672 pm_runtime_mark_last_busy(dev); 2673 pm_runtime_autosuspend(dev); 2674 return ret; 2675 } 2676 2677 long amdgpu_drm_ioctl(struct file *filp, 2678 unsigned int cmd, unsigned long arg) 2679 { 2680 struct drm_file *file_priv = filp->private_data; 2681 struct drm_device *dev; 2682 long ret; 2683 dev = file_priv->minor->dev; 2684 ret = pm_runtime_get_sync(dev->dev); 2685 if (ret < 0) 2686 goto out; 2687 2688 ret = drm_ioctl(filp, cmd, arg); 2689 2690 pm_runtime_mark_last_busy(dev->dev); 2691 out: 2692 pm_runtime_put_autosuspend(dev->dev); 2693 return ret; 2694 } 2695 2696 static const struct dev_pm_ops amdgpu_pm_ops = { 2697 .prepare = amdgpu_pmops_prepare, 2698 .complete = amdgpu_pmops_complete, 2699 .suspend = amdgpu_pmops_suspend, 2700 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2701 .resume = amdgpu_pmops_resume, 2702 .freeze = amdgpu_pmops_freeze, 2703 .thaw = amdgpu_pmops_thaw, 2704 .poweroff = amdgpu_pmops_poweroff, 2705 .restore = amdgpu_pmops_restore, 2706 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2707 .runtime_resume = amdgpu_pmops_runtime_resume, 2708 .runtime_idle = amdgpu_pmops_runtime_idle, 2709 }; 2710 2711 static int amdgpu_flush(struct file *f, fl_owner_t id) 2712 { 2713 struct drm_file *file_priv = f->private_data; 2714 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2715 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2716 2717 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2718 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2719 2720 return timeout >= 0 ? 0 : timeout; 2721 } 2722 2723 static const struct file_operations amdgpu_driver_kms_fops = { 2724 .owner = THIS_MODULE, 2725 .open = drm_open, 2726 .flush = amdgpu_flush, 2727 .release = drm_release, 2728 .unlocked_ioctl = amdgpu_drm_ioctl, 2729 .mmap = drm_gem_mmap, 2730 .poll = drm_poll, 2731 .read = drm_read, 2732 #ifdef CONFIG_COMPAT 2733 .compat_ioctl = amdgpu_kms_compat_ioctl, 2734 #endif 2735 #ifdef CONFIG_PROC_FS 2736 .show_fdinfo = amdgpu_show_fdinfo 2737 #endif 2738 }; 2739 2740 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2741 { 2742 struct drm_file *file; 2743 2744 if (!filp) 2745 return -EINVAL; 2746 2747 if (filp->f_op != &amdgpu_driver_kms_fops) { 2748 return -EINVAL; 2749 } 2750 2751 file = filp->private_data; 2752 *fpriv = file->driver_priv; 2753 return 0; 2754 } 2755 2756 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2757 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2758 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2759 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2760 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2761 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2762 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2763 /* KMS */ 2764 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2765 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2766 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2767 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2768 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2769 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2770 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2771 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2772 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2773 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2774 }; 2775 2776 static const struct drm_driver amdgpu_kms_driver = { 2777 .driver_features = 2778 DRIVER_ATOMIC | 2779 DRIVER_GEM | 2780 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2781 DRIVER_SYNCOBJ_TIMELINE, 2782 .open = amdgpu_driver_open_kms, 2783 .postclose = amdgpu_driver_postclose_kms, 2784 .lastclose = amdgpu_driver_lastclose_kms, 2785 .ioctls = amdgpu_ioctls_kms, 2786 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2787 .dumb_create = amdgpu_mode_dumb_create, 2788 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2789 .fops = &amdgpu_driver_kms_fops, 2790 .release = &amdgpu_driver_release_kms, 2791 2792 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2793 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2794 .gem_prime_import = amdgpu_gem_prime_import, 2795 .gem_prime_mmap = drm_gem_prime_mmap, 2796 2797 .name = DRIVER_NAME, 2798 .desc = DRIVER_DESC, 2799 .date = DRIVER_DATE, 2800 .major = KMS_DRIVER_MAJOR, 2801 .minor = KMS_DRIVER_MINOR, 2802 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2803 }; 2804 2805 static struct pci_error_handlers amdgpu_pci_err_handler = { 2806 .error_detected = amdgpu_pci_error_detected, 2807 .mmio_enabled = amdgpu_pci_mmio_enabled, 2808 .slot_reset = amdgpu_pci_slot_reset, 2809 .resume = amdgpu_pci_resume, 2810 }; 2811 2812 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2813 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2814 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2815 2816 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2817 &amdgpu_vram_mgr_attr_group, 2818 &amdgpu_gtt_mgr_attr_group, 2819 &amdgpu_vbios_version_attr_group, 2820 NULL, 2821 }; 2822 2823 2824 static struct pci_driver amdgpu_kms_pci_driver = { 2825 .name = DRIVER_NAME, 2826 .id_table = pciidlist, 2827 .probe = amdgpu_pci_probe, 2828 .remove = amdgpu_pci_remove, 2829 .shutdown = amdgpu_pci_shutdown, 2830 .driver.pm = &amdgpu_pm_ops, 2831 .err_handler = &amdgpu_pci_err_handler, 2832 .dev_groups = amdgpu_sysfs_groups, 2833 }; 2834 2835 static int __init amdgpu_init(void) 2836 { 2837 int r; 2838 2839 if (drm_firmware_drivers_only()) 2840 return -EINVAL; 2841 2842 r = amdgpu_sync_init(); 2843 if (r) 2844 goto error_sync; 2845 2846 r = amdgpu_fence_slab_init(); 2847 if (r) 2848 goto error_fence; 2849 2850 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2851 amdgpu_register_atpx_handler(); 2852 amdgpu_acpi_detect(); 2853 2854 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2855 amdgpu_amdkfd_init(); 2856 2857 /* let modprobe override vga console setting */ 2858 return pci_register_driver(&amdgpu_kms_pci_driver); 2859 2860 error_fence: 2861 amdgpu_sync_fini(); 2862 2863 error_sync: 2864 return r; 2865 } 2866 2867 static void __exit amdgpu_exit(void) 2868 { 2869 amdgpu_amdkfd_fini(); 2870 pci_unregister_driver(&amdgpu_kms_pci_driver); 2871 amdgpu_unregister_atpx_handler(); 2872 amdgpu_sync_fini(); 2873 amdgpu_fence_slab_fini(); 2874 mmu_notifier_synchronize(); 2875 } 2876 2877 module_init(amdgpu_init); 2878 module_exit(amdgpu_exit); 2879 2880 MODULE_AUTHOR(DRIVER_AUTHOR); 2881 MODULE_DESCRIPTION(DRIVER_DESC); 2882 MODULE_LICENSE("GPL and additional rights"); 2883