1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/amdgpu_drm.h> 27 #include <drm/drm_gem.h> 28 #include "amdgpu_drv.h" 29 30 #include <drm/drm_pciids.h> 31 #include <linux/console.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/vga_switcheroo.h> 35 #include <drm/drm_crtc_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_irq.h" 39 40 #include "amdgpu_amdkfd.h" 41 42 /* 43 * KMS wrapper. 44 * - 3.0.0 - initial driver 45 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 46 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 47 * at the end of IBs. 48 * - 3.3.0 - Add VM support for UVD on supported hardware. 49 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 50 * - 3.5.0 - Add support for new UVD_NO_OP register. 51 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 52 * - 3.7.0 - Add support for VCE clock list packet 53 * - 3.8.0 - Add support raster config init in the kernel 54 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 55 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 56 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 57 * - 3.12.0 - Add query for double offchip LDS buffers 58 * - 3.13.0 - Add PRT support 59 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 60 * - 3.15.0 - Export more gpu info for gfx9 61 * - 3.16.0 - Add reserved vmid support 62 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 63 * - 3.18.0 - Export gpu always on cu bitmap 64 * - 3.19.0 - Add support for UVD MJPEG decode 65 * - 3.20.0 - Add support for local BOs 66 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 67 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 68 * - 3.23.0 - Add query for VRAM lost counter 69 * - 3.24.0 - Add high priority compute support for gfx9 70 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 71 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 72 */ 73 #define KMS_DRIVER_MAJOR 3 74 #define KMS_DRIVER_MINOR 26 75 #define KMS_DRIVER_PATCHLEVEL 0 76 77 int amdgpu_vram_limit = 0; 78 int amdgpu_vis_vram_limit = 0; 79 int amdgpu_gart_size = -1; /* auto */ 80 int amdgpu_gtt_size = -1; /* auto */ 81 int amdgpu_moverate = -1; /* auto */ 82 int amdgpu_benchmarking = 0; 83 int amdgpu_testing = 0; 84 int amdgpu_audio = -1; 85 int amdgpu_disp_priority = 0; 86 int amdgpu_hw_i2c = 0; 87 int amdgpu_pcie_gen2 = -1; 88 int amdgpu_msi = -1; 89 int amdgpu_lockup_timeout = 10000; 90 int amdgpu_dpm = -1; 91 int amdgpu_fw_load_type = -1; 92 int amdgpu_aspm = -1; 93 int amdgpu_runtime_pm = -1; 94 uint amdgpu_ip_block_mask = 0xffffffff; 95 int amdgpu_bapm = -1; 96 int amdgpu_deep_color = 0; 97 int amdgpu_vm_size = -1; 98 int amdgpu_vm_fragment_size = -1; 99 int amdgpu_vm_block_size = -1; 100 int amdgpu_vm_fault_stop = 0; 101 int amdgpu_vm_debug = 0; 102 int amdgpu_vram_page_split = 512; 103 int amdgpu_vm_update_mode = -1; 104 int amdgpu_exp_hw_support = 0; 105 int amdgpu_dc = -1; 106 int amdgpu_dc_log = 0; 107 int amdgpu_sched_jobs = 32; 108 int amdgpu_sched_hw_submission = 2; 109 int amdgpu_no_evict = 0; 110 int amdgpu_direct_gma_size = 0; 111 uint amdgpu_pcie_gen_cap = 0; 112 uint amdgpu_pcie_lane_cap = 0; 113 uint amdgpu_cg_mask = 0xffffffff; 114 uint amdgpu_pg_mask = 0xffffffff; 115 uint amdgpu_sdma_phase_quantum = 32; 116 char *amdgpu_disable_cu = NULL; 117 char *amdgpu_virtual_display = NULL; 118 /* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/ 119 uint amdgpu_pp_feature_mask = 0xfffd3fff; 120 int amdgpu_ngg = 0; 121 int amdgpu_prim_buf_per_se = 0; 122 int amdgpu_pos_buf_per_se = 0; 123 int amdgpu_cntl_sb_buf_per_se = 0; 124 int amdgpu_param_buf_per_se = 0; 125 int amdgpu_job_hang_limit = 0; 126 int amdgpu_lbpw = -1; 127 int amdgpu_compute_multipipe = -1; 128 int amdgpu_gpu_recovery = -1; /* auto */ 129 int amdgpu_emu_mode = 0; 130 uint amdgpu_smu_memory_pool_size = 0; 131 132 /** 133 * DOC: vramlimit (int) 134 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 135 */ 136 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 137 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 138 139 /** 140 * DOC: vis_vramlimit (int) 141 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 142 */ 143 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 144 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 145 146 /** 147 * DOC: gartsize (uint) 148 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 149 */ 150 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 151 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 152 153 /** 154 * DOC: gttsize (int) 155 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 156 * otherwise 3/4 RAM size). 157 */ 158 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 159 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 160 161 /** 162 * DOC: moverate (int) 163 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 164 */ 165 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 166 module_param_named(moverate, amdgpu_moverate, int, 0600); 167 168 /** 169 * DOC: benchmark (int) 170 * Run benchmarks. The default is 0 (Skip benchmarks). 171 */ 172 MODULE_PARM_DESC(benchmark, "Run benchmark"); 173 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 174 175 /** 176 * DOC: test (int) 177 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 178 */ 179 MODULE_PARM_DESC(test, "Run tests"); 180 module_param_named(test, amdgpu_testing, int, 0444); 181 182 /** 183 * DOC: audio (int) 184 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 185 */ 186 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 187 module_param_named(audio, amdgpu_audio, int, 0444); 188 189 /** 190 * DOC: disp_priority (int) 191 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 192 */ 193 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 194 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 195 196 /** 197 * DOC: hw_i2c (int) 198 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 199 */ 200 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 201 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 202 203 /** 204 * DOC: pcie_gen2 (int) 205 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 206 */ 207 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 208 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 209 210 /** 211 * DOC: msi (int) 212 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 213 */ 214 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 215 module_param_named(msi, amdgpu_msi, int, 0444); 216 217 /** 218 * DOC: lockup_timeout (int) 219 * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000. 220 * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000. 221 */ 222 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)"); 223 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 224 225 /** 226 * DOC: dpm (int) 227 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto). 228 */ 229 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 230 module_param_named(dpm, amdgpu_dpm, int, 0444); 231 232 /** 233 * DOC: fw_load_type (int) 234 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 235 */ 236 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 237 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 238 239 /** 240 * DOC: aspm (int) 241 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 242 */ 243 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 244 module_param_named(aspm, amdgpu_aspm, int, 0444); 245 246 /** 247 * DOC: runpm (int) 248 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 249 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 250 */ 251 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 252 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 253 254 /** 255 * DOC: ip_block_mask (uint) 256 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 257 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 258 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 259 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 260 */ 261 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 262 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 263 264 /** 265 * DOC: bapm (int) 266 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 267 * The default -1 (auto, enabled) 268 */ 269 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 270 module_param_named(bapm, amdgpu_bapm, int, 0444); 271 272 /** 273 * DOC: deep_color (int) 274 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 275 */ 276 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 277 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 278 279 /** 280 * DOC: vm_size (int) 281 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 282 */ 283 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 284 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 285 286 /** 287 * DOC: vm_fragment_size (int) 288 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 289 */ 290 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 291 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 292 293 /** 294 * DOC: vm_block_size (int) 295 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 296 */ 297 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 298 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 299 300 /** 301 * DOC: vm_fault_stop (int) 302 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 303 */ 304 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 305 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 306 307 /** 308 * DOC: vm_debug (int) 309 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 310 */ 311 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 312 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 313 314 /** 315 * DOC: vm_update_mode (int) 316 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 317 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 318 */ 319 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 320 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 321 322 /** 323 * DOC: vram_page_split (int) 324 * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512. 325 */ 326 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); 327 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 328 329 /** 330 * DOC: exp_hw_support (int) 331 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 332 */ 333 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 334 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 335 336 /** 337 * DOC: dc (int) 338 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 339 */ 340 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 341 module_param_named(dc, amdgpu_dc, int, 0444); 342 343 MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty"); 344 module_param_named(dc_log, amdgpu_dc_log, int, 0444); 345 346 /** 347 * DOC: sched_jobs (int) 348 * Override the max number of jobs supported in the sw queue. The default is 32. 349 */ 350 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 351 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 352 353 /** 354 * DOC: sched_hw_submission (int) 355 * Override the max number of HW submissions. The default is 2. 356 */ 357 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 358 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 359 360 /** 361 * DOC: ppfeaturemask (uint) 362 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 363 * The default is the current set of stable power features. 364 */ 365 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 366 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 367 368 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); 369 module_param_named(no_evict, amdgpu_no_evict, int, 0444); 370 371 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); 372 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); 373 374 /** 375 * DOC: pcie_gen_cap (uint) 376 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 377 * The default is 0 (automatic for each asic). 378 */ 379 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 380 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 381 382 /** 383 * DOC: pcie_lane_cap (uint) 384 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 385 * The default is 0 (automatic for each asic). 386 */ 387 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 388 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 389 390 /** 391 * DOC: cg_mask (uint) 392 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 393 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 394 */ 395 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 396 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 397 398 /** 399 * DOC: pg_mask (uint) 400 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 401 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 402 */ 403 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 404 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 405 406 /** 407 * DOC: sdma_phase_quantum (uint) 408 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 409 */ 410 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 411 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 412 413 /** 414 * DOC: disable_cu (charp) 415 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 416 */ 417 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 418 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 419 420 /** 421 * DOC: virtual_display (charp) 422 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 423 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 424 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 425 * device at 26:00.0. The default is NULL. 426 */ 427 MODULE_PARM_DESC(virtual_display, 428 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 429 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 430 431 /** 432 * DOC: ngg (int) 433 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 434 */ 435 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 436 module_param_named(ngg, amdgpu_ngg, int, 0444); 437 438 /** 439 * DOC: prim_buf_per_se (int) 440 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 441 */ 442 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 443 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 444 445 /** 446 * DOC: pos_buf_per_se (int) 447 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 448 */ 449 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 450 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 451 452 /** 453 * DOC: cntl_sb_buf_per_se (int) 454 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 455 */ 456 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 457 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 458 459 /** 460 * DOC: param_buf_per_se (int) 461 * Override the size of Off-Chip Pramater Cache per Shader Engine in Byte. The default is 0 (depending on gfx). 462 */ 463 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); 464 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 465 466 /** 467 * DOC: job_hang_limit (int) 468 * Set how much time allow a job hang and not drop it. The default is 0. 469 */ 470 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 471 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 472 473 /** 474 * DOC: lbpw (int) 475 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 476 */ 477 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 478 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 479 480 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 481 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 482 483 /** 484 * DOC: gpu_recovery (int) 485 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 486 */ 487 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 488 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 489 490 /** 491 * DOC: emu_mode (int) 492 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 493 */ 494 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 495 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 496 497 /** 498 * DOC: si_support (int) 499 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 500 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 501 * otherwise using amdgpu driver. 502 */ 503 #ifdef CONFIG_DRM_AMDGPU_SI 504 505 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 506 int amdgpu_si_support = 0; 507 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 508 #else 509 int amdgpu_si_support = 1; 510 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 511 #endif 512 513 module_param_named(si_support, amdgpu_si_support, int, 0444); 514 #endif 515 516 /** 517 * DOC: cik_support (int) 518 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 519 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 520 * otherwise using amdgpu driver. 521 */ 522 #ifdef CONFIG_DRM_AMDGPU_CIK 523 524 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 525 int amdgpu_cik_support = 0; 526 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 527 #else 528 int amdgpu_cik_support = 1; 529 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 530 #endif 531 532 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 533 #endif 534 535 /** 536 * DOC: smu_memory_pool_size (uint) 537 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 538 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 539 */ 540 MODULE_PARM_DESC(smu_memory_pool_size, 541 "reserve gtt for smu debug usage, 0 = disable," 542 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 543 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 544 545 static const struct pci_device_id pciidlist[] = { 546 #ifdef CONFIG_DRM_AMDGPU_SI 547 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 548 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 549 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 550 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 551 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 552 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 553 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 554 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 555 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 556 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 557 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 558 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 559 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 560 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 561 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 562 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 563 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 564 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 565 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 566 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 567 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 568 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 569 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 570 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 571 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 572 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 573 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 574 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 575 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 576 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 577 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 578 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 579 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 580 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 581 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 582 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 583 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 584 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 585 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 586 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 587 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 588 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 589 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 590 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 591 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 592 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 593 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 594 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 595 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 596 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 597 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 598 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 599 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 600 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 601 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 602 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 603 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 604 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 605 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 606 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 607 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 608 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 609 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 610 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 611 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 612 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 613 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 614 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 615 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 616 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 617 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 618 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 619 #endif 620 #ifdef CONFIG_DRM_AMDGPU_CIK 621 /* Kaveri */ 622 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 623 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 624 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 625 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 626 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 627 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 628 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 629 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 630 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 631 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 632 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 633 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 634 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 635 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 636 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 637 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 638 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 639 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 640 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 641 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 642 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 643 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 644 /* Bonaire */ 645 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 646 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 647 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 648 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 649 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 650 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 651 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 652 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 653 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 654 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 655 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 656 /* Hawaii */ 657 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 658 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 659 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 660 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 661 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 662 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 663 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 664 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 665 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 666 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 667 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 668 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 669 /* Kabini */ 670 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 671 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 672 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 673 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 674 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 675 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 676 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 677 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 678 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 679 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 680 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 681 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 682 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 683 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 684 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 685 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 686 /* mullins */ 687 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 688 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 689 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 690 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 691 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 692 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 693 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 694 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 695 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 696 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 697 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 698 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 699 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 700 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 701 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 702 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 703 #endif 704 /* topaz */ 705 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 706 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 707 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 708 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 709 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 710 /* tonga */ 711 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 712 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 713 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 714 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 715 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 716 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 717 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 718 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 719 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 720 /* fiji */ 721 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 722 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 723 /* carrizo */ 724 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 725 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 726 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 727 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 728 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 729 /* stoney */ 730 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 731 /* Polaris11 */ 732 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 733 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 734 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 735 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 736 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 737 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 738 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 739 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 740 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 741 /* Polaris10 */ 742 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 743 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 744 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 745 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 746 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 747 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 748 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 749 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 750 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 751 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 752 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 753 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 754 /* Polaris12 */ 755 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 756 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 757 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 758 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 759 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 760 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 761 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 762 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 763 /* VEGAM */ 764 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 765 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 766 /* Vega 10 */ 767 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 768 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 769 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 770 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 771 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 772 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 773 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 774 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 775 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 776 /* Vega 12 */ 777 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 778 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 779 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 780 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 781 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 782 /* Vega 20 */ 783 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 784 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 785 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 786 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 787 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 788 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT}, 789 /* Raven */ 790 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 791 792 {0, 0, 0} 793 }; 794 795 MODULE_DEVICE_TABLE(pci, pciidlist); 796 797 static struct drm_driver kms_driver; 798 799 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 800 { 801 struct apertures_struct *ap; 802 bool primary = false; 803 804 ap = alloc_apertures(1); 805 if (!ap) 806 return -ENOMEM; 807 808 ap->ranges[0].base = pci_resource_start(pdev, 0); 809 ap->ranges[0].size = pci_resource_len(pdev, 0); 810 811 #ifdef CONFIG_X86 812 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 813 #endif 814 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 815 kfree(ap); 816 817 return 0; 818 } 819 820 821 static int amdgpu_pci_probe(struct pci_dev *pdev, 822 const struct pci_device_id *ent) 823 { 824 struct drm_device *dev; 825 unsigned long flags = ent->driver_data; 826 int ret, retry = 0; 827 bool supports_atomic = false; 828 829 if (!amdgpu_virtual_display && 830 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 831 supports_atomic = true; 832 833 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 834 DRM_INFO("This hardware requires experimental hardware support.\n" 835 "See modparam exp_hw_support\n"); 836 return -ENODEV; 837 } 838 839 /* 840 * Initialize amdkfd before starting radeon. If it was not loaded yet, 841 * defer radeon probing 842 */ 843 ret = amdgpu_amdkfd_init(); 844 if (ret == -EPROBE_DEFER) 845 return ret; 846 847 /* Get rid of things like offb */ 848 ret = amdgpu_kick_out_firmware_fb(pdev); 849 if (ret) 850 return ret; 851 852 /* warn the user if they mix atomic and non-atomic capable GPUs */ 853 if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) 854 DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); 855 /* support atomic early so the atomic debugfs stuff gets created */ 856 if (supports_atomic) 857 kms_driver.driver_features |= DRIVER_ATOMIC; 858 859 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 860 if (IS_ERR(dev)) 861 return PTR_ERR(dev); 862 863 ret = pci_enable_device(pdev); 864 if (ret) 865 goto err_free; 866 867 dev->pdev = pdev; 868 869 pci_set_drvdata(pdev, dev); 870 871 retry_init: 872 ret = drm_dev_register(dev, ent->driver_data); 873 if (ret == -EAGAIN && ++retry <= 3) { 874 DRM_INFO("retry init %d\n", retry); 875 /* Don't request EX mode too frequently which is attacking */ 876 msleep(5000); 877 goto retry_init; 878 } else if (ret) 879 goto err_pci; 880 881 return 0; 882 883 err_pci: 884 pci_disable_device(pdev); 885 err_free: 886 drm_dev_put(dev); 887 return ret; 888 } 889 890 static void 891 amdgpu_pci_remove(struct pci_dev *pdev) 892 { 893 struct drm_device *dev = pci_get_drvdata(pdev); 894 895 drm_dev_unregister(dev); 896 drm_dev_put(dev); 897 pci_disable_device(pdev); 898 pci_set_drvdata(pdev, NULL); 899 } 900 901 static void 902 amdgpu_pci_shutdown(struct pci_dev *pdev) 903 { 904 struct drm_device *dev = pci_get_drvdata(pdev); 905 struct amdgpu_device *adev = dev->dev_private; 906 907 /* if we are running in a VM, make sure the device 908 * torn down properly on reboot/shutdown. 909 * unfortunately we can't detect certain 910 * hypervisors so just do this all the time. 911 */ 912 amdgpu_device_ip_suspend(adev); 913 } 914 915 static int amdgpu_pmops_suspend(struct device *dev) 916 { 917 struct pci_dev *pdev = to_pci_dev(dev); 918 919 struct drm_device *drm_dev = pci_get_drvdata(pdev); 920 return amdgpu_device_suspend(drm_dev, true, true); 921 } 922 923 static int amdgpu_pmops_resume(struct device *dev) 924 { 925 struct pci_dev *pdev = to_pci_dev(dev); 926 struct drm_device *drm_dev = pci_get_drvdata(pdev); 927 928 /* GPU comes up enabled by the bios on resume */ 929 if (amdgpu_device_is_px(drm_dev)) { 930 pm_runtime_disable(dev); 931 pm_runtime_set_active(dev); 932 pm_runtime_enable(dev); 933 } 934 935 return amdgpu_device_resume(drm_dev, true, true); 936 } 937 938 static int amdgpu_pmops_freeze(struct device *dev) 939 { 940 struct pci_dev *pdev = to_pci_dev(dev); 941 942 struct drm_device *drm_dev = pci_get_drvdata(pdev); 943 return amdgpu_device_suspend(drm_dev, false, true); 944 } 945 946 static int amdgpu_pmops_thaw(struct device *dev) 947 { 948 struct pci_dev *pdev = to_pci_dev(dev); 949 950 struct drm_device *drm_dev = pci_get_drvdata(pdev); 951 return amdgpu_device_resume(drm_dev, false, true); 952 } 953 954 static int amdgpu_pmops_poweroff(struct device *dev) 955 { 956 struct pci_dev *pdev = to_pci_dev(dev); 957 958 struct drm_device *drm_dev = pci_get_drvdata(pdev); 959 return amdgpu_device_suspend(drm_dev, true, true); 960 } 961 962 static int amdgpu_pmops_restore(struct device *dev) 963 { 964 struct pci_dev *pdev = to_pci_dev(dev); 965 966 struct drm_device *drm_dev = pci_get_drvdata(pdev); 967 return amdgpu_device_resume(drm_dev, false, true); 968 } 969 970 static int amdgpu_pmops_runtime_suspend(struct device *dev) 971 { 972 struct pci_dev *pdev = to_pci_dev(dev); 973 struct drm_device *drm_dev = pci_get_drvdata(pdev); 974 int ret; 975 976 if (!amdgpu_device_is_px(drm_dev)) { 977 pm_runtime_forbid(dev); 978 return -EBUSY; 979 } 980 981 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 982 drm_kms_helper_poll_disable(drm_dev); 983 984 ret = amdgpu_device_suspend(drm_dev, false, false); 985 pci_save_state(pdev); 986 pci_disable_device(pdev); 987 pci_ignore_hotplug(pdev); 988 if (amdgpu_is_atpx_hybrid()) 989 pci_set_power_state(pdev, PCI_D3cold); 990 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 991 pci_set_power_state(pdev, PCI_D3hot); 992 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 993 994 return 0; 995 } 996 997 static int amdgpu_pmops_runtime_resume(struct device *dev) 998 { 999 struct pci_dev *pdev = to_pci_dev(dev); 1000 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1001 int ret; 1002 1003 if (!amdgpu_device_is_px(drm_dev)) 1004 return -EINVAL; 1005 1006 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1007 1008 if (amdgpu_is_atpx_hybrid() || 1009 !amdgpu_has_atpx_dgpu_power_cntl()) 1010 pci_set_power_state(pdev, PCI_D0); 1011 pci_restore_state(pdev); 1012 ret = pci_enable_device(pdev); 1013 if (ret) 1014 return ret; 1015 pci_set_master(pdev); 1016 1017 ret = amdgpu_device_resume(drm_dev, false, false); 1018 drm_kms_helper_poll_enable(drm_dev); 1019 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1020 return 0; 1021 } 1022 1023 static int amdgpu_pmops_runtime_idle(struct device *dev) 1024 { 1025 struct pci_dev *pdev = to_pci_dev(dev); 1026 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1027 struct drm_crtc *crtc; 1028 1029 if (!amdgpu_device_is_px(drm_dev)) { 1030 pm_runtime_forbid(dev); 1031 return -EBUSY; 1032 } 1033 1034 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1035 if (crtc->enabled) { 1036 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1037 return -EBUSY; 1038 } 1039 } 1040 1041 pm_runtime_mark_last_busy(dev); 1042 pm_runtime_autosuspend(dev); 1043 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1044 return 1; 1045 } 1046 1047 long amdgpu_drm_ioctl(struct file *filp, 1048 unsigned int cmd, unsigned long arg) 1049 { 1050 struct drm_file *file_priv = filp->private_data; 1051 struct drm_device *dev; 1052 long ret; 1053 dev = file_priv->minor->dev; 1054 ret = pm_runtime_get_sync(dev->dev); 1055 if (ret < 0) 1056 return ret; 1057 1058 ret = drm_ioctl(filp, cmd, arg); 1059 1060 pm_runtime_mark_last_busy(dev->dev); 1061 pm_runtime_put_autosuspend(dev->dev); 1062 return ret; 1063 } 1064 1065 static const struct dev_pm_ops amdgpu_pm_ops = { 1066 .suspend = amdgpu_pmops_suspend, 1067 .resume = amdgpu_pmops_resume, 1068 .freeze = amdgpu_pmops_freeze, 1069 .thaw = amdgpu_pmops_thaw, 1070 .poweroff = amdgpu_pmops_poweroff, 1071 .restore = amdgpu_pmops_restore, 1072 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1073 .runtime_resume = amdgpu_pmops_runtime_resume, 1074 .runtime_idle = amdgpu_pmops_runtime_idle, 1075 }; 1076 1077 static int amdgpu_flush(struct file *f, fl_owner_t id) 1078 { 1079 struct drm_file *file_priv = f->private_data; 1080 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1081 1082 amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr); 1083 1084 return 0; 1085 } 1086 1087 1088 static const struct file_operations amdgpu_driver_kms_fops = { 1089 .owner = THIS_MODULE, 1090 .open = drm_open, 1091 .flush = amdgpu_flush, 1092 .release = drm_release, 1093 .unlocked_ioctl = amdgpu_drm_ioctl, 1094 .mmap = amdgpu_mmap, 1095 .poll = drm_poll, 1096 .read = drm_read, 1097 #ifdef CONFIG_COMPAT 1098 .compat_ioctl = amdgpu_kms_compat_ioctl, 1099 #endif 1100 }; 1101 1102 static bool 1103 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1104 bool in_vblank_irq, int *vpos, int *hpos, 1105 ktime_t *stime, ktime_t *etime, 1106 const struct drm_display_mode *mode) 1107 { 1108 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1109 stime, etime, mode); 1110 } 1111 1112 static struct drm_driver kms_driver = { 1113 .driver_features = 1114 DRIVER_USE_AGP | 1115 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 1116 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1117 .load = amdgpu_driver_load_kms, 1118 .open = amdgpu_driver_open_kms, 1119 .postclose = amdgpu_driver_postclose_kms, 1120 .lastclose = amdgpu_driver_lastclose_kms, 1121 .unload = amdgpu_driver_unload_kms, 1122 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1123 .enable_vblank = amdgpu_enable_vblank_kms, 1124 .disable_vblank = amdgpu_disable_vblank_kms, 1125 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1126 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1127 .irq_handler = amdgpu_irq_handler, 1128 .ioctls = amdgpu_ioctls_kms, 1129 .gem_free_object_unlocked = amdgpu_gem_object_free, 1130 .gem_open_object = amdgpu_gem_object_open, 1131 .gem_close_object = amdgpu_gem_object_close, 1132 .dumb_create = amdgpu_mode_dumb_create, 1133 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1134 .fops = &amdgpu_driver_kms_fops, 1135 1136 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1137 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1138 .gem_prime_export = amdgpu_gem_prime_export, 1139 .gem_prime_import = amdgpu_gem_prime_import, 1140 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1141 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1142 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1143 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1144 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1145 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1146 1147 .name = DRIVER_NAME, 1148 .desc = DRIVER_DESC, 1149 .date = DRIVER_DATE, 1150 .major = KMS_DRIVER_MAJOR, 1151 .minor = KMS_DRIVER_MINOR, 1152 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1153 }; 1154 1155 static struct drm_driver *driver; 1156 static struct pci_driver *pdriver; 1157 1158 static struct pci_driver amdgpu_kms_pci_driver = { 1159 .name = DRIVER_NAME, 1160 .id_table = pciidlist, 1161 .probe = amdgpu_pci_probe, 1162 .remove = amdgpu_pci_remove, 1163 .shutdown = amdgpu_pci_shutdown, 1164 .driver.pm = &amdgpu_pm_ops, 1165 }; 1166 1167 1168 1169 static int __init amdgpu_init(void) 1170 { 1171 int r; 1172 1173 if (vgacon_text_force()) { 1174 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1175 return -EINVAL; 1176 } 1177 1178 r = amdgpu_sync_init(); 1179 if (r) 1180 goto error_sync; 1181 1182 r = amdgpu_fence_slab_init(); 1183 if (r) 1184 goto error_fence; 1185 1186 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1187 driver = &kms_driver; 1188 pdriver = &amdgpu_kms_pci_driver; 1189 driver->num_ioctls = amdgpu_max_kms_ioctl; 1190 amdgpu_register_atpx_handler(); 1191 /* let modprobe override vga console setting */ 1192 return pci_register_driver(pdriver); 1193 1194 error_fence: 1195 amdgpu_sync_fini(); 1196 1197 error_sync: 1198 return r; 1199 } 1200 1201 static void __exit amdgpu_exit(void) 1202 { 1203 amdgpu_amdkfd_fini(); 1204 pci_unregister_driver(pdriver); 1205 amdgpu_unregister_atpx_handler(); 1206 amdgpu_sync_fini(); 1207 amdgpu_fence_slab_fini(); 1208 } 1209 1210 module_init(amdgpu_init); 1211 module_exit(amdgpu_exit); 1212 1213 MODULE_AUTHOR(DRIVER_AUTHOR); 1214 MODULE_DESCRIPTION(DRIVER_DESC); 1215 MODULE_LICENSE("GPL and additional rights"); 1216