1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include "amdgpu_drv.h" 30 31 #include <drm/drm_pciids.h> 32 #include <linux/console.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "amdgpu.h" 40 #include "amdgpu_irq.h" 41 #include "amdgpu_dma_buf.h" 42 43 #include "amdgpu_amdkfd.h" 44 45 /* 46 * KMS wrapper. 47 * - 3.0.0 - initial driver 48 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 49 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 50 * at the end of IBs. 51 * - 3.3.0 - Add VM support for UVD on supported hardware. 52 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 53 * - 3.5.0 - Add support for new UVD_NO_OP register. 54 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 55 * - 3.7.0 - Add support for VCE clock list packet 56 * - 3.8.0 - Add support raster config init in the kernel 57 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 58 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 59 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 60 * - 3.12.0 - Add query for double offchip LDS buffers 61 * - 3.13.0 - Add PRT support 62 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 63 * - 3.15.0 - Export more gpu info for gfx9 64 * - 3.16.0 - Add reserved vmid support 65 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 66 * - 3.18.0 - Export gpu always on cu bitmap 67 * - 3.19.0 - Add support for UVD MJPEG decode 68 * - 3.20.0 - Add support for local BOs 69 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 70 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 71 * - 3.23.0 - Add query for VRAM lost counter 72 * - 3.24.0 - Add high priority compute support for gfx9 73 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 74 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 75 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 76 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 77 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 78 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 79 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 80 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 81 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 82 */ 83 #define KMS_DRIVER_MAJOR 3 84 #define KMS_DRIVER_MINOR 33 85 #define KMS_DRIVER_PATCHLEVEL 0 86 87 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 88 89 int amdgpu_vram_limit = 0; 90 int amdgpu_vis_vram_limit = 0; 91 int amdgpu_gart_size = -1; /* auto */ 92 int amdgpu_gtt_size = -1; /* auto */ 93 int amdgpu_moverate = -1; /* auto */ 94 int amdgpu_benchmarking = 0; 95 int amdgpu_testing = 0; 96 int amdgpu_audio = -1; 97 int amdgpu_disp_priority = 0; 98 int amdgpu_hw_i2c = 0; 99 int amdgpu_pcie_gen2 = -1; 100 int amdgpu_msi = -1; 101 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 102 int amdgpu_dpm = -1; 103 int amdgpu_fw_load_type = -1; 104 int amdgpu_aspm = -1; 105 int amdgpu_runtime_pm = -1; 106 uint amdgpu_ip_block_mask = 0xffffffff; 107 int amdgpu_bapm = -1; 108 int amdgpu_deep_color = 0; 109 int amdgpu_vm_size = -1; 110 int amdgpu_vm_fragment_size = -1; 111 int amdgpu_vm_block_size = -1; 112 int amdgpu_vm_fault_stop = 0; 113 int amdgpu_vm_debug = 0; 114 int amdgpu_vm_update_mode = -1; 115 int amdgpu_exp_hw_support = 0; 116 int amdgpu_dc = -1; 117 int amdgpu_sched_jobs = 32; 118 int amdgpu_sched_hw_submission = 2; 119 uint amdgpu_pcie_gen_cap = 0; 120 uint amdgpu_pcie_lane_cap = 0; 121 uint amdgpu_cg_mask = 0xffffffff; 122 uint amdgpu_pg_mask = 0xffffffff; 123 uint amdgpu_sdma_phase_quantum = 32; 124 char *amdgpu_disable_cu = NULL; 125 char *amdgpu_virtual_display = NULL; 126 /* OverDrive(bit 14) disabled by default*/ 127 uint amdgpu_pp_feature_mask = 0xffffbfff; 128 int amdgpu_ngg = 0; 129 int amdgpu_prim_buf_per_se = 0; 130 int amdgpu_pos_buf_per_se = 0; 131 int amdgpu_cntl_sb_buf_per_se = 0; 132 int amdgpu_param_buf_per_se = 0; 133 int amdgpu_job_hang_limit = 0; 134 int amdgpu_lbpw = -1; 135 int amdgpu_compute_multipipe = -1; 136 int amdgpu_gpu_recovery = -1; /* auto */ 137 int amdgpu_emu_mode = 0; 138 uint amdgpu_smu_memory_pool_size = 0; 139 /* FBC (bit 0) disabled by default*/ 140 uint amdgpu_dc_feature_mask = 0; 141 int amdgpu_async_gfx_ring = 1; 142 int amdgpu_mcbp = 0; 143 int amdgpu_discovery = -1; 144 int amdgpu_mes = 0; 145 int amdgpu_noretry; 146 147 struct amdgpu_mgpu_info mgpu_info = { 148 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 149 }; 150 int amdgpu_ras_enable = -1; 151 uint amdgpu_ras_mask = 0xffffffff; 152 153 /** 154 * DOC: vramlimit (int) 155 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 156 */ 157 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 158 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 159 160 /** 161 * DOC: vis_vramlimit (int) 162 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 163 */ 164 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 165 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 166 167 /** 168 * DOC: gartsize (uint) 169 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 170 */ 171 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 172 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 173 174 /** 175 * DOC: gttsize (int) 176 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 177 * otherwise 3/4 RAM size). 178 */ 179 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 180 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 181 182 /** 183 * DOC: moverate (int) 184 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 185 */ 186 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 187 module_param_named(moverate, amdgpu_moverate, int, 0600); 188 189 /** 190 * DOC: benchmark (int) 191 * Run benchmarks. The default is 0 (Skip benchmarks). 192 */ 193 MODULE_PARM_DESC(benchmark, "Run benchmark"); 194 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 195 196 /** 197 * DOC: test (int) 198 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 199 */ 200 MODULE_PARM_DESC(test, "Run tests"); 201 module_param_named(test, amdgpu_testing, int, 0444); 202 203 /** 204 * DOC: audio (int) 205 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 206 */ 207 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 208 module_param_named(audio, amdgpu_audio, int, 0444); 209 210 /** 211 * DOC: disp_priority (int) 212 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 213 */ 214 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 215 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 216 217 /** 218 * DOC: hw_i2c (int) 219 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 220 */ 221 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 222 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 223 224 /** 225 * DOC: pcie_gen2 (int) 226 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 227 */ 228 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 229 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 230 231 /** 232 * DOC: msi (int) 233 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 234 */ 235 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 236 module_param_named(msi, amdgpu_msi, int, 0444); 237 238 /** 239 * DOC: lockup_timeout (string) 240 * Set GPU scheduler timeout value in ms. 241 * 242 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 243 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 244 * to default timeout. 245 * - With one value specified, the setting will apply to all non-compute jobs. 246 * - With multiple values specified, the first one will be for GFX. The second one is for Compute. 247 * And the third and fourth ones are for SDMA and Video. 248 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 249 * jobs is 10000. And there is no timeout enforced on compute jobs. 250 */ 251 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs." 252 " 0: keep default value. negative: infinity timeout), " 253 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); 254 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 255 256 /** 257 * DOC: dpm (int) 258 * Override for dynamic power management setting 259 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 260 * The default is -1 (auto). 261 */ 262 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 263 module_param_named(dpm, amdgpu_dpm, int, 0444); 264 265 /** 266 * DOC: fw_load_type (int) 267 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 268 */ 269 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 270 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 271 272 /** 273 * DOC: aspm (int) 274 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 275 */ 276 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 277 module_param_named(aspm, amdgpu_aspm, int, 0444); 278 279 /** 280 * DOC: runpm (int) 281 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 282 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 283 */ 284 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 285 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 286 287 /** 288 * DOC: ip_block_mask (uint) 289 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 290 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 291 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 292 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 293 */ 294 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 295 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 296 297 /** 298 * DOC: bapm (int) 299 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 300 * The default -1 (auto, enabled) 301 */ 302 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 303 module_param_named(bapm, amdgpu_bapm, int, 0444); 304 305 /** 306 * DOC: deep_color (int) 307 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 308 */ 309 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 310 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 311 312 /** 313 * DOC: vm_size (int) 314 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 315 */ 316 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 317 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 318 319 /** 320 * DOC: vm_fragment_size (int) 321 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 322 */ 323 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 324 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 325 326 /** 327 * DOC: vm_block_size (int) 328 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 329 */ 330 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 331 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 332 333 /** 334 * DOC: vm_fault_stop (int) 335 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 336 */ 337 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 338 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 339 340 /** 341 * DOC: vm_debug (int) 342 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 343 */ 344 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 345 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 346 347 /** 348 * DOC: vm_update_mode (int) 349 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 350 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 351 */ 352 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 353 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 354 355 /** 356 * DOC: exp_hw_support (int) 357 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 358 */ 359 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 360 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 361 362 /** 363 * DOC: dc (int) 364 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 365 */ 366 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 367 module_param_named(dc, amdgpu_dc, int, 0444); 368 369 /** 370 * DOC: sched_jobs (int) 371 * Override the max number of jobs supported in the sw queue. The default is 32. 372 */ 373 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 374 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 375 376 /** 377 * DOC: sched_hw_submission (int) 378 * Override the max number of HW submissions. The default is 2. 379 */ 380 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 381 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 382 383 /** 384 * DOC: ppfeaturemask (uint) 385 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 386 * The default is the current set of stable power features. 387 */ 388 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 389 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 390 391 /** 392 * DOC: pcie_gen_cap (uint) 393 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 394 * The default is 0 (automatic for each asic). 395 */ 396 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 397 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 398 399 /** 400 * DOC: pcie_lane_cap (uint) 401 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 402 * The default is 0 (automatic for each asic). 403 */ 404 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 405 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 406 407 /** 408 * DOC: cg_mask (uint) 409 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 410 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 411 */ 412 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 413 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 414 415 /** 416 * DOC: pg_mask (uint) 417 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 418 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 419 */ 420 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 421 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 422 423 /** 424 * DOC: sdma_phase_quantum (uint) 425 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 426 */ 427 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 428 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 429 430 /** 431 * DOC: disable_cu (charp) 432 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 433 */ 434 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 435 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 436 437 /** 438 * DOC: virtual_display (charp) 439 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 440 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 441 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 442 * device at 26:00.0. The default is NULL. 443 */ 444 MODULE_PARM_DESC(virtual_display, 445 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 446 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 447 448 /** 449 * DOC: ngg (int) 450 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 451 */ 452 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 453 module_param_named(ngg, amdgpu_ngg, int, 0444); 454 455 /** 456 * DOC: prim_buf_per_se (int) 457 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 458 */ 459 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 460 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 461 462 /** 463 * DOC: pos_buf_per_se (int) 464 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 465 */ 466 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 467 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 468 469 /** 470 * DOC: cntl_sb_buf_per_se (int) 471 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 472 */ 473 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 474 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 475 476 /** 477 * DOC: param_buf_per_se (int) 478 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 479 * The default is 0 (depending on gfx). 480 */ 481 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 482 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 483 484 /** 485 * DOC: job_hang_limit (int) 486 * Set how much time allow a job hang and not drop it. The default is 0. 487 */ 488 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 489 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 490 491 /** 492 * DOC: lbpw (int) 493 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 494 */ 495 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 496 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 497 498 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 499 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 500 501 /** 502 * DOC: gpu_recovery (int) 503 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 504 */ 505 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 506 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 507 508 /** 509 * DOC: emu_mode (int) 510 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 511 */ 512 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 513 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 514 515 /** 516 * DOC: ras_enable (int) 517 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 518 */ 519 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 520 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 521 522 /** 523 * DOC: ras_mask (uint) 524 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 525 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 526 */ 527 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 528 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 529 530 /** 531 * DOC: si_support (int) 532 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 533 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 534 * otherwise using amdgpu driver. 535 */ 536 #ifdef CONFIG_DRM_AMDGPU_SI 537 538 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 539 int amdgpu_si_support = 0; 540 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 541 #else 542 int amdgpu_si_support = 1; 543 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 544 #endif 545 546 module_param_named(si_support, amdgpu_si_support, int, 0444); 547 #endif 548 549 /** 550 * DOC: cik_support (int) 551 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 552 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 553 * otherwise using amdgpu driver. 554 */ 555 #ifdef CONFIG_DRM_AMDGPU_CIK 556 557 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 558 int amdgpu_cik_support = 0; 559 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 560 #else 561 int amdgpu_cik_support = 1; 562 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 563 #endif 564 565 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 566 #endif 567 568 /** 569 * DOC: smu_memory_pool_size (uint) 570 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 571 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 572 */ 573 MODULE_PARM_DESC(smu_memory_pool_size, 574 "reserve gtt for smu debug usage, 0 = disable," 575 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 576 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 577 578 /** 579 * DOC: async_gfx_ring (int) 580 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 581 */ 582 MODULE_PARM_DESC(async_gfx_ring, 583 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 584 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 585 586 /** 587 * DOC: mcbp (int) 588 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 589 */ 590 MODULE_PARM_DESC(mcbp, 591 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 592 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 593 594 /** 595 * DOC: discovery (int) 596 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 597 * (-1 = auto (default), 0 = disabled, 1 = enabled) 598 */ 599 MODULE_PARM_DESC(discovery, 600 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 601 module_param_named(discovery, amdgpu_discovery, int, 0444); 602 603 /** 604 * DOC: mes (int) 605 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 606 * (0 = disabled (default), 1 = enabled) 607 */ 608 MODULE_PARM_DESC(mes, 609 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 610 module_param_named(mes, amdgpu_mes, int, 0444); 611 612 MODULE_PARM_DESC(noretry, 613 "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); 614 module_param_named(noretry, amdgpu_noretry, int, 0644); 615 616 #ifdef CONFIG_HSA_AMD 617 /** 618 * DOC: sched_policy (int) 619 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 620 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 621 * assigns queues to HQDs. 622 */ 623 int sched_policy = KFD_SCHED_POLICY_HWS; 624 module_param(sched_policy, int, 0444); 625 MODULE_PARM_DESC(sched_policy, 626 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 627 628 /** 629 * DOC: hws_max_conc_proc (int) 630 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 631 * number of VMIDs assigned to the HWS, which is also the default. 632 */ 633 int hws_max_conc_proc = 8; 634 module_param(hws_max_conc_proc, int, 0444); 635 MODULE_PARM_DESC(hws_max_conc_proc, 636 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 637 638 /** 639 * DOC: cwsr_enable (int) 640 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 641 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 642 * disables it. 643 */ 644 int cwsr_enable = 1; 645 module_param(cwsr_enable, int, 0444); 646 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 647 648 /** 649 * DOC: max_num_of_queues_per_device (int) 650 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 651 * is 4096. 652 */ 653 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 654 module_param(max_num_of_queues_per_device, int, 0444); 655 MODULE_PARM_DESC(max_num_of_queues_per_device, 656 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 657 658 /** 659 * DOC: send_sigterm (int) 660 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 661 * but just print errors on dmesg. Setting 1 enables sending sigterm. 662 */ 663 int send_sigterm; 664 module_param(send_sigterm, int, 0444); 665 MODULE_PARM_DESC(send_sigterm, 666 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 667 668 /** 669 * DOC: debug_largebar (int) 670 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 671 * system. This limits the VRAM size reported to ROCm applications to the visible 672 * size, usually 256MB. 673 * Default value is 0, diabled. 674 */ 675 int debug_largebar; 676 module_param(debug_largebar, int, 0444); 677 MODULE_PARM_DESC(debug_largebar, 678 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 679 680 /** 681 * DOC: ignore_crat (int) 682 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 683 * table to get information about AMD APUs. This option can serve as a workaround on 684 * systems with a broken CRAT table. 685 */ 686 int ignore_crat; 687 module_param(ignore_crat, int, 0444); 688 MODULE_PARM_DESC(ignore_crat, 689 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 690 691 /** 692 * DOC: halt_if_hws_hang (int) 693 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 694 * Setting 1 enables halt on hang. 695 */ 696 int halt_if_hws_hang; 697 module_param(halt_if_hws_hang, int, 0644); 698 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 699 700 /** 701 * DOC: hws_gws_support(bool) 702 * Whether HWS support gws barriers. Default value: false (not supported) 703 * This will be replaced with a MEC firmware version check once firmware 704 * is ready 705 */ 706 bool hws_gws_support; 707 module_param(hws_gws_support, bool, 0444); 708 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 709 710 /** 711 * DOC: queue_preemption_timeout_ms (int) 712 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 713 */ 714 int queue_preemption_timeout_ms = 9000; 715 module_param(queue_preemption_timeout_ms, int, 0644); 716 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 717 #endif 718 719 /** 720 * DOC: dcfeaturemask (uint) 721 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 722 * The default is the current set of stable display features. 723 */ 724 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 725 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 726 727 /** 728 * DOC: abmlevel (uint) 729 * Override the default ABM (Adaptive Backlight Management) level used for DC 730 * enabled hardware. Requires DMCU to be supported and loaded. 731 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 732 * default. Values 1-4 control the maximum allowable brightness reduction via 733 * the ABM algorithm, with 1 being the least reduction and 4 being the most 734 * reduction. 735 * 736 * Defaults to 0, or disabled. Userspace can still override this level later 737 * after boot. 738 */ 739 uint amdgpu_dm_abm_level = 0; 740 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 741 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 742 743 static const struct pci_device_id pciidlist[] = { 744 #ifdef CONFIG_DRM_AMDGPU_SI 745 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 746 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 747 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 748 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 749 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 750 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 751 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 752 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 753 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 754 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 755 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 756 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 757 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 758 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 759 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 760 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 761 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 762 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 763 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 764 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 765 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 766 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 767 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 768 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 769 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 770 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 771 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 772 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 773 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 774 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 775 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 776 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 777 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 778 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 779 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 780 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 781 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 782 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 783 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 784 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 785 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 786 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 787 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 788 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 789 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 790 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 791 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 792 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 793 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 794 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 795 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 796 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 797 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 798 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 799 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 800 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 801 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 802 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 803 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 804 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 805 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 806 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 807 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 808 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 809 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 810 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 811 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 812 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 813 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 814 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 815 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 816 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 817 #endif 818 #ifdef CONFIG_DRM_AMDGPU_CIK 819 /* Kaveri */ 820 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 821 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 822 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 823 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 824 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 825 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 826 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 827 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 828 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 829 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 830 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 831 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 832 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 833 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 834 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 835 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 836 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 837 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 838 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 839 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 840 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 841 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 842 /* Bonaire */ 843 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 844 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 845 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 846 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 847 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 848 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 849 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 850 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 851 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 852 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 853 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 854 /* Hawaii */ 855 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 856 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 857 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 858 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 859 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 860 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 861 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 862 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 863 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 864 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 865 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 866 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 867 /* Kabini */ 868 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 869 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 870 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 871 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 872 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 873 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 874 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 875 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 876 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 877 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 878 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 879 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 880 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 881 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 882 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 883 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 884 /* mullins */ 885 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 888 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 889 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 890 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 891 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 892 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 893 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 894 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 895 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 896 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 897 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 898 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 899 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 900 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 901 #endif 902 /* topaz */ 903 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 904 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 905 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 906 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 907 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 908 /* tonga */ 909 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 910 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 911 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 912 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 913 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 914 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 915 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 916 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 917 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 918 /* fiji */ 919 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 920 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 921 /* carrizo */ 922 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 923 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 924 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 925 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 926 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 927 /* stoney */ 928 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 929 /* Polaris11 */ 930 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 931 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 932 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 933 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 934 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 935 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 936 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 937 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 938 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 939 /* Polaris10 */ 940 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 941 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 942 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 943 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 944 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 945 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 946 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 947 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 948 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 949 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 950 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 951 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 952 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 953 /* Polaris12 */ 954 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 955 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 956 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 957 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 958 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 959 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 960 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 961 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 962 /* VEGAM */ 963 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 964 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 965 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 966 /* Vega 10 */ 967 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 968 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 969 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 970 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 971 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 972 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 973 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 974 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 975 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 976 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 977 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 978 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 979 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 980 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 981 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 982 /* Vega 12 */ 983 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 984 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 985 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 986 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 987 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 988 /* Vega 20 */ 989 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 990 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 991 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 992 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 993 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 994 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 995 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 996 /* Raven */ 997 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 998 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 999 /* Navi10 */ 1000 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1001 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1002 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1003 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1004 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1005 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1006 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1007 1008 {0, 0, 0} 1009 }; 1010 1011 MODULE_DEVICE_TABLE(pci, pciidlist); 1012 1013 static struct drm_driver kms_driver; 1014 1015 static int amdgpu_pci_probe(struct pci_dev *pdev, 1016 const struct pci_device_id *ent) 1017 { 1018 struct drm_device *dev; 1019 unsigned long flags = ent->driver_data; 1020 int ret, retry = 0; 1021 bool supports_atomic = false; 1022 1023 if (!amdgpu_virtual_display && 1024 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1025 supports_atomic = true; 1026 1027 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1028 DRM_INFO("This hardware requires experimental hardware support.\n" 1029 "See modparam exp_hw_support\n"); 1030 return -ENODEV; 1031 } 1032 1033 /* Get rid of things like offb */ 1034 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 1035 if (ret) 1036 return ret; 1037 1038 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1039 if (IS_ERR(dev)) 1040 return PTR_ERR(dev); 1041 1042 if (!supports_atomic) 1043 dev->driver_features &= ~DRIVER_ATOMIC; 1044 1045 ret = pci_enable_device(pdev); 1046 if (ret) 1047 goto err_free; 1048 1049 dev->pdev = pdev; 1050 1051 pci_set_drvdata(pdev, dev); 1052 1053 retry_init: 1054 ret = drm_dev_register(dev, ent->driver_data); 1055 if (ret == -EAGAIN && ++retry <= 3) { 1056 DRM_INFO("retry init %d\n", retry); 1057 /* Don't request EX mode too frequently which is attacking */ 1058 msleep(5000); 1059 goto retry_init; 1060 } else if (ret) 1061 goto err_pci; 1062 1063 return 0; 1064 1065 err_pci: 1066 pci_disable_device(pdev); 1067 err_free: 1068 drm_dev_put(dev); 1069 return ret; 1070 } 1071 1072 static void 1073 amdgpu_pci_remove(struct pci_dev *pdev) 1074 { 1075 struct drm_device *dev = pci_get_drvdata(pdev); 1076 1077 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 1078 drm_dev_unplug(dev); 1079 drm_dev_put(dev); 1080 pci_disable_device(pdev); 1081 pci_set_drvdata(pdev, NULL); 1082 } 1083 1084 static void 1085 amdgpu_pci_shutdown(struct pci_dev *pdev) 1086 { 1087 struct drm_device *dev = pci_get_drvdata(pdev); 1088 struct amdgpu_device *adev = dev->dev_private; 1089 1090 /* if we are running in a VM, make sure the device 1091 * torn down properly on reboot/shutdown. 1092 * unfortunately we can't detect certain 1093 * hypervisors so just do this all the time. 1094 */ 1095 amdgpu_device_ip_suspend(adev); 1096 } 1097 1098 static int amdgpu_pmops_suspend(struct device *dev) 1099 { 1100 struct pci_dev *pdev = to_pci_dev(dev); 1101 1102 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1103 return amdgpu_device_suspend(drm_dev, true, true); 1104 } 1105 1106 static int amdgpu_pmops_resume(struct device *dev) 1107 { 1108 struct pci_dev *pdev = to_pci_dev(dev); 1109 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1110 1111 /* GPU comes up enabled by the bios on resume */ 1112 if (amdgpu_device_is_px(drm_dev)) { 1113 pm_runtime_disable(dev); 1114 pm_runtime_set_active(dev); 1115 pm_runtime_enable(dev); 1116 } 1117 1118 return amdgpu_device_resume(drm_dev, true, true); 1119 } 1120 1121 static int amdgpu_pmops_freeze(struct device *dev) 1122 { 1123 struct pci_dev *pdev = to_pci_dev(dev); 1124 1125 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1126 return amdgpu_device_suspend(drm_dev, false, true); 1127 } 1128 1129 static int amdgpu_pmops_thaw(struct device *dev) 1130 { 1131 struct pci_dev *pdev = to_pci_dev(dev); 1132 1133 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1134 return amdgpu_device_resume(drm_dev, false, true); 1135 } 1136 1137 static int amdgpu_pmops_poweroff(struct device *dev) 1138 { 1139 struct pci_dev *pdev = to_pci_dev(dev); 1140 1141 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1142 return amdgpu_device_suspend(drm_dev, true, true); 1143 } 1144 1145 static int amdgpu_pmops_restore(struct device *dev) 1146 { 1147 struct pci_dev *pdev = to_pci_dev(dev); 1148 1149 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1150 return amdgpu_device_resume(drm_dev, false, true); 1151 } 1152 1153 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1154 { 1155 struct pci_dev *pdev = to_pci_dev(dev); 1156 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1157 int ret; 1158 1159 if (!amdgpu_device_is_px(drm_dev)) { 1160 pm_runtime_forbid(dev); 1161 return -EBUSY; 1162 } 1163 1164 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1165 drm_kms_helper_poll_disable(drm_dev); 1166 1167 ret = amdgpu_device_suspend(drm_dev, false, false); 1168 pci_save_state(pdev); 1169 pci_disable_device(pdev); 1170 pci_ignore_hotplug(pdev); 1171 if (amdgpu_is_atpx_hybrid()) 1172 pci_set_power_state(pdev, PCI_D3cold); 1173 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1174 pci_set_power_state(pdev, PCI_D3hot); 1175 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1176 1177 return 0; 1178 } 1179 1180 static int amdgpu_pmops_runtime_resume(struct device *dev) 1181 { 1182 struct pci_dev *pdev = to_pci_dev(dev); 1183 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1184 int ret; 1185 1186 if (!amdgpu_device_is_px(drm_dev)) 1187 return -EINVAL; 1188 1189 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1190 1191 if (amdgpu_is_atpx_hybrid() || 1192 !amdgpu_has_atpx_dgpu_power_cntl()) 1193 pci_set_power_state(pdev, PCI_D0); 1194 pci_restore_state(pdev); 1195 ret = pci_enable_device(pdev); 1196 if (ret) 1197 return ret; 1198 pci_set_master(pdev); 1199 1200 ret = amdgpu_device_resume(drm_dev, false, false); 1201 drm_kms_helper_poll_enable(drm_dev); 1202 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1203 return 0; 1204 } 1205 1206 static int amdgpu_pmops_runtime_idle(struct device *dev) 1207 { 1208 struct pci_dev *pdev = to_pci_dev(dev); 1209 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1210 struct drm_crtc *crtc; 1211 1212 if (!amdgpu_device_is_px(drm_dev)) { 1213 pm_runtime_forbid(dev); 1214 return -EBUSY; 1215 } 1216 1217 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1218 if (crtc->enabled) { 1219 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1220 return -EBUSY; 1221 } 1222 } 1223 1224 pm_runtime_mark_last_busy(dev); 1225 pm_runtime_autosuspend(dev); 1226 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1227 return 1; 1228 } 1229 1230 long amdgpu_drm_ioctl(struct file *filp, 1231 unsigned int cmd, unsigned long arg) 1232 { 1233 struct drm_file *file_priv = filp->private_data; 1234 struct drm_device *dev; 1235 long ret; 1236 dev = file_priv->minor->dev; 1237 ret = pm_runtime_get_sync(dev->dev); 1238 if (ret < 0) 1239 return ret; 1240 1241 ret = drm_ioctl(filp, cmd, arg); 1242 1243 pm_runtime_mark_last_busy(dev->dev); 1244 pm_runtime_put_autosuspend(dev->dev); 1245 return ret; 1246 } 1247 1248 static const struct dev_pm_ops amdgpu_pm_ops = { 1249 .suspend = amdgpu_pmops_suspend, 1250 .resume = amdgpu_pmops_resume, 1251 .freeze = amdgpu_pmops_freeze, 1252 .thaw = amdgpu_pmops_thaw, 1253 .poweroff = amdgpu_pmops_poweroff, 1254 .restore = amdgpu_pmops_restore, 1255 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1256 .runtime_resume = amdgpu_pmops_runtime_resume, 1257 .runtime_idle = amdgpu_pmops_runtime_idle, 1258 }; 1259 1260 static int amdgpu_flush(struct file *f, fl_owner_t id) 1261 { 1262 struct drm_file *file_priv = f->private_data; 1263 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1264 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1265 1266 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1267 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1268 1269 return timeout >= 0 ? 0 : timeout; 1270 } 1271 1272 static const struct file_operations amdgpu_driver_kms_fops = { 1273 .owner = THIS_MODULE, 1274 .open = drm_open, 1275 .flush = amdgpu_flush, 1276 .release = drm_release, 1277 .unlocked_ioctl = amdgpu_drm_ioctl, 1278 .mmap = amdgpu_mmap, 1279 .poll = drm_poll, 1280 .read = drm_read, 1281 #ifdef CONFIG_COMPAT 1282 .compat_ioctl = amdgpu_kms_compat_ioctl, 1283 #endif 1284 }; 1285 1286 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1287 { 1288 struct drm_file *file; 1289 1290 if (!filp) 1291 return -EINVAL; 1292 1293 if (filp->f_op != &amdgpu_driver_kms_fops) { 1294 return -EINVAL; 1295 } 1296 1297 file = filp->private_data; 1298 *fpriv = file->driver_priv; 1299 return 0; 1300 } 1301 1302 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 1303 { 1304 char *input = amdgpu_lockup_timeout; 1305 char *timeout_setting = NULL; 1306 int index = 0; 1307 long timeout; 1308 int ret = 0; 1309 1310 /* 1311 * By default timeout for non compute jobs is 10000. 1312 * And there is no timeout enforced on compute jobs. 1313 */ 1314 adev->gfx_timeout = msecs_to_jiffies(10000); 1315 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1316 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; 1317 1318 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1319 while ((timeout_setting = strsep(&input, ",")) && 1320 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1321 ret = kstrtol(timeout_setting, 0, &timeout); 1322 if (ret) 1323 return ret; 1324 1325 if (timeout == 0) { 1326 index++; 1327 continue; 1328 } else if (timeout < 0) { 1329 timeout = MAX_SCHEDULE_TIMEOUT; 1330 } else { 1331 timeout = msecs_to_jiffies(timeout); 1332 } 1333 1334 switch (index++) { 1335 case 0: 1336 adev->gfx_timeout = timeout; 1337 break; 1338 case 1: 1339 adev->compute_timeout = timeout; 1340 break; 1341 case 2: 1342 adev->sdma_timeout = timeout; 1343 break; 1344 case 3: 1345 adev->video_timeout = timeout; 1346 break; 1347 default: 1348 break; 1349 } 1350 } 1351 /* 1352 * There is only one value specified and 1353 * it should apply to all non-compute jobs. 1354 */ 1355 if (index == 1) 1356 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1357 } 1358 1359 return ret; 1360 } 1361 1362 static bool 1363 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1364 bool in_vblank_irq, int *vpos, int *hpos, 1365 ktime_t *stime, ktime_t *etime, 1366 const struct drm_display_mode *mode) 1367 { 1368 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1369 stime, etime, mode); 1370 } 1371 1372 static struct drm_driver kms_driver = { 1373 .driver_features = 1374 DRIVER_USE_AGP | DRIVER_ATOMIC | 1375 DRIVER_GEM | 1376 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1377 .load = amdgpu_driver_load_kms, 1378 .open = amdgpu_driver_open_kms, 1379 .postclose = amdgpu_driver_postclose_kms, 1380 .lastclose = amdgpu_driver_lastclose_kms, 1381 .unload = amdgpu_driver_unload_kms, 1382 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1383 .enable_vblank = amdgpu_enable_vblank_kms, 1384 .disable_vblank = amdgpu_disable_vblank_kms, 1385 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1386 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1387 .irq_handler = amdgpu_irq_handler, 1388 .ioctls = amdgpu_ioctls_kms, 1389 .gem_free_object_unlocked = amdgpu_gem_object_free, 1390 .gem_open_object = amdgpu_gem_object_open, 1391 .gem_close_object = amdgpu_gem_object_close, 1392 .dumb_create = amdgpu_mode_dumb_create, 1393 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1394 .fops = &amdgpu_driver_kms_fops, 1395 1396 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1397 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1398 .gem_prime_export = amdgpu_gem_prime_export, 1399 .gem_prime_import = amdgpu_gem_prime_import, 1400 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1401 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1402 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1403 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1404 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1405 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1406 1407 .name = DRIVER_NAME, 1408 .desc = DRIVER_DESC, 1409 .date = DRIVER_DATE, 1410 .major = KMS_DRIVER_MAJOR, 1411 .minor = KMS_DRIVER_MINOR, 1412 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1413 }; 1414 1415 static struct pci_driver amdgpu_kms_pci_driver = { 1416 .name = DRIVER_NAME, 1417 .id_table = pciidlist, 1418 .probe = amdgpu_pci_probe, 1419 .remove = amdgpu_pci_remove, 1420 .shutdown = amdgpu_pci_shutdown, 1421 .driver.pm = &amdgpu_pm_ops, 1422 }; 1423 1424 1425 1426 static int __init amdgpu_init(void) 1427 { 1428 int r; 1429 1430 if (vgacon_text_force()) { 1431 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1432 return -EINVAL; 1433 } 1434 1435 r = amdgpu_sync_init(); 1436 if (r) 1437 goto error_sync; 1438 1439 r = amdgpu_fence_slab_init(); 1440 if (r) 1441 goto error_fence; 1442 1443 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1444 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1445 amdgpu_register_atpx_handler(); 1446 1447 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1448 amdgpu_amdkfd_init(); 1449 1450 /* let modprobe override vga console setting */ 1451 return pci_register_driver(&amdgpu_kms_pci_driver); 1452 1453 error_fence: 1454 amdgpu_sync_fini(); 1455 1456 error_sync: 1457 return r; 1458 } 1459 1460 static void __exit amdgpu_exit(void) 1461 { 1462 amdgpu_amdkfd_fini(); 1463 pci_unregister_driver(&amdgpu_kms_pci_driver); 1464 amdgpu_unregister_atpx_handler(); 1465 amdgpu_sync_fini(); 1466 amdgpu_fence_slab_fini(); 1467 } 1468 1469 module_init(amdgpu_init); 1470 module_exit(amdgpu_exit); 1471 1472 MODULE_AUTHOR(DRIVER_AUTHOR); 1473 MODULE_DESCRIPTION(DRIVER_DESC); 1474 MODULE_LICENSE("GPL and additional rights"); 1475