1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/amdgpu_drm.h> 27 #include <drm/drm_gem.h> 28 #include "amdgpu_drv.h" 29 30 #include <drm/drm_pciids.h> 31 #include <linux/console.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/vga_switcheroo.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_irq.h" 39 #include "amdgpu_dma_buf.h" 40 41 #include "amdgpu_amdkfd.h" 42 43 /* 44 * KMS wrapper. 45 * - 3.0.0 - initial driver 46 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 47 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 48 * at the end of IBs. 49 * - 3.3.0 - Add VM support for UVD on supported hardware. 50 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 51 * - 3.5.0 - Add support for new UVD_NO_OP register. 52 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 53 * - 3.7.0 - Add support for VCE clock list packet 54 * - 3.8.0 - Add support raster config init in the kernel 55 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 56 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 57 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 58 * - 3.12.0 - Add query for double offchip LDS buffers 59 * - 3.13.0 - Add PRT support 60 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 61 * - 3.15.0 - Export more gpu info for gfx9 62 * - 3.16.0 - Add reserved vmid support 63 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 64 * - 3.18.0 - Export gpu always on cu bitmap 65 * - 3.19.0 - Add support for UVD MJPEG decode 66 * - 3.20.0 - Add support for local BOs 67 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 68 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 69 * - 3.23.0 - Add query for VRAM lost counter 70 * - 3.24.0 - Add high priority compute support for gfx9 71 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 72 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 73 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 74 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 75 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 76 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 77 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 78 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 79 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 80 */ 81 #define KMS_DRIVER_MAJOR 3 82 #define KMS_DRIVER_MINOR 33 83 #define KMS_DRIVER_PATCHLEVEL 0 84 85 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 86 87 int amdgpu_vram_limit = 0; 88 int amdgpu_vis_vram_limit = 0; 89 int amdgpu_gart_size = -1; /* auto */ 90 int amdgpu_gtt_size = -1; /* auto */ 91 int amdgpu_moverate = -1; /* auto */ 92 int amdgpu_benchmarking = 0; 93 int amdgpu_testing = 0; 94 int amdgpu_audio = -1; 95 int amdgpu_disp_priority = 0; 96 int amdgpu_hw_i2c = 0; 97 int amdgpu_pcie_gen2 = -1; 98 int amdgpu_msi = -1; 99 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 100 int amdgpu_dpm = -1; 101 int amdgpu_fw_load_type = -1; 102 int amdgpu_aspm = -1; 103 int amdgpu_runtime_pm = -1; 104 uint amdgpu_ip_block_mask = 0xffffffff; 105 int amdgpu_bapm = -1; 106 int amdgpu_deep_color = 0; 107 int amdgpu_vm_size = -1; 108 int amdgpu_vm_fragment_size = -1; 109 int amdgpu_vm_block_size = -1; 110 int amdgpu_vm_fault_stop = 0; 111 int amdgpu_vm_debug = 0; 112 int amdgpu_vm_update_mode = -1; 113 int amdgpu_exp_hw_support = 0; 114 int amdgpu_dc = -1; 115 int amdgpu_sched_jobs = 32; 116 int amdgpu_sched_hw_submission = 2; 117 uint amdgpu_pcie_gen_cap = 0; 118 uint amdgpu_pcie_lane_cap = 0; 119 uint amdgpu_cg_mask = 0xffffffff; 120 uint amdgpu_pg_mask = 0xffffffff; 121 uint amdgpu_sdma_phase_quantum = 32; 122 char *amdgpu_disable_cu = NULL; 123 char *amdgpu_virtual_display = NULL; 124 /* OverDrive(bit 14) disabled by default*/ 125 uint amdgpu_pp_feature_mask = 0xffffbfff; 126 int amdgpu_ngg = 0; 127 int amdgpu_prim_buf_per_se = 0; 128 int amdgpu_pos_buf_per_se = 0; 129 int amdgpu_cntl_sb_buf_per_se = 0; 130 int amdgpu_param_buf_per_se = 0; 131 int amdgpu_job_hang_limit = 0; 132 int amdgpu_lbpw = -1; 133 int amdgpu_compute_multipipe = -1; 134 int amdgpu_gpu_recovery = -1; /* auto */ 135 int amdgpu_emu_mode = 0; 136 uint amdgpu_smu_memory_pool_size = 0; 137 /* FBC (bit 0) disabled by default*/ 138 uint amdgpu_dc_feature_mask = 0; 139 140 struct amdgpu_mgpu_info mgpu_info = { 141 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 142 }; 143 int amdgpu_ras_enable = -1; 144 uint amdgpu_ras_mask = 0xffffffff; 145 146 /** 147 * DOC: vramlimit (int) 148 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 149 */ 150 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 151 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 152 153 /** 154 * DOC: vis_vramlimit (int) 155 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 156 */ 157 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 158 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 159 160 /** 161 * DOC: gartsize (uint) 162 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 163 */ 164 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 165 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 166 167 /** 168 * DOC: gttsize (int) 169 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 170 * otherwise 3/4 RAM size). 171 */ 172 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 173 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 174 175 /** 176 * DOC: moverate (int) 177 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 178 */ 179 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 180 module_param_named(moverate, amdgpu_moverate, int, 0600); 181 182 /** 183 * DOC: benchmark (int) 184 * Run benchmarks. The default is 0 (Skip benchmarks). 185 */ 186 MODULE_PARM_DESC(benchmark, "Run benchmark"); 187 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 188 189 /** 190 * DOC: test (int) 191 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 192 */ 193 MODULE_PARM_DESC(test, "Run tests"); 194 module_param_named(test, amdgpu_testing, int, 0444); 195 196 /** 197 * DOC: audio (int) 198 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 199 */ 200 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 201 module_param_named(audio, amdgpu_audio, int, 0444); 202 203 /** 204 * DOC: disp_priority (int) 205 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 206 */ 207 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 208 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 209 210 /** 211 * DOC: hw_i2c (int) 212 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 213 */ 214 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 215 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 216 217 /** 218 * DOC: pcie_gen2 (int) 219 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 220 */ 221 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 222 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 223 224 /** 225 * DOC: msi (int) 226 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 227 */ 228 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 229 module_param_named(msi, amdgpu_msi, int, 0444); 230 231 /** 232 * DOC: lockup_timeout (string) 233 * Set GPU scheduler timeout value in ms. 234 * 235 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 236 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 237 * to default timeout. 238 * - With one value specified, the setting will apply to all non-compute jobs. 239 * - With multiple values specified, the first one will be for GFX. The second one is for Compute. 240 * And the third and fourth ones are for SDMA and Video. 241 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 242 * jobs is 10000. And there is no timeout enforced on compute jobs. 243 */ 244 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and no timeout for compute jobs), " 245 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); 246 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 247 248 /** 249 * DOC: dpm (int) 250 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto). 251 */ 252 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 253 module_param_named(dpm, amdgpu_dpm, int, 0444); 254 255 /** 256 * DOC: fw_load_type (int) 257 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 258 */ 259 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 260 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 261 262 /** 263 * DOC: aspm (int) 264 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 265 */ 266 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 267 module_param_named(aspm, amdgpu_aspm, int, 0444); 268 269 /** 270 * DOC: runpm (int) 271 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 272 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 273 */ 274 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 275 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 276 277 /** 278 * DOC: ip_block_mask (uint) 279 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 280 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 281 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 282 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 283 */ 284 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 285 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 286 287 /** 288 * DOC: bapm (int) 289 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 290 * The default -1 (auto, enabled) 291 */ 292 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 293 module_param_named(bapm, amdgpu_bapm, int, 0444); 294 295 /** 296 * DOC: deep_color (int) 297 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 298 */ 299 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 300 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 301 302 /** 303 * DOC: vm_size (int) 304 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 305 */ 306 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 307 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 308 309 /** 310 * DOC: vm_fragment_size (int) 311 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 312 */ 313 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 314 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 315 316 /** 317 * DOC: vm_block_size (int) 318 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 319 */ 320 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 321 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 322 323 /** 324 * DOC: vm_fault_stop (int) 325 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 326 */ 327 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 328 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 329 330 /** 331 * DOC: vm_debug (int) 332 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 333 */ 334 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 335 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 336 337 /** 338 * DOC: vm_update_mode (int) 339 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 340 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 341 */ 342 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 343 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 344 345 /** 346 * DOC: exp_hw_support (int) 347 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 348 */ 349 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 350 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 351 352 /** 353 * DOC: dc (int) 354 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 355 */ 356 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 357 module_param_named(dc, amdgpu_dc, int, 0444); 358 359 /** 360 * DOC: sched_jobs (int) 361 * Override the max number of jobs supported in the sw queue. The default is 32. 362 */ 363 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 364 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 365 366 /** 367 * DOC: sched_hw_submission (int) 368 * Override the max number of HW submissions. The default is 2. 369 */ 370 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 371 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 372 373 /** 374 * DOC: ppfeaturemask (uint) 375 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 376 * The default is the current set of stable power features. 377 */ 378 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 379 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 380 381 /** 382 * DOC: pcie_gen_cap (uint) 383 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 384 * The default is 0 (automatic for each asic). 385 */ 386 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 387 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 388 389 /** 390 * DOC: pcie_lane_cap (uint) 391 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 392 * The default is 0 (automatic for each asic). 393 */ 394 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 395 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 396 397 /** 398 * DOC: cg_mask (uint) 399 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 400 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 401 */ 402 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 403 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 404 405 /** 406 * DOC: pg_mask (uint) 407 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 408 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 409 */ 410 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 411 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 412 413 /** 414 * DOC: sdma_phase_quantum (uint) 415 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 416 */ 417 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 418 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 419 420 /** 421 * DOC: disable_cu (charp) 422 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 423 */ 424 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 425 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 426 427 /** 428 * DOC: virtual_display (charp) 429 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 430 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 431 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 432 * device at 26:00.0. The default is NULL. 433 */ 434 MODULE_PARM_DESC(virtual_display, 435 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 436 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 437 438 /** 439 * DOC: ngg (int) 440 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 441 */ 442 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 443 module_param_named(ngg, amdgpu_ngg, int, 0444); 444 445 /** 446 * DOC: prim_buf_per_se (int) 447 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 448 */ 449 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 450 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 451 452 /** 453 * DOC: pos_buf_per_se (int) 454 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 455 */ 456 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 457 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 458 459 /** 460 * DOC: cntl_sb_buf_per_se (int) 461 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 462 */ 463 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 464 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 465 466 /** 467 * DOC: param_buf_per_se (int) 468 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 469 * The default is 0 (depending on gfx). 470 */ 471 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 472 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 473 474 /** 475 * DOC: job_hang_limit (int) 476 * Set how much time allow a job hang and not drop it. The default is 0. 477 */ 478 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 479 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 480 481 /** 482 * DOC: lbpw (int) 483 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 484 */ 485 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 486 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 487 488 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 489 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 490 491 /** 492 * DOC: gpu_recovery (int) 493 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 494 */ 495 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 496 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 497 498 /** 499 * DOC: emu_mode (int) 500 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 501 */ 502 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 503 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 504 505 /** 506 * DOC: ras_enable (int) 507 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 508 */ 509 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 510 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 511 512 /** 513 * DOC: ras_mask (uint) 514 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 515 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 516 */ 517 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 518 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 519 520 /** 521 * DOC: si_support (int) 522 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 523 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 524 * otherwise using amdgpu driver. 525 */ 526 #ifdef CONFIG_DRM_AMDGPU_SI 527 528 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 529 int amdgpu_si_support = 0; 530 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 531 #else 532 int amdgpu_si_support = 1; 533 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 534 #endif 535 536 module_param_named(si_support, amdgpu_si_support, int, 0444); 537 #endif 538 539 /** 540 * DOC: cik_support (int) 541 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 542 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 543 * otherwise using amdgpu driver. 544 */ 545 #ifdef CONFIG_DRM_AMDGPU_CIK 546 547 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 548 int amdgpu_cik_support = 0; 549 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 550 #else 551 int amdgpu_cik_support = 1; 552 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 553 #endif 554 555 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 556 #endif 557 558 /** 559 * DOC: smu_memory_pool_size (uint) 560 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 561 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 562 */ 563 MODULE_PARM_DESC(smu_memory_pool_size, 564 "reserve gtt for smu debug usage, 0 = disable," 565 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 566 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 567 568 #ifdef CONFIG_HSA_AMD 569 /** 570 * DOC: sched_policy (int) 571 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 572 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 573 * assigns queues to HQDs. 574 */ 575 int sched_policy = KFD_SCHED_POLICY_HWS; 576 module_param(sched_policy, int, 0444); 577 MODULE_PARM_DESC(sched_policy, 578 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 579 580 /** 581 * DOC: hws_max_conc_proc (int) 582 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 583 * number of VMIDs assigned to the HWS, which is also the default. 584 */ 585 int hws_max_conc_proc = 8; 586 module_param(hws_max_conc_proc, int, 0444); 587 MODULE_PARM_DESC(hws_max_conc_proc, 588 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 589 590 /** 591 * DOC: cwsr_enable (int) 592 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 593 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 594 * disables it. 595 */ 596 int cwsr_enable = 1; 597 module_param(cwsr_enable, int, 0444); 598 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 599 600 /** 601 * DOC: max_num_of_queues_per_device (int) 602 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 603 * is 4096. 604 */ 605 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 606 module_param(max_num_of_queues_per_device, int, 0444); 607 MODULE_PARM_DESC(max_num_of_queues_per_device, 608 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 609 610 /** 611 * DOC: send_sigterm (int) 612 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 613 * but just print errors on dmesg. Setting 1 enables sending sigterm. 614 */ 615 int send_sigterm; 616 module_param(send_sigterm, int, 0444); 617 MODULE_PARM_DESC(send_sigterm, 618 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 619 620 /** 621 * DOC: debug_largebar (int) 622 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 623 * system. This limits the VRAM size reported to ROCm applications to the visible 624 * size, usually 256MB. 625 * Default value is 0, diabled. 626 */ 627 int debug_largebar; 628 module_param(debug_largebar, int, 0444); 629 MODULE_PARM_DESC(debug_largebar, 630 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 631 632 /** 633 * DOC: ignore_crat (int) 634 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 635 * table to get information about AMD APUs. This option can serve as a workaround on 636 * systems with a broken CRAT table. 637 */ 638 int ignore_crat; 639 module_param(ignore_crat, int, 0444); 640 MODULE_PARM_DESC(ignore_crat, 641 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 642 643 /** 644 * DOC: noretry (int) 645 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry. 646 * Setting 1 disables retry. 647 * Retry is needed for recoverable page faults. 648 */ 649 int noretry; 650 module_param(noretry, int, 0644); 651 MODULE_PARM_DESC(noretry, 652 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); 653 654 /** 655 * DOC: halt_if_hws_hang (int) 656 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 657 * Setting 1 enables halt on hang. 658 */ 659 int halt_if_hws_hang; 660 module_param(halt_if_hws_hang, int, 0644); 661 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 662 663 /** 664 * DOC: hws_gws_support(bool) 665 * Whether HWS support gws barriers. Default value: false (not supported) 666 * This will be replaced with a MEC firmware version check once firmware 667 * is ready 668 */ 669 bool hws_gws_support; 670 module_param(hws_gws_support, bool, 0444); 671 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 672 #endif 673 674 /** 675 * DOC: dcfeaturemask (uint) 676 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 677 * The default is the current set of stable display features. 678 */ 679 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 680 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 681 682 /** 683 * DOC: abmlevel (uint) 684 * Override the default ABM (Adaptive Backlight Management) level used for DC 685 * enabled hardware. Requires DMCU to be supported and loaded. 686 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 687 * default. Values 1-4 control the maximum allowable brightness reduction via 688 * the ABM algorithm, with 1 being the least reduction and 4 being the most 689 * reduction. 690 * 691 * Defaults to 0, or disabled. Userspace can still override this level later 692 * after boot. 693 */ 694 uint amdgpu_dm_abm_level = 0; 695 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 696 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 697 698 static const struct pci_device_id pciidlist[] = { 699 #ifdef CONFIG_DRM_AMDGPU_SI 700 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 701 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 702 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 703 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 704 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 705 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 706 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 707 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 708 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 709 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 710 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 711 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 712 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 713 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 714 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 715 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 716 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 717 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 718 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 719 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 720 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 721 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 722 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 723 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 724 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 725 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 726 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 727 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 728 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 729 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 730 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 731 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 732 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 733 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 734 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 735 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 736 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 737 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 738 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 739 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 740 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 741 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 742 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 743 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 744 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 745 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 746 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 747 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 748 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 749 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 750 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 751 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 752 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 753 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 754 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 755 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 756 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 757 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 758 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 759 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 760 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 761 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 762 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 763 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 764 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 765 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 766 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 767 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 768 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 769 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 770 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 771 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 772 #endif 773 #ifdef CONFIG_DRM_AMDGPU_CIK 774 /* Kaveri */ 775 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 776 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 777 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 778 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 779 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 780 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 781 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 782 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 783 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 784 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 785 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 786 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 787 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 788 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 789 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 790 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 791 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 792 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 793 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 794 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 795 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 796 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 797 /* Bonaire */ 798 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 799 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 800 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 801 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 802 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 803 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 804 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 805 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 806 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 807 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 808 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 809 /* Hawaii */ 810 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 811 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 812 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 813 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 814 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 815 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 816 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 817 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 818 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 819 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 820 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 821 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 822 /* Kabini */ 823 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 824 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 825 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 826 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 827 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 828 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 829 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 830 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 831 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 832 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 833 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 834 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 835 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 836 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 837 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 838 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 839 /* mullins */ 840 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 841 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 842 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 843 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 844 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 845 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 846 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 847 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 848 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 849 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 850 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 851 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 852 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 853 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 854 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 855 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 856 #endif 857 /* topaz */ 858 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 859 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 860 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 861 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 862 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 863 /* tonga */ 864 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 865 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 866 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 867 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 868 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 869 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 870 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 871 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 872 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 873 /* fiji */ 874 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 875 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 876 /* carrizo */ 877 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 878 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 879 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 880 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 881 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 882 /* stoney */ 883 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 884 /* Polaris11 */ 885 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 886 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 887 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 888 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 889 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 890 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 891 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 892 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 893 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 894 /* Polaris10 */ 895 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 896 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 897 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 898 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 899 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 900 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 901 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 902 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 903 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 904 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 905 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 906 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 907 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 908 /* Polaris12 */ 909 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 910 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 911 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 912 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 913 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 914 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 915 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 916 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 917 /* VEGAM */ 918 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 919 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 920 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 921 /* Vega 10 */ 922 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 923 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 924 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 925 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 926 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 927 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 928 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 929 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 930 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 931 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 932 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 933 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 934 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 935 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 936 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 937 /* Vega 12 */ 938 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 939 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 940 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 941 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 942 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 943 /* Vega 20 */ 944 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 945 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 946 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 947 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 948 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 949 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 950 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 951 /* Raven */ 952 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 953 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 954 955 {0, 0, 0} 956 }; 957 958 MODULE_DEVICE_TABLE(pci, pciidlist); 959 960 static struct drm_driver kms_driver; 961 962 static int amdgpu_pci_probe(struct pci_dev *pdev, 963 const struct pci_device_id *ent) 964 { 965 struct drm_device *dev; 966 unsigned long flags = ent->driver_data; 967 int ret, retry = 0; 968 bool supports_atomic = false; 969 970 if (!amdgpu_virtual_display && 971 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 972 supports_atomic = true; 973 974 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 975 DRM_INFO("This hardware requires experimental hardware support.\n" 976 "See modparam exp_hw_support\n"); 977 return -ENODEV; 978 } 979 980 /* Get rid of things like offb */ 981 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 982 if (ret) 983 return ret; 984 985 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 986 if (IS_ERR(dev)) 987 return PTR_ERR(dev); 988 989 if (!supports_atomic) 990 dev->driver_features &= ~DRIVER_ATOMIC; 991 992 ret = pci_enable_device(pdev); 993 if (ret) 994 goto err_free; 995 996 dev->pdev = pdev; 997 998 pci_set_drvdata(pdev, dev); 999 1000 retry_init: 1001 ret = drm_dev_register(dev, ent->driver_data); 1002 if (ret == -EAGAIN && ++retry <= 3) { 1003 DRM_INFO("retry init %d\n", retry); 1004 /* Don't request EX mode too frequently which is attacking */ 1005 msleep(5000); 1006 goto retry_init; 1007 } else if (ret) 1008 goto err_pci; 1009 1010 return 0; 1011 1012 err_pci: 1013 pci_disable_device(pdev); 1014 err_free: 1015 drm_dev_put(dev); 1016 return ret; 1017 } 1018 1019 static void 1020 amdgpu_pci_remove(struct pci_dev *pdev) 1021 { 1022 struct drm_device *dev = pci_get_drvdata(pdev); 1023 1024 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 1025 drm_dev_unplug(dev); 1026 drm_dev_put(dev); 1027 pci_disable_device(pdev); 1028 pci_set_drvdata(pdev, NULL); 1029 } 1030 1031 static void 1032 amdgpu_pci_shutdown(struct pci_dev *pdev) 1033 { 1034 struct drm_device *dev = pci_get_drvdata(pdev); 1035 struct amdgpu_device *adev = dev->dev_private; 1036 1037 /* if we are running in a VM, make sure the device 1038 * torn down properly on reboot/shutdown. 1039 * unfortunately we can't detect certain 1040 * hypervisors so just do this all the time. 1041 */ 1042 amdgpu_device_ip_suspend(adev); 1043 } 1044 1045 static int amdgpu_pmops_suspend(struct device *dev) 1046 { 1047 struct pci_dev *pdev = to_pci_dev(dev); 1048 1049 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1050 return amdgpu_device_suspend(drm_dev, true, true); 1051 } 1052 1053 static int amdgpu_pmops_resume(struct device *dev) 1054 { 1055 struct pci_dev *pdev = to_pci_dev(dev); 1056 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1057 1058 /* GPU comes up enabled by the bios on resume */ 1059 if (amdgpu_device_is_px(drm_dev)) { 1060 pm_runtime_disable(dev); 1061 pm_runtime_set_active(dev); 1062 pm_runtime_enable(dev); 1063 } 1064 1065 return amdgpu_device_resume(drm_dev, true, true); 1066 } 1067 1068 static int amdgpu_pmops_freeze(struct device *dev) 1069 { 1070 struct pci_dev *pdev = to_pci_dev(dev); 1071 1072 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1073 return amdgpu_device_suspend(drm_dev, false, true); 1074 } 1075 1076 static int amdgpu_pmops_thaw(struct device *dev) 1077 { 1078 struct pci_dev *pdev = to_pci_dev(dev); 1079 1080 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1081 return amdgpu_device_resume(drm_dev, false, true); 1082 } 1083 1084 static int amdgpu_pmops_poweroff(struct device *dev) 1085 { 1086 struct pci_dev *pdev = to_pci_dev(dev); 1087 1088 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1089 return amdgpu_device_suspend(drm_dev, true, true); 1090 } 1091 1092 static int amdgpu_pmops_restore(struct device *dev) 1093 { 1094 struct pci_dev *pdev = to_pci_dev(dev); 1095 1096 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1097 return amdgpu_device_resume(drm_dev, false, true); 1098 } 1099 1100 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1101 { 1102 struct pci_dev *pdev = to_pci_dev(dev); 1103 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1104 int ret; 1105 1106 if (!amdgpu_device_is_px(drm_dev)) { 1107 pm_runtime_forbid(dev); 1108 return -EBUSY; 1109 } 1110 1111 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1112 drm_kms_helper_poll_disable(drm_dev); 1113 1114 ret = amdgpu_device_suspend(drm_dev, false, false); 1115 pci_save_state(pdev); 1116 pci_disable_device(pdev); 1117 pci_ignore_hotplug(pdev); 1118 if (amdgpu_is_atpx_hybrid()) 1119 pci_set_power_state(pdev, PCI_D3cold); 1120 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1121 pci_set_power_state(pdev, PCI_D3hot); 1122 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1123 1124 return 0; 1125 } 1126 1127 static int amdgpu_pmops_runtime_resume(struct device *dev) 1128 { 1129 struct pci_dev *pdev = to_pci_dev(dev); 1130 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1131 int ret; 1132 1133 if (!amdgpu_device_is_px(drm_dev)) 1134 return -EINVAL; 1135 1136 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1137 1138 if (amdgpu_is_atpx_hybrid() || 1139 !amdgpu_has_atpx_dgpu_power_cntl()) 1140 pci_set_power_state(pdev, PCI_D0); 1141 pci_restore_state(pdev); 1142 ret = pci_enable_device(pdev); 1143 if (ret) 1144 return ret; 1145 pci_set_master(pdev); 1146 1147 ret = amdgpu_device_resume(drm_dev, false, false); 1148 drm_kms_helper_poll_enable(drm_dev); 1149 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1150 return 0; 1151 } 1152 1153 static int amdgpu_pmops_runtime_idle(struct device *dev) 1154 { 1155 struct pci_dev *pdev = to_pci_dev(dev); 1156 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1157 struct drm_crtc *crtc; 1158 1159 if (!amdgpu_device_is_px(drm_dev)) { 1160 pm_runtime_forbid(dev); 1161 return -EBUSY; 1162 } 1163 1164 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1165 if (crtc->enabled) { 1166 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1167 return -EBUSY; 1168 } 1169 } 1170 1171 pm_runtime_mark_last_busy(dev); 1172 pm_runtime_autosuspend(dev); 1173 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1174 return 1; 1175 } 1176 1177 long amdgpu_drm_ioctl(struct file *filp, 1178 unsigned int cmd, unsigned long arg) 1179 { 1180 struct drm_file *file_priv = filp->private_data; 1181 struct drm_device *dev; 1182 long ret; 1183 dev = file_priv->minor->dev; 1184 ret = pm_runtime_get_sync(dev->dev); 1185 if (ret < 0) 1186 return ret; 1187 1188 ret = drm_ioctl(filp, cmd, arg); 1189 1190 pm_runtime_mark_last_busy(dev->dev); 1191 pm_runtime_put_autosuspend(dev->dev); 1192 return ret; 1193 } 1194 1195 static const struct dev_pm_ops amdgpu_pm_ops = { 1196 .suspend = amdgpu_pmops_suspend, 1197 .resume = amdgpu_pmops_resume, 1198 .freeze = amdgpu_pmops_freeze, 1199 .thaw = amdgpu_pmops_thaw, 1200 .poweroff = amdgpu_pmops_poweroff, 1201 .restore = amdgpu_pmops_restore, 1202 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1203 .runtime_resume = amdgpu_pmops_runtime_resume, 1204 .runtime_idle = amdgpu_pmops_runtime_idle, 1205 }; 1206 1207 static int amdgpu_flush(struct file *f, fl_owner_t id) 1208 { 1209 struct drm_file *file_priv = f->private_data; 1210 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1211 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1212 1213 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1214 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1215 1216 return timeout >= 0 ? 0 : timeout; 1217 } 1218 1219 static const struct file_operations amdgpu_driver_kms_fops = { 1220 .owner = THIS_MODULE, 1221 .open = drm_open, 1222 .flush = amdgpu_flush, 1223 .release = drm_release, 1224 .unlocked_ioctl = amdgpu_drm_ioctl, 1225 .mmap = amdgpu_mmap, 1226 .poll = drm_poll, 1227 .read = drm_read, 1228 #ifdef CONFIG_COMPAT 1229 .compat_ioctl = amdgpu_kms_compat_ioctl, 1230 #endif 1231 }; 1232 1233 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1234 { 1235 struct drm_file *file; 1236 1237 if (!filp) 1238 return -EINVAL; 1239 1240 if (filp->f_op != &amdgpu_driver_kms_fops) { 1241 return -EINVAL; 1242 } 1243 1244 file = filp->private_data; 1245 *fpriv = file->driver_priv; 1246 return 0; 1247 } 1248 1249 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 1250 { 1251 char *input = amdgpu_lockup_timeout; 1252 char *timeout_setting = NULL; 1253 int index = 0; 1254 long timeout; 1255 int ret = 0; 1256 1257 /* 1258 * By default timeout for non compute jobs is 10000. 1259 * And there is no timeout enforced on compute jobs. 1260 */ 1261 adev->gfx_timeout = adev->sdma_timeout = adev->video_timeout = 10000; 1262 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; 1263 1264 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1265 while ((timeout_setting = strsep(&input, ",")) && 1266 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1267 ret = kstrtol(timeout_setting, 0, &timeout); 1268 if (ret) 1269 return ret; 1270 1271 /* Invalidate 0 and negative values */ 1272 if (timeout <= 0) { 1273 index++; 1274 continue; 1275 } 1276 1277 switch (index++) { 1278 case 0: 1279 adev->gfx_timeout = timeout; 1280 break; 1281 case 1: 1282 adev->compute_timeout = timeout; 1283 break; 1284 case 2: 1285 adev->sdma_timeout = timeout; 1286 break; 1287 case 3: 1288 adev->video_timeout = timeout; 1289 break; 1290 default: 1291 break; 1292 } 1293 } 1294 /* 1295 * There is only one value specified and 1296 * it should apply to all non-compute jobs. 1297 */ 1298 if (index == 1) 1299 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1300 } 1301 1302 return ret; 1303 } 1304 1305 static bool 1306 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1307 bool in_vblank_irq, int *vpos, int *hpos, 1308 ktime_t *stime, ktime_t *etime, 1309 const struct drm_display_mode *mode) 1310 { 1311 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1312 stime, etime, mode); 1313 } 1314 1315 static struct drm_driver kms_driver = { 1316 .driver_features = 1317 DRIVER_USE_AGP | DRIVER_ATOMIC | 1318 DRIVER_GEM | 1319 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1320 .load = amdgpu_driver_load_kms, 1321 .open = amdgpu_driver_open_kms, 1322 .postclose = amdgpu_driver_postclose_kms, 1323 .lastclose = amdgpu_driver_lastclose_kms, 1324 .unload = amdgpu_driver_unload_kms, 1325 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1326 .enable_vblank = amdgpu_enable_vblank_kms, 1327 .disable_vblank = amdgpu_disable_vblank_kms, 1328 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1329 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1330 .irq_handler = amdgpu_irq_handler, 1331 .ioctls = amdgpu_ioctls_kms, 1332 .gem_free_object_unlocked = amdgpu_gem_object_free, 1333 .gem_open_object = amdgpu_gem_object_open, 1334 .gem_close_object = amdgpu_gem_object_close, 1335 .dumb_create = amdgpu_mode_dumb_create, 1336 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1337 .fops = &amdgpu_driver_kms_fops, 1338 1339 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1340 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1341 .gem_prime_export = amdgpu_gem_prime_export, 1342 .gem_prime_import = amdgpu_gem_prime_import, 1343 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1344 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1345 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1346 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1347 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1348 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1349 1350 .name = DRIVER_NAME, 1351 .desc = DRIVER_DESC, 1352 .date = DRIVER_DATE, 1353 .major = KMS_DRIVER_MAJOR, 1354 .minor = KMS_DRIVER_MINOR, 1355 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1356 }; 1357 1358 static struct pci_driver amdgpu_kms_pci_driver = { 1359 .name = DRIVER_NAME, 1360 .id_table = pciidlist, 1361 .probe = amdgpu_pci_probe, 1362 .remove = amdgpu_pci_remove, 1363 .shutdown = amdgpu_pci_shutdown, 1364 .driver.pm = &amdgpu_pm_ops, 1365 }; 1366 1367 1368 1369 static int __init amdgpu_init(void) 1370 { 1371 int r; 1372 1373 if (vgacon_text_force()) { 1374 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1375 return -EINVAL; 1376 } 1377 1378 r = amdgpu_sync_init(); 1379 if (r) 1380 goto error_sync; 1381 1382 r = amdgpu_fence_slab_init(); 1383 if (r) 1384 goto error_fence; 1385 1386 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1387 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1388 amdgpu_register_atpx_handler(); 1389 1390 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1391 amdgpu_amdkfd_init(); 1392 1393 /* let modprobe override vga console setting */ 1394 return pci_register_driver(&amdgpu_kms_pci_driver); 1395 1396 error_fence: 1397 amdgpu_sync_fini(); 1398 1399 error_sync: 1400 return r; 1401 } 1402 1403 static void __exit amdgpu_exit(void) 1404 { 1405 amdgpu_amdkfd_fini(); 1406 pci_unregister_driver(&amdgpu_kms_pci_driver); 1407 amdgpu_unregister_atpx_handler(); 1408 amdgpu_sync_fini(); 1409 amdgpu_fence_slab_fini(); 1410 } 1411 1412 module_init(amdgpu_init); 1413 module_exit(amdgpu_exit); 1414 1415 MODULE_AUTHOR(DRIVER_AUTHOR); 1416 MODULE_DESCRIPTION(DRIVER_DESC); 1417 MODULE_LICENSE("GPL and additional rights"); 1418