1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 */ 54 #define KMS_DRIVER_MAJOR 3 55 #define KMS_DRIVER_MINOR 1 56 #define KMS_DRIVER_PATCHLEVEL 0 57 58 int amdgpu_vram_limit = 0; 59 int amdgpu_gart_size = -1; /* auto */ 60 int amdgpu_benchmarking = 0; 61 int amdgpu_testing = 0; 62 int amdgpu_audio = -1; 63 int amdgpu_disp_priority = 0; 64 int amdgpu_hw_i2c = 0; 65 int amdgpu_pcie_gen2 = -1; 66 int amdgpu_msi = -1; 67 int amdgpu_lockup_timeout = 0; 68 int amdgpu_dpm = -1; 69 int amdgpu_smc_load_fw = 1; 70 int amdgpu_aspm = -1; 71 int amdgpu_runtime_pm = -1; 72 int amdgpu_hard_reset = 0; 73 unsigned amdgpu_ip_block_mask = 0xffffffff; 74 int amdgpu_bapm = -1; 75 int amdgpu_deep_color = 0; 76 int amdgpu_vm_size = 64; 77 int amdgpu_vm_block_size = -1; 78 int amdgpu_vm_fault_stop = 0; 79 int amdgpu_vm_debug = 0; 80 int amdgpu_exp_hw_support = 0; 81 int amdgpu_enable_scheduler = 1; 82 int amdgpu_sched_jobs = 16; 83 int amdgpu_sched_hw_submission = 2; 84 int amdgpu_enable_semaphores = 0; 85 86 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 87 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 88 89 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 90 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 91 92 MODULE_PARM_DESC(benchmark, "Run benchmark"); 93 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 94 95 MODULE_PARM_DESC(test, "Run tests"); 96 module_param_named(test, amdgpu_testing, int, 0444); 97 98 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 99 module_param_named(audio, amdgpu_audio, int, 0444); 100 101 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 102 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 103 104 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 105 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 106 107 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 108 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 109 110 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 111 module_param_named(msi, amdgpu_msi, int, 0444); 112 113 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 114 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 115 116 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 117 module_param_named(dpm, amdgpu_dpm, int, 0444); 118 119 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 120 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 121 122 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 123 module_param_named(aspm, amdgpu_aspm, int, 0444); 124 125 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 126 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 127 128 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 129 module_param_named(hard_reset, amdgpu_hard_reset, int, 0444); 130 131 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 132 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 133 134 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 135 module_param_named(bapm, amdgpu_bapm, int, 0444); 136 137 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 138 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 139 140 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 141 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 142 143 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 144 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 145 146 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 147 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 148 149 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 150 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 151 152 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 153 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 154 155 MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)"); 156 module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444); 157 158 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)"); 159 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 160 161 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 162 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 163 164 MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))"); 165 module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644); 166 167 static struct pci_device_id pciidlist[] = { 168 #ifdef CONFIG_DRM_AMDGPU_CIK 169 /* Kaveri */ 170 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 171 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 172 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 173 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 174 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 175 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 176 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 177 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 178 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 179 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 180 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 181 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 182 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 183 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 184 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 185 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 186 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 187 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 188 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 189 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 190 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 191 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 192 /* Bonaire */ 193 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 194 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 195 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 196 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 197 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 198 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 199 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 200 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 201 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 202 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 203 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 204 /* Hawaii */ 205 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 206 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 207 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 208 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 209 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 210 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 211 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 212 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 213 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 214 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 215 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 216 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 217 /* Kabini */ 218 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 219 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 220 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 221 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 222 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 223 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 224 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 225 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 226 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 227 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 228 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 229 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 230 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 231 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 232 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 233 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 234 /* mullins */ 235 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 236 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 237 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 238 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 239 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 240 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 241 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 242 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 243 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 244 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 245 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 246 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 247 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 248 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 249 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 250 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 251 #endif 252 /* topaz */ 253 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 254 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 255 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 256 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 257 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, 258 /* tonga */ 259 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 260 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 261 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 262 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 263 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 264 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 265 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 266 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 267 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 268 /* fiji */ 269 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 270 /* carrizo */ 271 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 272 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 273 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 274 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 275 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 276 /* stoney */ 277 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 278 279 {0, 0, 0} 280 }; 281 282 MODULE_DEVICE_TABLE(pci, pciidlist); 283 284 static struct drm_driver kms_driver; 285 286 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 287 { 288 struct apertures_struct *ap; 289 bool primary = false; 290 291 ap = alloc_apertures(1); 292 if (!ap) 293 return -ENOMEM; 294 295 ap->ranges[0].base = pci_resource_start(pdev, 0); 296 ap->ranges[0].size = pci_resource_len(pdev, 0); 297 298 #ifdef CONFIG_X86 299 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 300 #endif 301 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 302 kfree(ap); 303 304 return 0; 305 } 306 307 static int amdgpu_pci_probe(struct pci_dev *pdev, 308 const struct pci_device_id *ent) 309 { 310 unsigned long flags = ent->driver_data; 311 int ret; 312 313 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 314 DRM_INFO("This hardware requires experimental hardware support.\n" 315 "See modparam exp_hw_support\n"); 316 return -ENODEV; 317 } 318 319 /* Get rid of things like offb */ 320 ret = amdgpu_kick_out_firmware_fb(pdev); 321 if (ret) 322 return ret; 323 324 return drm_get_pci_dev(pdev, ent, &kms_driver); 325 } 326 327 static void 328 amdgpu_pci_remove(struct pci_dev *pdev) 329 { 330 struct drm_device *dev = pci_get_drvdata(pdev); 331 332 drm_put_dev(dev); 333 } 334 335 static int amdgpu_pmops_suspend(struct device *dev) 336 { 337 struct pci_dev *pdev = to_pci_dev(dev); 338 struct drm_device *drm_dev = pci_get_drvdata(pdev); 339 return amdgpu_suspend_kms(drm_dev, true, true); 340 } 341 342 static int amdgpu_pmops_resume(struct device *dev) 343 { 344 struct pci_dev *pdev = to_pci_dev(dev); 345 struct drm_device *drm_dev = pci_get_drvdata(pdev); 346 return amdgpu_resume_kms(drm_dev, true, true); 347 } 348 349 static int amdgpu_pmops_freeze(struct device *dev) 350 { 351 struct pci_dev *pdev = to_pci_dev(dev); 352 struct drm_device *drm_dev = pci_get_drvdata(pdev); 353 return amdgpu_suspend_kms(drm_dev, false, true); 354 } 355 356 static int amdgpu_pmops_thaw(struct device *dev) 357 { 358 struct pci_dev *pdev = to_pci_dev(dev); 359 struct drm_device *drm_dev = pci_get_drvdata(pdev); 360 return amdgpu_resume_kms(drm_dev, false, true); 361 } 362 363 static int amdgpu_pmops_runtime_suspend(struct device *dev) 364 { 365 struct pci_dev *pdev = to_pci_dev(dev); 366 struct drm_device *drm_dev = pci_get_drvdata(pdev); 367 int ret; 368 369 if (!amdgpu_device_is_px(drm_dev)) { 370 pm_runtime_forbid(dev); 371 return -EBUSY; 372 } 373 374 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 375 drm_kms_helper_poll_disable(drm_dev); 376 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 377 378 ret = amdgpu_suspend_kms(drm_dev, false, false); 379 pci_save_state(pdev); 380 pci_disable_device(pdev); 381 pci_ignore_hotplug(pdev); 382 pci_set_power_state(pdev, PCI_D3cold); 383 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 384 385 return 0; 386 } 387 388 static int amdgpu_pmops_runtime_resume(struct device *dev) 389 { 390 struct pci_dev *pdev = to_pci_dev(dev); 391 struct drm_device *drm_dev = pci_get_drvdata(pdev); 392 int ret; 393 394 if (!amdgpu_device_is_px(drm_dev)) 395 return -EINVAL; 396 397 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 398 399 pci_set_power_state(pdev, PCI_D0); 400 pci_restore_state(pdev); 401 ret = pci_enable_device(pdev); 402 if (ret) 403 return ret; 404 pci_set_master(pdev); 405 406 ret = amdgpu_resume_kms(drm_dev, false, false); 407 drm_kms_helper_poll_enable(drm_dev); 408 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 409 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 410 return 0; 411 } 412 413 static int amdgpu_pmops_runtime_idle(struct device *dev) 414 { 415 struct pci_dev *pdev = to_pci_dev(dev); 416 struct drm_device *drm_dev = pci_get_drvdata(pdev); 417 struct drm_crtc *crtc; 418 419 if (!amdgpu_device_is_px(drm_dev)) { 420 pm_runtime_forbid(dev); 421 return -EBUSY; 422 } 423 424 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 425 if (crtc->enabled) { 426 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 427 return -EBUSY; 428 } 429 } 430 431 pm_runtime_mark_last_busy(dev); 432 pm_runtime_autosuspend(dev); 433 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 434 return 1; 435 } 436 437 long amdgpu_drm_ioctl(struct file *filp, 438 unsigned int cmd, unsigned long arg) 439 { 440 struct drm_file *file_priv = filp->private_data; 441 struct drm_device *dev; 442 long ret; 443 dev = file_priv->minor->dev; 444 ret = pm_runtime_get_sync(dev->dev); 445 if (ret < 0) 446 return ret; 447 448 ret = drm_ioctl(filp, cmd, arg); 449 450 pm_runtime_mark_last_busy(dev->dev); 451 pm_runtime_put_autosuspend(dev->dev); 452 return ret; 453 } 454 455 static const struct dev_pm_ops amdgpu_pm_ops = { 456 .suspend = amdgpu_pmops_suspend, 457 .resume = amdgpu_pmops_resume, 458 .freeze = amdgpu_pmops_freeze, 459 .thaw = amdgpu_pmops_thaw, 460 .poweroff = amdgpu_pmops_freeze, 461 .restore = amdgpu_pmops_resume, 462 .runtime_suspend = amdgpu_pmops_runtime_suspend, 463 .runtime_resume = amdgpu_pmops_runtime_resume, 464 .runtime_idle = amdgpu_pmops_runtime_idle, 465 }; 466 467 static const struct file_operations amdgpu_driver_kms_fops = { 468 .owner = THIS_MODULE, 469 .open = drm_open, 470 .release = drm_release, 471 .unlocked_ioctl = amdgpu_drm_ioctl, 472 .mmap = amdgpu_mmap, 473 .poll = drm_poll, 474 .read = drm_read, 475 #ifdef CONFIG_COMPAT 476 .compat_ioctl = amdgpu_kms_compat_ioctl, 477 #endif 478 }; 479 480 static struct drm_driver kms_driver = { 481 .driver_features = 482 DRIVER_USE_AGP | 483 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 484 DRIVER_PRIME | DRIVER_RENDER, 485 .dev_priv_size = 0, 486 .load = amdgpu_driver_load_kms, 487 .open = amdgpu_driver_open_kms, 488 .preclose = amdgpu_driver_preclose_kms, 489 .postclose = amdgpu_driver_postclose_kms, 490 .lastclose = amdgpu_driver_lastclose_kms, 491 .set_busid = drm_pci_set_busid, 492 .unload = amdgpu_driver_unload_kms, 493 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 494 .enable_vblank = amdgpu_enable_vblank_kms, 495 .disable_vblank = amdgpu_disable_vblank_kms, 496 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 497 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 498 #if defined(CONFIG_DEBUG_FS) 499 .debugfs_init = amdgpu_debugfs_init, 500 .debugfs_cleanup = amdgpu_debugfs_cleanup, 501 #endif 502 .irq_preinstall = amdgpu_irq_preinstall, 503 .irq_postinstall = amdgpu_irq_postinstall, 504 .irq_uninstall = amdgpu_irq_uninstall, 505 .irq_handler = amdgpu_irq_handler, 506 .ioctls = amdgpu_ioctls_kms, 507 .gem_free_object = amdgpu_gem_object_free, 508 .gem_open_object = amdgpu_gem_object_open, 509 .gem_close_object = amdgpu_gem_object_close, 510 .dumb_create = amdgpu_mode_dumb_create, 511 .dumb_map_offset = amdgpu_mode_dumb_mmap, 512 .dumb_destroy = drm_gem_dumb_destroy, 513 .fops = &amdgpu_driver_kms_fops, 514 515 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 516 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 517 .gem_prime_export = amdgpu_gem_prime_export, 518 .gem_prime_import = drm_gem_prime_import, 519 .gem_prime_pin = amdgpu_gem_prime_pin, 520 .gem_prime_unpin = amdgpu_gem_prime_unpin, 521 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 522 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 523 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 524 .gem_prime_vmap = amdgpu_gem_prime_vmap, 525 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 526 527 .name = DRIVER_NAME, 528 .desc = DRIVER_DESC, 529 .date = DRIVER_DATE, 530 .major = KMS_DRIVER_MAJOR, 531 .minor = KMS_DRIVER_MINOR, 532 .patchlevel = KMS_DRIVER_PATCHLEVEL, 533 }; 534 535 static struct drm_driver *driver; 536 static struct pci_driver *pdriver; 537 538 static struct pci_driver amdgpu_kms_pci_driver = { 539 .name = DRIVER_NAME, 540 .id_table = pciidlist, 541 .probe = amdgpu_pci_probe, 542 .remove = amdgpu_pci_remove, 543 .driver.pm = &amdgpu_pm_ops, 544 }; 545 546 static int __init amdgpu_init(void) 547 { 548 #ifdef CONFIG_VGA_CONSOLE 549 if (vgacon_text_force()) { 550 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 551 return -EINVAL; 552 } 553 #endif 554 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 555 driver = &kms_driver; 556 pdriver = &amdgpu_kms_pci_driver; 557 driver->driver_features |= DRIVER_MODESET; 558 driver->num_ioctls = amdgpu_max_kms_ioctl; 559 amdgpu_register_atpx_handler(); 560 561 amdgpu_amdkfd_init(); 562 563 /* let modprobe override vga console setting */ 564 return drm_pci_init(driver, pdriver); 565 } 566 567 static void __exit amdgpu_exit(void) 568 { 569 amdgpu_amdkfd_fini(); 570 drm_pci_exit(driver, pdriver); 571 amdgpu_unregister_atpx_handler(); 572 } 573 574 module_init(amdgpu_init); 575 module_exit(amdgpu_exit); 576 577 MODULE_AUTHOR(DRIVER_AUTHOR); 578 MODULE_DESCRIPTION(DRIVER_DESC); 579 MODULE_LICENSE("GPL and additional rights"); 580