1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/amdgpu_drm.h> 27 #include <drm/drm_gem.h> 28 #include "amdgpu_drv.h" 29 30 #include <drm/drm_pciids.h> 31 #include <linux/console.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/vga_switcheroo.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_irq.h" 39 #include "amdgpu_dma_buf.h" 40 41 #include "amdgpu_amdkfd.h" 42 43 /* 44 * KMS wrapper. 45 * - 3.0.0 - initial driver 46 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 47 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 48 * at the end of IBs. 49 * - 3.3.0 - Add VM support for UVD on supported hardware. 50 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 51 * - 3.5.0 - Add support for new UVD_NO_OP register. 52 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 53 * - 3.7.0 - Add support for VCE clock list packet 54 * - 3.8.0 - Add support raster config init in the kernel 55 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 56 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 57 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 58 * - 3.12.0 - Add query for double offchip LDS buffers 59 * - 3.13.0 - Add PRT support 60 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 61 * - 3.15.0 - Export more gpu info for gfx9 62 * - 3.16.0 - Add reserved vmid support 63 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 64 * - 3.18.0 - Export gpu always on cu bitmap 65 * - 3.19.0 - Add support for UVD MJPEG decode 66 * - 3.20.0 - Add support for local BOs 67 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 68 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 69 * - 3.23.0 - Add query for VRAM lost counter 70 * - 3.24.0 - Add high priority compute support for gfx9 71 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 72 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 73 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 74 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 75 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 76 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 77 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 78 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 79 */ 80 #define KMS_DRIVER_MAJOR 3 81 #define KMS_DRIVER_MINOR 32 82 #define KMS_DRIVER_PATCHLEVEL 0 83 84 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 85 86 int amdgpu_vram_limit = 0; 87 int amdgpu_vis_vram_limit = 0; 88 int amdgpu_gart_size = -1; /* auto */ 89 int amdgpu_gtt_size = -1; /* auto */ 90 int amdgpu_moverate = -1; /* auto */ 91 int amdgpu_benchmarking = 0; 92 int amdgpu_testing = 0; 93 int amdgpu_audio = -1; 94 int amdgpu_disp_priority = 0; 95 int amdgpu_hw_i2c = 0; 96 int amdgpu_pcie_gen2 = -1; 97 int amdgpu_msi = -1; 98 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 99 int amdgpu_dpm = -1; 100 int amdgpu_fw_load_type = -1; 101 int amdgpu_aspm = -1; 102 int amdgpu_runtime_pm = -1; 103 uint amdgpu_ip_block_mask = 0xffffffff; 104 int amdgpu_bapm = -1; 105 int amdgpu_deep_color = 0; 106 int amdgpu_vm_size = -1; 107 int amdgpu_vm_fragment_size = -1; 108 int amdgpu_vm_block_size = -1; 109 int amdgpu_vm_fault_stop = 0; 110 int amdgpu_vm_debug = 0; 111 int amdgpu_vram_page_split = 512; 112 int amdgpu_vm_update_mode = -1; 113 int amdgpu_exp_hw_support = 0; 114 int amdgpu_dc = -1; 115 int amdgpu_sched_jobs = 32; 116 int amdgpu_sched_hw_submission = 2; 117 uint amdgpu_pcie_gen_cap = 0; 118 uint amdgpu_pcie_lane_cap = 0; 119 uint amdgpu_cg_mask = 0xffffffff; 120 uint amdgpu_pg_mask = 0xffffffff; 121 uint amdgpu_sdma_phase_quantum = 32; 122 char *amdgpu_disable_cu = NULL; 123 char *amdgpu_virtual_display = NULL; 124 /* OverDrive(bit 14) disabled by default*/ 125 uint amdgpu_pp_feature_mask = 0xffffbfff; 126 int amdgpu_ngg = 0; 127 int amdgpu_prim_buf_per_se = 0; 128 int amdgpu_pos_buf_per_se = 0; 129 int amdgpu_cntl_sb_buf_per_se = 0; 130 int amdgpu_param_buf_per_se = 0; 131 int amdgpu_job_hang_limit = 0; 132 int amdgpu_lbpw = -1; 133 int amdgpu_compute_multipipe = -1; 134 int amdgpu_gpu_recovery = -1; /* auto */ 135 int amdgpu_emu_mode = 0; 136 uint amdgpu_smu_memory_pool_size = 0; 137 /* FBC (bit 0) disabled by default*/ 138 uint amdgpu_dc_feature_mask = 0; 139 140 struct amdgpu_mgpu_info mgpu_info = { 141 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 142 }; 143 int amdgpu_ras_enable = -1; 144 uint amdgpu_ras_mask = 0xffffffff; 145 146 /** 147 * DOC: vramlimit (int) 148 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 149 */ 150 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 151 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 152 153 /** 154 * DOC: vis_vramlimit (int) 155 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 156 */ 157 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 158 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 159 160 /** 161 * DOC: gartsize (uint) 162 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 163 */ 164 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 165 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 166 167 /** 168 * DOC: gttsize (int) 169 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 170 * otherwise 3/4 RAM size). 171 */ 172 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 173 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 174 175 /** 176 * DOC: moverate (int) 177 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 178 */ 179 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 180 module_param_named(moverate, amdgpu_moverate, int, 0600); 181 182 /** 183 * DOC: benchmark (int) 184 * Run benchmarks. The default is 0 (Skip benchmarks). 185 */ 186 MODULE_PARM_DESC(benchmark, "Run benchmark"); 187 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 188 189 /** 190 * DOC: test (int) 191 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 192 */ 193 MODULE_PARM_DESC(test, "Run tests"); 194 module_param_named(test, amdgpu_testing, int, 0444); 195 196 /** 197 * DOC: audio (int) 198 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 199 */ 200 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 201 module_param_named(audio, amdgpu_audio, int, 0444); 202 203 /** 204 * DOC: disp_priority (int) 205 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 206 */ 207 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 208 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 209 210 /** 211 * DOC: hw_i2c (int) 212 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 213 */ 214 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 215 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 216 217 /** 218 * DOC: pcie_gen2 (int) 219 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 220 */ 221 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 222 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 223 224 /** 225 * DOC: msi (int) 226 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 227 */ 228 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 229 module_param_named(msi, amdgpu_msi, int, 0444); 230 231 /** 232 * DOC: lockup_timeout (string) 233 * Set GPU scheduler timeout value in ms. 234 * 235 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 236 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 237 * to default timeout. 238 * - With one value specified, the setting will apply to all non-compute jobs. 239 * - With multiple values specified, the first one will be for GFX. The second one is for Compute. 240 * And the third and fourth ones are for SDMA and Video. 241 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 242 * jobs is 10000. And there is no timeout enforced on compute jobs. 243 */ 244 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and no timeout for compute jobs), " 245 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); 246 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 247 248 /** 249 * DOC: dpm (int) 250 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto). 251 */ 252 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 253 module_param_named(dpm, amdgpu_dpm, int, 0444); 254 255 /** 256 * DOC: fw_load_type (int) 257 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 258 */ 259 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 260 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 261 262 /** 263 * DOC: aspm (int) 264 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 265 */ 266 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 267 module_param_named(aspm, amdgpu_aspm, int, 0444); 268 269 /** 270 * DOC: runpm (int) 271 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 272 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 273 */ 274 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 275 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 276 277 /** 278 * DOC: ip_block_mask (uint) 279 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 280 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 281 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 282 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 283 */ 284 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 285 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 286 287 /** 288 * DOC: bapm (int) 289 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 290 * The default -1 (auto, enabled) 291 */ 292 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 293 module_param_named(bapm, amdgpu_bapm, int, 0444); 294 295 /** 296 * DOC: deep_color (int) 297 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 298 */ 299 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 300 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 301 302 /** 303 * DOC: vm_size (int) 304 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 305 */ 306 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 307 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 308 309 /** 310 * DOC: vm_fragment_size (int) 311 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 312 */ 313 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 314 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 315 316 /** 317 * DOC: vm_block_size (int) 318 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 319 */ 320 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 321 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 322 323 /** 324 * DOC: vm_fault_stop (int) 325 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 326 */ 327 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 328 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 329 330 /** 331 * DOC: vm_debug (int) 332 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 333 */ 334 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 335 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 336 337 /** 338 * DOC: vm_update_mode (int) 339 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 340 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 341 */ 342 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 343 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 344 345 /** 346 * DOC: vram_page_split (int) 347 * Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512. 348 */ 349 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); 350 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 351 352 /** 353 * DOC: exp_hw_support (int) 354 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 355 */ 356 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 357 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 358 359 /** 360 * DOC: dc (int) 361 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 362 */ 363 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 364 module_param_named(dc, amdgpu_dc, int, 0444); 365 366 /** 367 * DOC: sched_jobs (int) 368 * Override the max number of jobs supported in the sw queue. The default is 32. 369 */ 370 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 371 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 372 373 /** 374 * DOC: sched_hw_submission (int) 375 * Override the max number of HW submissions. The default is 2. 376 */ 377 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 378 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 379 380 /** 381 * DOC: ppfeaturemask (uint) 382 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 383 * The default is the current set of stable power features. 384 */ 385 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 386 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 387 388 /** 389 * DOC: pcie_gen_cap (uint) 390 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 391 * The default is 0 (automatic for each asic). 392 */ 393 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 394 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 395 396 /** 397 * DOC: pcie_lane_cap (uint) 398 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 399 * The default is 0 (automatic for each asic). 400 */ 401 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 402 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 403 404 /** 405 * DOC: cg_mask (uint) 406 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 407 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 408 */ 409 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 410 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 411 412 /** 413 * DOC: pg_mask (uint) 414 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 415 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 416 */ 417 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 418 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 419 420 /** 421 * DOC: sdma_phase_quantum (uint) 422 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 423 */ 424 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 425 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 426 427 /** 428 * DOC: disable_cu (charp) 429 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 430 */ 431 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 432 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 433 434 /** 435 * DOC: virtual_display (charp) 436 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 437 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 438 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 439 * device at 26:00.0. The default is NULL. 440 */ 441 MODULE_PARM_DESC(virtual_display, 442 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 443 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 444 445 /** 446 * DOC: ngg (int) 447 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 448 */ 449 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 450 module_param_named(ngg, amdgpu_ngg, int, 0444); 451 452 /** 453 * DOC: prim_buf_per_se (int) 454 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 455 */ 456 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 457 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 458 459 /** 460 * DOC: pos_buf_per_se (int) 461 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 462 */ 463 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 464 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 465 466 /** 467 * DOC: cntl_sb_buf_per_se (int) 468 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 469 */ 470 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 471 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 472 473 /** 474 * DOC: param_buf_per_se (int) 475 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 476 * The default is 0 (depending on gfx). 477 */ 478 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 479 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 480 481 /** 482 * DOC: job_hang_limit (int) 483 * Set how much time allow a job hang and not drop it. The default is 0. 484 */ 485 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 486 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 487 488 /** 489 * DOC: lbpw (int) 490 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 491 */ 492 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 493 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 494 495 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 496 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 497 498 /** 499 * DOC: gpu_recovery (int) 500 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 501 */ 502 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 503 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 504 505 /** 506 * DOC: emu_mode (int) 507 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 508 */ 509 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 510 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 511 512 /** 513 * DOC: ras_enable (int) 514 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 515 */ 516 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 517 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 518 519 /** 520 * DOC: ras_mask (uint) 521 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 522 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 523 */ 524 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 525 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 526 527 /** 528 * DOC: si_support (int) 529 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 530 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 531 * otherwise using amdgpu driver. 532 */ 533 #ifdef CONFIG_DRM_AMDGPU_SI 534 535 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 536 int amdgpu_si_support = 0; 537 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 538 #else 539 int amdgpu_si_support = 1; 540 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 541 #endif 542 543 module_param_named(si_support, amdgpu_si_support, int, 0444); 544 #endif 545 546 /** 547 * DOC: cik_support (int) 548 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 549 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 550 * otherwise using amdgpu driver. 551 */ 552 #ifdef CONFIG_DRM_AMDGPU_CIK 553 554 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 555 int amdgpu_cik_support = 0; 556 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 557 #else 558 int amdgpu_cik_support = 1; 559 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 560 #endif 561 562 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 563 #endif 564 565 /** 566 * DOC: smu_memory_pool_size (uint) 567 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 568 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 569 */ 570 MODULE_PARM_DESC(smu_memory_pool_size, 571 "reserve gtt for smu debug usage, 0 = disable," 572 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 573 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 574 575 #ifdef CONFIG_HSA_AMD 576 /** 577 * DOC: sched_policy (int) 578 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 579 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 580 * assigns queues to HQDs. 581 */ 582 int sched_policy = KFD_SCHED_POLICY_HWS; 583 module_param(sched_policy, int, 0444); 584 MODULE_PARM_DESC(sched_policy, 585 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 586 587 /** 588 * DOC: hws_max_conc_proc (int) 589 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 590 * number of VMIDs assigned to the HWS, which is also the default. 591 */ 592 int hws_max_conc_proc = 8; 593 module_param(hws_max_conc_proc, int, 0444); 594 MODULE_PARM_DESC(hws_max_conc_proc, 595 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 596 597 /** 598 * DOC: cwsr_enable (int) 599 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 600 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 601 * disables it. 602 */ 603 int cwsr_enable = 1; 604 module_param(cwsr_enable, int, 0444); 605 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 606 607 /** 608 * DOC: max_num_of_queues_per_device (int) 609 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 610 * is 4096. 611 */ 612 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 613 module_param(max_num_of_queues_per_device, int, 0444); 614 MODULE_PARM_DESC(max_num_of_queues_per_device, 615 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 616 617 /** 618 * DOC: send_sigterm (int) 619 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 620 * but just print errors on dmesg. Setting 1 enables sending sigterm. 621 */ 622 int send_sigterm; 623 module_param(send_sigterm, int, 0444); 624 MODULE_PARM_DESC(send_sigterm, 625 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 626 627 /** 628 * DOC: debug_largebar (int) 629 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 630 * system. This limits the VRAM size reported to ROCm applications to the visible 631 * size, usually 256MB. 632 * Default value is 0, diabled. 633 */ 634 int debug_largebar; 635 module_param(debug_largebar, int, 0444); 636 MODULE_PARM_DESC(debug_largebar, 637 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 638 639 /** 640 * DOC: ignore_crat (int) 641 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 642 * table to get information about AMD APUs. This option can serve as a workaround on 643 * systems with a broken CRAT table. 644 */ 645 int ignore_crat; 646 module_param(ignore_crat, int, 0444); 647 MODULE_PARM_DESC(ignore_crat, 648 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 649 650 /** 651 * DOC: noretry (int) 652 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry. 653 * Setting 1 disables retry. 654 * Retry is needed for recoverable page faults. 655 */ 656 int noretry; 657 module_param(noretry, int, 0644); 658 MODULE_PARM_DESC(noretry, 659 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); 660 661 /** 662 * DOC: halt_if_hws_hang (int) 663 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 664 * Setting 1 enables halt on hang. 665 */ 666 int halt_if_hws_hang; 667 module_param(halt_if_hws_hang, int, 0644); 668 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 669 670 /** 671 * DOC: hws_gws_support(bool) 672 * Whether HWS support gws barriers. Default value: false (not supported) 673 * This will be replaced with a MEC firmware version check once firmware 674 * is ready 675 */ 676 bool hws_gws_support; 677 module_param(hws_gws_support, bool, 0444); 678 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 679 #endif 680 681 /** 682 * DOC: dcfeaturemask (uint) 683 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 684 * The default is the current set of stable display features. 685 */ 686 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 687 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 688 689 static const struct pci_device_id pciidlist[] = { 690 #ifdef CONFIG_DRM_AMDGPU_SI 691 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 692 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 693 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 694 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 695 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 696 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 697 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 698 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 699 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 700 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 701 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 702 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 703 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 704 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 705 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 706 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 707 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 708 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 709 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 710 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 711 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 712 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 713 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 714 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 715 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 716 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 717 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 718 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 719 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 720 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 721 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 722 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 723 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 724 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 725 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 726 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 727 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 728 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 729 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 730 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 731 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 732 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 733 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 734 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 735 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 736 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 737 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 738 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 739 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 740 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 741 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 742 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 743 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 744 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 745 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 746 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 747 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 748 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 749 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 750 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 751 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 752 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 753 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 754 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 755 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 756 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 757 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 758 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 759 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 760 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 761 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 762 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 763 #endif 764 #ifdef CONFIG_DRM_AMDGPU_CIK 765 /* Kaveri */ 766 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 767 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 768 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 769 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 770 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 771 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 772 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 773 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 774 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 775 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 776 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 777 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 778 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 779 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 780 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 781 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 782 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 783 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 784 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 785 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 786 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 787 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 788 /* Bonaire */ 789 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 790 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 791 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 792 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 793 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 794 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 795 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 796 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 797 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 798 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 799 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 800 /* Hawaii */ 801 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 802 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 803 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 804 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 805 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 806 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 807 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 808 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 809 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 810 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 811 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 812 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 813 /* Kabini */ 814 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 815 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 816 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 817 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 818 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 819 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 820 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 821 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 822 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 823 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 824 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 825 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 826 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 827 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 828 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 829 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 830 /* mullins */ 831 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 832 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 833 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 834 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 835 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 836 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 837 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 838 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 839 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 840 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 841 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 842 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 843 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 844 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 845 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 846 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 847 #endif 848 /* topaz */ 849 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 850 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 851 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 852 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 853 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 854 /* tonga */ 855 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 856 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 857 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 858 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 859 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 860 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 861 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 862 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 863 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 864 /* fiji */ 865 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 866 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 867 /* carrizo */ 868 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 869 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 870 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 871 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 872 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 873 /* stoney */ 874 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 875 /* Polaris11 */ 876 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 877 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 878 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 879 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 880 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 881 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 882 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 883 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 884 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 885 /* Polaris10 */ 886 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 887 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 888 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 889 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 890 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 891 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 892 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 893 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 894 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 895 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 896 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 897 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 898 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 899 /* Polaris12 */ 900 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 901 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 902 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 903 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 904 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 905 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 906 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 907 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 908 /* VEGAM */ 909 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 910 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 911 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 912 /* Vega 10 */ 913 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 914 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 915 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 916 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 917 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 918 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 919 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 920 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 921 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 922 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 923 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 924 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 925 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 926 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 927 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 928 /* Vega 12 */ 929 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 930 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 931 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 932 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 933 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 934 /* Vega 20 */ 935 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 936 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 937 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 938 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 939 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 940 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 941 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 942 /* Raven */ 943 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 944 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 945 946 {0, 0, 0} 947 }; 948 949 MODULE_DEVICE_TABLE(pci, pciidlist); 950 951 static struct drm_driver kms_driver; 952 953 static int amdgpu_pci_probe(struct pci_dev *pdev, 954 const struct pci_device_id *ent) 955 { 956 struct drm_device *dev; 957 unsigned long flags = ent->driver_data; 958 int ret, retry = 0; 959 bool supports_atomic = false; 960 961 if (!amdgpu_virtual_display && 962 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 963 supports_atomic = true; 964 965 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 966 DRM_INFO("This hardware requires experimental hardware support.\n" 967 "See modparam exp_hw_support\n"); 968 return -ENODEV; 969 } 970 971 /* Get rid of things like offb */ 972 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 973 if (ret) 974 return ret; 975 976 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 977 if (IS_ERR(dev)) 978 return PTR_ERR(dev); 979 980 if (!supports_atomic) 981 dev->driver_features &= ~DRIVER_ATOMIC; 982 983 ret = pci_enable_device(pdev); 984 if (ret) 985 goto err_free; 986 987 dev->pdev = pdev; 988 989 pci_set_drvdata(pdev, dev); 990 991 retry_init: 992 ret = drm_dev_register(dev, ent->driver_data); 993 if (ret == -EAGAIN && ++retry <= 3) { 994 DRM_INFO("retry init %d\n", retry); 995 /* Don't request EX mode too frequently which is attacking */ 996 msleep(5000); 997 goto retry_init; 998 } else if (ret) 999 goto err_pci; 1000 1001 return 0; 1002 1003 err_pci: 1004 pci_disable_device(pdev); 1005 err_free: 1006 drm_dev_put(dev); 1007 return ret; 1008 } 1009 1010 static void 1011 amdgpu_pci_remove(struct pci_dev *pdev) 1012 { 1013 struct drm_device *dev = pci_get_drvdata(pdev); 1014 1015 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 1016 drm_dev_unplug(dev); 1017 drm_dev_put(dev); 1018 pci_disable_device(pdev); 1019 pci_set_drvdata(pdev, NULL); 1020 } 1021 1022 static void 1023 amdgpu_pci_shutdown(struct pci_dev *pdev) 1024 { 1025 struct drm_device *dev = pci_get_drvdata(pdev); 1026 struct amdgpu_device *adev = dev->dev_private; 1027 1028 /* if we are running in a VM, make sure the device 1029 * torn down properly on reboot/shutdown. 1030 * unfortunately we can't detect certain 1031 * hypervisors so just do this all the time. 1032 */ 1033 amdgpu_device_ip_suspend(adev); 1034 } 1035 1036 static int amdgpu_pmops_suspend(struct device *dev) 1037 { 1038 struct pci_dev *pdev = to_pci_dev(dev); 1039 1040 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1041 return amdgpu_device_suspend(drm_dev, true, true); 1042 } 1043 1044 static int amdgpu_pmops_resume(struct device *dev) 1045 { 1046 struct pci_dev *pdev = to_pci_dev(dev); 1047 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1048 1049 /* GPU comes up enabled by the bios on resume */ 1050 if (amdgpu_device_is_px(drm_dev)) { 1051 pm_runtime_disable(dev); 1052 pm_runtime_set_active(dev); 1053 pm_runtime_enable(dev); 1054 } 1055 1056 return amdgpu_device_resume(drm_dev, true, true); 1057 } 1058 1059 static int amdgpu_pmops_freeze(struct device *dev) 1060 { 1061 struct pci_dev *pdev = to_pci_dev(dev); 1062 1063 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1064 return amdgpu_device_suspend(drm_dev, false, true); 1065 } 1066 1067 static int amdgpu_pmops_thaw(struct device *dev) 1068 { 1069 struct pci_dev *pdev = to_pci_dev(dev); 1070 1071 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1072 return amdgpu_device_resume(drm_dev, false, true); 1073 } 1074 1075 static int amdgpu_pmops_poweroff(struct device *dev) 1076 { 1077 struct pci_dev *pdev = to_pci_dev(dev); 1078 1079 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1080 return amdgpu_device_suspend(drm_dev, true, true); 1081 } 1082 1083 static int amdgpu_pmops_restore(struct device *dev) 1084 { 1085 struct pci_dev *pdev = to_pci_dev(dev); 1086 1087 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1088 return amdgpu_device_resume(drm_dev, false, true); 1089 } 1090 1091 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1092 { 1093 struct pci_dev *pdev = to_pci_dev(dev); 1094 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1095 int ret; 1096 1097 if (!amdgpu_device_is_px(drm_dev)) { 1098 pm_runtime_forbid(dev); 1099 return -EBUSY; 1100 } 1101 1102 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1103 drm_kms_helper_poll_disable(drm_dev); 1104 1105 ret = amdgpu_device_suspend(drm_dev, false, false); 1106 pci_save_state(pdev); 1107 pci_disable_device(pdev); 1108 pci_ignore_hotplug(pdev); 1109 if (amdgpu_is_atpx_hybrid()) 1110 pci_set_power_state(pdev, PCI_D3cold); 1111 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1112 pci_set_power_state(pdev, PCI_D3hot); 1113 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1114 1115 return 0; 1116 } 1117 1118 static int amdgpu_pmops_runtime_resume(struct device *dev) 1119 { 1120 struct pci_dev *pdev = to_pci_dev(dev); 1121 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1122 int ret; 1123 1124 if (!amdgpu_device_is_px(drm_dev)) 1125 return -EINVAL; 1126 1127 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1128 1129 if (amdgpu_is_atpx_hybrid() || 1130 !amdgpu_has_atpx_dgpu_power_cntl()) 1131 pci_set_power_state(pdev, PCI_D0); 1132 pci_restore_state(pdev); 1133 ret = pci_enable_device(pdev); 1134 if (ret) 1135 return ret; 1136 pci_set_master(pdev); 1137 1138 ret = amdgpu_device_resume(drm_dev, false, false); 1139 drm_kms_helper_poll_enable(drm_dev); 1140 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1141 return 0; 1142 } 1143 1144 static int amdgpu_pmops_runtime_idle(struct device *dev) 1145 { 1146 struct pci_dev *pdev = to_pci_dev(dev); 1147 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1148 struct drm_crtc *crtc; 1149 1150 if (!amdgpu_device_is_px(drm_dev)) { 1151 pm_runtime_forbid(dev); 1152 return -EBUSY; 1153 } 1154 1155 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1156 if (crtc->enabled) { 1157 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1158 return -EBUSY; 1159 } 1160 } 1161 1162 pm_runtime_mark_last_busy(dev); 1163 pm_runtime_autosuspend(dev); 1164 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1165 return 1; 1166 } 1167 1168 long amdgpu_drm_ioctl(struct file *filp, 1169 unsigned int cmd, unsigned long arg) 1170 { 1171 struct drm_file *file_priv = filp->private_data; 1172 struct drm_device *dev; 1173 long ret; 1174 dev = file_priv->minor->dev; 1175 ret = pm_runtime_get_sync(dev->dev); 1176 if (ret < 0) 1177 return ret; 1178 1179 ret = drm_ioctl(filp, cmd, arg); 1180 1181 pm_runtime_mark_last_busy(dev->dev); 1182 pm_runtime_put_autosuspend(dev->dev); 1183 return ret; 1184 } 1185 1186 static const struct dev_pm_ops amdgpu_pm_ops = { 1187 .suspend = amdgpu_pmops_suspend, 1188 .resume = amdgpu_pmops_resume, 1189 .freeze = amdgpu_pmops_freeze, 1190 .thaw = amdgpu_pmops_thaw, 1191 .poweroff = amdgpu_pmops_poweroff, 1192 .restore = amdgpu_pmops_restore, 1193 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1194 .runtime_resume = amdgpu_pmops_runtime_resume, 1195 .runtime_idle = amdgpu_pmops_runtime_idle, 1196 }; 1197 1198 static int amdgpu_flush(struct file *f, fl_owner_t id) 1199 { 1200 struct drm_file *file_priv = f->private_data; 1201 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1202 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1203 1204 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1205 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1206 1207 return timeout >= 0 ? 0 : timeout; 1208 } 1209 1210 static const struct file_operations amdgpu_driver_kms_fops = { 1211 .owner = THIS_MODULE, 1212 .open = drm_open, 1213 .flush = amdgpu_flush, 1214 .release = drm_release, 1215 .unlocked_ioctl = amdgpu_drm_ioctl, 1216 .mmap = amdgpu_mmap, 1217 .poll = drm_poll, 1218 .read = drm_read, 1219 #ifdef CONFIG_COMPAT 1220 .compat_ioctl = amdgpu_kms_compat_ioctl, 1221 #endif 1222 }; 1223 1224 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1225 { 1226 struct drm_file *file; 1227 1228 if (!filp) 1229 return -EINVAL; 1230 1231 if (filp->f_op != &amdgpu_driver_kms_fops) { 1232 return -EINVAL; 1233 } 1234 1235 file = filp->private_data; 1236 *fpriv = file->driver_priv; 1237 return 0; 1238 } 1239 1240 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 1241 { 1242 char *input = amdgpu_lockup_timeout; 1243 char *timeout_setting = NULL; 1244 int index = 0; 1245 long timeout; 1246 int ret = 0; 1247 1248 /* 1249 * By default timeout for non compute jobs is 10000. 1250 * And there is no timeout enforced on compute jobs. 1251 */ 1252 adev->gfx_timeout = adev->sdma_timeout = adev->video_timeout = 10000; 1253 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; 1254 1255 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1256 while ((timeout_setting = strsep(&input, ",")) && 1257 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1258 ret = kstrtol(timeout_setting, 0, &timeout); 1259 if (ret) 1260 return ret; 1261 1262 /* Invalidate 0 and negative values */ 1263 if (timeout <= 0) { 1264 index++; 1265 continue; 1266 } 1267 1268 switch (index++) { 1269 case 0: 1270 adev->gfx_timeout = timeout; 1271 break; 1272 case 1: 1273 adev->compute_timeout = timeout; 1274 break; 1275 case 2: 1276 adev->sdma_timeout = timeout; 1277 break; 1278 case 3: 1279 adev->video_timeout = timeout; 1280 break; 1281 default: 1282 break; 1283 } 1284 } 1285 /* 1286 * There is only one value specified and 1287 * it should apply to all non-compute jobs. 1288 */ 1289 if (index == 1) 1290 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1291 } 1292 1293 return ret; 1294 } 1295 1296 static bool 1297 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1298 bool in_vblank_irq, int *vpos, int *hpos, 1299 ktime_t *stime, ktime_t *etime, 1300 const struct drm_display_mode *mode) 1301 { 1302 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1303 stime, etime, mode); 1304 } 1305 1306 static struct drm_driver kms_driver = { 1307 .driver_features = 1308 DRIVER_USE_AGP | DRIVER_ATOMIC | 1309 DRIVER_GEM | 1310 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1311 DRIVER_SYNCOBJ_TIMELINE, 1312 .load = amdgpu_driver_load_kms, 1313 .open = amdgpu_driver_open_kms, 1314 .postclose = amdgpu_driver_postclose_kms, 1315 .lastclose = amdgpu_driver_lastclose_kms, 1316 .unload = amdgpu_driver_unload_kms, 1317 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1318 .enable_vblank = amdgpu_enable_vblank_kms, 1319 .disable_vblank = amdgpu_disable_vblank_kms, 1320 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1321 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1322 .irq_handler = amdgpu_irq_handler, 1323 .ioctls = amdgpu_ioctls_kms, 1324 .gem_free_object_unlocked = amdgpu_gem_object_free, 1325 .gem_open_object = amdgpu_gem_object_open, 1326 .gem_close_object = amdgpu_gem_object_close, 1327 .dumb_create = amdgpu_mode_dumb_create, 1328 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1329 .fops = &amdgpu_driver_kms_fops, 1330 1331 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1332 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1333 .gem_prime_export = amdgpu_gem_prime_export, 1334 .gem_prime_import = amdgpu_gem_prime_import, 1335 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1336 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1337 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1338 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1339 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1340 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1341 1342 .name = DRIVER_NAME, 1343 .desc = DRIVER_DESC, 1344 .date = DRIVER_DATE, 1345 .major = KMS_DRIVER_MAJOR, 1346 .minor = KMS_DRIVER_MINOR, 1347 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1348 }; 1349 1350 static struct pci_driver amdgpu_kms_pci_driver = { 1351 .name = DRIVER_NAME, 1352 .id_table = pciidlist, 1353 .probe = amdgpu_pci_probe, 1354 .remove = amdgpu_pci_remove, 1355 .shutdown = amdgpu_pci_shutdown, 1356 .driver.pm = &amdgpu_pm_ops, 1357 }; 1358 1359 1360 1361 static int __init amdgpu_init(void) 1362 { 1363 int r; 1364 1365 if (vgacon_text_force()) { 1366 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1367 return -EINVAL; 1368 } 1369 1370 r = amdgpu_sync_init(); 1371 if (r) 1372 goto error_sync; 1373 1374 r = amdgpu_fence_slab_init(); 1375 if (r) 1376 goto error_fence; 1377 1378 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1379 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1380 amdgpu_register_atpx_handler(); 1381 1382 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1383 amdgpu_amdkfd_init(); 1384 1385 /* let modprobe override vga console setting */ 1386 return pci_register_driver(&amdgpu_kms_pci_driver); 1387 1388 error_fence: 1389 amdgpu_sync_fini(); 1390 1391 error_sync: 1392 return r; 1393 } 1394 1395 static void __exit amdgpu_exit(void) 1396 { 1397 amdgpu_amdkfd_fini(); 1398 pci_unregister_driver(&amdgpu_kms_pci_driver); 1399 amdgpu_unregister_atpx_handler(); 1400 amdgpu_sync_fini(); 1401 amdgpu_fence_slab_fini(); 1402 } 1403 1404 module_init(amdgpu_init); 1405 module_exit(amdgpu_exit); 1406 1407 MODULE_AUTHOR(DRIVER_AUTHOR); 1408 MODULE_DESCRIPTION(DRIVER_DESC); 1409 MODULE_LICENSE("GPL and additional rights"); 1410