1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/cc_platform.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 */ 103 #define KMS_DRIVER_MAJOR 3 104 #define KMS_DRIVER_MINOR 44 105 #define KMS_DRIVER_PATCHLEVEL 0 106 107 int amdgpu_vram_limit; 108 int amdgpu_vis_vram_limit; 109 int amdgpu_gart_size = -1; /* auto */ 110 int amdgpu_gtt_size = -1; /* auto */ 111 int amdgpu_moverate = -1; /* auto */ 112 int amdgpu_benchmarking; 113 int amdgpu_testing; 114 int amdgpu_audio = -1; 115 int amdgpu_disp_priority; 116 int amdgpu_hw_i2c; 117 int amdgpu_pcie_gen2 = -1; 118 int amdgpu_msi = -1; 119 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 120 int amdgpu_dpm = -1; 121 int amdgpu_fw_load_type = -1; 122 int amdgpu_aspm = -1; 123 int amdgpu_runtime_pm = -1; 124 uint amdgpu_ip_block_mask = 0xffffffff; 125 int amdgpu_bapm = -1; 126 int amdgpu_deep_color; 127 int amdgpu_vm_size = -1; 128 int amdgpu_vm_fragment_size = -1; 129 int amdgpu_vm_block_size = -1; 130 int amdgpu_vm_fault_stop; 131 int amdgpu_vm_debug; 132 int amdgpu_vm_update_mode = -1; 133 int amdgpu_exp_hw_support; 134 int amdgpu_dc = -1; 135 int amdgpu_sched_jobs = 32; 136 int amdgpu_sched_hw_submission = 2; 137 uint amdgpu_pcie_gen_cap; 138 uint amdgpu_pcie_lane_cap; 139 uint amdgpu_cg_mask = 0xffffffff; 140 uint amdgpu_pg_mask = 0xffffffff; 141 uint amdgpu_sdma_phase_quantum = 32; 142 char *amdgpu_disable_cu = NULL; 143 char *amdgpu_virtual_display = NULL; 144 145 /* 146 * OverDrive(bit 14) disabled by default 147 * GFX DCS(bit 19) disabled by default 148 */ 149 uint amdgpu_pp_feature_mask = 0xfff7bfff; 150 uint amdgpu_force_long_training; 151 int amdgpu_job_hang_limit; 152 int amdgpu_lbpw = -1; 153 int amdgpu_compute_multipipe = -1; 154 int amdgpu_gpu_recovery = -1; /* auto */ 155 int amdgpu_emu_mode; 156 uint amdgpu_smu_memory_pool_size; 157 int amdgpu_smu_pptable_id = -1; 158 /* 159 * FBC (bit 0) disabled by default 160 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 161 * - With this, for multiple monitors in sync(e.g. with the same model), 162 * mclk switching will be allowed. And the mclk will be not foced to the 163 * highest. That helps saving some idle power. 164 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 165 * PSR (bit 3) disabled by default 166 * EDP NO POWER SEQUENCING (bit 4) disabled by default 167 */ 168 uint amdgpu_dc_feature_mask = 2; 169 uint amdgpu_dc_debug_mask; 170 int amdgpu_async_gfx_ring = 1; 171 int amdgpu_mcbp; 172 int amdgpu_discovery = -1; 173 int amdgpu_mes; 174 int amdgpu_noretry = -1; 175 int amdgpu_force_asic_type = -1; 176 int amdgpu_tmz = -1; /* auto */ 177 uint amdgpu_freesync_vid_mode; 178 int amdgpu_reset_method = -1; /* auto */ 179 int amdgpu_num_kcq = -1; 180 int amdgpu_smartshift_bias; 181 182 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 183 184 struct amdgpu_mgpu_info mgpu_info = { 185 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 186 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 187 mgpu_info.delayed_reset_work, 188 amdgpu_drv_delayed_reset_work_handler, 0), 189 }; 190 int amdgpu_ras_enable = -1; 191 uint amdgpu_ras_mask = 0xffffffff; 192 int amdgpu_bad_page_threshold = -1; 193 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 194 .timeout_fatal_disable = false, 195 .period = 0x0, /* default to 0x0 (timeout disable) */ 196 }; 197 198 /** 199 * DOC: vramlimit (int) 200 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 201 */ 202 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 203 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 204 205 /** 206 * DOC: vis_vramlimit (int) 207 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 208 */ 209 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 210 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 211 212 /** 213 * DOC: gartsize (uint) 214 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 215 */ 216 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 217 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 218 219 /** 220 * DOC: gttsize (int) 221 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 222 * otherwise 3/4 RAM size). 223 */ 224 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 225 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 226 227 /** 228 * DOC: moverate (int) 229 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 230 */ 231 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 232 module_param_named(moverate, amdgpu_moverate, int, 0600); 233 234 /** 235 * DOC: benchmark (int) 236 * Run benchmarks. The default is 0 (Skip benchmarks). 237 */ 238 MODULE_PARM_DESC(benchmark, "Run benchmark"); 239 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 240 241 /** 242 * DOC: test (int) 243 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 244 */ 245 MODULE_PARM_DESC(test, "Run tests"); 246 module_param_named(test, amdgpu_testing, int, 0444); 247 248 /** 249 * DOC: audio (int) 250 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 251 */ 252 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 253 module_param_named(audio, amdgpu_audio, int, 0444); 254 255 /** 256 * DOC: disp_priority (int) 257 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 258 */ 259 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 260 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 261 262 /** 263 * DOC: hw_i2c (int) 264 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 265 */ 266 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 267 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 268 269 /** 270 * DOC: pcie_gen2 (int) 271 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 272 */ 273 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 274 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 275 276 /** 277 * DOC: msi (int) 278 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 279 */ 280 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 281 module_param_named(msi, amdgpu_msi, int, 0444); 282 283 /** 284 * DOC: lockup_timeout (string) 285 * Set GPU scheduler timeout value in ms. 286 * 287 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 288 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 289 * to the default timeout. 290 * 291 * - With one value specified, the setting will apply to all non-compute jobs. 292 * - With multiple values specified, the first one will be for GFX. 293 * The second one is for Compute. The third and fourth ones are 294 * for SDMA and Video. 295 * 296 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 297 * jobs is 10000. The timeout for compute is 60000. 298 */ 299 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 300 "for passthrough or sriov, 10000 for all jobs." 301 " 0: keep default value. negative: infinity timeout), " 302 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 303 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 304 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 305 306 /** 307 * DOC: dpm (int) 308 * Override for dynamic power management setting 309 * (0 = disable, 1 = enable) 310 * The default is -1 (auto). 311 */ 312 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 313 module_param_named(dpm, amdgpu_dpm, int, 0444); 314 315 /** 316 * DOC: fw_load_type (int) 317 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 318 */ 319 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 320 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 321 322 /** 323 * DOC: aspm (int) 324 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 325 */ 326 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 327 module_param_named(aspm, amdgpu_aspm, int, 0444); 328 329 /** 330 * DOC: runpm (int) 331 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 332 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 333 * Setting the value to 0 disables this functionality. 334 */ 335 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 336 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 337 338 /** 339 * DOC: ip_block_mask (uint) 340 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 341 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 342 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 343 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 344 */ 345 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 346 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 347 348 /** 349 * DOC: bapm (int) 350 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 351 * The default -1 (auto, enabled) 352 */ 353 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 354 module_param_named(bapm, amdgpu_bapm, int, 0444); 355 356 /** 357 * DOC: deep_color (int) 358 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 359 */ 360 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 361 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 362 363 /** 364 * DOC: vm_size (int) 365 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 366 */ 367 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 368 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 369 370 /** 371 * DOC: vm_fragment_size (int) 372 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 373 */ 374 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 375 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 376 377 /** 378 * DOC: vm_block_size (int) 379 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 380 */ 381 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 382 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 383 384 /** 385 * DOC: vm_fault_stop (int) 386 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 387 */ 388 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 389 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 390 391 /** 392 * DOC: vm_debug (int) 393 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 394 */ 395 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 396 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 397 398 /** 399 * DOC: vm_update_mode (int) 400 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 401 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 402 */ 403 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 404 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 405 406 /** 407 * DOC: exp_hw_support (int) 408 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 409 */ 410 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 411 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 412 413 /** 414 * DOC: dc (int) 415 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 416 */ 417 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 418 module_param_named(dc, amdgpu_dc, int, 0444); 419 420 /** 421 * DOC: sched_jobs (int) 422 * Override the max number of jobs supported in the sw queue. The default is 32. 423 */ 424 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 425 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 426 427 /** 428 * DOC: sched_hw_submission (int) 429 * Override the max number of HW submissions. The default is 2. 430 */ 431 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 432 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 433 434 /** 435 * DOC: ppfeaturemask (hexint) 436 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 437 * The default is the current set of stable power features. 438 */ 439 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 440 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 441 442 /** 443 * DOC: forcelongtraining (uint) 444 * Force long memory training in resume. 445 * The default is zero, indicates short training in resume. 446 */ 447 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 448 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 449 450 /** 451 * DOC: pcie_gen_cap (uint) 452 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 453 * The default is 0 (automatic for each asic). 454 */ 455 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 456 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 457 458 /** 459 * DOC: pcie_lane_cap (uint) 460 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 461 * The default is 0 (automatic for each asic). 462 */ 463 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 464 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 465 466 /** 467 * DOC: cg_mask (uint) 468 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 469 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 470 */ 471 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 472 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 473 474 /** 475 * DOC: pg_mask (uint) 476 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 477 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 478 */ 479 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 480 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 481 482 /** 483 * DOC: sdma_phase_quantum (uint) 484 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 485 */ 486 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 487 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 488 489 /** 490 * DOC: disable_cu (charp) 491 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 492 */ 493 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 494 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 495 496 /** 497 * DOC: virtual_display (charp) 498 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 499 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 500 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 501 * device at 26:00.0. The default is NULL. 502 */ 503 MODULE_PARM_DESC(virtual_display, 504 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 505 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 506 507 /** 508 * DOC: job_hang_limit (int) 509 * Set how much time allow a job hang and not drop it. The default is 0. 510 */ 511 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 512 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 513 514 /** 515 * DOC: lbpw (int) 516 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 517 */ 518 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 519 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 520 521 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 522 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 523 524 /** 525 * DOC: gpu_recovery (int) 526 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 527 */ 528 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 529 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 530 531 /** 532 * DOC: emu_mode (int) 533 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 534 */ 535 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 536 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 537 538 /** 539 * DOC: ras_enable (int) 540 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 541 */ 542 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 543 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 544 545 /** 546 * DOC: ras_mask (uint) 547 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 548 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 549 */ 550 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 551 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 552 553 /** 554 * DOC: timeout_fatal_disable (bool) 555 * Disable Watchdog timeout fatal error event 556 */ 557 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 558 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 559 560 /** 561 * DOC: timeout_period (uint) 562 * Modify the watchdog timeout max_cycles as (1 << period) 563 */ 564 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 565 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 566 567 /** 568 * DOC: si_support (int) 569 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 570 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 571 * otherwise using amdgpu driver. 572 */ 573 #ifdef CONFIG_DRM_AMDGPU_SI 574 575 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 576 int amdgpu_si_support = 0; 577 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 578 #else 579 int amdgpu_si_support = 1; 580 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 581 #endif 582 583 module_param_named(si_support, amdgpu_si_support, int, 0444); 584 #endif 585 586 /** 587 * DOC: cik_support (int) 588 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 589 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 590 * otherwise using amdgpu driver. 591 */ 592 #ifdef CONFIG_DRM_AMDGPU_CIK 593 594 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 595 int amdgpu_cik_support = 0; 596 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 597 #else 598 int amdgpu_cik_support = 1; 599 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 600 #endif 601 602 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 603 #endif 604 605 /** 606 * DOC: smu_memory_pool_size (uint) 607 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 608 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 609 */ 610 MODULE_PARM_DESC(smu_memory_pool_size, 611 "reserve gtt for smu debug usage, 0 = disable," 612 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 613 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 614 615 /** 616 * DOC: async_gfx_ring (int) 617 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 618 */ 619 MODULE_PARM_DESC(async_gfx_ring, 620 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 621 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 622 623 /** 624 * DOC: mcbp (int) 625 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 626 */ 627 MODULE_PARM_DESC(mcbp, 628 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 629 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 630 631 /** 632 * DOC: discovery (int) 633 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 634 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 635 */ 636 MODULE_PARM_DESC(discovery, 637 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 638 module_param_named(discovery, amdgpu_discovery, int, 0444); 639 640 /** 641 * DOC: mes (int) 642 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 643 * (0 = disabled (default), 1 = enabled) 644 */ 645 MODULE_PARM_DESC(mes, 646 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 647 module_param_named(mes, amdgpu_mes, int, 0444); 648 649 /** 650 * DOC: noretry (int) 651 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 652 * do not support per-process XNACK this also disables retry page faults. 653 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 654 */ 655 MODULE_PARM_DESC(noretry, 656 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 657 module_param_named(noretry, amdgpu_noretry, int, 0644); 658 659 /** 660 * DOC: force_asic_type (int) 661 * A non negative value used to specify the asic type for all supported GPUs. 662 */ 663 MODULE_PARM_DESC(force_asic_type, 664 "A non negative value used to specify the asic type for all supported GPUs"); 665 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 666 667 668 669 #ifdef CONFIG_HSA_AMD 670 /** 671 * DOC: sched_policy (int) 672 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 673 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 674 * assigns queues to HQDs. 675 */ 676 int sched_policy = KFD_SCHED_POLICY_HWS; 677 module_param(sched_policy, int, 0444); 678 MODULE_PARM_DESC(sched_policy, 679 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 680 681 /** 682 * DOC: hws_max_conc_proc (int) 683 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 684 * number of VMIDs assigned to the HWS, which is also the default. 685 */ 686 int hws_max_conc_proc = 8; 687 module_param(hws_max_conc_proc, int, 0444); 688 MODULE_PARM_DESC(hws_max_conc_proc, 689 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 690 691 /** 692 * DOC: cwsr_enable (int) 693 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 694 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 695 * disables it. 696 */ 697 int cwsr_enable = 1; 698 module_param(cwsr_enable, int, 0444); 699 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 700 701 /** 702 * DOC: max_num_of_queues_per_device (int) 703 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 704 * is 4096. 705 */ 706 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 707 module_param(max_num_of_queues_per_device, int, 0444); 708 MODULE_PARM_DESC(max_num_of_queues_per_device, 709 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 710 711 /** 712 * DOC: send_sigterm (int) 713 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 714 * but just print errors on dmesg. Setting 1 enables sending sigterm. 715 */ 716 int send_sigterm; 717 module_param(send_sigterm, int, 0444); 718 MODULE_PARM_DESC(send_sigterm, 719 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 720 721 /** 722 * DOC: debug_largebar (int) 723 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 724 * system. This limits the VRAM size reported to ROCm applications to the visible 725 * size, usually 256MB. 726 * Default value is 0, diabled. 727 */ 728 int debug_largebar; 729 module_param(debug_largebar, int, 0444); 730 MODULE_PARM_DESC(debug_largebar, 731 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 732 733 /** 734 * DOC: ignore_crat (int) 735 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 736 * table to get information about AMD APUs. This option can serve as a workaround on 737 * systems with a broken CRAT table. 738 * 739 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 740 * whehter use CRAT) 741 */ 742 int ignore_crat; 743 module_param(ignore_crat, int, 0444); 744 MODULE_PARM_DESC(ignore_crat, 745 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 746 747 /** 748 * DOC: halt_if_hws_hang (int) 749 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 750 * Setting 1 enables halt on hang. 751 */ 752 int halt_if_hws_hang; 753 module_param(halt_if_hws_hang, int, 0644); 754 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 755 756 /** 757 * DOC: hws_gws_support(bool) 758 * Assume that HWS supports GWS barriers regardless of what firmware version 759 * check says. Default value: false (rely on MEC2 firmware version check). 760 */ 761 bool hws_gws_support; 762 module_param(hws_gws_support, bool, 0444); 763 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 764 765 /** 766 * DOC: queue_preemption_timeout_ms (int) 767 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 768 */ 769 int queue_preemption_timeout_ms = 9000; 770 module_param(queue_preemption_timeout_ms, int, 0644); 771 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 772 773 /** 774 * DOC: debug_evictions(bool) 775 * Enable extra debug messages to help determine the cause of evictions 776 */ 777 bool debug_evictions; 778 module_param(debug_evictions, bool, 0644); 779 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 780 781 /** 782 * DOC: no_system_mem_limit(bool) 783 * Disable system memory limit, to support multiple process shared memory 784 */ 785 bool no_system_mem_limit; 786 module_param(no_system_mem_limit, bool, 0644); 787 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 788 789 /** 790 * DOC: no_queue_eviction_on_vm_fault (int) 791 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 792 */ 793 int amdgpu_no_queue_eviction_on_vm_fault = 0; 794 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 795 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 796 #endif 797 798 /** 799 * DOC: dcfeaturemask (uint) 800 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 801 * The default is the current set of stable display features. 802 */ 803 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 804 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 805 806 /** 807 * DOC: dcdebugmask (uint) 808 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 809 */ 810 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 811 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 812 813 /** 814 * DOC: abmlevel (uint) 815 * Override the default ABM (Adaptive Backlight Management) level used for DC 816 * enabled hardware. Requires DMCU to be supported and loaded. 817 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 818 * default. Values 1-4 control the maximum allowable brightness reduction via 819 * the ABM algorithm, with 1 being the least reduction and 4 being the most 820 * reduction. 821 * 822 * Defaults to 0, or disabled. Userspace can still override this level later 823 * after boot. 824 */ 825 uint amdgpu_dm_abm_level; 826 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 827 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 828 829 int amdgpu_backlight = -1; 830 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 831 module_param_named(backlight, amdgpu_backlight, bint, 0444); 832 833 /** 834 * DOC: tmz (int) 835 * Trusted Memory Zone (TMZ) is a method to protect data being written 836 * to or read from memory. 837 * 838 * The default value: 0 (off). TODO: change to auto till it is completed. 839 */ 840 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 841 module_param_named(tmz, amdgpu_tmz, int, 0444); 842 843 /** 844 * DOC: freesync_video (uint) 845 * Enable the optimization to adjust front porch timing to achieve seamless 846 * mode change experience when setting a freesync supported mode for which full 847 * modeset is not needed. 848 * 849 * The Display Core will add a set of modes derived from the base FreeSync 850 * video mode into the corresponding connector's mode list based on commonly 851 * used refresh rates and VRR range of the connected display, when users enable 852 * this feature. From the userspace perspective, they can see a seamless mode 853 * change experience when the change between different refresh rates under the 854 * same resolution. Additionally, userspace applications such as Video playback 855 * can read this modeset list and change the refresh rate based on the video 856 * frame rate. Finally, the userspace can also derive an appropriate mode for a 857 * particular refresh rate based on the FreeSync Mode and add it to the 858 * connector's mode list. 859 * 860 * Note: This is an experimental feature. 861 * 862 * The default value: 0 (off). 863 */ 864 MODULE_PARM_DESC( 865 freesync_video, 866 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 867 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 868 869 /** 870 * DOC: reset_method (int) 871 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 872 */ 873 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 874 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 875 876 /** 877 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 878 * threshold value of faulty pages detected by RAS ECC, which may 879 * result in the GPU entering bad status when the number of total 880 * faulty pages by ECC exceeds the threshold value. 881 */ 882 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 883 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 884 885 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 886 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 887 888 /** 889 * DOC: smu_pptable_id (int) 890 * Used to override pptable id. id = 0 use VBIOS pptable. 891 * id > 0 use the soft pptable with specicfied id. 892 */ 893 MODULE_PARM_DESC(smu_pptable_id, 894 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 895 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 896 897 /* These devices are not supported by amdgpu. 898 * They are supported by the mach64, r128, radeon drivers 899 */ 900 static const u16 amdgpu_unsupported_pciidlist[] = { 901 /* mach64 */ 902 0x4354, 903 0x4358, 904 0x4554, 905 0x4742, 906 0x4744, 907 0x4749, 908 0x474C, 909 0x474D, 910 0x474E, 911 0x474F, 912 0x4750, 913 0x4751, 914 0x4752, 915 0x4753, 916 0x4754, 917 0x4755, 918 0x4756, 919 0x4757, 920 0x4758, 921 0x4759, 922 0x475A, 923 0x4C42, 924 0x4C44, 925 0x4C47, 926 0x4C49, 927 0x4C4D, 928 0x4C4E, 929 0x4C50, 930 0x4C51, 931 0x4C52, 932 0x4C53, 933 0x5654, 934 0x5655, 935 0x5656, 936 /* r128 */ 937 0x4c45, 938 0x4c46, 939 0x4d46, 940 0x4d4c, 941 0x5041, 942 0x5042, 943 0x5043, 944 0x5044, 945 0x5045, 946 0x5046, 947 0x5047, 948 0x5048, 949 0x5049, 950 0x504A, 951 0x504B, 952 0x504C, 953 0x504D, 954 0x504E, 955 0x504F, 956 0x5050, 957 0x5051, 958 0x5052, 959 0x5053, 960 0x5054, 961 0x5055, 962 0x5056, 963 0x5057, 964 0x5058, 965 0x5245, 966 0x5246, 967 0x5247, 968 0x524b, 969 0x524c, 970 0x534d, 971 0x5446, 972 0x544C, 973 0x5452, 974 /* radeon */ 975 0x3150, 976 0x3151, 977 0x3152, 978 0x3154, 979 0x3155, 980 0x3E50, 981 0x3E54, 982 0x4136, 983 0x4137, 984 0x4144, 985 0x4145, 986 0x4146, 987 0x4147, 988 0x4148, 989 0x4149, 990 0x414A, 991 0x414B, 992 0x4150, 993 0x4151, 994 0x4152, 995 0x4153, 996 0x4154, 997 0x4155, 998 0x4156, 999 0x4237, 1000 0x4242, 1001 0x4336, 1002 0x4337, 1003 0x4437, 1004 0x4966, 1005 0x4967, 1006 0x4A48, 1007 0x4A49, 1008 0x4A4A, 1009 0x4A4B, 1010 0x4A4C, 1011 0x4A4D, 1012 0x4A4E, 1013 0x4A4F, 1014 0x4A50, 1015 0x4A54, 1016 0x4B48, 1017 0x4B49, 1018 0x4B4A, 1019 0x4B4B, 1020 0x4B4C, 1021 0x4C57, 1022 0x4C58, 1023 0x4C59, 1024 0x4C5A, 1025 0x4C64, 1026 0x4C66, 1027 0x4C67, 1028 0x4E44, 1029 0x4E45, 1030 0x4E46, 1031 0x4E47, 1032 0x4E48, 1033 0x4E49, 1034 0x4E4A, 1035 0x4E4B, 1036 0x4E50, 1037 0x4E51, 1038 0x4E52, 1039 0x4E53, 1040 0x4E54, 1041 0x4E56, 1042 0x5144, 1043 0x5145, 1044 0x5146, 1045 0x5147, 1046 0x5148, 1047 0x514C, 1048 0x514D, 1049 0x5157, 1050 0x5158, 1051 0x5159, 1052 0x515A, 1053 0x515E, 1054 0x5460, 1055 0x5462, 1056 0x5464, 1057 0x5548, 1058 0x5549, 1059 0x554A, 1060 0x554B, 1061 0x554C, 1062 0x554D, 1063 0x554E, 1064 0x554F, 1065 0x5550, 1066 0x5551, 1067 0x5552, 1068 0x5554, 1069 0x564A, 1070 0x564B, 1071 0x564F, 1072 0x5652, 1073 0x5653, 1074 0x5657, 1075 0x5834, 1076 0x5835, 1077 0x5954, 1078 0x5955, 1079 0x5974, 1080 0x5975, 1081 0x5960, 1082 0x5961, 1083 0x5962, 1084 0x5964, 1085 0x5965, 1086 0x5969, 1087 0x5a41, 1088 0x5a42, 1089 0x5a61, 1090 0x5a62, 1091 0x5b60, 1092 0x5b62, 1093 0x5b63, 1094 0x5b64, 1095 0x5b65, 1096 0x5c61, 1097 0x5c63, 1098 0x5d48, 1099 0x5d49, 1100 0x5d4a, 1101 0x5d4c, 1102 0x5d4d, 1103 0x5d4e, 1104 0x5d4f, 1105 0x5d50, 1106 0x5d52, 1107 0x5d57, 1108 0x5e48, 1109 0x5e4a, 1110 0x5e4b, 1111 0x5e4c, 1112 0x5e4d, 1113 0x5e4f, 1114 0x6700, 1115 0x6701, 1116 0x6702, 1117 0x6703, 1118 0x6704, 1119 0x6705, 1120 0x6706, 1121 0x6707, 1122 0x6708, 1123 0x6709, 1124 0x6718, 1125 0x6719, 1126 0x671c, 1127 0x671d, 1128 0x671f, 1129 0x6720, 1130 0x6721, 1131 0x6722, 1132 0x6723, 1133 0x6724, 1134 0x6725, 1135 0x6726, 1136 0x6727, 1137 0x6728, 1138 0x6729, 1139 0x6738, 1140 0x6739, 1141 0x673e, 1142 0x6740, 1143 0x6741, 1144 0x6742, 1145 0x6743, 1146 0x6744, 1147 0x6745, 1148 0x6746, 1149 0x6747, 1150 0x6748, 1151 0x6749, 1152 0x674A, 1153 0x6750, 1154 0x6751, 1155 0x6758, 1156 0x6759, 1157 0x675B, 1158 0x675D, 1159 0x675F, 1160 0x6760, 1161 0x6761, 1162 0x6762, 1163 0x6763, 1164 0x6764, 1165 0x6765, 1166 0x6766, 1167 0x6767, 1168 0x6768, 1169 0x6770, 1170 0x6771, 1171 0x6772, 1172 0x6778, 1173 0x6779, 1174 0x677B, 1175 0x6840, 1176 0x6841, 1177 0x6842, 1178 0x6843, 1179 0x6849, 1180 0x684C, 1181 0x6850, 1182 0x6858, 1183 0x6859, 1184 0x6880, 1185 0x6888, 1186 0x6889, 1187 0x688A, 1188 0x688C, 1189 0x688D, 1190 0x6898, 1191 0x6899, 1192 0x689b, 1193 0x689c, 1194 0x689d, 1195 0x689e, 1196 0x68a0, 1197 0x68a1, 1198 0x68a8, 1199 0x68a9, 1200 0x68b0, 1201 0x68b8, 1202 0x68b9, 1203 0x68ba, 1204 0x68be, 1205 0x68bf, 1206 0x68c0, 1207 0x68c1, 1208 0x68c7, 1209 0x68c8, 1210 0x68c9, 1211 0x68d8, 1212 0x68d9, 1213 0x68da, 1214 0x68de, 1215 0x68e0, 1216 0x68e1, 1217 0x68e4, 1218 0x68e5, 1219 0x68e8, 1220 0x68e9, 1221 0x68f1, 1222 0x68f2, 1223 0x68f8, 1224 0x68f9, 1225 0x68fa, 1226 0x68fe, 1227 0x7100, 1228 0x7101, 1229 0x7102, 1230 0x7103, 1231 0x7104, 1232 0x7105, 1233 0x7106, 1234 0x7108, 1235 0x7109, 1236 0x710A, 1237 0x710B, 1238 0x710C, 1239 0x710E, 1240 0x710F, 1241 0x7140, 1242 0x7141, 1243 0x7142, 1244 0x7143, 1245 0x7144, 1246 0x7145, 1247 0x7146, 1248 0x7147, 1249 0x7149, 1250 0x714A, 1251 0x714B, 1252 0x714C, 1253 0x714D, 1254 0x714E, 1255 0x714F, 1256 0x7151, 1257 0x7152, 1258 0x7153, 1259 0x715E, 1260 0x715F, 1261 0x7180, 1262 0x7181, 1263 0x7183, 1264 0x7186, 1265 0x7187, 1266 0x7188, 1267 0x718A, 1268 0x718B, 1269 0x718C, 1270 0x718D, 1271 0x718F, 1272 0x7193, 1273 0x7196, 1274 0x719B, 1275 0x719F, 1276 0x71C0, 1277 0x71C1, 1278 0x71C2, 1279 0x71C3, 1280 0x71C4, 1281 0x71C5, 1282 0x71C6, 1283 0x71C7, 1284 0x71CD, 1285 0x71CE, 1286 0x71D2, 1287 0x71D4, 1288 0x71D5, 1289 0x71D6, 1290 0x71DA, 1291 0x71DE, 1292 0x7200, 1293 0x7210, 1294 0x7211, 1295 0x7240, 1296 0x7243, 1297 0x7244, 1298 0x7245, 1299 0x7246, 1300 0x7247, 1301 0x7248, 1302 0x7249, 1303 0x724A, 1304 0x724B, 1305 0x724C, 1306 0x724D, 1307 0x724E, 1308 0x724F, 1309 0x7280, 1310 0x7281, 1311 0x7283, 1312 0x7284, 1313 0x7287, 1314 0x7288, 1315 0x7289, 1316 0x728B, 1317 0x728C, 1318 0x7290, 1319 0x7291, 1320 0x7293, 1321 0x7297, 1322 0x7834, 1323 0x7835, 1324 0x791e, 1325 0x791f, 1326 0x793f, 1327 0x7941, 1328 0x7942, 1329 0x796c, 1330 0x796d, 1331 0x796e, 1332 0x796f, 1333 0x9400, 1334 0x9401, 1335 0x9402, 1336 0x9403, 1337 0x9405, 1338 0x940A, 1339 0x940B, 1340 0x940F, 1341 0x94A0, 1342 0x94A1, 1343 0x94A3, 1344 0x94B1, 1345 0x94B3, 1346 0x94B4, 1347 0x94B5, 1348 0x94B9, 1349 0x9440, 1350 0x9441, 1351 0x9442, 1352 0x9443, 1353 0x9444, 1354 0x9446, 1355 0x944A, 1356 0x944B, 1357 0x944C, 1358 0x944E, 1359 0x9450, 1360 0x9452, 1361 0x9456, 1362 0x945A, 1363 0x945B, 1364 0x945E, 1365 0x9460, 1366 0x9462, 1367 0x946A, 1368 0x946B, 1369 0x947A, 1370 0x947B, 1371 0x9480, 1372 0x9487, 1373 0x9488, 1374 0x9489, 1375 0x948A, 1376 0x948F, 1377 0x9490, 1378 0x9491, 1379 0x9495, 1380 0x9498, 1381 0x949C, 1382 0x949E, 1383 0x949F, 1384 0x94C0, 1385 0x94C1, 1386 0x94C3, 1387 0x94C4, 1388 0x94C5, 1389 0x94C6, 1390 0x94C7, 1391 0x94C8, 1392 0x94C9, 1393 0x94CB, 1394 0x94CC, 1395 0x94CD, 1396 0x9500, 1397 0x9501, 1398 0x9504, 1399 0x9505, 1400 0x9506, 1401 0x9507, 1402 0x9508, 1403 0x9509, 1404 0x950F, 1405 0x9511, 1406 0x9515, 1407 0x9517, 1408 0x9519, 1409 0x9540, 1410 0x9541, 1411 0x9542, 1412 0x954E, 1413 0x954F, 1414 0x9552, 1415 0x9553, 1416 0x9555, 1417 0x9557, 1418 0x955f, 1419 0x9580, 1420 0x9581, 1421 0x9583, 1422 0x9586, 1423 0x9587, 1424 0x9588, 1425 0x9589, 1426 0x958A, 1427 0x958B, 1428 0x958C, 1429 0x958D, 1430 0x958E, 1431 0x958F, 1432 0x9590, 1433 0x9591, 1434 0x9593, 1435 0x9595, 1436 0x9596, 1437 0x9597, 1438 0x9598, 1439 0x9599, 1440 0x959B, 1441 0x95C0, 1442 0x95C2, 1443 0x95C4, 1444 0x95C5, 1445 0x95C6, 1446 0x95C7, 1447 0x95C9, 1448 0x95CC, 1449 0x95CD, 1450 0x95CE, 1451 0x95CF, 1452 0x9610, 1453 0x9611, 1454 0x9612, 1455 0x9613, 1456 0x9614, 1457 0x9615, 1458 0x9616, 1459 0x9640, 1460 0x9641, 1461 0x9642, 1462 0x9643, 1463 0x9644, 1464 0x9645, 1465 0x9647, 1466 0x9648, 1467 0x9649, 1468 0x964a, 1469 0x964b, 1470 0x964c, 1471 0x964e, 1472 0x964f, 1473 0x9710, 1474 0x9711, 1475 0x9712, 1476 0x9713, 1477 0x9714, 1478 0x9715, 1479 0x9802, 1480 0x9803, 1481 0x9804, 1482 0x9805, 1483 0x9806, 1484 0x9807, 1485 0x9808, 1486 0x9809, 1487 0x980A, 1488 0x9900, 1489 0x9901, 1490 0x9903, 1491 0x9904, 1492 0x9905, 1493 0x9906, 1494 0x9907, 1495 0x9908, 1496 0x9909, 1497 0x990A, 1498 0x990B, 1499 0x990C, 1500 0x990D, 1501 0x990E, 1502 0x990F, 1503 0x9910, 1504 0x9913, 1505 0x9917, 1506 0x9918, 1507 0x9919, 1508 0x9990, 1509 0x9991, 1510 0x9992, 1511 0x9993, 1512 0x9994, 1513 0x9995, 1514 0x9996, 1515 0x9997, 1516 0x9998, 1517 0x9999, 1518 0x999A, 1519 0x999B, 1520 0x999C, 1521 0x999D, 1522 0x99A0, 1523 0x99A2, 1524 0x99A4, 1525 }; 1526 1527 static const struct pci_device_id pciidlist[] = { 1528 #ifdef CONFIG_DRM_AMDGPU_SI 1529 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1530 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1531 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1532 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1533 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1534 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1535 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1536 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1537 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1538 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1539 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1540 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1541 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1542 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1543 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1544 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1545 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1546 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1547 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1548 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1549 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1550 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1551 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1552 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1553 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1554 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1555 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1556 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1557 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1558 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1559 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1560 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1561 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1562 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1563 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1564 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1565 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1566 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1567 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1568 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1569 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1570 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1571 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1572 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1573 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1574 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1575 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1576 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1577 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1578 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1579 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1580 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1581 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1582 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1583 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1584 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1585 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1586 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1587 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1588 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1589 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1590 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1591 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1592 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1593 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1594 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1595 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1596 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1597 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1598 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1599 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1600 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1601 #endif 1602 #ifdef CONFIG_DRM_AMDGPU_CIK 1603 /* Kaveri */ 1604 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1605 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1606 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1607 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1608 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1609 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1610 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1611 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1612 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1613 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1614 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1615 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1616 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1617 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1618 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1619 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1620 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1621 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1622 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1623 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1624 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1625 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1626 /* Bonaire */ 1627 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1630 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1631 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1632 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1633 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1634 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1635 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1636 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1637 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1638 /* Hawaii */ 1639 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1640 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1641 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1642 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1643 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1644 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1645 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1646 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1647 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1648 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1649 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1650 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1651 /* Kabini */ 1652 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1653 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1654 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1655 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1656 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1657 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1658 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1659 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1660 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1661 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1662 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1663 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1664 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1665 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1666 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1667 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1668 /* mullins */ 1669 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1670 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1671 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1672 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1673 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1674 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1675 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1676 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1677 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1678 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1679 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1680 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1681 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1682 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1683 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1684 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1685 #endif 1686 /* topaz */ 1687 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1688 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1689 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1690 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1691 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1692 /* tonga */ 1693 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1694 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1695 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1696 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1697 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1698 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1699 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1700 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1701 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1702 /* fiji */ 1703 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1704 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1705 /* carrizo */ 1706 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1707 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1708 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1709 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1710 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1711 /* stoney */ 1712 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1713 /* Polaris11 */ 1714 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1715 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1716 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1717 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1718 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1719 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1720 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1721 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1722 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1723 /* Polaris10 */ 1724 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1725 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1726 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1727 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1728 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1729 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1730 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1731 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1732 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1733 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1734 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1735 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1736 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1737 /* Polaris12 */ 1738 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1739 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1740 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1741 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1742 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1743 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1744 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1745 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1746 /* VEGAM */ 1747 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1748 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1749 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1750 /* Vega 10 */ 1751 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1752 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1753 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1754 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1755 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1756 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1757 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1758 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1759 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1760 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1761 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1762 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1763 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1764 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1765 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1766 /* Vega 12 */ 1767 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1768 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1769 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1770 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1771 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1772 /* Vega 20 */ 1773 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1774 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1775 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1776 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1777 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1778 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1779 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1780 /* Raven */ 1781 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1782 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1783 /* Arcturus */ 1784 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1785 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1786 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1787 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1788 /* Navi10 */ 1789 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1790 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1791 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1792 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1793 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1794 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1795 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1796 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1797 /* Navi14 */ 1798 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1799 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1800 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1801 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1802 1803 /* Renoir */ 1804 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1805 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1806 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1807 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1808 1809 /* Navi12 */ 1810 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1811 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1812 1813 /* Sienna_Cichlid */ 1814 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1815 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1816 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1817 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1818 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1819 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1820 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1821 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1822 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1823 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1824 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1825 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1826 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1827 1828 /* Van Gogh */ 1829 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1830 1831 /* Yellow Carp */ 1832 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1833 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1834 1835 /* Navy_Flounder */ 1836 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1837 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1838 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1839 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1840 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1841 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1842 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1843 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1844 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1845 1846 /* DIMGREY_CAVEFISH */ 1847 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1848 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1849 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1850 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1851 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1852 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1853 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1854 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1855 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1856 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1857 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1858 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1859 1860 /* Aldebaran */ 1861 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1862 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1863 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1864 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1865 1866 /* CYAN_SKILLFISH */ 1867 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1868 1869 /* BEIGE_GOBY */ 1870 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1871 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1872 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1873 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1874 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1875 1876 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1877 .class = PCI_CLASS_DISPLAY_VGA << 8, 1878 .class_mask = 0xffffff, 1879 .driver_data = CHIP_IP_DISCOVERY }, 1880 1881 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1882 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1883 .class_mask = 0xffffff, 1884 .driver_data = CHIP_IP_DISCOVERY }, 1885 1886 {0, 0, 0} 1887 }; 1888 1889 MODULE_DEVICE_TABLE(pci, pciidlist); 1890 1891 static const struct drm_driver amdgpu_kms_driver; 1892 1893 static int amdgpu_pci_probe(struct pci_dev *pdev, 1894 const struct pci_device_id *ent) 1895 { 1896 struct drm_device *ddev; 1897 struct amdgpu_device *adev; 1898 unsigned long flags = ent->driver_data; 1899 int ret, retry = 0, i; 1900 bool supports_atomic = false; 1901 1902 /* skip devices which are owned by radeon */ 1903 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1904 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 1905 return -ENODEV; 1906 } 1907 1908 if (flags == 0) { 1909 DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n"); 1910 return -ENODEV; 1911 } 1912 1913 if (amdgpu_virtual_display || 1914 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1915 supports_atomic = true; 1916 1917 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1918 DRM_INFO("This hardware requires experimental hardware support.\n" 1919 "See modparam exp_hw_support\n"); 1920 return -ENODEV; 1921 } 1922 1923 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1924 * however, SME requires an indirect IOMMU mapping because the encryption 1925 * bit is beyond the DMA mask of the chip. 1926 */ 1927 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 1928 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1929 dev_info(&pdev->dev, 1930 "SME is not compatible with RAVEN\n"); 1931 return -ENOTSUPP; 1932 } 1933 1934 #ifdef CONFIG_DRM_AMDGPU_SI 1935 if (!amdgpu_si_support) { 1936 switch (flags & AMD_ASIC_MASK) { 1937 case CHIP_TAHITI: 1938 case CHIP_PITCAIRN: 1939 case CHIP_VERDE: 1940 case CHIP_OLAND: 1941 case CHIP_HAINAN: 1942 dev_info(&pdev->dev, 1943 "SI support provided by radeon.\n"); 1944 dev_info(&pdev->dev, 1945 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1946 ); 1947 return -ENODEV; 1948 } 1949 } 1950 #endif 1951 #ifdef CONFIG_DRM_AMDGPU_CIK 1952 if (!amdgpu_cik_support) { 1953 switch (flags & AMD_ASIC_MASK) { 1954 case CHIP_KAVERI: 1955 case CHIP_BONAIRE: 1956 case CHIP_HAWAII: 1957 case CHIP_KABINI: 1958 case CHIP_MULLINS: 1959 dev_info(&pdev->dev, 1960 "CIK support provided by radeon.\n"); 1961 dev_info(&pdev->dev, 1962 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1963 ); 1964 return -ENODEV; 1965 } 1966 } 1967 #endif 1968 1969 /* Get rid of things like offb */ 1970 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 1971 if (ret) 1972 return ret; 1973 1974 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1975 if (IS_ERR(adev)) 1976 return PTR_ERR(adev); 1977 1978 adev->dev = &pdev->dev; 1979 adev->pdev = pdev; 1980 ddev = adev_to_drm(adev); 1981 1982 if (!supports_atomic) 1983 ddev->driver_features &= ~DRIVER_ATOMIC; 1984 1985 ret = pci_enable_device(pdev); 1986 if (ret) 1987 return ret; 1988 1989 pci_set_drvdata(pdev, ddev); 1990 1991 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1992 if (ret) 1993 goto err_pci; 1994 1995 retry_init: 1996 ret = drm_dev_register(ddev, ent->driver_data); 1997 if (ret == -EAGAIN && ++retry <= 3) { 1998 DRM_INFO("retry init %d\n", retry); 1999 /* Don't request EX mode too frequently which is attacking */ 2000 msleep(5000); 2001 goto retry_init; 2002 } else if (ret) { 2003 goto err_pci; 2004 } 2005 2006 ret = amdgpu_debugfs_init(adev); 2007 if (ret) 2008 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2009 2010 return 0; 2011 2012 err_pci: 2013 pci_disable_device(pdev); 2014 return ret; 2015 } 2016 2017 static void 2018 amdgpu_pci_remove(struct pci_dev *pdev) 2019 { 2020 struct drm_device *dev = pci_get_drvdata(pdev); 2021 2022 drm_dev_unplug(dev); 2023 amdgpu_driver_unload_kms(dev); 2024 2025 /* 2026 * Flush any in flight DMA operations from device. 2027 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2028 * StatusTransactions Pending bit. 2029 */ 2030 pci_disable_device(pdev); 2031 pci_wait_for_pending_transaction(pdev); 2032 } 2033 2034 static void 2035 amdgpu_pci_shutdown(struct pci_dev *pdev) 2036 { 2037 struct drm_device *dev = pci_get_drvdata(pdev); 2038 struct amdgpu_device *adev = drm_to_adev(dev); 2039 2040 if (amdgpu_ras_intr_triggered()) 2041 return; 2042 2043 /* if we are running in a VM, make sure the device 2044 * torn down properly on reboot/shutdown. 2045 * unfortunately we can't detect certain 2046 * hypervisors so just do this all the time. 2047 */ 2048 if (!amdgpu_passthrough(adev)) 2049 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2050 amdgpu_device_ip_suspend(adev); 2051 adev->mp1_state = PP_MP1_STATE_NONE; 2052 } 2053 2054 /** 2055 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2056 * 2057 * @work: work_struct. 2058 */ 2059 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2060 { 2061 struct list_head device_list; 2062 struct amdgpu_device *adev; 2063 int i, r; 2064 struct amdgpu_reset_context reset_context; 2065 2066 memset(&reset_context, 0, sizeof(reset_context)); 2067 2068 mutex_lock(&mgpu_info.mutex); 2069 if (mgpu_info.pending_reset == true) { 2070 mutex_unlock(&mgpu_info.mutex); 2071 return; 2072 } 2073 mgpu_info.pending_reset = true; 2074 mutex_unlock(&mgpu_info.mutex); 2075 2076 /* Use a common context, just need to make sure full reset is done */ 2077 reset_context.method = AMD_RESET_METHOD_NONE; 2078 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2079 2080 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2081 adev = mgpu_info.gpu_ins[i].adev; 2082 reset_context.reset_req_dev = adev; 2083 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2084 if (r) { 2085 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2086 r, adev_to_drm(adev)->unique); 2087 } 2088 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2089 r = -EALREADY; 2090 } 2091 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2092 adev = mgpu_info.gpu_ins[i].adev; 2093 flush_work(&adev->xgmi_reset_work); 2094 adev->gmc.xgmi.pending_reset = false; 2095 } 2096 2097 /* reset function will rebuild the xgmi hive info , clear it now */ 2098 for (i = 0; i < mgpu_info.num_dgpu; i++) 2099 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2100 2101 INIT_LIST_HEAD(&device_list); 2102 2103 for (i = 0; i < mgpu_info.num_dgpu; i++) 2104 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2105 2106 /* unregister the GPU first, reset function will add them back */ 2107 list_for_each_entry(adev, &device_list, reset_list) 2108 amdgpu_unregister_gpu_instance(adev); 2109 2110 /* Use a common context, just need to make sure full reset is done */ 2111 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2112 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2113 2114 if (r) { 2115 DRM_ERROR("reinit gpus failure"); 2116 return; 2117 } 2118 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2119 adev = mgpu_info.gpu_ins[i].adev; 2120 if (!adev->kfd.init_complete) 2121 amdgpu_amdkfd_device_init(adev); 2122 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2123 } 2124 return; 2125 } 2126 2127 static int amdgpu_pmops_prepare(struct device *dev) 2128 { 2129 struct drm_device *drm_dev = dev_get_drvdata(dev); 2130 2131 /* Return a positive number here so 2132 * DPM_FLAG_SMART_SUSPEND works properly 2133 */ 2134 if (amdgpu_device_supports_boco(drm_dev)) 2135 return pm_runtime_suspended(dev) && 2136 pm_suspend_via_firmware(); 2137 2138 return 0; 2139 } 2140 2141 static void amdgpu_pmops_complete(struct device *dev) 2142 { 2143 /* nothing to do */ 2144 } 2145 2146 static int amdgpu_pmops_suspend(struct device *dev) 2147 { 2148 struct drm_device *drm_dev = dev_get_drvdata(dev); 2149 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2150 int r; 2151 2152 if (amdgpu_acpi_is_s0ix_active(adev)) 2153 adev->in_s0ix = true; 2154 adev->in_s3 = true; 2155 r = amdgpu_device_suspend(drm_dev, true); 2156 adev->in_s3 = false; 2157 if (r) 2158 return r; 2159 if (!adev->in_s0ix) 2160 r = amdgpu_asic_reset(adev); 2161 return r; 2162 } 2163 2164 static int amdgpu_pmops_resume(struct device *dev) 2165 { 2166 struct drm_device *drm_dev = dev_get_drvdata(dev); 2167 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2168 int r; 2169 2170 /* Avoids registers access if device is physically gone */ 2171 if (!pci_device_is_present(adev->pdev)) 2172 adev->no_hw_access = true; 2173 2174 r = amdgpu_device_resume(drm_dev, true); 2175 if (amdgpu_acpi_is_s0ix_active(adev)) 2176 adev->in_s0ix = false; 2177 return r; 2178 } 2179 2180 static int amdgpu_pmops_freeze(struct device *dev) 2181 { 2182 struct drm_device *drm_dev = dev_get_drvdata(dev); 2183 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2184 int r; 2185 2186 adev->in_s4 = true; 2187 r = amdgpu_device_suspend(drm_dev, true); 2188 adev->in_s4 = false; 2189 if (r) 2190 return r; 2191 return amdgpu_asic_reset(adev); 2192 } 2193 2194 static int amdgpu_pmops_thaw(struct device *dev) 2195 { 2196 struct drm_device *drm_dev = dev_get_drvdata(dev); 2197 2198 return amdgpu_device_resume(drm_dev, true); 2199 } 2200 2201 static int amdgpu_pmops_poweroff(struct device *dev) 2202 { 2203 struct drm_device *drm_dev = dev_get_drvdata(dev); 2204 2205 return amdgpu_device_suspend(drm_dev, true); 2206 } 2207 2208 static int amdgpu_pmops_restore(struct device *dev) 2209 { 2210 struct drm_device *drm_dev = dev_get_drvdata(dev); 2211 2212 return amdgpu_device_resume(drm_dev, true); 2213 } 2214 2215 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2216 { 2217 struct pci_dev *pdev = to_pci_dev(dev); 2218 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2219 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2220 int ret, i; 2221 2222 if (!adev->runpm) { 2223 pm_runtime_forbid(dev); 2224 return -EBUSY; 2225 } 2226 2227 /* wait for all rings to drain before suspending */ 2228 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2229 struct amdgpu_ring *ring = adev->rings[i]; 2230 if (ring && ring->sched.ready) { 2231 ret = amdgpu_fence_wait_empty(ring); 2232 if (ret) 2233 return -EBUSY; 2234 } 2235 } 2236 2237 adev->in_runpm = true; 2238 if (amdgpu_device_supports_px(drm_dev)) 2239 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2240 2241 /* 2242 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2243 * proper cleanups and put itself into a state ready for PNP. That 2244 * can address some random resuming failure observed on BOCO capable 2245 * platforms. 2246 * TODO: this may be also needed for PX capable platform. 2247 */ 2248 if (amdgpu_device_supports_boco(drm_dev)) 2249 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2250 2251 ret = amdgpu_device_suspend(drm_dev, false); 2252 if (ret) { 2253 adev->in_runpm = false; 2254 if (amdgpu_device_supports_boco(drm_dev)) 2255 adev->mp1_state = PP_MP1_STATE_NONE; 2256 return ret; 2257 } 2258 2259 if (amdgpu_device_supports_boco(drm_dev)) 2260 adev->mp1_state = PP_MP1_STATE_NONE; 2261 2262 if (amdgpu_device_supports_px(drm_dev)) { 2263 /* Only need to handle PCI state in the driver for ATPX 2264 * PCI core handles it for _PR3. 2265 */ 2266 amdgpu_device_cache_pci_state(pdev); 2267 pci_disable_device(pdev); 2268 pci_ignore_hotplug(pdev); 2269 pci_set_power_state(pdev, PCI_D3cold); 2270 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2271 } else if (amdgpu_device_supports_boco(drm_dev)) { 2272 /* nothing to do */ 2273 } else if (amdgpu_device_supports_baco(drm_dev)) { 2274 amdgpu_device_baco_enter(drm_dev); 2275 } 2276 2277 return 0; 2278 } 2279 2280 static int amdgpu_pmops_runtime_resume(struct device *dev) 2281 { 2282 struct pci_dev *pdev = to_pci_dev(dev); 2283 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2284 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2285 int ret; 2286 2287 if (!adev->runpm) 2288 return -EINVAL; 2289 2290 /* Avoids registers access if device is physically gone */ 2291 if (!pci_device_is_present(adev->pdev)) 2292 adev->no_hw_access = true; 2293 2294 if (amdgpu_device_supports_px(drm_dev)) { 2295 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2296 2297 /* Only need to handle PCI state in the driver for ATPX 2298 * PCI core handles it for _PR3. 2299 */ 2300 pci_set_power_state(pdev, PCI_D0); 2301 amdgpu_device_load_pci_state(pdev); 2302 ret = pci_enable_device(pdev); 2303 if (ret) 2304 return ret; 2305 pci_set_master(pdev); 2306 } else if (amdgpu_device_supports_boco(drm_dev)) { 2307 /* Only need to handle PCI state in the driver for ATPX 2308 * PCI core handles it for _PR3. 2309 */ 2310 pci_set_master(pdev); 2311 } else if (amdgpu_device_supports_baco(drm_dev)) { 2312 amdgpu_device_baco_exit(drm_dev); 2313 } 2314 ret = amdgpu_device_resume(drm_dev, false); 2315 if (ret) 2316 return ret; 2317 2318 if (amdgpu_device_supports_px(drm_dev)) 2319 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2320 adev->in_runpm = false; 2321 return 0; 2322 } 2323 2324 static int amdgpu_pmops_runtime_idle(struct device *dev) 2325 { 2326 struct drm_device *drm_dev = dev_get_drvdata(dev); 2327 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2328 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2329 int ret = 1; 2330 2331 if (!adev->runpm) { 2332 pm_runtime_forbid(dev); 2333 return -EBUSY; 2334 } 2335 2336 if (amdgpu_device_has_dc_support(adev)) { 2337 struct drm_crtc *crtc; 2338 2339 drm_for_each_crtc(crtc, drm_dev) { 2340 drm_modeset_lock(&crtc->mutex, NULL); 2341 if (crtc->state->active) 2342 ret = -EBUSY; 2343 drm_modeset_unlock(&crtc->mutex); 2344 if (ret < 0) 2345 break; 2346 } 2347 2348 } else { 2349 struct drm_connector *list_connector; 2350 struct drm_connector_list_iter iter; 2351 2352 mutex_lock(&drm_dev->mode_config.mutex); 2353 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2354 2355 drm_connector_list_iter_begin(drm_dev, &iter); 2356 drm_for_each_connector_iter(list_connector, &iter) { 2357 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2358 ret = -EBUSY; 2359 break; 2360 } 2361 } 2362 2363 drm_connector_list_iter_end(&iter); 2364 2365 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2366 mutex_unlock(&drm_dev->mode_config.mutex); 2367 } 2368 2369 if (ret == -EBUSY) 2370 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2371 2372 pm_runtime_mark_last_busy(dev); 2373 pm_runtime_autosuspend(dev); 2374 return ret; 2375 } 2376 2377 long amdgpu_drm_ioctl(struct file *filp, 2378 unsigned int cmd, unsigned long arg) 2379 { 2380 struct drm_file *file_priv = filp->private_data; 2381 struct drm_device *dev; 2382 long ret; 2383 dev = file_priv->minor->dev; 2384 ret = pm_runtime_get_sync(dev->dev); 2385 if (ret < 0) 2386 goto out; 2387 2388 ret = drm_ioctl(filp, cmd, arg); 2389 2390 pm_runtime_mark_last_busy(dev->dev); 2391 out: 2392 pm_runtime_put_autosuspend(dev->dev); 2393 return ret; 2394 } 2395 2396 static const struct dev_pm_ops amdgpu_pm_ops = { 2397 .prepare = amdgpu_pmops_prepare, 2398 .complete = amdgpu_pmops_complete, 2399 .suspend = amdgpu_pmops_suspend, 2400 .resume = amdgpu_pmops_resume, 2401 .freeze = amdgpu_pmops_freeze, 2402 .thaw = amdgpu_pmops_thaw, 2403 .poweroff = amdgpu_pmops_poweroff, 2404 .restore = amdgpu_pmops_restore, 2405 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2406 .runtime_resume = amdgpu_pmops_runtime_resume, 2407 .runtime_idle = amdgpu_pmops_runtime_idle, 2408 }; 2409 2410 static int amdgpu_flush(struct file *f, fl_owner_t id) 2411 { 2412 struct drm_file *file_priv = f->private_data; 2413 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2414 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2415 2416 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2417 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2418 2419 return timeout >= 0 ? 0 : timeout; 2420 } 2421 2422 static const struct file_operations amdgpu_driver_kms_fops = { 2423 .owner = THIS_MODULE, 2424 .open = drm_open, 2425 .flush = amdgpu_flush, 2426 .release = drm_release, 2427 .unlocked_ioctl = amdgpu_drm_ioctl, 2428 .mmap = drm_gem_mmap, 2429 .poll = drm_poll, 2430 .read = drm_read, 2431 #ifdef CONFIG_COMPAT 2432 .compat_ioctl = amdgpu_kms_compat_ioctl, 2433 #endif 2434 #ifdef CONFIG_PROC_FS 2435 .show_fdinfo = amdgpu_show_fdinfo 2436 #endif 2437 }; 2438 2439 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2440 { 2441 struct drm_file *file; 2442 2443 if (!filp) 2444 return -EINVAL; 2445 2446 if (filp->f_op != &amdgpu_driver_kms_fops) { 2447 return -EINVAL; 2448 } 2449 2450 file = filp->private_data; 2451 *fpriv = file->driver_priv; 2452 return 0; 2453 } 2454 2455 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2456 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2457 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2458 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2459 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2460 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2461 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2462 /* KMS */ 2463 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2464 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2465 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2466 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2467 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2468 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2469 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2470 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2471 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2472 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2473 }; 2474 2475 static const struct drm_driver amdgpu_kms_driver = { 2476 .driver_features = 2477 DRIVER_ATOMIC | 2478 DRIVER_GEM | 2479 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2480 DRIVER_SYNCOBJ_TIMELINE, 2481 .open = amdgpu_driver_open_kms, 2482 .postclose = amdgpu_driver_postclose_kms, 2483 .lastclose = amdgpu_driver_lastclose_kms, 2484 .ioctls = amdgpu_ioctls_kms, 2485 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2486 .dumb_create = amdgpu_mode_dumb_create, 2487 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2488 .fops = &amdgpu_driver_kms_fops, 2489 .release = &amdgpu_driver_release_kms, 2490 2491 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2492 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2493 .gem_prime_import = amdgpu_gem_prime_import, 2494 .gem_prime_mmap = drm_gem_prime_mmap, 2495 2496 .name = DRIVER_NAME, 2497 .desc = DRIVER_DESC, 2498 .date = DRIVER_DATE, 2499 .major = KMS_DRIVER_MAJOR, 2500 .minor = KMS_DRIVER_MINOR, 2501 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2502 }; 2503 2504 static struct pci_error_handlers amdgpu_pci_err_handler = { 2505 .error_detected = amdgpu_pci_error_detected, 2506 .mmio_enabled = amdgpu_pci_mmio_enabled, 2507 .slot_reset = amdgpu_pci_slot_reset, 2508 .resume = amdgpu_pci_resume, 2509 }; 2510 2511 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2512 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2513 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2514 2515 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2516 &amdgpu_vram_mgr_attr_group, 2517 &amdgpu_gtt_mgr_attr_group, 2518 &amdgpu_vbios_version_attr_group, 2519 NULL, 2520 }; 2521 2522 2523 static struct pci_driver amdgpu_kms_pci_driver = { 2524 .name = DRIVER_NAME, 2525 .id_table = pciidlist, 2526 .probe = amdgpu_pci_probe, 2527 .remove = amdgpu_pci_remove, 2528 .shutdown = amdgpu_pci_shutdown, 2529 .driver.pm = &amdgpu_pm_ops, 2530 .err_handler = &amdgpu_pci_err_handler, 2531 .dev_groups = amdgpu_sysfs_groups, 2532 }; 2533 2534 static int __init amdgpu_init(void) 2535 { 2536 int r; 2537 2538 if (vgacon_text_force()) { 2539 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 2540 return -EINVAL; 2541 } 2542 2543 r = amdgpu_sync_init(); 2544 if (r) 2545 goto error_sync; 2546 2547 r = amdgpu_fence_slab_init(); 2548 if (r) 2549 goto error_fence; 2550 2551 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2552 amdgpu_register_atpx_handler(); 2553 amdgpu_acpi_detect(); 2554 2555 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2556 amdgpu_amdkfd_init(); 2557 2558 /* let modprobe override vga console setting */ 2559 return pci_register_driver(&amdgpu_kms_pci_driver); 2560 2561 error_fence: 2562 amdgpu_sync_fini(); 2563 2564 error_sync: 2565 return r; 2566 } 2567 2568 static void __exit amdgpu_exit(void) 2569 { 2570 amdgpu_amdkfd_fini(); 2571 pci_unregister_driver(&amdgpu_kms_pci_driver); 2572 amdgpu_unregister_atpx_handler(); 2573 amdgpu_sync_fini(); 2574 amdgpu_fence_slab_fini(); 2575 mmu_notifier_synchronize(); 2576 } 2577 2578 module_init(amdgpu_init); 2579 module_exit(amdgpu_exit); 2580 2581 MODULE_AUTHOR(DRIVER_AUTHOR); 2582 MODULE_DESCRIPTION(DRIVER_DESC); 2583 MODULE_LICENSE("GPL and additional rights"); 2584