1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 * - 3.42.0 - Add 16bpc fixed point display support 99 * - 3.43.0 - Add device hot plug/unplug support 100 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 101 * - 3.45.0 - Add context ioctl stable pstate interface 102 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 103 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 104 * - 3.48.0 - Add IP discovery version info to HW INFO 105 * 3.49.0 - Add gang submit into CS IOCTL 106 */ 107 #define KMS_DRIVER_MAJOR 3 108 #define KMS_DRIVER_MINOR 49 109 #define KMS_DRIVER_PATCHLEVEL 0 110 111 int amdgpu_vram_limit; 112 int amdgpu_vis_vram_limit; 113 int amdgpu_gart_size = -1; /* auto */ 114 int amdgpu_gtt_size = -1; /* auto */ 115 int amdgpu_moverate = -1; /* auto */ 116 int amdgpu_audio = -1; 117 int amdgpu_disp_priority; 118 int amdgpu_hw_i2c; 119 int amdgpu_pcie_gen2 = -1; 120 int amdgpu_msi = -1; 121 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 122 int amdgpu_dpm = -1; 123 int amdgpu_fw_load_type = -1; 124 int amdgpu_aspm = -1; 125 int amdgpu_runtime_pm = -1; 126 uint amdgpu_ip_block_mask = 0xffffffff; 127 int amdgpu_bapm = -1; 128 int amdgpu_deep_color; 129 int amdgpu_vm_size = -1; 130 int amdgpu_vm_fragment_size = -1; 131 int amdgpu_vm_block_size = -1; 132 int amdgpu_vm_fault_stop; 133 int amdgpu_vm_debug; 134 int amdgpu_vm_update_mode = -1; 135 int amdgpu_exp_hw_support; 136 int amdgpu_dc = -1; 137 int amdgpu_sched_jobs = 32; 138 int amdgpu_sched_hw_submission = 2; 139 uint amdgpu_pcie_gen_cap; 140 uint amdgpu_pcie_lane_cap; 141 u64 amdgpu_cg_mask = 0xffffffffffffffff; 142 uint amdgpu_pg_mask = 0xffffffff; 143 uint amdgpu_sdma_phase_quantum = 32; 144 char *amdgpu_disable_cu = NULL; 145 char *amdgpu_virtual_display = NULL; 146 147 /* 148 * OverDrive(bit 14) disabled by default 149 * GFX DCS(bit 19) disabled by default 150 */ 151 uint amdgpu_pp_feature_mask = 0xfff7bfff; 152 uint amdgpu_force_long_training; 153 int amdgpu_job_hang_limit; 154 int amdgpu_lbpw = -1; 155 int amdgpu_compute_multipipe = -1; 156 int amdgpu_gpu_recovery = -1; /* auto */ 157 int amdgpu_emu_mode; 158 uint amdgpu_smu_memory_pool_size; 159 int amdgpu_smu_pptable_id = -1; 160 /* 161 * FBC (bit 0) disabled by default 162 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 163 * - With this, for multiple monitors in sync(e.g. with the same model), 164 * mclk switching will be allowed. And the mclk will be not foced to the 165 * highest. That helps saving some idle power. 166 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 167 * PSR (bit 3) disabled by default 168 * EDP NO POWER SEQUENCING (bit 4) disabled by default 169 */ 170 uint amdgpu_dc_feature_mask = 2; 171 uint amdgpu_dc_debug_mask; 172 uint amdgpu_dc_visual_confirm; 173 int amdgpu_async_gfx_ring = 1; 174 int amdgpu_mcbp; 175 int amdgpu_discovery = -1; 176 int amdgpu_mes; 177 int amdgpu_mes_kiq; 178 int amdgpu_noretry = -1; 179 int amdgpu_force_asic_type = -1; 180 int amdgpu_tmz = -1; /* auto */ 181 int amdgpu_reset_method = -1; /* auto */ 182 int amdgpu_num_kcq = -1; 183 int amdgpu_smartshift_bias; 184 int amdgpu_use_xgmi_p2p = 1; 185 int amdgpu_vcnfw_log; 186 187 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 188 189 struct amdgpu_mgpu_info mgpu_info = { 190 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 191 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 192 mgpu_info.delayed_reset_work, 193 amdgpu_drv_delayed_reset_work_handler, 0), 194 }; 195 int amdgpu_ras_enable = -1; 196 uint amdgpu_ras_mask = 0xffffffff; 197 int amdgpu_bad_page_threshold = -1; 198 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 199 .timeout_fatal_disable = false, 200 .period = 0x0, /* default to 0x0 (timeout disable) */ 201 }; 202 203 /** 204 * DOC: vramlimit (int) 205 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 206 */ 207 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 208 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 209 210 /** 211 * DOC: vis_vramlimit (int) 212 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 213 */ 214 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 215 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 216 217 /** 218 * DOC: gartsize (uint) 219 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 220 */ 221 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 222 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 223 224 /** 225 * DOC: gttsize (int) 226 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 227 * otherwise 3/4 RAM size). 228 */ 229 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 230 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 231 232 /** 233 * DOC: moverate (int) 234 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 235 */ 236 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 237 module_param_named(moverate, amdgpu_moverate, int, 0600); 238 239 /** 240 * DOC: audio (int) 241 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 242 */ 243 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 244 module_param_named(audio, amdgpu_audio, int, 0444); 245 246 /** 247 * DOC: disp_priority (int) 248 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 249 */ 250 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 251 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 252 253 /** 254 * DOC: hw_i2c (int) 255 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 256 */ 257 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 258 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 259 260 /** 261 * DOC: pcie_gen2 (int) 262 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 263 */ 264 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 265 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 266 267 /** 268 * DOC: msi (int) 269 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 270 */ 271 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 272 module_param_named(msi, amdgpu_msi, int, 0444); 273 274 /** 275 * DOC: lockup_timeout (string) 276 * Set GPU scheduler timeout value in ms. 277 * 278 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 279 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 280 * to the default timeout. 281 * 282 * - With one value specified, the setting will apply to all non-compute jobs. 283 * - With multiple values specified, the first one will be for GFX. 284 * The second one is for Compute. The third and fourth ones are 285 * for SDMA and Video. 286 * 287 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 288 * jobs is 10000. The timeout for compute is 60000. 289 */ 290 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 291 "for passthrough or sriov, 10000 for all jobs." 292 " 0: keep default value. negative: infinity timeout), " 293 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 294 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 295 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 296 297 /** 298 * DOC: dpm (int) 299 * Override for dynamic power management setting 300 * (0 = disable, 1 = enable) 301 * The default is -1 (auto). 302 */ 303 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 304 module_param_named(dpm, amdgpu_dpm, int, 0444); 305 306 /** 307 * DOC: fw_load_type (int) 308 * Set different firmware loading type for debugging, if supported. 309 * Set to 0 to force direct loading if supported by the ASIC. Set 310 * to -1 to select the default loading mode for the ASIC, as defined 311 * by the driver. The default is -1 (auto). 312 */ 313 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 314 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 315 316 /** 317 * DOC: aspm (int) 318 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 319 */ 320 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 321 module_param_named(aspm, amdgpu_aspm, int, 0444); 322 323 /** 324 * DOC: runpm (int) 325 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 326 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 327 * Setting the value to 0 disables this functionality. 328 */ 329 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 330 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 331 332 /** 333 * DOC: ip_block_mask (uint) 334 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 335 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 336 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 337 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 338 */ 339 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 340 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 341 342 /** 343 * DOC: bapm (int) 344 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 345 * The default -1 (auto, enabled) 346 */ 347 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 348 module_param_named(bapm, amdgpu_bapm, int, 0444); 349 350 /** 351 * DOC: deep_color (int) 352 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 353 */ 354 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 355 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 356 357 /** 358 * DOC: vm_size (int) 359 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 360 */ 361 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 362 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 363 364 /** 365 * DOC: vm_fragment_size (int) 366 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 367 */ 368 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 369 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 370 371 /** 372 * DOC: vm_block_size (int) 373 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 374 */ 375 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 376 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 377 378 /** 379 * DOC: vm_fault_stop (int) 380 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 381 */ 382 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 383 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 384 385 /** 386 * DOC: vm_debug (int) 387 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 388 */ 389 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 390 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 391 392 /** 393 * DOC: vm_update_mode (int) 394 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 395 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 396 */ 397 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 398 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 399 400 /** 401 * DOC: exp_hw_support (int) 402 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 403 */ 404 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 405 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 406 407 /** 408 * DOC: dc (int) 409 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 410 */ 411 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 412 module_param_named(dc, amdgpu_dc, int, 0444); 413 414 /** 415 * DOC: sched_jobs (int) 416 * Override the max number of jobs supported in the sw queue. The default is 32. 417 */ 418 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 419 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 420 421 /** 422 * DOC: sched_hw_submission (int) 423 * Override the max number of HW submissions. The default is 2. 424 */ 425 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 426 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 427 428 /** 429 * DOC: ppfeaturemask (hexint) 430 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 431 * The default is the current set of stable power features. 432 */ 433 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 434 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 435 436 /** 437 * DOC: forcelongtraining (uint) 438 * Force long memory training in resume. 439 * The default is zero, indicates short training in resume. 440 */ 441 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 442 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 443 444 /** 445 * DOC: pcie_gen_cap (uint) 446 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 447 * The default is 0 (automatic for each asic). 448 */ 449 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 450 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 451 452 /** 453 * DOC: pcie_lane_cap (uint) 454 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 455 * The default is 0 (automatic for each asic). 456 */ 457 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 458 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 459 460 /** 461 * DOC: cg_mask (ullong) 462 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 463 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 464 */ 465 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 466 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 467 468 /** 469 * DOC: pg_mask (uint) 470 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 471 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 472 */ 473 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 474 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 475 476 /** 477 * DOC: sdma_phase_quantum (uint) 478 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 479 */ 480 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 481 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 482 483 /** 484 * DOC: disable_cu (charp) 485 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 486 */ 487 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 488 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 489 490 /** 491 * DOC: virtual_display (charp) 492 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 493 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 494 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 495 * device at 26:00.0. The default is NULL. 496 */ 497 MODULE_PARM_DESC(virtual_display, 498 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 499 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 500 501 /** 502 * DOC: job_hang_limit (int) 503 * Set how much time allow a job hang and not drop it. The default is 0. 504 */ 505 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 506 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 507 508 /** 509 * DOC: lbpw (int) 510 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 511 */ 512 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 513 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 514 515 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 516 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 517 518 /** 519 * DOC: gpu_recovery (int) 520 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 521 */ 522 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 523 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 524 525 /** 526 * DOC: emu_mode (int) 527 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 528 */ 529 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 530 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 531 532 /** 533 * DOC: ras_enable (int) 534 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 535 */ 536 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 537 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 538 539 /** 540 * DOC: ras_mask (uint) 541 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 542 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 543 */ 544 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 545 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 546 547 /** 548 * DOC: timeout_fatal_disable (bool) 549 * Disable Watchdog timeout fatal error event 550 */ 551 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 552 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 553 554 /** 555 * DOC: timeout_period (uint) 556 * Modify the watchdog timeout max_cycles as (1 << period) 557 */ 558 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 559 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 560 561 /** 562 * DOC: si_support (int) 563 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 564 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 565 * otherwise using amdgpu driver. 566 */ 567 #ifdef CONFIG_DRM_AMDGPU_SI 568 569 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 570 int amdgpu_si_support = 0; 571 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 572 #else 573 int amdgpu_si_support = 1; 574 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 575 #endif 576 577 module_param_named(si_support, amdgpu_si_support, int, 0444); 578 #endif 579 580 /** 581 * DOC: cik_support (int) 582 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 583 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 584 * otherwise using amdgpu driver. 585 */ 586 #ifdef CONFIG_DRM_AMDGPU_CIK 587 588 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 589 int amdgpu_cik_support = 0; 590 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 591 #else 592 int amdgpu_cik_support = 1; 593 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 594 #endif 595 596 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 597 #endif 598 599 /** 600 * DOC: smu_memory_pool_size (uint) 601 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 602 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 603 */ 604 MODULE_PARM_DESC(smu_memory_pool_size, 605 "reserve gtt for smu debug usage, 0 = disable," 606 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 607 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 608 609 /** 610 * DOC: async_gfx_ring (int) 611 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 612 */ 613 MODULE_PARM_DESC(async_gfx_ring, 614 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 615 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 616 617 /** 618 * DOC: mcbp (int) 619 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 620 */ 621 MODULE_PARM_DESC(mcbp, 622 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 623 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 624 625 /** 626 * DOC: discovery (int) 627 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 628 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 629 */ 630 MODULE_PARM_DESC(discovery, 631 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 632 module_param_named(discovery, amdgpu_discovery, int, 0444); 633 634 /** 635 * DOC: mes (int) 636 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 637 * (0 = disabled (default), 1 = enabled) 638 */ 639 MODULE_PARM_DESC(mes, 640 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 641 module_param_named(mes, amdgpu_mes, int, 0444); 642 643 /** 644 * DOC: mes_kiq (int) 645 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 646 * (0 = disabled (default), 1 = enabled) 647 */ 648 MODULE_PARM_DESC(mes_kiq, 649 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 650 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 651 652 /** 653 * DOC: noretry (int) 654 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 655 * do not support per-process XNACK this also disables retry page faults. 656 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 657 */ 658 MODULE_PARM_DESC(noretry, 659 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 660 module_param_named(noretry, amdgpu_noretry, int, 0644); 661 662 /** 663 * DOC: force_asic_type (int) 664 * A non negative value used to specify the asic type for all supported GPUs. 665 */ 666 MODULE_PARM_DESC(force_asic_type, 667 "A non negative value used to specify the asic type for all supported GPUs"); 668 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 669 670 /** 671 * DOC: use_xgmi_p2p (int) 672 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 673 */ 674 MODULE_PARM_DESC(use_xgmi_p2p, 675 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 676 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 677 678 679 #ifdef CONFIG_HSA_AMD 680 /** 681 * DOC: sched_policy (int) 682 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 683 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 684 * assigns queues to HQDs. 685 */ 686 int sched_policy = KFD_SCHED_POLICY_HWS; 687 module_param(sched_policy, int, 0444); 688 MODULE_PARM_DESC(sched_policy, 689 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 690 691 /** 692 * DOC: hws_max_conc_proc (int) 693 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 694 * number of VMIDs assigned to the HWS, which is also the default. 695 */ 696 int hws_max_conc_proc = -1; 697 module_param(hws_max_conc_proc, int, 0444); 698 MODULE_PARM_DESC(hws_max_conc_proc, 699 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 700 701 /** 702 * DOC: cwsr_enable (int) 703 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 704 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 705 * disables it. 706 */ 707 int cwsr_enable = 1; 708 module_param(cwsr_enable, int, 0444); 709 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 710 711 /** 712 * DOC: max_num_of_queues_per_device (int) 713 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 714 * is 4096. 715 */ 716 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 717 module_param(max_num_of_queues_per_device, int, 0444); 718 MODULE_PARM_DESC(max_num_of_queues_per_device, 719 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 720 721 /** 722 * DOC: send_sigterm (int) 723 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 724 * but just print errors on dmesg. Setting 1 enables sending sigterm. 725 */ 726 int send_sigterm; 727 module_param(send_sigterm, int, 0444); 728 MODULE_PARM_DESC(send_sigterm, 729 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 730 731 /** 732 * DOC: debug_largebar (int) 733 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 734 * system. This limits the VRAM size reported to ROCm applications to the visible 735 * size, usually 256MB. 736 * Default value is 0, diabled. 737 */ 738 int debug_largebar; 739 module_param(debug_largebar, int, 0444); 740 MODULE_PARM_DESC(debug_largebar, 741 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 742 743 /** 744 * DOC: ignore_crat (int) 745 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 746 * table to get information about AMD APUs. This option can serve as a workaround on 747 * systems with a broken CRAT table. 748 * 749 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 750 * whether use CRAT) 751 */ 752 int ignore_crat; 753 module_param(ignore_crat, int, 0444); 754 MODULE_PARM_DESC(ignore_crat, 755 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 756 757 /** 758 * DOC: halt_if_hws_hang (int) 759 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 760 * Setting 1 enables halt on hang. 761 */ 762 int halt_if_hws_hang; 763 module_param(halt_if_hws_hang, int, 0644); 764 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 765 766 /** 767 * DOC: hws_gws_support(bool) 768 * Assume that HWS supports GWS barriers regardless of what firmware version 769 * check says. Default value: false (rely on MEC2 firmware version check). 770 */ 771 bool hws_gws_support; 772 module_param(hws_gws_support, bool, 0444); 773 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 774 775 /** 776 * DOC: queue_preemption_timeout_ms (int) 777 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 778 */ 779 int queue_preemption_timeout_ms = 9000; 780 module_param(queue_preemption_timeout_ms, int, 0644); 781 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 782 783 /** 784 * DOC: debug_evictions(bool) 785 * Enable extra debug messages to help determine the cause of evictions 786 */ 787 bool debug_evictions; 788 module_param(debug_evictions, bool, 0644); 789 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 790 791 /** 792 * DOC: no_system_mem_limit(bool) 793 * Disable system memory limit, to support multiple process shared memory 794 */ 795 bool no_system_mem_limit; 796 module_param(no_system_mem_limit, bool, 0644); 797 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 798 799 /** 800 * DOC: no_queue_eviction_on_vm_fault (int) 801 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 802 */ 803 int amdgpu_no_queue_eviction_on_vm_fault = 0; 804 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 805 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 806 #endif 807 808 /** 809 * DOC: pcie_p2p (bool) 810 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 811 */ 812 #ifdef CONFIG_HSA_AMD_P2P 813 bool pcie_p2p = true; 814 module_param(pcie_p2p, bool, 0444); 815 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 816 #endif 817 818 /** 819 * DOC: dcfeaturemask (uint) 820 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 821 * The default is the current set of stable display features. 822 */ 823 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 824 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 825 826 /** 827 * DOC: dcdebugmask (uint) 828 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 829 */ 830 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 831 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 832 833 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 834 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 835 836 /** 837 * DOC: abmlevel (uint) 838 * Override the default ABM (Adaptive Backlight Management) level used for DC 839 * enabled hardware. Requires DMCU to be supported and loaded. 840 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 841 * default. Values 1-4 control the maximum allowable brightness reduction via 842 * the ABM algorithm, with 1 being the least reduction and 4 being the most 843 * reduction. 844 * 845 * Defaults to 0, or disabled. Userspace can still override this level later 846 * after boot. 847 */ 848 uint amdgpu_dm_abm_level; 849 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 850 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 851 852 int amdgpu_backlight = -1; 853 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 854 module_param_named(backlight, amdgpu_backlight, bint, 0444); 855 856 /** 857 * DOC: tmz (int) 858 * Trusted Memory Zone (TMZ) is a method to protect data being written 859 * to or read from memory. 860 * 861 * The default value: 0 (off). TODO: change to auto till it is completed. 862 */ 863 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 864 module_param_named(tmz, amdgpu_tmz, int, 0444); 865 866 /** 867 * DOC: reset_method (int) 868 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 869 */ 870 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 871 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 872 873 /** 874 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 875 * threshold value of faulty pages detected by RAS ECC, which may 876 * result in the GPU entering bad status when the number of total 877 * faulty pages by ECC exceeds the threshold value. 878 */ 879 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 880 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 881 882 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 883 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 884 885 /** 886 * DOC: vcnfw_log (int) 887 * Enable vcnfw log output for debugging, the default is disabled. 888 */ 889 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 890 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 891 892 /** 893 * DOC: smu_pptable_id (int) 894 * Used to override pptable id. id = 0 use VBIOS pptable. 895 * id > 0 use the soft pptable with specicfied id. 896 */ 897 MODULE_PARM_DESC(smu_pptable_id, 898 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 899 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 900 901 /* These devices are not supported by amdgpu. 902 * They are supported by the mach64, r128, radeon drivers 903 */ 904 static const u16 amdgpu_unsupported_pciidlist[] = { 905 /* mach64 */ 906 0x4354, 907 0x4358, 908 0x4554, 909 0x4742, 910 0x4744, 911 0x4749, 912 0x474C, 913 0x474D, 914 0x474E, 915 0x474F, 916 0x4750, 917 0x4751, 918 0x4752, 919 0x4753, 920 0x4754, 921 0x4755, 922 0x4756, 923 0x4757, 924 0x4758, 925 0x4759, 926 0x475A, 927 0x4C42, 928 0x4C44, 929 0x4C47, 930 0x4C49, 931 0x4C4D, 932 0x4C4E, 933 0x4C50, 934 0x4C51, 935 0x4C52, 936 0x4C53, 937 0x5654, 938 0x5655, 939 0x5656, 940 /* r128 */ 941 0x4c45, 942 0x4c46, 943 0x4d46, 944 0x4d4c, 945 0x5041, 946 0x5042, 947 0x5043, 948 0x5044, 949 0x5045, 950 0x5046, 951 0x5047, 952 0x5048, 953 0x5049, 954 0x504A, 955 0x504B, 956 0x504C, 957 0x504D, 958 0x504E, 959 0x504F, 960 0x5050, 961 0x5051, 962 0x5052, 963 0x5053, 964 0x5054, 965 0x5055, 966 0x5056, 967 0x5057, 968 0x5058, 969 0x5245, 970 0x5246, 971 0x5247, 972 0x524b, 973 0x524c, 974 0x534d, 975 0x5446, 976 0x544C, 977 0x5452, 978 /* radeon */ 979 0x3150, 980 0x3151, 981 0x3152, 982 0x3154, 983 0x3155, 984 0x3E50, 985 0x3E54, 986 0x4136, 987 0x4137, 988 0x4144, 989 0x4145, 990 0x4146, 991 0x4147, 992 0x4148, 993 0x4149, 994 0x414A, 995 0x414B, 996 0x4150, 997 0x4151, 998 0x4152, 999 0x4153, 1000 0x4154, 1001 0x4155, 1002 0x4156, 1003 0x4237, 1004 0x4242, 1005 0x4336, 1006 0x4337, 1007 0x4437, 1008 0x4966, 1009 0x4967, 1010 0x4A48, 1011 0x4A49, 1012 0x4A4A, 1013 0x4A4B, 1014 0x4A4C, 1015 0x4A4D, 1016 0x4A4E, 1017 0x4A4F, 1018 0x4A50, 1019 0x4A54, 1020 0x4B48, 1021 0x4B49, 1022 0x4B4A, 1023 0x4B4B, 1024 0x4B4C, 1025 0x4C57, 1026 0x4C58, 1027 0x4C59, 1028 0x4C5A, 1029 0x4C64, 1030 0x4C66, 1031 0x4C67, 1032 0x4E44, 1033 0x4E45, 1034 0x4E46, 1035 0x4E47, 1036 0x4E48, 1037 0x4E49, 1038 0x4E4A, 1039 0x4E4B, 1040 0x4E50, 1041 0x4E51, 1042 0x4E52, 1043 0x4E53, 1044 0x4E54, 1045 0x4E56, 1046 0x5144, 1047 0x5145, 1048 0x5146, 1049 0x5147, 1050 0x5148, 1051 0x514C, 1052 0x514D, 1053 0x5157, 1054 0x5158, 1055 0x5159, 1056 0x515A, 1057 0x515E, 1058 0x5460, 1059 0x5462, 1060 0x5464, 1061 0x5548, 1062 0x5549, 1063 0x554A, 1064 0x554B, 1065 0x554C, 1066 0x554D, 1067 0x554E, 1068 0x554F, 1069 0x5550, 1070 0x5551, 1071 0x5552, 1072 0x5554, 1073 0x564A, 1074 0x564B, 1075 0x564F, 1076 0x5652, 1077 0x5653, 1078 0x5657, 1079 0x5834, 1080 0x5835, 1081 0x5954, 1082 0x5955, 1083 0x5974, 1084 0x5975, 1085 0x5960, 1086 0x5961, 1087 0x5962, 1088 0x5964, 1089 0x5965, 1090 0x5969, 1091 0x5a41, 1092 0x5a42, 1093 0x5a61, 1094 0x5a62, 1095 0x5b60, 1096 0x5b62, 1097 0x5b63, 1098 0x5b64, 1099 0x5b65, 1100 0x5c61, 1101 0x5c63, 1102 0x5d48, 1103 0x5d49, 1104 0x5d4a, 1105 0x5d4c, 1106 0x5d4d, 1107 0x5d4e, 1108 0x5d4f, 1109 0x5d50, 1110 0x5d52, 1111 0x5d57, 1112 0x5e48, 1113 0x5e4a, 1114 0x5e4b, 1115 0x5e4c, 1116 0x5e4d, 1117 0x5e4f, 1118 0x6700, 1119 0x6701, 1120 0x6702, 1121 0x6703, 1122 0x6704, 1123 0x6705, 1124 0x6706, 1125 0x6707, 1126 0x6708, 1127 0x6709, 1128 0x6718, 1129 0x6719, 1130 0x671c, 1131 0x671d, 1132 0x671f, 1133 0x6720, 1134 0x6721, 1135 0x6722, 1136 0x6723, 1137 0x6724, 1138 0x6725, 1139 0x6726, 1140 0x6727, 1141 0x6728, 1142 0x6729, 1143 0x6738, 1144 0x6739, 1145 0x673e, 1146 0x6740, 1147 0x6741, 1148 0x6742, 1149 0x6743, 1150 0x6744, 1151 0x6745, 1152 0x6746, 1153 0x6747, 1154 0x6748, 1155 0x6749, 1156 0x674A, 1157 0x6750, 1158 0x6751, 1159 0x6758, 1160 0x6759, 1161 0x675B, 1162 0x675D, 1163 0x675F, 1164 0x6760, 1165 0x6761, 1166 0x6762, 1167 0x6763, 1168 0x6764, 1169 0x6765, 1170 0x6766, 1171 0x6767, 1172 0x6768, 1173 0x6770, 1174 0x6771, 1175 0x6772, 1176 0x6778, 1177 0x6779, 1178 0x677B, 1179 0x6840, 1180 0x6841, 1181 0x6842, 1182 0x6843, 1183 0x6849, 1184 0x684C, 1185 0x6850, 1186 0x6858, 1187 0x6859, 1188 0x6880, 1189 0x6888, 1190 0x6889, 1191 0x688A, 1192 0x688C, 1193 0x688D, 1194 0x6898, 1195 0x6899, 1196 0x689b, 1197 0x689c, 1198 0x689d, 1199 0x689e, 1200 0x68a0, 1201 0x68a1, 1202 0x68a8, 1203 0x68a9, 1204 0x68b0, 1205 0x68b8, 1206 0x68b9, 1207 0x68ba, 1208 0x68be, 1209 0x68bf, 1210 0x68c0, 1211 0x68c1, 1212 0x68c7, 1213 0x68c8, 1214 0x68c9, 1215 0x68d8, 1216 0x68d9, 1217 0x68da, 1218 0x68de, 1219 0x68e0, 1220 0x68e1, 1221 0x68e4, 1222 0x68e5, 1223 0x68e8, 1224 0x68e9, 1225 0x68f1, 1226 0x68f2, 1227 0x68f8, 1228 0x68f9, 1229 0x68fa, 1230 0x68fe, 1231 0x7100, 1232 0x7101, 1233 0x7102, 1234 0x7103, 1235 0x7104, 1236 0x7105, 1237 0x7106, 1238 0x7108, 1239 0x7109, 1240 0x710A, 1241 0x710B, 1242 0x710C, 1243 0x710E, 1244 0x710F, 1245 0x7140, 1246 0x7141, 1247 0x7142, 1248 0x7143, 1249 0x7144, 1250 0x7145, 1251 0x7146, 1252 0x7147, 1253 0x7149, 1254 0x714A, 1255 0x714B, 1256 0x714C, 1257 0x714D, 1258 0x714E, 1259 0x714F, 1260 0x7151, 1261 0x7152, 1262 0x7153, 1263 0x715E, 1264 0x715F, 1265 0x7180, 1266 0x7181, 1267 0x7183, 1268 0x7186, 1269 0x7187, 1270 0x7188, 1271 0x718A, 1272 0x718B, 1273 0x718C, 1274 0x718D, 1275 0x718F, 1276 0x7193, 1277 0x7196, 1278 0x719B, 1279 0x719F, 1280 0x71C0, 1281 0x71C1, 1282 0x71C2, 1283 0x71C3, 1284 0x71C4, 1285 0x71C5, 1286 0x71C6, 1287 0x71C7, 1288 0x71CD, 1289 0x71CE, 1290 0x71D2, 1291 0x71D4, 1292 0x71D5, 1293 0x71D6, 1294 0x71DA, 1295 0x71DE, 1296 0x7200, 1297 0x7210, 1298 0x7211, 1299 0x7240, 1300 0x7243, 1301 0x7244, 1302 0x7245, 1303 0x7246, 1304 0x7247, 1305 0x7248, 1306 0x7249, 1307 0x724A, 1308 0x724B, 1309 0x724C, 1310 0x724D, 1311 0x724E, 1312 0x724F, 1313 0x7280, 1314 0x7281, 1315 0x7283, 1316 0x7284, 1317 0x7287, 1318 0x7288, 1319 0x7289, 1320 0x728B, 1321 0x728C, 1322 0x7290, 1323 0x7291, 1324 0x7293, 1325 0x7297, 1326 0x7834, 1327 0x7835, 1328 0x791e, 1329 0x791f, 1330 0x793f, 1331 0x7941, 1332 0x7942, 1333 0x796c, 1334 0x796d, 1335 0x796e, 1336 0x796f, 1337 0x9400, 1338 0x9401, 1339 0x9402, 1340 0x9403, 1341 0x9405, 1342 0x940A, 1343 0x940B, 1344 0x940F, 1345 0x94A0, 1346 0x94A1, 1347 0x94A3, 1348 0x94B1, 1349 0x94B3, 1350 0x94B4, 1351 0x94B5, 1352 0x94B9, 1353 0x9440, 1354 0x9441, 1355 0x9442, 1356 0x9443, 1357 0x9444, 1358 0x9446, 1359 0x944A, 1360 0x944B, 1361 0x944C, 1362 0x944E, 1363 0x9450, 1364 0x9452, 1365 0x9456, 1366 0x945A, 1367 0x945B, 1368 0x945E, 1369 0x9460, 1370 0x9462, 1371 0x946A, 1372 0x946B, 1373 0x947A, 1374 0x947B, 1375 0x9480, 1376 0x9487, 1377 0x9488, 1378 0x9489, 1379 0x948A, 1380 0x948F, 1381 0x9490, 1382 0x9491, 1383 0x9495, 1384 0x9498, 1385 0x949C, 1386 0x949E, 1387 0x949F, 1388 0x94C0, 1389 0x94C1, 1390 0x94C3, 1391 0x94C4, 1392 0x94C5, 1393 0x94C6, 1394 0x94C7, 1395 0x94C8, 1396 0x94C9, 1397 0x94CB, 1398 0x94CC, 1399 0x94CD, 1400 0x9500, 1401 0x9501, 1402 0x9504, 1403 0x9505, 1404 0x9506, 1405 0x9507, 1406 0x9508, 1407 0x9509, 1408 0x950F, 1409 0x9511, 1410 0x9515, 1411 0x9517, 1412 0x9519, 1413 0x9540, 1414 0x9541, 1415 0x9542, 1416 0x954E, 1417 0x954F, 1418 0x9552, 1419 0x9553, 1420 0x9555, 1421 0x9557, 1422 0x955f, 1423 0x9580, 1424 0x9581, 1425 0x9583, 1426 0x9586, 1427 0x9587, 1428 0x9588, 1429 0x9589, 1430 0x958A, 1431 0x958B, 1432 0x958C, 1433 0x958D, 1434 0x958E, 1435 0x958F, 1436 0x9590, 1437 0x9591, 1438 0x9593, 1439 0x9595, 1440 0x9596, 1441 0x9597, 1442 0x9598, 1443 0x9599, 1444 0x959B, 1445 0x95C0, 1446 0x95C2, 1447 0x95C4, 1448 0x95C5, 1449 0x95C6, 1450 0x95C7, 1451 0x95C9, 1452 0x95CC, 1453 0x95CD, 1454 0x95CE, 1455 0x95CF, 1456 0x9610, 1457 0x9611, 1458 0x9612, 1459 0x9613, 1460 0x9614, 1461 0x9615, 1462 0x9616, 1463 0x9640, 1464 0x9641, 1465 0x9642, 1466 0x9643, 1467 0x9644, 1468 0x9645, 1469 0x9647, 1470 0x9648, 1471 0x9649, 1472 0x964a, 1473 0x964b, 1474 0x964c, 1475 0x964e, 1476 0x964f, 1477 0x9710, 1478 0x9711, 1479 0x9712, 1480 0x9713, 1481 0x9714, 1482 0x9715, 1483 0x9802, 1484 0x9803, 1485 0x9804, 1486 0x9805, 1487 0x9806, 1488 0x9807, 1489 0x9808, 1490 0x9809, 1491 0x980A, 1492 0x9900, 1493 0x9901, 1494 0x9903, 1495 0x9904, 1496 0x9905, 1497 0x9906, 1498 0x9907, 1499 0x9908, 1500 0x9909, 1501 0x990A, 1502 0x990B, 1503 0x990C, 1504 0x990D, 1505 0x990E, 1506 0x990F, 1507 0x9910, 1508 0x9913, 1509 0x9917, 1510 0x9918, 1511 0x9919, 1512 0x9990, 1513 0x9991, 1514 0x9992, 1515 0x9993, 1516 0x9994, 1517 0x9995, 1518 0x9996, 1519 0x9997, 1520 0x9998, 1521 0x9999, 1522 0x999A, 1523 0x999B, 1524 0x999C, 1525 0x999D, 1526 0x99A0, 1527 0x99A2, 1528 0x99A4, 1529 /* radeon secondary ids */ 1530 0x3171, 1531 0x3e70, 1532 0x4164, 1533 0x4165, 1534 0x4166, 1535 0x4168, 1536 0x4170, 1537 0x4171, 1538 0x4172, 1539 0x4173, 1540 0x496e, 1541 0x4a69, 1542 0x4a6a, 1543 0x4a6b, 1544 0x4a70, 1545 0x4a74, 1546 0x4b69, 1547 0x4b6b, 1548 0x4b6c, 1549 0x4c6e, 1550 0x4e64, 1551 0x4e65, 1552 0x4e66, 1553 0x4e67, 1554 0x4e68, 1555 0x4e69, 1556 0x4e6a, 1557 0x4e71, 1558 0x4f73, 1559 0x5569, 1560 0x556b, 1561 0x556d, 1562 0x556f, 1563 0x5571, 1564 0x5854, 1565 0x5874, 1566 0x5940, 1567 0x5941, 1568 0x5b72, 1569 0x5b73, 1570 0x5b74, 1571 0x5b75, 1572 0x5d44, 1573 0x5d45, 1574 0x5d6d, 1575 0x5d6f, 1576 0x5d72, 1577 0x5d77, 1578 0x5e6b, 1579 0x5e6d, 1580 0x7120, 1581 0x7124, 1582 0x7129, 1583 0x712e, 1584 0x712f, 1585 0x7162, 1586 0x7163, 1587 0x7166, 1588 0x7167, 1589 0x7172, 1590 0x7173, 1591 0x71a0, 1592 0x71a1, 1593 0x71a3, 1594 0x71a7, 1595 0x71bb, 1596 0x71e0, 1597 0x71e1, 1598 0x71e2, 1599 0x71e6, 1600 0x71e7, 1601 0x71f2, 1602 0x7269, 1603 0x726b, 1604 0x726e, 1605 0x72a0, 1606 0x72a8, 1607 0x72b1, 1608 0x72b3, 1609 0x793f, 1610 }; 1611 1612 static const struct pci_device_id pciidlist[] = { 1613 #ifdef CONFIG_DRM_AMDGPU_SI 1614 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1615 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1616 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1617 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1618 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1619 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1620 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1621 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1622 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1623 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1624 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1625 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1626 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1627 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1630 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1631 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1632 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1633 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1634 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1635 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1636 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1637 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1638 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1639 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1640 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1641 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1642 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1643 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1644 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1647 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1648 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1649 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1650 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1651 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1652 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1653 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1654 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1656 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1658 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1659 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1660 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1661 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1662 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1663 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1664 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1665 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1666 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1667 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1668 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1669 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1670 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1671 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1674 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1675 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1676 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1677 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1678 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1679 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1680 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1681 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1682 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1683 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1684 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1685 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1686 #endif 1687 #ifdef CONFIG_DRM_AMDGPU_CIK 1688 /* Kaveri */ 1689 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1690 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1691 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1692 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1693 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1694 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1695 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1696 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1697 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1698 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1699 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1700 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1701 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1702 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1703 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1704 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1705 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1706 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1707 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1708 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1709 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1710 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1711 /* Bonaire */ 1712 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1717 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1718 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1719 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1720 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1721 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1722 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1723 /* Hawaii */ 1724 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1725 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1726 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1727 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1728 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1729 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1730 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1731 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1732 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1733 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1734 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1735 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1736 /* Kabini */ 1737 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1739 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1741 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1743 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1744 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1745 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1746 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1747 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1748 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1750 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1751 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1752 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1753 /* mullins */ 1754 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1755 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1756 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1757 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1761 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1763 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1764 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1765 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1766 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1767 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1768 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1769 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1770 #endif 1771 /* topaz */ 1772 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1773 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1774 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1775 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1776 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1777 /* tonga */ 1778 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1779 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1780 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1781 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1782 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1783 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1784 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1785 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1786 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1787 /* fiji */ 1788 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1789 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1790 /* carrizo */ 1791 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1792 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1793 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1794 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1795 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1796 /* stoney */ 1797 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1798 /* Polaris11 */ 1799 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1800 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1801 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1802 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1803 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1804 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1805 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1806 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1807 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1808 /* Polaris10 */ 1809 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1810 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1811 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1812 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1813 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1814 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1815 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1816 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1817 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1818 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1819 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1820 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1821 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1822 /* Polaris12 */ 1823 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1824 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1825 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1826 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1827 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1828 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1829 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1830 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1831 /* VEGAM */ 1832 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1833 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1834 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1835 /* Vega 10 */ 1836 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1837 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1838 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1839 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1840 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1841 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1842 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1843 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1844 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1845 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1846 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1847 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1848 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1849 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1850 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1851 /* Vega 12 */ 1852 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1853 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1854 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1855 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1856 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1857 /* Vega 20 */ 1858 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1859 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1860 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1861 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1862 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1863 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1864 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1865 /* Raven */ 1866 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1867 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1868 /* Arcturus */ 1869 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1870 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1871 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1872 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1873 /* Navi10 */ 1874 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1875 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1876 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1877 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1878 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1879 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1880 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1881 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1882 /* Navi14 */ 1883 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1884 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1885 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1886 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1887 1888 /* Renoir */ 1889 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1890 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1891 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1892 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1893 1894 /* Navi12 */ 1895 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1896 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1897 1898 /* Sienna_Cichlid */ 1899 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1900 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1901 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1902 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1903 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1904 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1905 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1906 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1907 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1908 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1909 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1910 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1911 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1912 1913 /* Van Gogh */ 1914 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1915 1916 /* Yellow Carp */ 1917 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1918 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1919 1920 /* Navy_Flounder */ 1921 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1922 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1923 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1924 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1925 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1926 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1927 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1928 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1929 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1930 1931 /* DIMGREY_CAVEFISH */ 1932 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1933 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1934 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1935 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1936 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1937 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1938 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1939 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1940 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1941 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1942 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1943 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1944 1945 /* Aldebaran */ 1946 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1947 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1948 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1949 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1950 1951 /* CYAN_SKILLFISH */ 1952 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1953 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1954 1955 /* BEIGE_GOBY */ 1956 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1957 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1958 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1959 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1960 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1961 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1962 1963 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1964 .class = PCI_CLASS_DISPLAY_VGA << 8, 1965 .class_mask = 0xffffff, 1966 .driver_data = CHIP_IP_DISCOVERY }, 1967 1968 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1969 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1970 .class_mask = 0xffffff, 1971 .driver_data = CHIP_IP_DISCOVERY }, 1972 1973 {0, 0, 0} 1974 }; 1975 1976 MODULE_DEVICE_TABLE(pci, pciidlist); 1977 1978 static const struct drm_driver amdgpu_kms_driver; 1979 1980 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1981 { 1982 struct pci_dev *p = NULL; 1983 int i; 1984 1985 /* 0 - GPU 1986 * 1 - audio 1987 * 2 - USB 1988 * 3 - UCSI 1989 */ 1990 for (i = 1; i < 4; i++) { 1991 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1992 adev->pdev->bus->number, i); 1993 if (p) { 1994 pm_runtime_get_sync(&p->dev); 1995 pm_runtime_mark_last_busy(&p->dev); 1996 pm_runtime_put_autosuspend(&p->dev); 1997 pci_dev_put(p); 1998 } 1999 } 2000 } 2001 2002 static int amdgpu_pci_probe(struct pci_dev *pdev, 2003 const struct pci_device_id *ent) 2004 { 2005 struct drm_device *ddev; 2006 struct amdgpu_device *adev; 2007 unsigned long flags = ent->driver_data; 2008 int ret, retry = 0, i; 2009 bool supports_atomic = false; 2010 2011 /* skip devices which are owned by radeon */ 2012 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2013 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2014 return -ENODEV; 2015 } 2016 2017 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2018 amdgpu_aspm = 0; 2019 2020 if (amdgpu_virtual_display || 2021 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2022 supports_atomic = true; 2023 2024 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2025 DRM_INFO("This hardware requires experimental hardware support.\n" 2026 "See modparam exp_hw_support\n"); 2027 return -ENODEV; 2028 } 2029 2030 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2031 * however, SME requires an indirect IOMMU mapping because the encryption 2032 * bit is beyond the DMA mask of the chip. 2033 */ 2034 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2035 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2036 dev_info(&pdev->dev, 2037 "SME is not compatible with RAVEN\n"); 2038 return -ENOTSUPP; 2039 } 2040 2041 #ifdef CONFIG_DRM_AMDGPU_SI 2042 if (!amdgpu_si_support) { 2043 switch (flags & AMD_ASIC_MASK) { 2044 case CHIP_TAHITI: 2045 case CHIP_PITCAIRN: 2046 case CHIP_VERDE: 2047 case CHIP_OLAND: 2048 case CHIP_HAINAN: 2049 dev_info(&pdev->dev, 2050 "SI support provided by radeon.\n"); 2051 dev_info(&pdev->dev, 2052 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2053 ); 2054 return -ENODEV; 2055 } 2056 } 2057 #endif 2058 #ifdef CONFIG_DRM_AMDGPU_CIK 2059 if (!amdgpu_cik_support) { 2060 switch (flags & AMD_ASIC_MASK) { 2061 case CHIP_KAVERI: 2062 case CHIP_BONAIRE: 2063 case CHIP_HAWAII: 2064 case CHIP_KABINI: 2065 case CHIP_MULLINS: 2066 dev_info(&pdev->dev, 2067 "CIK support provided by radeon.\n"); 2068 dev_info(&pdev->dev, 2069 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2070 ); 2071 return -ENODEV; 2072 } 2073 } 2074 #endif 2075 2076 /* Get rid of things like offb */ 2077 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2078 if (ret) 2079 return ret; 2080 2081 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2082 if (IS_ERR(adev)) 2083 return PTR_ERR(adev); 2084 2085 adev->dev = &pdev->dev; 2086 adev->pdev = pdev; 2087 ddev = adev_to_drm(adev); 2088 2089 if (!supports_atomic) 2090 ddev->driver_features &= ~DRIVER_ATOMIC; 2091 2092 ret = pci_enable_device(pdev); 2093 if (ret) 2094 return ret; 2095 2096 pci_set_drvdata(pdev, ddev); 2097 2098 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2099 if (ret) 2100 goto err_pci; 2101 2102 retry_init: 2103 ret = drm_dev_register(ddev, ent->driver_data); 2104 if (ret == -EAGAIN && ++retry <= 3) { 2105 DRM_INFO("retry init %d\n", retry); 2106 /* Don't request EX mode too frequently which is attacking */ 2107 msleep(5000); 2108 goto retry_init; 2109 } else if (ret) { 2110 goto err_pci; 2111 } 2112 2113 /* 2114 * 1. don't init fbdev on hw without DCE 2115 * 2. don't init fbdev if there are no connectors 2116 */ 2117 if (adev->mode_info.mode_config_initialized && 2118 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2119 /* select 8 bpp console on low vram cards */ 2120 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2121 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2122 else 2123 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2124 } 2125 2126 ret = amdgpu_debugfs_init(adev); 2127 if (ret) 2128 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2129 2130 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2131 /* only need to skip on ATPX */ 2132 if (amdgpu_device_supports_px(ddev)) 2133 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2134 /* we want direct complete for BOCO */ 2135 if (amdgpu_device_supports_boco(ddev)) 2136 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2137 DPM_FLAG_SMART_SUSPEND | 2138 DPM_FLAG_MAY_SKIP_RESUME); 2139 pm_runtime_use_autosuspend(ddev->dev); 2140 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2141 2142 pm_runtime_allow(ddev->dev); 2143 2144 pm_runtime_mark_last_busy(ddev->dev); 2145 pm_runtime_put_autosuspend(ddev->dev); 2146 2147 /* 2148 * For runpm implemented via BACO, PMFW will handle the 2149 * timing for BACO in and out: 2150 * - put ASIC into BACO state only when both video and 2151 * audio functions are in D3 state. 2152 * - pull ASIC out of BACO state when either video or 2153 * audio function is in D0 state. 2154 * Also, at startup, PMFW assumes both functions are in 2155 * D0 state. 2156 * 2157 * So if snd driver was loaded prior to amdgpu driver 2158 * and audio function was put into D3 state, there will 2159 * be no PMFW-aware D-state transition(D0->D3) on runpm 2160 * suspend. Thus the BACO will be not correctly kicked in. 2161 * 2162 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2163 * into D0 state. Then there will be a PMFW-aware D-state 2164 * transition(D0->D3) on runpm suspend. 2165 */ 2166 if (amdgpu_device_supports_baco(ddev) && 2167 !(adev->flags & AMD_IS_APU) && 2168 (adev->asic_type >= CHIP_NAVI10)) 2169 amdgpu_get_secondary_funcs(adev); 2170 } 2171 2172 return 0; 2173 2174 err_pci: 2175 pci_disable_device(pdev); 2176 return ret; 2177 } 2178 2179 static void 2180 amdgpu_pci_remove(struct pci_dev *pdev) 2181 { 2182 struct drm_device *dev = pci_get_drvdata(pdev); 2183 struct amdgpu_device *adev = drm_to_adev(dev); 2184 2185 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2186 pm_runtime_get_sync(dev->dev); 2187 pm_runtime_forbid(dev->dev); 2188 } 2189 2190 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) { 2191 bool need_to_reset_gpu = false; 2192 2193 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2194 struct amdgpu_hive_info *hive; 2195 2196 hive = amdgpu_get_xgmi_hive(adev); 2197 if (hive->device_remove_count == 0) 2198 need_to_reset_gpu = true; 2199 hive->device_remove_count++; 2200 amdgpu_put_xgmi_hive(hive); 2201 } else { 2202 need_to_reset_gpu = true; 2203 } 2204 2205 /* Workaround for ASICs need to reset SMU. 2206 * Called only when the first device is removed. 2207 */ 2208 if (need_to_reset_gpu) { 2209 struct amdgpu_reset_context reset_context; 2210 2211 adev->shutdown = true; 2212 memset(&reset_context, 0, sizeof(reset_context)); 2213 reset_context.method = AMD_RESET_METHOD_NONE; 2214 reset_context.reset_req_dev = adev; 2215 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2216 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2217 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2218 } 2219 } 2220 2221 amdgpu_driver_unload_kms(dev); 2222 2223 drm_dev_unplug(dev); 2224 2225 /* 2226 * Flush any in flight DMA operations from device. 2227 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2228 * StatusTransactions Pending bit. 2229 */ 2230 pci_disable_device(pdev); 2231 pci_wait_for_pending_transaction(pdev); 2232 } 2233 2234 static void 2235 amdgpu_pci_shutdown(struct pci_dev *pdev) 2236 { 2237 struct drm_device *dev = pci_get_drvdata(pdev); 2238 struct amdgpu_device *adev = drm_to_adev(dev); 2239 2240 if (amdgpu_ras_intr_triggered()) 2241 return; 2242 2243 /* if we are running in a VM, make sure the device 2244 * torn down properly on reboot/shutdown. 2245 * unfortunately we can't detect certain 2246 * hypervisors so just do this all the time. 2247 */ 2248 if (!amdgpu_passthrough(adev)) 2249 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2250 amdgpu_device_ip_suspend(adev); 2251 adev->mp1_state = PP_MP1_STATE_NONE; 2252 } 2253 2254 /** 2255 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2256 * 2257 * @work: work_struct. 2258 */ 2259 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2260 { 2261 struct list_head device_list; 2262 struct amdgpu_device *adev; 2263 int i, r; 2264 struct amdgpu_reset_context reset_context; 2265 2266 memset(&reset_context, 0, sizeof(reset_context)); 2267 2268 mutex_lock(&mgpu_info.mutex); 2269 if (mgpu_info.pending_reset == true) { 2270 mutex_unlock(&mgpu_info.mutex); 2271 return; 2272 } 2273 mgpu_info.pending_reset = true; 2274 mutex_unlock(&mgpu_info.mutex); 2275 2276 /* Use a common context, just need to make sure full reset is done */ 2277 reset_context.method = AMD_RESET_METHOD_NONE; 2278 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2279 2280 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2281 adev = mgpu_info.gpu_ins[i].adev; 2282 reset_context.reset_req_dev = adev; 2283 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2284 if (r) { 2285 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2286 r, adev_to_drm(adev)->unique); 2287 } 2288 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2289 r = -EALREADY; 2290 } 2291 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2292 adev = mgpu_info.gpu_ins[i].adev; 2293 flush_work(&adev->xgmi_reset_work); 2294 adev->gmc.xgmi.pending_reset = false; 2295 } 2296 2297 /* reset function will rebuild the xgmi hive info , clear it now */ 2298 for (i = 0; i < mgpu_info.num_dgpu; i++) 2299 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2300 2301 INIT_LIST_HEAD(&device_list); 2302 2303 for (i = 0; i < mgpu_info.num_dgpu; i++) 2304 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2305 2306 /* unregister the GPU first, reset function will add them back */ 2307 list_for_each_entry(adev, &device_list, reset_list) 2308 amdgpu_unregister_gpu_instance(adev); 2309 2310 /* Use a common context, just need to make sure full reset is done */ 2311 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2312 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2313 2314 if (r) { 2315 DRM_ERROR("reinit gpus failure"); 2316 return; 2317 } 2318 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2319 adev = mgpu_info.gpu_ins[i].adev; 2320 if (!adev->kfd.init_complete) 2321 amdgpu_amdkfd_device_init(adev); 2322 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2323 } 2324 return; 2325 } 2326 2327 static int amdgpu_pmops_prepare(struct device *dev) 2328 { 2329 struct drm_device *drm_dev = dev_get_drvdata(dev); 2330 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2331 2332 /* Return a positive number here so 2333 * DPM_FLAG_SMART_SUSPEND works properly 2334 */ 2335 if (amdgpu_device_supports_boco(drm_dev)) 2336 return pm_runtime_suspended(dev); 2337 2338 /* if we will not support s3 or s2i for the device 2339 * then skip suspend 2340 */ 2341 if (!amdgpu_acpi_is_s0ix_active(adev) && 2342 !amdgpu_acpi_is_s3_active(adev)) 2343 return 1; 2344 2345 return 0; 2346 } 2347 2348 static void amdgpu_pmops_complete(struct device *dev) 2349 { 2350 /* nothing to do */ 2351 } 2352 2353 static int amdgpu_pmops_suspend(struct device *dev) 2354 { 2355 struct drm_device *drm_dev = dev_get_drvdata(dev); 2356 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2357 2358 if (amdgpu_acpi_is_s0ix_active(adev)) 2359 adev->in_s0ix = true; 2360 else 2361 adev->in_s3 = true; 2362 return amdgpu_device_suspend(drm_dev, true); 2363 } 2364 2365 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2366 { 2367 struct drm_device *drm_dev = dev_get_drvdata(dev); 2368 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2369 2370 if (amdgpu_acpi_should_gpu_reset(adev)) 2371 return amdgpu_asic_reset(adev); 2372 2373 return 0; 2374 } 2375 2376 static int amdgpu_pmops_resume(struct device *dev) 2377 { 2378 struct drm_device *drm_dev = dev_get_drvdata(dev); 2379 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2380 int r; 2381 2382 /* Avoids registers access if device is physically gone */ 2383 if (!pci_device_is_present(adev->pdev)) 2384 adev->no_hw_access = true; 2385 2386 r = amdgpu_device_resume(drm_dev, true); 2387 if (amdgpu_acpi_is_s0ix_active(adev)) 2388 adev->in_s0ix = false; 2389 else 2390 adev->in_s3 = false; 2391 return r; 2392 } 2393 2394 static int amdgpu_pmops_freeze(struct device *dev) 2395 { 2396 struct drm_device *drm_dev = dev_get_drvdata(dev); 2397 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2398 int r; 2399 2400 adev->in_s4 = true; 2401 r = amdgpu_device_suspend(drm_dev, true); 2402 adev->in_s4 = false; 2403 if (r) 2404 return r; 2405 return amdgpu_asic_reset(adev); 2406 } 2407 2408 static int amdgpu_pmops_thaw(struct device *dev) 2409 { 2410 struct drm_device *drm_dev = dev_get_drvdata(dev); 2411 2412 return amdgpu_device_resume(drm_dev, true); 2413 } 2414 2415 static int amdgpu_pmops_poweroff(struct device *dev) 2416 { 2417 struct drm_device *drm_dev = dev_get_drvdata(dev); 2418 2419 return amdgpu_device_suspend(drm_dev, true); 2420 } 2421 2422 static int amdgpu_pmops_restore(struct device *dev) 2423 { 2424 struct drm_device *drm_dev = dev_get_drvdata(dev); 2425 2426 return amdgpu_device_resume(drm_dev, true); 2427 } 2428 2429 static int amdgpu_runtime_idle_check_display(struct device *dev) 2430 { 2431 struct pci_dev *pdev = to_pci_dev(dev); 2432 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2433 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2434 2435 if (adev->mode_info.num_crtc) { 2436 struct drm_connector *list_connector; 2437 struct drm_connector_list_iter iter; 2438 int ret = 0; 2439 2440 /* XXX: Return busy if any displays are connected to avoid 2441 * possible display wakeups after runtime resume due to 2442 * hotplug events in case any displays were connected while 2443 * the GPU was in suspend. Remove this once that is fixed. 2444 */ 2445 mutex_lock(&drm_dev->mode_config.mutex); 2446 drm_connector_list_iter_begin(drm_dev, &iter); 2447 drm_for_each_connector_iter(list_connector, &iter) { 2448 if (list_connector->status == connector_status_connected) { 2449 ret = -EBUSY; 2450 break; 2451 } 2452 } 2453 drm_connector_list_iter_end(&iter); 2454 mutex_unlock(&drm_dev->mode_config.mutex); 2455 2456 if (ret) 2457 return ret; 2458 2459 if (amdgpu_device_has_dc_support(adev)) { 2460 struct drm_crtc *crtc; 2461 2462 drm_for_each_crtc(crtc, drm_dev) { 2463 drm_modeset_lock(&crtc->mutex, NULL); 2464 if (crtc->state->active) 2465 ret = -EBUSY; 2466 drm_modeset_unlock(&crtc->mutex); 2467 if (ret < 0) 2468 break; 2469 } 2470 } else { 2471 mutex_lock(&drm_dev->mode_config.mutex); 2472 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2473 2474 drm_connector_list_iter_begin(drm_dev, &iter); 2475 drm_for_each_connector_iter(list_connector, &iter) { 2476 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2477 ret = -EBUSY; 2478 break; 2479 } 2480 } 2481 2482 drm_connector_list_iter_end(&iter); 2483 2484 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2485 mutex_unlock(&drm_dev->mode_config.mutex); 2486 } 2487 if (ret) 2488 return ret; 2489 } 2490 2491 return 0; 2492 } 2493 2494 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2495 { 2496 struct pci_dev *pdev = to_pci_dev(dev); 2497 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2498 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2499 int ret, i; 2500 2501 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2502 pm_runtime_forbid(dev); 2503 return -EBUSY; 2504 } 2505 2506 ret = amdgpu_runtime_idle_check_display(dev); 2507 if (ret) 2508 return ret; 2509 2510 /* wait for all rings to drain before suspending */ 2511 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2512 struct amdgpu_ring *ring = adev->rings[i]; 2513 if (ring && ring->sched.ready) { 2514 ret = amdgpu_fence_wait_empty(ring); 2515 if (ret) 2516 return -EBUSY; 2517 } 2518 } 2519 2520 adev->in_runpm = true; 2521 if (amdgpu_device_supports_px(drm_dev)) 2522 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2523 2524 /* 2525 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2526 * proper cleanups and put itself into a state ready for PNP. That 2527 * can address some random resuming failure observed on BOCO capable 2528 * platforms. 2529 * TODO: this may be also needed for PX capable platform. 2530 */ 2531 if (amdgpu_device_supports_boco(drm_dev)) 2532 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2533 2534 ret = amdgpu_device_suspend(drm_dev, false); 2535 if (ret) { 2536 adev->in_runpm = false; 2537 if (amdgpu_device_supports_boco(drm_dev)) 2538 adev->mp1_state = PP_MP1_STATE_NONE; 2539 return ret; 2540 } 2541 2542 if (amdgpu_device_supports_boco(drm_dev)) 2543 adev->mp1_state = PP_MP1_STATE_NONE; 2544 2545 if (amdgpu_device_supports_px(drm_dev)) { 2546 /* Only need to handle PCI state in the driver for ATPX 2547 * PCI core handles it for _PR3. 2548 */ 2549 amdgpu_device_cache_pci_state(pdev); 2550 pci_disable_device(pdev); 2551 pci_ignore_hotplug(pdev); 2552 pci_set_power_state(pdev, PCI_D3cold); 2553 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2554 } else if (amdgpu_device_supports_boco(drm_dev)) { 2555 /* nothing to do */ 2556 } else if (amdgpu_device_supports_baco(drm_dev)) { 2557 amdgpu_device_baco_enter(drm_dev); 2558 } 2559 2560 return 0; 2561 } 2562 2563 static int amdgpu_pmops_runtime_resume(struct device *dev) 2564 { 2565 struct pci_dev *pdev = to_pci_dev(dev); 2566 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2567 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2568 int ret; 2569 2570 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2571 return -EINVAL; 2572 2573 /* Avoids registers access if device is physically gone */ 2574 if (!pci_device_is_present(adev->pdev)) 2575 adev->no_hw_access = true; 2576 2577 if (amdgpu_device_supports_px(drm_dev)) { 2578 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2579 2580 /* Only need to handle PCI state in the driver for ATPX 2581 * PCI core handles it for _PR3. 2582 */ 2583 pci_set_power_state(pdev, PCI_D0); 2584 amdgpu_device_load_pci_state(pdev); 2585 ret = pci_enable_device(pdev); 2586 if (ret) 2587 return ret; 2588 pci_set_master(pdev); 2589 } else if (amdgpu_device_supports_boco(drm_dev)) { 2590 /* Only need to handle PCI state in the driver for ATPX 2591 * PCI core handles it for _PR3. 2592 */ 2593 pci_set_master(pdev); 2594 } else if (amdgpu_device_supports_baco(drm_dev)) { 2595 amdgpu_device_baco_exit(drm_dev); 2596 } 2597 ret = amdgpu_device_resume(drm_dev, false); 2598 if (ret) { 2599 if (amdgpu_device_supports_px(drm_dev)) 2600 pci_disable_device(pdev); 2601 return ret; 2602 } 2603 2604 if (amdgpu_device_supports_px(drm_dev)) 2605 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2606 adev->in_runpm = false; 2607 return 0; 2608 } 2609 2610 static int amdgpu_pmops_runtime_idle(struct device *dev) 2611 { 2612 struct drm_device *drm_dev = dev_get_drvdata(dev); 2613 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2614 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2615 int ret = 1; 2616 2617 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2618 pm_runtime_forbid(dev); 2619 return -EBUSY; 2620 } 2621 2622 ret = amdgpu_runtime_idle_check_display(dev); 2623 2624 pm_runtime_mark_last_busy(dev); 2625 pm_runtime_autosuspend(dev); 2626 return ret; 2627 } 2628 2629 long amdgpu_drm_ioctl(struct file *filp, 2630 unsigned int cmd, unsigned long arg) 2631 { 2632 struct drm_file *file_priv = filp->private_data; 2633 struct drm_device *dev; 2634 long ret; 2635 dev = file_priv->minor->dev; 2636 ret = pm_runtime_get_sync(dev->dev); 2637 if (ret < 0) 2638 goto out; 2639 2640 ret = drm_ioctl(filp, cmd, arg); 2641 2642 pm_runtime_mark_last_busy(dev->dev); 2643 out: 2644 pm_runtime_put_autosuspend(dev->dev); 2645 return ret; 2646 } 2647 2648 static const struct dev_pm_ops amdgpu_pm_ops = { 2649 .prepare = amdgpu_pmops_prepare, 2650 .complete = amdgpu_pmops_complete, 2651 .suspend = amdgpu_pmops_suspend, 2652 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2653 .resume = amdgpu_pmops_resume, 2654 .freeze = amdgpu_pmops_freeze, 2655 .thaw = amdgpu_pmops_thaw, 2656 .poweroff = amdgpu_pmops_poweroff, 2657 .restore = amdgpu_pmops_restore, 2658 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2659 .runtime_resume = amdgpu_pmops_runtime_resume, 2660 .runtime_idle = amdgpu_pmops_runtime_idle, 2661 }; 2662 2663 static int amdgpu_flush(struct file *f, fl_owner_t id) 2664 { 2665 struct drm_file *file_priv = f->private_data; 2666 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2667 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2668 2669 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2670 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2671 2672 return timeout >= 0 ? 0 : timeout; 2673 } 2674 2675 static const struct file_operations amdgpu_driver_kms_fops = { 2676 .owner = THIS_MODULE, 2677 .open = drm_open, 2678 .flush = amdgpu_flush, 2679 .release = drm_release, 2680 .unlocked_ioctl = amdgpu_drm_ioctl, 2681 .mmap = drm_gem_mmap, 2682 .poll = drm_poll, 2683 .read = drm_read, 2684 #ifdef CONFIG_COMPAT 2685 .compat_ioctl = amdgpu_kms_compat_ioctl, 2686 #endif 2687 #ifdef CONFIG_PROC_FS 2688 .show_fdinfo = amdgpu_show_fdinfo 2689 #endif 2690 }; 2691 2692 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2693 { 2694 struct drm_file *file; 2695 2696 if (!filp) 2697 return -EINVAL; 2698 2699 if (filp->f_op != &amdgpu_driver_kms_fops) { 2700 return -EINVAL; 2701 } 2702 2703 file = filp->private_data; 2704 *fpriv = file->driver_priv; 2705 return 0; 2706 } 2707 2708 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2709 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2710 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2711 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2712 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2713 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2714 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2715 /* KMS */ 2716 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2717 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2718 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2719 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2720 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2721 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2722 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2723 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2724 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2725 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2726 }; 2727 2728 static const struct drm_driver amdgpu_kms_driver = { 2729 .driver_features = 2730 DRIVER_ATOMIC | 2731 DRIVER_GEM | 2732 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2733 DRIVER_SYNCOBJ_TIMELINE, 2734 .open = amdgpu_driver_open_kms, 2735 .postclose = amdgpu_driver_postclose_kms, 2736 .lastclose = amdgpu_driver_lastclose_kms, 2737 .ioctls = amdgpu_ioctls_kms, 2738 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2739 .dumb_create = amdgpu_mode_dumb_create, 2740 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2741 .fops = &amdgpu_driver_kms_fops, 2742 .release = &amdgpu_driver_release_kms, 2743 2744 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2745 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2746 .gem_prime_import = amdgpu_gem_prime_import, 2747 .gem_prime_mmap = drm_gem_prime_mmap, 2748 2749 .name = DRIVER_NAME, 2750 .desc = DRIVER_DESC, 2751 .date = DRIVER_DATE, 2752 .major = KMS_DRIVER_MAJOR, 2753 .minor = KMS_DRIVER_MINOR, 2754 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2755 }; 2756 2757 static struct pci_error_handlers amdgpu_pci_err_handler = { 2758 .error_detected = amdgpu_pci_error_detected, 2759 .mmio_enabled = amdgpu_pci_mmio_enabled, 2760 .slot_reset = amdgpu_pci_slot_reset, 2761 .resume = amdgpu_pci_resume, 2762 }; 2763 2764 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2765 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2766 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2767 2768 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2769 &amdgpu_vram_mgr_attr_group, 2770 &amdgpu_gtt_mgr_attr_group, 2771 &amdgpu_vbios_version_attr_group, 2772 NULL, 2773 }; 2774 2775 2776 static struct pci_driver amdgpu_kms_pci_driver = { 2777 .name = DRIVER_NAME, 2778 .id_table = pciidlist, 2779 .probe = amdgpu_pci_probe, 2780 .remove = amdgpu_pci_remove, 2781 .shutdown = amdgpu_pci_shutdown, 2782 .driver.pm = &amdgpu_pm_ops, 2783 .err_handler = &amdgpu_pci_err_handler, 2784 .dev_groups = amdgpu_sysfs_groups, 2785 }; 2786 2787 static int __init amdgpu_init(void) 2788 { 2789 int r; 2790 2791 if (drm_firmware_drivers_only()) 2792 return -EINVAL; 2793 2794 r = amdgpu_sync_init(); 2795 if (r) 2796 goto error_sync; 2797 2798 r = amdgpu_fence_slab_init(); 2799 if (r) 2800 goto error_fence; 2801 2802 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2803 amdgpu_register_atpx_handler(); 2804 amdgpu_acpi_detect(); 2805 2806 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2807 amdgpu_amdkfd_init(); 2808 2809 /* let modprobe override vga console setting */ 2810 return pci_register_driver(&amdgpu_kms_pci_driver); 2811 2812 error_fence: 2813 amdgpu_sync_fini(); 2814 2815 error_sync: 2816 return r; 2817 } 2818 2819 static void __exit amdgpu_exit(void) 2820 { 2821 amdgpu_amdkfd_fini(); 2822 pci_unregister_driver(&amdgpu_kms_pci_driver); 2823 amdgpu_unregister_atpx_handler(); 2824 amdgpu_sync_fini(); 2825 amdgpu_fence_slab_fini(); 2826 mmu_notifier_synchronize(); 2827 } 2828 2829 module_init(amdgpu_init); 2830 module_exit(amdgpu_exit); 2831 2832 MODULE_AUTHOR(DRIVER_AUTHOR); 2833 MODULE_DESCRIPTION(DRIVER_DESC); 2834 MODULE_LICENSE("GPL and additional rights"); 2835