1 /*
2  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_aperture.h>
27 #include <drm/drm_drv.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_vblank.h>
30 #include <drm/drm_managed.h>
31 #include "amdgpu_drv.h"
32 
33 #include <drm/drm_pciids.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/cc_platform.h>
41 #include <linux/fb.h>
42 #include <linux/dynamic_debug.h>
43 
44 #include "amdgpu.h"
45 #include "amdgpu_irq.h"
46 #include "amdgpu_dma_buf.h"
47 #include "amdgpu_sched.h"
48 #include "amdgpu_fdinfo.h"
49 #include "amdgpu_amdkfd.h"
50 
51 #include "amdgpu_ras.h"
52 #include "amdgpu_xgmi.h"
53 #include "amdgpu_reset.h"
54 
55 /*
56  * KMS wrapper.
57  * - 3.0.0 - initial driver
58  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
59  * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
60  *           at the end of IBs.
61  * - 3.3.0 - Add VM support for UVD on supported hardware.
62  * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
63  * - 3.5.0 - Add support for new UVD_NO_OP register.
64  * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
65  * - 3.7.0 - Add support for VCE clock list packet
66  * - 3.8.0 - Add support raster config init in the kernel
67  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
68  * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
69  * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
70  * - 3.12.0 - Add query for double offchip LDS buffers
71  * - 3.13.0 - Add PRT support
72  * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
73  * - 3.15.0 - Export more gpu info for gfx9
74  * - 3.16.0 - Add reserved vmid support
75  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
76  * - 3.18.0 - Export gpu always on cu bitmap
77  * - 3.19.0 - Add support for UVD MJPEG decode
78  * - 3.20.0 - Add support for local BOs
79  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
80  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
81  * - 3.23.0 - Add query for VRAM lost counter
82  * - 3.24.0 - Add high priority compute support for gfx9
83  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
84  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
85  * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
86  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
87  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
88  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
89  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
90  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
91  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
92  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
93  * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
94  * - 3.36.0 - Allow reading more status registers on si/cik
95  * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
96  * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
97  * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
98  * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
99  * - 3.41.0 - Add video codec query
100  * - 3.42.0 - Add 16bpc fixed point display support
101  * - 3.43.0 - Add device hot plug/unplug support
102  * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
103  * - 3.45.0 - Add context ioctl stable pstate interface
104  * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
105  * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106  * - 3.48.0 - Add IP discovery version info to HW INFO
107  *   3.49.0 - Add gang submit into CS IOCTL
108  */
109 #define KMS_DRIVER_MAJOR	3
110 #define KMS_DRIVER_MINOR	49
111 #define KMS_DRIVER_PATCHLEVEL	0
112 
113 int amdgpu_vram_limit;
114 int amdgpu_vis_vram_limit;
115 int amdgpu_gart_size = -1; /* auto */
116 int amdgpu_gtt_size = -1; /* auto */
117 int amdgpu_moverate = -1; /* auto */
118 int amdgpu_audio = -1;
119 int amdgpu_disp_priority;
120 int amdgpu_hw_i2c;
121 int amdgpu_pcie_gen2 = -1;
122 int amdgpu_msi = -1;
123 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
124 int amdgpu_dpm = -1;
125 int amdgpu_fw_load_type = -1;
126 int amdgpu_aspm = -1;
127 int amdgpu_runtime_pm = -1;
128 uint amdgpu_ip_block_mask = 0xffffffff;
129 int amdgpu_bapm = -1;
130 int amdgpu_deep_color;
131 int amdgpu_vm_size = -1;
132 int amdgpu_vm_fragment_size = -1;
133 int amdgpu_vm_block_size = -1;
134 int amdgpu_vm_fault_stop;
135 int amdgpu_vm_debug;
136 int amdgpu_vm_update_mode = -1;
137 int amdgpu_exp_hw_support;
138 int amdgpu_dc = -1;
139 int amdgpu_sched_jobs = 32;
140 int amdgpu_sched_hw_submission = 2;
141 uint amdgpu_pcie_gen_cap;
142 uint amdgpu_pcie_lane_cap;
143 u64 amdgpu_cg_mask = 0xffffffffffffffff;
144 uint amdgpu_pg_mask = 0xffffffff;
145 uint amdgpu_sdma_phase_quantum = 32;
146 char *amdgpu_disable_cu = NULL;
147 char *amdgpu_virtual_display = NULL;
148 
149 /*
150  * OverDrive(bit 14) disabled by default
151  * GFX DCS(bit 19) disabled by default
152  */
153 uint amdgpu_pp_feature_mask = 0xfff7bfff;
154 uint amdgpu_force_long_training;
155 int amdgpu_job_hang_limit;
156 int amdgpu_lbpw = -1;
157 int amdgpu_compute_multipipe = -1;
158 int amdgpu_gpu_recovery = -1; /* auto */
159 int amdgpu_emu_mode;
160 uint amdgpu_smu_memory_pool_size;
161 int amdgpu_smu_pptable_id = -1;
162 /*
163  * FBC (bit 0) disabled by default
164  * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
165  *   - With this, for multiple monitors in sync(e.g. with the same model),
166  *     mclk switching will be allowed. And the mclk will be not foced to the
167  *     highest. That helps saving some idle power.
168  * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
169  * PSR (bit 3) disabled by default
170  * EDP NO POWER SEQUENCING (bit 4) disabled by default
171  */
172 uint amdgpu_dc_feature_mask = 2;
173 uint amdgpu_dc_debug_mask;
174 uint amdgpu_dc_visual_confirm;
175 int amdgpu_async_gfx_ring = 1;
176 int amdgpu_mcbp;
177 int amdgpu_discovery = -1;
178 int amdgpu_mes;
179 int amdgpu_mes_kiq;
180 int amdgpu_noretry = -1;
181 int amdgpu_force_asic_type = -1;
182 int amdgpu_tmz = -1; /* auto */
183 int amdgpu_reset_method = -1; /* auto */
184 int amdgpu_num_kcq = -1;
185 int amdgpu_smartshift_bias;
186 int amdgpu_use_xgmi_p2p = 1;
187 int amdgpu_vcnfw_log;
188 
189 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
190 
191 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
192 			"DRM_UT_CORE",
193 			"DRM_UT_DRIVER",
194 			"DRM_UT_KMS",
195 			"DRM_UT_PRIME",
196 			"DRM_UT_ATOMIC",
197 			"DRM_UT_VBL",
198 			"DRM_UT_STATE",
199 			"DRM_UT_LEASE",
200 			"DRM_UT_DP",
201 			"DRM_UT_DRMRES");
202 
203 struct amdgpu_mgpu_info mgpu_info = {
204 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
205 	.delayed_reset_work = __DELAYED_WORK_INITIALIZER(
206 			mgpu_info.delayed_reset_work,
207 			amdgpu_drv_delayed_reset_work_handler, 0),
208 };
209 int amdgpu_ras_enable = -1;
210 uint amdgpu_ras_mask = 0xffffffff;
211 int amdgpu_bad_page_threshold = -1;
212 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
213 	.timeout_fatal_disable = false,
214 	.period = 0x0, /* default to 0x0 (timeout disable) */
215 };
216 
217 /**
218  * DOC: vramlimit (int)
219  * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
220  */
221 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
222 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
223 
224 /**
225  * DOC: vis_vramlimit (int)
226  * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visible VRAM).
227  */
228 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
229 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
230 
231 /**
232  * DOC: gartsize (uint)
233  * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
234  */
235 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
236 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
237 
238 /**
239  * DOC: gttsize (int)
240  * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
241  * otherwise 3/4 RAM size).
242  */
243 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
244 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
245 
246 /**
247  * DOC: moverate (int)
248  * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
249  */
250 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
251 module_param_named(moverate, amdgpu_moverate, int, 0600);
252 
253 /**
254  * DOC: audio (int)
255  * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
256  */
257 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
258 module_param_named(audio, amdgpu_audio, int, 0444);
259 
260 /**
261  * DOC: disp_priority (int)
262  * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
263  */
264 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
265 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
266 
267 /**
268  * DOC: hw_i2c (int)
269  * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
270  */
271 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
272 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
273 
274 /**
275  * DOC: pcie_gen2 (int)
276  * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
277  */
278 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
279 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
280 
281 /**
282  * DOC: msi (int)
283  * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
284  */
285 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
286 module_param_named(msi, amdgpu_msi, int, 0444);
287 
288 /**
289  * DOC: lockup_timeout (string)
290  * Set GPU scheduler timeout value in ms.
291  *
292  * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
293  * multiple values specified. 0 and negative values are invalidated. They will be adjusted
294  * to the default timeout.
295  *
296  * - With one value specified, the setting will apply to all non-compute jobs.
297  * - With multiple values specified, the first one will be for GFX.
298  *   The second one is for Compute. The third and fourth ones are
299  *   for SDMA and Video.
300  *
301  * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
302  * jobs is 10000. The timeout for compute is 60000.
303  */
304 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
305 		"for passthrough or sriov, 10000 for all jobs."
306 		" 0: keep default value. negative: infinity timeout), "
307 		"format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
308 		"for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
309 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
310 
311 /**
312  * DOC: dpm (int)
313  * Override for dynamic power management setting
314  * (0 = disable, 1 = enable)
315  * The default is -1 (auto).
316  */
317 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
318 module_param_named(dpm, amdgpu_dpm, int, 0444);
319 
320 /**
321  * DOC: fw_load_type (int)
322  * Set different firmware loading type for debugging, if supported.
323  * Set to 0 to force direct loading if supported by the ASIC.  Set
324  * to -1 to select the default loading mode for the ASIC, as defined
325  * by the driver.  The default is -1 (auto).
326  */
327 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
328 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
329 
330 /**
331  * DOC: aspm (int)
332  * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
333  */
334 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
335 module_param_named(aspm, amdgpu_aspm, int, 0444);
336 
337 /**
338  * DOC: runpm (int)
339  * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
340  * the dGPUs when they are idle if supported. The default is -1 (auto enable).
341  * Setting the value to 0 disables this functionality.
342  */
343 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
344 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
345 
346 /**
347  * DOC: ip_block_mask (uint)
348  * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
349  * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
350  * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
351  * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
352  */
353 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
354 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
355 
356 /**
357  * DOC: bapm (int)
358  * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
359  * The default -1 (auto, enabled)
360  */
361 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
362 module_param_named(bapm, amdgpu_bapm, int, 0444);
363 
364 /**
365  * DOC: deep_color (int)
366  * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
367  */
368 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
369 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
370 
371 /**
372  * DOC: vm_size (int)
373  * Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (automatic for each asic).
374  */
375 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
376 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
377 
378 /**
379  * DOC: vm_fragment_size (int)
380  * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
381  */
382 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
383 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
384 
385 /**
386  * DOC: vm_block_size (int)
387  * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
388  */
389 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
390 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
391 
392 /**
393  * DOC: vm_fault_stop (int)
394  * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
395  */
396 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
397 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
398 
399 /**
400  * DOC: vm_debug (int)
401  * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
402  */
403 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
404 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
405 
406 /**
407  * DOC: vm_update_mode (int)
408  * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
409  * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
410  */
411 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
412 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
413 
414 /**
415  * DOC: exp_hw_support (int)
416  * Enable experimental hw support (1 = enable). The default is 0 (disabled).
417  */
418 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
419 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
420 
421 /**
422  * DOC: dc (int)
423  * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
424  */
425 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
426 module_param_named(dc, amdgpu_dc, int, 0444);
427 
428 /**
429  * DOC: sched_jobs (int)
430  * Override the max number of jobs supported in the sw queue. The default is 32.
431  */
432 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
433 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
434 
435 /**
436  * DOC: sched_hw_submission (int)
437  * Override the max number of HW submissions. The default is 2.
438  */
439 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
440 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
441 
442 /**
443  * DOC: ppfeaturemask (hexint)
444  * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
445  * The default is the current set of stable power features.
446  */
447 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
448 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
449 
450 /**
451  * DOC: forcelongtraining (uint)
452  * Force long memory training in resume.
453  * The default is zero, indicates short training in resume.
454  */
455 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
456 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
457 
458 /**
459  * DOC: pcie_gen_cap (uint)
460  * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
461  * The default is 0 (automatic for each asic).
462  */
463 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
464 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
465 
466 /**
467  * DOC: pcie_lane_cap (uint)
468  * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
469  * The default is 0 (automatic for each asic).
470  */
471 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
472 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
473 
474 /**
475  * DOC: cg_mask (ullong)
476  * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
477  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
478  */
479 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
480 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
481 
482 /**
483  * DOC: pg_mask (uint)
484  * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
485  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
486  */
487 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
488 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
489 
490 /**
491  * DOC: sdma_phase_quantum (uint)
492  * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
493  */
494 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
495 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
496 
497 /**
498  * DOC: disable_cu (charp)
499  * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
500  */
501 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
502 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
503 
504 /**
505  * DOC: virtual_display (charp)
506  * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
507  * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
508  * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
509  * device at 26:00.0. The default is NULL.
510  */
511 MODULE_PARM_DESC(virtual_display,
512 		 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
513 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
514 
515 /**
516  * DOC: job_hang_limit (int)
517  * Set how much time allow a job hang and not drop it. The default is 0.
518  */
519 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
520 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
521 
522 /**
523  * DOC: lbpw (int)
524  * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
525  */
526 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
527 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
528 
529 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
530 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
531 
532 /**
533  * DOC: gpu_recovery (int)
534  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
535  */
536 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
537 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
538 
539 /**
540  * DOC: emu_mode (int)
541  * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
542  */
543 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
544 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
545 
546 /**
547  * DOC: ras_enable (int)
548  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
549  */
550 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
551 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
552 
553 /**
554  * DOC: ras_mask (uint)
555  * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
556  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
557  */
558 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
559 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
560 
561 /**
562  * DOC: timeout_fatal_disable (bool)
563  * Disable Watchdog timeout fatal error event
564  */
565 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
566 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
567 
568 /**
569  * DOC: timeout_period (uint)
570  * Modify the watchdog timeout max_cycles as (1 << period)
571  */
572 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
573 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
574 
575 /**
576  * DOC: si_support (int)
577  * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
578  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
579  * otherwise using amdgpu driver.
580  */
581 #ifdef CONFIG_DRM_AMDGPU_SI
582 
583 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
584 int amdgpu_si_support = 0;
585 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
586 #else
587 int amdgpu_si_support = 1;
588 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
589 #endif
590 
591 module_param_named(si_support, amdgpu_si_support, int, 0444);
592 #endif
593 
594 /**
595  * DOC: cik_support (int)
596  * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
597  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
598  * otherwise using amdgpu driver.
599  */
600 #ifdef CONFIG_DRM_AMDGPU_CIK
601 
602 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
603 int amdgpu_cik_support = 0;
604 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
605 #else
606 int amdgpu_cik_support = 1;
607 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
608 #endif
609 
610 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
611 #endif
612 
613 /**
614  * DOC: smu_memory_pool_size (uint)
615  * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
616  * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
617  */
618 MODULE_PARM_DESC(smu_memory_pool_size,
619 	"reserve gtt for smu debug usage, 0 = disable,"
620 		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
621 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
622 
623 /**
624  * DOC: async_gfx_ring (int)
625  * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
626  */
627 MODULE_PARM_DESC(async_gfx_ring,
628 	"Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
629 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
630 
631 /**
632  * DOC: mcbp (int)
633  * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
634  */
635 MODULE_PARM_DESC(mcbp,
636 	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
637 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
638 
639 /**
640  * DOC: discovery (int)
641  * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
642  * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
643  */
644 MODULE_PARM_DESC(discovery,
645 	"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
646 module_param_named(discovery, amdgpu_discovery, int, 0444);
647 
648 /**
649  * DOC: mes (int)
650  * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
651  * (0 = disabled (default), 1 = enabled)
652  */
653 MODULE_PARM_DESC(mes,
654 	"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
655 module_param_named(mes, amdgpu_mes, int, 0444);
656 
657 /**
658  * DOC: mes_kiq (int)
659  * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
660  * (0 = disabled (default), 1 = enabled)
661  */
662 MODULE_PARM_DESC(mes_kiq,
663 	"Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
664 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
665 
666 /**
667  * DOC: noretry (int)
668  * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
669  * do not support per-process XNACK this also disables retry page faults.
670  * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
671  */
672 MODULE_PARM_DESC(noretry,
673 	"Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
674 module_param_named(noretry, amdgpu_noretry, int, 0644);
675 
676 /**
677  * DOC: force_asic_type (int)
678  * A non negative value used to specify the asic type for all supported GPUs.
679  */
680 MODULE_PARM_DESC(force_asic_type,
681 	"A non negative value used to specify the asic type for all supported GPUs");
682 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
683 
684 /**
685  * DOC: use_xgmi_p2p (int)
686  * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
687  */
688 MODULE_PARM_DESC(use_xgmi_p2p,
689 	"Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
690 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
691 
692 
693 #ifdef CONFIG_HSA_AMD
694 /**
695  * DOC: sched_policy (int)
696  * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
697  * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
698  * assigns queues to HQDs.
699  */
700 int sched_policy = KFD_SCHED_POLICY_HWS;
701 module_param(sched_policy, int, 0444);
702 MODULE_PARM_DESC(sched_policy,
703 	"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
704 
705 /**
706  * DOC: hws_max_conc_proc (int)
707  * Maximum number of processes that HWS can schedule concurrently. The maximum is the
708  * number of VMIDs assigned to the HWS, which is also the default.
709  */
710 int hws_max_conc_proc = -1;
711 module_param(hws_max_conc_proc, int, 0444);
712 MODULE_PARM_DESC(hws_max_conc_proc,
713 	"Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
714 
715 /**
716  * DOC: cwsr_enable (int)
717  * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
718  * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
719  * disables it.
720  */
721 int cwsr_enable = 1;
722 module_param(cwsr_enable, int, 0444);
723 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
724 
725 /**
726  * DOC: max_num_of_queues_per_device (int)
727  * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
728  * is 4096.
729  */
730 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
731 module_param(max_num_of_queues_per_device, int, 0444);
732 MODULE_PARM_DESC(max_num_of_queues_per_device,
733 	"Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
734 
735 /**
736  * DOC: send_sigterm (int)
737  * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
738  * but just print errors on dmesg. Setting 1 enables sending sigterm.
739  */
740 int send_sigterm;
741 module_param(send_sigterm, int, 0444);
742 MODULE_PARM_DESC(send_sigterm,
743 	"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
744 
745 /**
746  * DOC: debug_largebar (int)
747  * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
748  * system. This limits the VRAM size reported to ROCm applications to the visible
749  * size, usually 256MB.
750  * Default value is 0, diabled.
751  */
752 int debug_largebar;
753 module_param(debug_largebar, int, 0444);
754 MODULE_PARM_DESC(debug_largebar,
755 	"Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
756 
757 /**
758  * DOC: ignore_crat (int)
759  * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
760  * table to get information about AMD APUs. This option can serve as a workaround on
761  * systems with a broken CRAT table.
762  *
763  * Default is auto (according to asic type, iommu_v2, and crat table, to decide
764  * whether use CRAT)
765  */
766 int ignore_crat;
767 module_param(ignore_crat, int, 0444);
768 MODULE_PARM_DESC(ignore_crat,
769 	"Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
770 
771 /**
772  * DOC: halt_if_hws_hang (int)
773  * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
774  * Setting 1 enables halt on hang.
775  */
776 int halt_if_hws_hang;
777 module_param(halt_if_hws_hang, int, 0644);
778 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
779 
780 /**
781  * DOC: hws_gws_support(bool)
782  * Assume that HWS supports GWS barriers regardless of what firmware version
783  * check says. Default value: false (rely on MEC2 firmware version check).
784  */
785 bool hws_gws_support;
786 module_param(hws_gws_support, bool, 0444);
787 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
788 
789 /**
790   * DOC: queue_preemption_timeout_ms (int)
791   * queue preemption timeout in ms (1 = Minimum, 9000 = default)
792   */
793 int queue_preemption_timeout_ms = 9000;
794 module_param(queue_preemption_timeout_ms, int, 0644);
795 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
796 
797 /**
798  * DOC: debug_evictions(bool)
799  * Enable extra debug messages to help determine the cause of evictions
800  */
801 bool debug_evictions;
802 module_param(debug_evictions, bool, 0644);
803 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
804 
805 /**
806  * DOC: no_system_mem_limit(bool)
807  * Disable system memory limit, to support multiple process shared memory
808  */
809 bool no_system_mem_limit;
810 module_param(no_system_mem_limit, bool, 0644);
811 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
812 
813 /**
814  * DOC: no_queue_eviction_on_vm_fault (int)
815  * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
816  */
817 int amdgpu_no_queue_eviction_on_vm_fault = 0;
818 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
819 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
820 #endif
821 
822 /**
823  * DOC: pcie_p2p (bool)
824  * Enable PCIe P2P (requires large-BAR). Default value: true (on)
825  */
826 #ifdef CONFIG_HSA_AMD_P2P
827 bool pcie_p2p = true;
828 module_param(pcie_p2p, bool, 0444);
829 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
830 #endif
831 
832 /**
833  * DOC: dcfeaturemask (uint)
834  * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
835  * The default is the current set of stable display features.
836  */
837 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
838 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
839 
840 /**
841  * DOC: dcdebugmask (uint)
842  * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
843  */
844 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
845 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
846 
847 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
848 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
849 
850 /**
851  * DOC: abmlevel (uint)
852  * Override the default ABM (Adaptive Backlight Management) level used for DC
853  * enabled hardware. Requires DMCU to be supported and loaded.
854  * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
855  * default. Values 1-4 control the maximum allowable brightness reduction via
856  * the ABM algorithm, with 1 being the least reduction and 4 being the most
857  * reduction.
858  *
859  * Defaults to 0, or disabled. Userspace can still override this level later
860  * after boot.
861  */
862 uint amdgpu_dm_abm_level;
863 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
864 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
865 
866 int amdgpu_backlight = -1;
867 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
868 module_param_named(backlight, amdgpu_backlight, bint, 0444);
869 
870 /**
871  * DOC: tmz (int)
872  * Trusted Memory Zone (TMZ) is a method to protect data being written
873  * to or read from memory.
874  *
875  * The default value: 0 (off).  TODO: change to auto till it is completed.
876  */
877 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
878 module_param_named(tmz, amdgpu_tmz, int, 0444);
879 
880 /**
881  * DOC: reset_method (int)
882  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
883  */
884 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
885 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
886 
887 /**
888  * DOC: bad_page_threshold (int) Bad page threshold is specifies the
889  * threshold value of faulty pages detected by RAS ECC, which may
890  * result in the GPU entering bad status when the number of total
891  * faulty pages by ECC exceeds the threshold value.
892  */
893 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
894 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
895 
896 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
897 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
898 
899 /**
900  * DOC: vcnfw_log (int)
901  * Enable vcnfw log output for debugging, the default is disabled.
902  */
903 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
904 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
905 
906 /**
907  * DOC: smu_pptable_id (int)
908  * Used to override pptable id. id = 0 use VBIOS pptable.
909  * id > 0 use the soft pptable with specicfied id.
910  */
911 MODULE_PARM_DESC(smu_pptable_id,
912 	"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
913 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
914 
915 /* These devices are not supported by amdgpu.
916  * They are supported by the mach64, r128, radeon drivers
917  */
918 static const u16 amdgpu_unsupported_pciidlist[] = {
919 	/* mach64 */
920 	0x4354,
921 	0x4358,
922 	0x4554,
923 	0x4742,
924 	0x4744,
925 	0x4749,
926 	0x474C,
927 	0x474D,
928 	0x474E,
929 	0x474F,
930 	0x4750,
931 	0x4751,
932 	0x4752,
933 	0x4753,
934 	0x4754,
935 	0x4755,
936 	0x4756,
937 	0x4757,
938 	0x4758,
939 	0x4759,
940 	0x475A,
941 	0x4C42,
942 	0x4C44,
943 	0x4C47,
944 	0x4C49,
945 	0x4C4D,
946 	0x4C4E,
947 	0x4C50,
948 	0x4C51,
949 	0x4C52,
950 	0x4C53,
951 	0x5654,
952 	0x5655,
953 	0x5656,
954 	/* r128 */
955 	0x4c45,
956 	0x4c46,
957 	0x4d46,
958 	0x4d4c,
959 	0x5041,
960 	0x5042,
961 	0x5043,
962 	0x5044,
963 	0x5045,
964 	0x5046,
965 	0x5047,
966 	0x5048,
967 	0x5049,
968 	0x504A,
969 	0x504B,
970 	0x504C,
971 	0x504D,
972 	0x504E,
973 	0x504F,
974 	0x5050,
975 	0x5051,
976 	0x5052,
977 	0x5053,
978 	0x5054,
979 	0x5055,
980 	0x5056,
981 	0x5057,
982 	0x5058,
983 	0x5245,
984 	0x5246,
985 	0x5247,
986 	0x524b,
987 	0x524c,
988 	0x534d,
989 	0x5446,
990 	0x544C,
991 	0x5452,
992 	/* radeon */
993 	0x3150,
994 	0x3151,
995 	0x3152,
996 	0x3154,
997 	0x3155,
998 	0x3E50,
999 	0x3E54,
1000 	0x4136,
1001 	0x4137,
1002 	0x4144,
1003 	0x4145,
1004 	0x4146,
1005 	0x4147,
1006 	0x4148,
1007 	0x4149,
1008 	0x414A,
1009 	0x414B,
1010 	0x4150,
1011 	0x4151,
1012 	0x4152,
1013 	0x4153,
1014 	0x4154,
1015 	0x4155,
1016 	0x4156,
1017 	0x4237,
1018 	0x4242,
1019 	0x4336,
1020 	0x4337,
1021 	0x4437,
1022 	0x4966,
1023 	0x4967,
1024 	0x4A48,
1025 	0x4A49,
1026 	0x4A4A,
1027 	0x4A4B,
1028 	0x4A4C,
1029 	0x4A4D,
1030 	0x4A4E,
1031 	0x4A4F,
1032 	0x4A50,
1033 	0x4A54,
1034 	0x4B48,
1035 	0x4B49,
1036 	0x4B4A,
1037 	0x4B4B,
1038 	0x4B4C,
1039 	0x4C57,
1040 	0x4C58,
1041 	0x4C59,
1042 	0x4C5A,
1043 	0x4C64,
1044 	0x4C66,
1045 	0x4C67,
1046 	0x4E44,
1047 	0x4E45,
1048 	0x4E46,
1049 	0x4E47,
1050 	0x4E48,
1051 	0x4E49,
1052 	0x4E4A,
1053 	0x4E4B,
1054 	0x4E50,
1055 	0x4E51,
1056 	0x4E52,
1057 	0x4E53,
1058 	0x4E54,
1059 	0x4E56,
1060 	0x5144,
1061 	0x5145,
1062 	0x5146,
1063 	0x5147,
1064 	0x5148,
1065 	0x514C,
1066 	0x514D,
1067 	0x5157,
1068 	0x5158,
1069 	0x5159,
1070 	0x515A,
1071 	0x515E,
1072 	0x5460,
1073 	0x5462,
1074 	0x5464,
1075 	0x5548,
1076 	0x5549,
1077 	0x554A,
1078 	0x554B,
1079 	0x554C,
1080 	0x554D,
1081 	0x554E,
1082 	0x554F,
1083 	0x5550,
1084 	0x5551,
1085 	0x5552,
1086 	0x5554,
1087 	0x564A,
1088 	0x564B,
1089 	0x564F,
1090 	0x5652,
1091 	0x5653,
1092 	0x5657,
1093 	0x5834,
1094 	0x5835,
1095 	0x5954,
1096 	0x5955,
1097 	0x5974,
1098 	0x5975,
1099 	0x5960,
1100 	0x5961,
1101 	0x5962,
1102 	0x5964,
1103 	0x5965,
1104 	0x5969,
1105 	0x5a41,
1106 	0x5a42,
1107 	0x5a61,
1108 	0x5a62,
1109 	0x5b60,
1110 	0x5b62,
1111 	0x5b63,
1112 	0x5b64,
1113 	0x5b65,
1114 	0x5c61,
1115 	0x5c63,
1116 	0x5d48,
1117 	0x5d49,
1118 	0x5d4a,
1119 	0x5d4c,
1120 	0x5d4d,
1121 	0x5d4e,
1122 	0x5d4f,
1123 	0x5d50,
1124 	0x5d52,
1125 	0x5d57,
1126 	0x5e48,
1127 	0x5e4a,
1128 	0x5e4b,
1129 	0x5e4c,
1130 	0x5e4d,
1131 	0x5e4f,
1132 	0x6700,
1133 	0x6701,
1134 	0x6702,
1135 	0x6703,
1136 	0x6704,
1137 	0x6705,
1138 	0x6706,
1139 	0x6707,
1140 	0x6708,
1141 	0x6709,
1142 	0x6718,
1143 	0x6719,
1144 	0x671c,
1145 	0x671d,
1146 	0x671f,
1147 	0x6720,
1148 	0x6721,
1149 	0x6722,
1150 	0x6723,
1151 	0x6724,
1152 	0x6725,
1153 	0x6726,
1154 	0x6727,
1155 	0x6728,
1156 	0x6729,
1157 	0x6738,
1158 	0x6739,
1159 	0x673e,
1160 	0x6740,
1161 	0x6741,
1162 	0x6742,
1163 	0x6743,
1164 	0x6744,
1165 	0x6745,
1166 	0x6746,
1167 	0x6747,
1168 	0x6748,
1169 	0x6749,
1170 	0x674A,
1171 	0x6750,
1172 	0x6751,
1173 	0x6758,
1174 	0x6759,
1175 	0x675B,
1176 	0x675D,
1177 	0x675F,
1178 	0x6760,
1179 	0x6761,
1180 	0x6762,
1181 	0x6763,
1182 	0x6764,
1183 	0x6765,
1184 	0x6766,
1185 	0x6767,
1186 	0x6768,
1187 	0x6770,
1188 	0x6771,
1189 	0x6772,
1190 	0x6778,
1191 	0x6779,
1192 	0x677B,
1193 	0x6840,
1194 	0x6841,
1195 	0x6842,
1196 	0x6843,
1197 	0x6849,
1198 	0x684C,
1199 	0x6850,
1200 	0x6858,
1201 	0x6859,
1202 	0x6880,
1203 	0x6888,
1204 	0x6889,
1205 	0x688A,
1206 	0x688C,
1207 	0x688D,
1208 	0x6898,
1209 	0x6899,
1210 	0x689b,
1211 	0x689c,
1212 	0x689d,
1213 	0x689e,
1214 	0x68a0,
1215 	0x68a1,
1216 	0x68a8,
1217 	0x68a9,
1218 	0x68b0,
1219 	0x68b8,
1220 	0x68b9,
1221 	0x68ba,
1222 	0x68be,
1223 	0x68bf,
1224 	0x68c0,
1225 	0x68c1,
1226 	0x68c7,
1227 	0x68c8,
1228 	0x68c9,
1229 	0x68d8,
1230 	0x68d9,
1231 	0x68da,
1232 	0x68de,
1233 	0x68e0,
1234 	0x68e1,
1235 	0x68e4,
1236 	0x68e5,
1237 	0x68e8,
1238 	0x68e9,
1239 	0x68f1,
1240 	0x68f2,
1241 	0x68f8,
1242 	0x68f9,
1243 	0x68fa,
1244 	0x68fe,
1245 	0x7100,
1246 	0x7101,
1247 	0x7102,
1248 	0x7103,
1249 	0x7104,
1250 	0x7105,
1251 	0x7106,
1252 	0x7108,
1253 	0x7109,
1254 	0x710A,
1255 	0x710B,
1256 	0x710C,
1257 	0x710E,
1258 	0x710F,
1259 	0x7140,
1260 	0x7141,
1261 	0x7142,
1262 	0x7143,
1263 	0x7144,
1264 	0x7145,
1265 	0x7146,
1266 	0x7147,
1267 	0x7149,
1268 	0x714A,
1269 	0x714B,
1270 	0x714C,
1271 	0x714D,
1272 	0x714E,
1273 	0x714F,
1274 	0x7151,
1275 	0x7152,
1276 	0x7153,
1277 	0x715E,
1278 	0x715F,
1279 	0x7180,
1280 	0x7181,
1281 	0x7183,
1282 	0x7186,
1283 	0x7187,
1284 	0x7188,
1285 	0x718A,
1286 	0x718B,
1287 	0x718C,
1288 	0x718D,
1289 	0x718F,
1290 	0x7193,
1291 	0x7196,
1292 	0x719B,
1293 	0x719F,
1294 	0x71C0,
1295 	0x71C1,
1296 	0x71C2,
1297 	0x71C3,
1298 	0x71C4,
1299 	0x71C5,
1300 	0x71C6,
1301 	0x71C7,
1302 	0x71CD,
1303 	0x71CE,
1304 	0x71D2,
1305 	0x71D4,
1306 	0x71D5,
1307 	0x71D6,
1308 	0x71DA,
1309 	0x71DE,
1310 	0x7200,
1311 	0x7210,
1312 	0x7211,
1313 	0x7240,
1314 	0x7243,
1315 	0x7244,
1316 	0x7245,
1317 	0x7246,
1318 	0x7247,
1319 	0x7248,
1320 	0x7249,
1321 	0x724A,
1322 	0x724B,
1323 	0x724C,
1324 	0x724D,
1325 	0x724E,
1326 	0x724F,
1327 	0x7280,
1328 	0x7281,
1329 	0x7283,
1330 	0x7284,
1331 	0x7287,
1332 	0x7288,
1333 	0x7289,
1334 	0x728B,
1335 	0x728C,
1336 	0x7290,
1337 	0x7291,
1338 	0x7293,
1339 	0x7297,
1340 	0x7834,
1341 	0x7835,
1342 	0x791e,
1343 	0x791f,
1344 	0x793f,
1345 	0x7941,
1346 	0x7942,
1347 	0x796c,
1348 	0x796d,
1349 	0x796e,
1350 	0x796f,
1351 	0x9400,
1352 	0x9401,
1353 	0x9402,
1354 	0x9403,
1355 	0x9405,
1356 	0x940A,
1357 	0x940B,
1358 	0x940F,
1359 	0x94A0,
1360 	0x94A1,
1361 	0x94A3,
1362 	0x94B1,
1363 	0x94B3,
1364 	0x94B4,
1365 	0x94B5,
1366 	0x94B9,
1367 	0x9440,
1368 	0x9441,
1369 	0x9442,
1370 	0x9443,
1371 	0x9444,
1372 	0x9446,
1373 	0x944A,
1374 	0x944B,
1375 	0x944C,
1376 	0x944E,
1377 	0x9450,
1378 	0x9452,
1379 	0x9456,
1380 	0x945A,
1381 	0x945B,
1382 	0x945E,
1383 	0x9460,
1384 	0x9462,
1385 	0x946A,
1386 	0x946B,
1387 	0x947A,
1388 	0x947B,
1389 	0x9480,
1390 	0x9487,
1391 	0x9488,
1392 	0x9489,
1393 	0x948A,
1394 	0x948F,
1395 	0x9490,
1396 	0x9491,
1397 	0x9495,
1398 	0x9498,
1399 	0x949C,
1400 	0x949E,
1401 	0x949F,
1402 	0x94C0,
1403 	0x94C1,
1404 	0x94C3,
1405 	0x94C4,
1406 	0x94C5,
1407 	0x94C6,
1408 	0x94C7,
1409 	0x94C8,
1410 	0x94C9,
1411 	0x94CB,
1412 	0x94CC,
1413 	0x94CD,
1414 	0x9500,
1415 	0x9501,
1416 	0x9504,
1417 	0x9505,
1418 	0x9506,
1419 	0x9507,
1420 	0x9508,
1421 	0x9509,
1422 	0x950F,
1423 	0x9511,
1424 	0x9515,
1425 	0x9517,
1426 	0x9519,
1427 	0x9540,
1428 	0x9541,
1429 	0x9542,
1430 	0x954E,
1431 	0x954F,
1432 	0x9552,
1433 	0x9553,
1434 	0x9555,
1435 	0x9557,
1436 	0x955f,
1437 	0x9580,
1438 	0x9581,
1439 	0x9583,
1440 	0x9586,
1441 	0x9587,
1442 	0x9588,
1443 	0x9589,
1444 	0x958A,
1445 	0x958B,
1446 	0x958C,
1447 	0x958D,
1448 	0x958E,
1449 	0x958F,
1450 	0x9590,
1451 	0x9591,
1452 	0x9593,
1453 	0x9595,
1454 	0x9596,
1455 	0x9597,
1456 	0x9598,
1457 	0x9599,
1458 	0x959B,
1459 	0x95C0,
1460 	0x95C2,
1461 	0x95C4,
1462 	0x95C5,
1463 	0x95C6,
1464 	0x95C7,
1465 	0x95C9,
1466 	0x95CC,
1467 	0x95CD,
1468 	0x95CE,
1469 	0x95CF,
1470 	0x9610,
1471 	0x9611,
1472 	0x9612,
1473 	0x9613,
1474 	0x9614,
1475 	0x9615,
1476 	0x9616,
1477 	0x9640,
1478 	0x9641,
1479 	0x9642,
1480 	0x9643,
1481 	0x9644,
1482 	0x9645,
1483 	0x9647,
1484 	0x9648,
1485 	0x9649,
1486 	0x964a,
1487 	0x964b,
1488 	0x964c,
1489 	0x964e,
1490 	0x964f,
1491 	0x9710,
1492 	0x9711,
1493 	0x9712,
1494 	0x9713,
1495 	0x9714,
1496 	0x9715,
1497 	0x9802,
1498 	0x9803,
1499 	0x9804,
1500 	0x9805,
1501 	0x9806,
1502 	0x9807,
1503 	0x9808,
1504 	0x9809,
1505 	0x980A,
1506 	0x9900,
1507 	0x9901,
1508 	0x9903,
1509 	0x9904,
1510 	0x9905,
1511 	0x9906,
1512 	0x9907,
1513 	0x9908,
1514 	0x9909,
1515 	0x990A,
1516 	0x990B,
1517 	0x990C,
1518 	0x990D,
1519 	0x990E,
1520 	0x990F,
1521 	0x9910,
1522 	0x9913,
1523 	0x9917,
1524 	0x9918,
1525 	0x9919,
1526 	0x9990,
1527 	0x9991,
1528 	0x9992,
1529 	0x9993,
1530 	0x9994,
1531 	0x9995,
1532 	0x9996,
1533 	0x9997,
1534 	0x9998,
1535 	0x9999,
1536 	0x999A,
1537 	0x999B,
1538 	0x999C,
1539 	0x999D,
1540 	0x99A0,
1541 	0x99A2,
1542 	0x99A4,
1543 	/* radeon secondary ids */
1544 	0x3171,
1545 	0x3e70,
1546 	0x4164,
1547 	0x4165,
1548 	0x4166,
1549 	0x4168,
1550 	0x4170,
1551 	0x4171,
1552 	0x4172,
1553 	0x4173,
1554 	0x496e,
1555 	0x4a69,
1556 	0x4a6a,
1557 	0x4a6b,
1558 	0x4a70,
1559 	0x4a74,
1560 	0x4b69,
1561 	0x4b6b,
1562 	0x4b6c,
1563 	0x4c6e,
1564 	0x4e64,
1565 	0x4e65,
1566 	0x4e66,
1567 	0x4e67,
1568 	0x4e68,
1569 	0x4e69,
1570 	0x4e6a,
1571 	0x4e71,
1572 	0x4f73,
1573 	0x5569,
1574 	0x556b,
1575 	0x556d,
1576 	0x556f,
1577 	0x5571,
1578 	0x5854,
1579 	0x5874,
1580 	0x5940,
1581 	0x5941,
1582 	0x5b72,
1583 	0x5b73,
1584 	0x5b74,
1585 	0x5b75,
1586 	0x5d44,
1587 	0x5d45,
1588 	0x5d6d,
1589 	0x5d6f,
1590 	0x5d72,
1591 	0x5d77,
1592 	0x5e6b,
1593 	0x5e6d,
1594 	0x7120,
1595 	0x7124,
1596 	0x7129,
1597 	0x712e,
1598 	0x712f,
1599 	0x7162,
1600 	0x7163,
1601 	0x7166,
1602 	0x7167,
1603 	0x7172,
1604 	0x7173,
1605 	0x71a0,
1606 	0x71a1,
1607 	0x71a3,
1608 	0x71a7,
1609 	0x71bb,
1610 	0x71e0,
1611 	0x71e1,
1612 	0x71e2,
1613 	0x71e6,
1614 	0x71e7,
1615 	0x71f2,
1616 	0x7269,
1617 	0x726b,
1618 	0x726e,
1619 	0x72a0,
1620 	0x72a8,
1621 	0x72b1,
1622 	0x72b3,
1623 	0x793f,
1624 };
1625 
1626 static const struct pci_device_id pciidlist[] = {
1627 #ifdef  CONFIG_DRM_AMDGPU_SI
1628 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1629 	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1630 	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1631 	{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1632 	{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1633 	{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1634 	{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1635 	{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1636 	{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1637 	{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1638 	{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1639 	{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1640 	{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1641 	{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1642 	{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1643 	{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1644 	{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1645 	{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1646 	{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1647 	{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1648 	{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1649 	{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1650 	{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1651 	{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1652 	{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1653 	{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1654 	{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1655 	{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1656 	{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1657 	{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1658 	{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1659 	{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1660 	{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1661 	{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1662 	{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1663 	{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1664 	{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1665 	{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1666 	{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1667 	{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1668 	{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1669 	{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1670 	{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1671 	{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1672 	{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1673 	{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1674 	{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1675 	{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1676 	{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1677 	{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1678 	{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1679 	{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1680 	{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1681 	{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1682 	{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1683 	{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1684 	{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1685 	{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1686 	{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1687 	{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1688 	{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1689 	{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1690 	{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1691 	{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1692 	{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1693 	{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1694 	{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1695 	{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1696 	{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1697 	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1698 	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1699 	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1700 #endif
1701 #ifdef CONFIG_DRM_AMDGPU_CIK
1702 	/* Kaveri */
1703 	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1704 	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1705 	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1706 	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1707 	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1708 	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1709 	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1710 	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1711 	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1712 	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1713 	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1714 	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1715 	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1716 	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1717 	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1718 	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1719 	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1720 	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1721 	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1722 	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1723 	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1724 	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1725 	/* Bonaire */
1726 	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1727 	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1728 	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1729 	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1730 	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1731 	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1732 	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1733 	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1734 	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1735 	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1736 	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1737 	/* Hawaii */
1738 	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1739 	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1740 	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1741 	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1742 	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1743 	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1744 	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1745 	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1746 	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1747 	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1748 	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1749 	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1750 	/* Kabini */
1751 	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1752 	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1753 	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1754 	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1755 	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1756 	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1757 	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1758 	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1759 	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1760 	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1761 	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1762 	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1763 	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1764 	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1765 	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1766 	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1767 	/* mullins */
1768 	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1769 	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1770 	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1771 	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1772 	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1773 	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1774 	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1775 	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1776 	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1777 	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1778 	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1779 	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1780 	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1781 	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1782 	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1783 	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1784 #endif
1785 	/* topaz */
1786 	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1787 	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1788 	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1789 	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1790 	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1791 	/* tonga */
1792 	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1793 	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1794 	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1795 	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1796 	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1797 	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1798 	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1799 	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1800 	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1801 	/* fiji */
1802 	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1803 	{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1804 	/* carrizo */
1805 	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1806 	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1807 	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1808 	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1809 	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1810 	/* stoney */
1811 	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1812 	/* Polaris11 */
1813 	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1814 	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1815 	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1816 	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1817 	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1818 	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1819 	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1820 	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1821 	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1822 	/* Polaris10 */
1823 	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1824 	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1825 	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1826 	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1827 	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1828 	{0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1829 	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1830 	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1831 	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1832 	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1833 	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1834 	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1835 	{0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1836 	/* Polaris12 */
1837 	{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1838 	{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1839 	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1840 	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1841 	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1842 	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1843 	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1844 	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1845 	/* VEGAM */
1846 	{0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1847 	{0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1848 	{0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1849 	/* Vega 10 */
1850 	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1851 	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1852 	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1853 	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1854 	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1855 	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1856 	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1857 	{0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1858 	{0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1859 	{0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1860 	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1861 	{0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1862 	{0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1863 	{0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1864 	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1865 	/* Vega 12 */
1866 	{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1867 	{0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1868 	{0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1869 	{0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1870 	{0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1871 	/* Vega 20 */
1872 	{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1873 	{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1874 	{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1875 	{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1876 	{0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1877 	{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1878 	{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1879 	/* Raven */
1880 	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1881 	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1882 	/* Arcturus */
1883 	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1884 	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1885 	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1886 	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1887 	/* Navi10 */
1888 	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1889 	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1890 	{0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1891 	{0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1892 	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1893 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1894 	{0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1895 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1896 	/* Navi14 */
1897 	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1898 	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1899 	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1900 	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1901 
1902 	/* Renoir */
1903 	{0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1904 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1905 	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1906 	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1907 
1908 	/* Navi12 */
1909 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1910 	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1911 
1912 	/* Sienna_Cichlid */
1913 	{0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1914 	{0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1915 	{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1916 	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1917 	{0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1918 	{0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1919 	{0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1920 	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1921 	{0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1922 	{0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1923 	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1924 	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1925 	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1926 
1927 	/* Van Gogh */
1928 	{0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1929 
1930 	/* Yellow Carp */
1931 	{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1932 	{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1933 
1934 	/* Navy_Flounder */
1935 	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1936 	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1937 	{0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1938 	{0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1939 	{0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1940 	{0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1941 	{0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1942 	{0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1943 	{0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1944 
1945 	/* DIMGREY_CAVEFISH */
1946 	{0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1947 	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1948 	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1949 	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1950 	{0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1951 	{0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1952 	{0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1953 	{0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1954 	{0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1955 	{0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1956 	{0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1957 	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1958 
1959 	/* Aldebaran */
1960 	{0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1961 	{0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1962 	{0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1963 	{0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1964 
1965 	/* CYAN_SKILLFISH */
1966 	{0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1967 	{0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1968 
1969 	/* BEIGE_GOBY */
1970 	{0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1971 	{0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1972 	{0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1973 	{0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1974 	{0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1975 	{0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1976 
1977 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
1978 	  .class = PCI_CLASS_DISPLAY_VGA << 8,
1979 	  .class_mask = 0xffffff,
1980 	  .driver_data = CHIP_IP_DISCOVERY },
1981 
1982 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
1983 	  .class = PCI_CLASS_DISPLAY_OTHER << 8,
1984 	  .class_mask = 0xffffff,
1985 	  .driver_data = CHIP_IP_DISCOVERY },
1986 
1987 	{0, 0, 0}
1988 };
1989 
1990 MODULE_DEVICE_TABLE(pci, pciidlist);
1991 
1992 static const struct drm_driver amdgpu_kms_driver;
1993 
1994 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
1995 {
1996 	struct pci_dev *p = NULL;
1997 	int i;
1998 
1999 	/* 0 - GPU
2000 	 * 1 - audio
2001 	 * 2 - USB
2002 	 * 3 - UCSI
2003 	 */
2004 	for (i = 1; i < 4; i++) {
2005 		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2006 						adev->pdev->bus->number, i);
2007 		if (p) {
2008 			pm_runtime_get_sync(&p->dev);
2009 			pm_runtime_mark_last_busy(&p->dev);
2010 			pm_runtime_put_autosuspend(&p->dev);
2011 			pci_dev_put(p);
2012 		}
2013 	}
2014 }
2015 
2016 static int amdgpu_pci_probe(struct pci_dev *pdev,
2017 			    const struct pci_device_id *ent)
2018 {
2019 	struct drm_device *ddev;
2020 	struct amdgpu_device *adev;
2021 	unsigned long flags = ent->driver_data;
2022 	int ret, retry = 0, i;
2023 	bool supports_atomic = false;
2024 
2025 	/* skip devices which are owned by radeon */
2026 	for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2027 		if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2028 			return -ENODEV;
2029 	}
2030 
2031 	if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2032 		amdgpu_aspm = 0;
2033 
2034 	if (amdgpu_virtual_display ||
2035 	    amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2036 		supports_atomic = true;
2037 
2038 	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2039 		DRM_INFO("This hardware requires experimental hardware support.\n"
2040 			 "See modparam exp_hw_support\n");
2041 		return -ENODEV;
2042 	}
2043 
2044 	/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2045 	 * however, SME requires an indirect IOMMU mapping because the encryption
2046 	 * bit is beyond the DMA mask of the chip.
2047 	 */
2048 	if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2049 	    ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2050 		dev_info(&pdev->dev,
2051 			 "SME is not compatible with RAVEN\n");
2052 		return -ENOTSUPP;
2053 	}
2054 
2055 #ifdef CONFIG_DRM_AMDGPU_SI
2056 	if (!amdgpu_si_support) {
2057 		switch (flags & AMD_ASIC_MASK) {
2058 		case CHIP_TAHITI:
2059 		case CHIP_PITCAIRN:
2060 		case CHIP_VERDE:
2061 		case CHIP_OLAND:
2062 		case CHIP_HAINAN:
2063 			dev_info(&pdev->dev,
2064 				 "SI support provided by radeon.\n");
2065 			dev_info(&pdev->dev,
2066 				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2067 				);
2068 			return -ENODEV;
2069 		}
2070 	}
2071 #endif
2072 #ifdef CONFIG_DRM_AMDGPU_CIK
2073 	if (!amdgpu_cik_support) {
2074 		switch (flags & AMD_ASIC_MASK) {
2075 		case CHIP_KAVERI:
2076 		case CHIP_BONAIRE:
2077 		case CHIP_HAWAII:
2078 		case CHIP_KABINI:
2079 		case CHIP_MULLINS:
2080 			dev_info(&pdev->dev,
2081 				 "CIK support provided by radeon.\n");
2082 			dev_info(&pdev->dev,
2083 				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2084 				);
2085 			return -ENODEV;
2086 		}
2087 	}
2088 #endif
2089 
2090 	/* Get rid of things like offb */
2091 	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
2092 	if (ret)
2093 		return ret;
2094 
2095 	adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2096 	if (IS_ERR(adev))
2097 		return PTR_ERR(adev);
2098 
2099 	adev->dev  = &pdev->dev;
2100 	adev->pdev = pdev;
2101 	ddev = adev_to_drm(adev);
2102 
2103 	if (!supports_atomic)
2104 		ddev->driver_features &= ~DRIVER_ATOMIC;
2105 
2106 	ret = pci_enable_device(pdev);
2107 	if (ret)
2108 		return ret;
2109 
2110 	pci_set_drvdata(pdev, ddev);
2111 
2112 	ret = amdgpu_driver_load_kms(adev, ent->driver_data);
2113 	if (ret)
2114 		goto err_pci;
2115 
2116 retry_init:
2117 	ret = drm_dev_register(ddev, ent->driver_data);
2118 	if (ret == -EAGAIN && ++retry <= 3) {
2119 		DRM_INFO("retry init %d\n", retry);
2120 		/* Don't request EX mode too frequently which is attacking */
2121 		msleep(5000);
2122 		goto retry_init;
2123 	} else if (ret) {
2124 		goto err_pci;
2125 	}
2126 
2127 	/*
2128 	 * 1. don't init fbdev on hw without DCE
2129 	 * 2. don't init fbdev if there are no connectors
2130 	 */
2131 	if (adev->mode_info.mode_config_initialized &&
2132 	    !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2133 		/* select 8 bpp console on low vram cards */
2134 		if (adev->gmc.real_vram_size <= (32*1024*1024))
2135 			drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2136 		else
2137 			drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2138 	}
2139 
2140 	ret = amdgpu_debugfs_init(adev);
2141 	if (ret)
2142 		DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2143 
2144 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2145 		/* only need to skip on ATPX */
2146 		if (amdgpu_device_supports_px(ddev))
2147 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2148 		/* we want direct complete for BOCO */
2149 		if (amdgpu_device_supports_boco(ddev))
2150 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2151 						DPM_FLAG_SMART_SUSPEND |
2152 						DPM_FLAG_MAY_SKIP_RESUME);
2153 		pm_runtime_use_autosuspend(ddev->dev);
2154 		pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2155 
2156 		pm_runtime_allow(ddev->dev);
2157 
2158 		pm_runtime_mark_last_busy(ddev->dev);
2159 		pm_runtime_put_autosuspend(ddev->dev);
2160 
2161 		/*
2162 		 * For runpm implemented via BACO, PMFW will handle the
2163 		 * timing for BACO in and out:
2164 		 *   - put ASIC into BACO state only when both video and
2165 		 *     audio functions are in D3 state.
2166 		 *   - pull ASIC out of BACO state when either video or
2167 		 *     audio function is in D0 state.
2168 		 * Also, at startup, PMFW assumes both functions are in
2169 		 * D0 state.
2170 		 *
2171 		 * So if snd driver was loaded prior to amdgpu driver
2172 		 * and audio function was put into D3 state, there will
2173 		 * be no PMFW-aware D-state transition(D0->D3) on runpm
2174 		 * suspend. Thus the BACO will be not correctly kicked in.
2175 		 *
2176 		 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2177 		 * into D0 state. Then there will be a PMFW-aware D-state
2178 		 * transition(D0->D3) on runpm suspend.
2179 		 */
2180 		if (amdgpu_device_supports_baco(ddev) &&
2181 		    !(adev->flags & AMD_IS_APU) &&
2182 		    (adev->asic_type >= CHIP_NAVI10))
2183 			amdgpu_get_secondary_funcs(adev);
2184 	}
2185 
2186 	return 0;
2187 
2188 err_pci:
2189 	pci_disable_device(pdev);
2190 	return ret;
2191 }
2192 
2193 static void
2194 amdgpu_pci_remove(struct pci_dev *pdev)
2195 {
2196 	struct drm_device *dev = pci_get_drvdata(pdev);
2197 	struct amdgpu_device *adev = drm_to_adev(dev);
2198 
2199 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2200 		pm_runtime_get_sync(dev->dev);
2201 		pm_runtime_forbid(dev->dev);
2202 	}
2203 
2204 	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2205 	    !amdgpu_sriov_vf(adev)) {
2206 		bool need_to_reset_gpu = false;
2207 
2208 		if (adev->gmc.xgmi.num_physical_nodes > 1) {
2209 			struct amdgpu_hive_info *hive;
2210 
2211 			hive = amdgpu_get_xgmi_hive(adev);
2212 			if (hive->device_remove_count == 0)
2213 				need_to_reset_gpu = true;
2214 			hive->device_remove_count++;
2215 			amdgpu_put_xgmi_hive(hive);
2216 		} else {
2217 			need_to_reset_gpu = true;
2218 		}
2219 
2220 		/* Workaround for ASICs need to reset SMU.
2221 		 * Called only when the first device is removed.
2222 		 */
2223 		if (need_to_reset_gpu) {
2224 			struct amdgpu_reset_context reset_context;
2225 
2226 			adev->shutdown = true;
2227 			memset(&reset_context, 0, sizeof(reset_context));
2228 			reset_context.method = AMD_RESET_METHOD_NONE;
2229 			reset_context.reset_req_dev = adev;
2230 			set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2231 			set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2232 			amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2233 		}
2234 	}
2235 
2236 	amdgpu_driver_unload_kms(dev);
2237 
2238 	drm_dev_unplug(dev);
2239 
2240 	/*
2241 	 * Flush any in flight DMA operations from device.
2242 	 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2243 	 * StatusTransactions Pending bit.
2244 	 */
2245 	pci_disable_device(pdev);
2246 	pci_wait_for_pending_transaction(pdev);
2247 }
2248 
2249 static void
2250 amdgpu_pci_shutdown(struct pci_dev *pdev)
2251 {
2252 	struct drm_device *dev = pci_get_drvdata(pdev);
2253 	struct amdgpu_device *adev = drm_to_adev(dev);
2254 
2255 	if (amdgpu_ras_intr_triggered())
2256 		return;
2257 
2258 	/* if we are running in a VM, make sure the device
2259 	 * torn down properly on reboot/shutdown.
2260 	 * unfortunately we can't detect certain
2261 	 * hypervisors so just do this all the time.
2262 	 */
2263 	if (!amdgpu_passthrough(adev))
2264 		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2265 	amdgpu_device_ip_suspend(adev);
2266 	adev->mp1_state = PP_MP1_STATE_NONE;
2267 }
2268 
2269 /**
2270  * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2271  *
2272  * @work: work_struct.
2273  */
2274 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2275 {
2276 	struct list_head device_list;
2277 	struct amdgpu_device *adev;
2278 	int i, r;
2279 	struct amdgpu_reset_context reset_context;
2280 
2281 	memset(&reset_context, 0, sizeof(reset_context));
2282 
2283 	mutex_lock(&mgpu_info.mutex);
2284 	if (mgpu_info.pending_reset == true) {
2285 		mutex_unlock(&mgpu_info.mutex);
2286 		return;
2287 	}
2288 	mgpu_info.pending_reset = true;
2289 	mutex_unlock(&mgpu_info.mutex);
2290 
2291 	/* Use a common context, just need to make sure full reset is done */
2292 	reset_context.method = AMD_RESET_METHOD_NONE;
2293 	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2294 
2295 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2296 		adev = mgpu_info.gpu_ins[i].adev;
2297 		reset_context.reset_req_dev = adev;
2298 		r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2299 		if (r) {
2300 			dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2301 				r, adev_to_drm(adev)->unique);
2302 		}
2303 		if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2304 			r = -EALREADY;
2305 	}
2306 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2307 		adev = mgpu_info.gpu_ins[i].adev;
2308 		flush_work(&adev->xgmi_reset_work);
2309 		adev->gmc.xgmi.pending_reset = false;
2310 	}
2311 
2312 	/* reset function will rebuild the xgmi hive info , clear it now */
2313 	for (i = 0; i < mgpu_info.num_dgpu; i++)
2314 		amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2315 
2316 	INIT_LIST_HEAD(&device_list);
2317 
2318 	for (i = 0; i < mgpu_info.num_dgpu; i++)
2319 		list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2320 
2321 	/* unregister the GPU first, reset function will add them back */
2322 	list_for_each_entry(adev, &device_list, reset_list)
2323 		amdgpu_unregister_gpu_instance(adev);
2324 
2325 	/* Use a common context, just need to make sure full reset is done */
2326 	set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2327 	r = amdgpu_do_asic_reset(&device_list, &reset_context);
2328 
2329 	if (r) {
2330 		DRM_ERROR("reinit gpus failure");
2331 		return;
2332 	}
2333 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2334 		adev = mgpu_info.gpu_ins[i].adev;
2335 		if (!adev->kfd.init_complete)
2336 			amdgpu_amdkfd_device_init(adev);
2337 		amdgpu_ttm_set_buffer_funcs_status(adev, true);
2338 	}
2339 	return;
2340 }
2341 
2342 static int amdgpu_pmops_prepare(struct device *dev)
2343 {
2344 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2345 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2346 
2347 	/* Return a positive number here so
2348 	 * DPM_FLAG_SMART_SUSPEND works properly
2349 	 */
2350 	if (amdgpu_device_supports_boco(drm_dev))
2351 		return pm_runtime_suspended(dev);
2352 
2353 	/* if we will not support s3 or s2i for the device
2354 	 *  then skip suspend
2355 	 */
2356 	if (!amdgpu_acpi_is_s0ix_active(adev) &&
2357 	    !amdgpu_acpi_is_s3_active(adev))
2358 		return 1;
2359 
2360 	return 0;
2361 }
2362 
2363 static void amdgpu_pmops_complete(struct device *dev)
2364 {
2365 	/* nothing to do */
2366 }
2367 
2368 static int amdgpu_pmops_suspend(struct device *dev)
2369 {
2370 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2371 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2372 
2373 	if (amdgpu_acpi_is_s0ix_active(adev))
2374 		adev->in_s0ix = true;
2375 	else
2376 		adev->in_s3 = true;
2377 	return amdgpu_device_suspend(drm_dev, true);
2378 }
2379 
2380 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2381 {
2382 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2383 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2384 
2385 	if (amdgpu_acpi_should_gpu_reset(adev))
2386 		return amdgpu_asic_reset(adev);
2387 
2388 	return 0;
2389 }
2390 
2391 static int amdgpu_pmops_resume(struct device *dev)
2392 {
2393 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2394 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2395 	int r;
2396 
2397 	/* Avoids registers access if device is physically gone */
2398 	if (!pci_device_is_present(adev->pdev))
2399 		adev->no_hw_access = true;
2400 
2401 	r = amdgpu_device_resume(drm_dev, true);
2402 	if (amdgpu_acpi_is_s0ix_active(adev))
2403 		adev->in_s0ix = false;
2404 	else
2405 		adev->in_s3 = false;
2406 	return r;
2407 }
2408 
2409 static int amdgpu_pmops_freeze(struct device *dev)
2410 {
2411 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2412 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2413 	int r;
2414 
2415 	adev->in_s4 = true;
2416 	r = amdgpu_device_suspend(drm_dev, true);
2417 	adev->in_s4 = false;
2418 	if (r)
2419 		return r;
2420 	return amdgpu_asic_reset(adev);
2421 }
2422 
2423 static int amdgpu_pmops_thaw(struct device *dev)
2424 {
2425 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2426 
2427 	return amdgpu_device_resume(drm_dev, true);
2428 }
2429 
2430 static int amdgpu_pmops_poweroff(struct device *dev)
2431 {
2432 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2433 
2434 	return amdgpu_device_suspend(drm_dev, true);
2435 }
2436 
2437 static int amdgpu_pmops_restore(struct device *dev)
2438 {
2439 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2440 
2441 	return amdgpu_device_resume(drm_dev, true);
2442 }
2443 
2444 static int amdgpu_runtime_idle_check_display(struct device *dev)
2445 {
2446 	struct pci_dev *pdev = to_pci_dev(dev);
2447 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2448 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2449 
2450 	if (adev->mode_info.num_crtc) {
2451 		struct drm_connector *list_connector;
2452 		struct drm_connector_list_iter iter;
2453 		int ret = 0;
2454 
2455 		/* XXX: Return busy if any displays are connected to avoid
2456 		 * possible display wakeups after runtime resume due to
2457 		 * hotplug events in case any displays were connected while
2458 		 * the GPU was in suspend.  Remove this once that is fixed.
2459 		 */
2460 		mutex_lock(&drm_dev->mode_config.mutex);
2461 		drm_connector_list_iter_begin(drm_dev, &iter);
2462 		drm_for_each_connector_iter(list_connector, &iter) {
2463 			if (list_connector->status == connector_status_connected) {
2464 				ret = -EBUSY;
2465 				break;
2466 			}
2467 		}
2468 		drm_connector_list_iter_end(&iter);
2469 		mutex_unlock(&drm_dev->mode_config.mutex);
2470 
2471 		if (ret)
2472 			return ret;
2473 
2474 		if (amdgpu_device_has_dc_support(adev)) {
2475 			struct drm_crtc *crtc;
2476 
2477 			drm_for_each_crtc(crtc, drm_dev) {
2478 				drm_modeset_lock(&crtc->mutex, NULL);
2479 				if (crtc->state->active)
2480 					ret = -EBUSY;
2481 				drm_modeset_unlock(&crtc->mutex);
2482 				if (ret < 0)
2483 					break;
2484 			}
2485 		} else {
2486 			mutex_lock(&drm_dev->mode_config.mutex);
2487 			drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2488 
2489 			drm_connector_list_iter_begin(drm_dev, &iter);
2490 			drm_for_each_connector_iter(list_connector, &iter) {
2491 				if (list_connector->dpms ==  DRM_MODE_DPMS_ON) {
2492 					ret = -EBUSY;
2493 					break;
2494 				}
2495 			}
2496 
2497 			drm_connector_list_iter_end(&iter);
2498 
2499 			drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2500 			mutex_unlock(&drm_dev->mode_config.mutex);
2501 		}
2502 		if (ret)
2503 			return ret;
2504 	}
2505 
2506 	return 0;
2507 }
2508 
2509 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2510 {
2511 	struct pci_dev *pdev = to_pci_dev(dev);
2512 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2513 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2514 	int ret, i;
2515 
2516 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2517 		pm_runtime_forbid(dev);
2518 		return -EBUSY;
2519 	}
2520 
2521 	ret = amdgpu_runtime_idle_check_display(dev);
2522 	if (ret)
2523 		return ret;
2524 
2525 	/* wait for all rings to drain before suspending */
2526 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2527 		struct amdgpu_ring *ring = adev->rings[i];
2528 		if (ring && ring->sched.ready) {
2529 			ret = amdgpu_fence_wait_empty(ring);
2530 			if (ret)
2531 				return -EBUSY;
2532 		}
2533 	}
2534 
2535 	adev->in_runpm = true;
2536 	if (amdgpu_device_supports_px(drm_dev))
2537 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2538 
2539 	/*
2540 	 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2541 	 * proper cleanups and put itself into a state ready for PNP. That
2542 	 * can address some random resuming failure observed on BOCO capable
2543 	 * platforms.
2544 	 * TODO: this may be also needed for PX capable platform.
2545 	 */
2546 	if (amdgpu_device_supports_boco(drm_dev))
2547 		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2548 
2549 	ret = amdgpu_device_suspend(drm_dev, false);
2550 	if (ret) {
2551 		adev->in_runpm = false;
2552 		if (amdgpu_device_supports_boco(drm_dev))
2553 			adev->mp1_state = PP_MP1_STATE_NONE;
2554 		return ret;
2555 	}
2556 
2557 	if (amdgpu_device_supports_boco(drm_dev))
2558 		adev->mp1_state = PP_MP1_STATE_NONE;
2559 
2560 	if (amdgpu_device_supports_px(drm_dev)) {
2561 		/* Only need to handle PCI state in the driver for ATPX
2562 		 * PCI core handles it for _PR3.
2563 		 */
2564 		amdgpu_device_cache_pci_state(pdev);
2565 		pci_disable_device(pdev);
2566 		pci_ignore_hotplug(pdev);
2567 		pci_set_power_state(pdev, PCI_D3cold);
2568 		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2569 	} else if (amdgpu_device_supports_boco(drm_dev)) {
2570 		/* nothing to do */
2571 	} else if (amdgpu_device_supports_baco(drm_dev)) {
2572 		amdgpu_device_baco_enter(drm_dev);
2573 	}
2574 
2575 	return 0;
2576 }
2577 
2578 static int amdgpu_pmops_runtime_resume(struct device *dev)
2579 {
2580 	struct pci_dev *pdev = to_pci_dev(dev);
2581 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2582 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2583 	int ret;
2584 
2585 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2586 		return -EINVAL;
2587 
2588 	/* Avoids registers access if device is physically gone */
2589 	if (!pci_device_is_present(adev->pdev))
2590 		adev->no_hw_access = true;
2591 
2592 	if (amdgpu_device_supports_px(drm_dev)) {
2593 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2594 
2595 		/* Only need to handle PCI state in the driver for ATPX
2596 		 * PCI core handles it for _PR3.
2597 		 */
2598 		pci_set_power_state(pdev, PCI_D0);
2599 		amdgpu_device_load_pci_state(pdev);
2600 		ret = pci_enable_device(pdev);
2601 		if (ret)
2602 			return ret;
2603 		pci_set_master(pdev);
2604 	} else if (amdgpu_device_supports_boco(drm_dev)) {
2605 		/* Only need to handle PCI state in the driver for ATPX
2606 		 * PCI core handles it for _PR3.
2607 		 */
2608 		pci_set_master(pdev);
2609 	} else if (amdgpu_device_supports_baco(drm_dev)) {
2610 		amdgpu_device_baco_exit(drm_dev);
2611 	}
2612 	ret = amdgpu_device_resume(drm_dev, false);
2613 	if (ret) {
2614 		if (amdgpu_device_supports_px(drm_dev))
2615 			pci_disable_device(pdev);
2616 		return ret;
2617 	}
2618 
2619 	if (amdgpu_device_supports_px(drm_dev))
2620 		drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2621 	adev->in_runpm = false;
2622 	return 0;
2623 }
2624 
2625 static int amdgpu_pmops_runtime_idle(struct device *dev)
2626 {
2627 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2628 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2629 	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2630 	int ret = 1;
2631 
2632 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2633 		pm_runtime_forbid(dev);
2634 		return -EBUSY;
2635 	}
2636 
2637 	ret = amdgpu_runtime_idle_check_display(dev);
2638 
2639 	pm_runtime_mark_last_busy(dev);
2640 	pm_runtime_autosuspend(dev);
2641 	return ret;
2642 }
2643 
2644 long amdgpu_drm_ioctl(struct file *filp,
2645 		      unsigned int cmd, unsigned long arg)
2646 {
2647 	struct drm_file *file_priv = filp->private_data;
2648 	struct drm_device *dev;
2649 	long ret;
2650 	dev = file_priv->minor->dev;
2651 	ret = pm_runtime_get_sync(dev->dev);
2652 	if (ret < 0)
2653 		goto out;
2654 
2655 	ret = drm_ioctl(filp, cmd, arg);
2656 
2657 	pm_runtime_mark_last_busy(dev->dev);
2658 out:
2659 	pm_runtime_put_autosuspend(dev->dev);
2660 	return ret;
2661 }
2662 
2663 static const struct dev_pm_ops amdgpu_pm_ops = {
2664 	.prepare = amdgpu_pmops_prepare,
2665 	.complete = amdgpu_pmops_complete,
2666 	.suspend = amdgpu_pmops_suspend,
2667 	.suspend_noirq = amdgpu_pmops_suspend_noirq,
2668 	.resume = amdgpu_pmops_resume,
2669 	.freeze = amdgpu_pmops_freeze,
2670 	.thaw = amdgpu_pmops_thaw,
2671 	.poweroff = amdgpu_pmops_poweroff,
2672 	.restore = amdgpu_pmops_restore,
2673 	.runtime_suspend = amdgpu_pmops_runtime_suspend,
2674 	.runtime_resume = amdgpu_pmops_runtime_resume,
2675 	.runtime_idle = amdgpu_pmops_runtime_idle,
2676 };
2677 
2678 static int amdgpu_flush(struct file *f, fl_owner_t id)
2679 {
2680 	struct drm_file *file_priv = f->private_data;
2681 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2682 	long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2683 
2684 	timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2685 	timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2686 
2687 	return timeout >= 0 ? 0 : timeout;
2688 }
2689 
2690 static const struct file_operations amdgpu_driver_kms_fops = {
2691 	.owner = THIS_MODULE,
2692 	.open = drm_open,
2693 	.flush = amdgpu_flush,
2694 	.release = drm_release,
2695 	.unlocked_ioctl = amdgpu_drm_ioctl,
2696 	.mmap = drm_gem_mmap,
2697 	.poll = drm_poll,
2698 	.read = drm_read,
2699 #ifdef CONFIG_COMPAT
2700 	.compat_ioctl = amdgpu_kms_compat_ioctl,
2701 #endif
2702 #ifdef CONFIG_PROC_FS
2703 	.show_fdinfo = amdgpu_show_fdinfo
2704 #endif
2705 };
2706 
2707 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2708 {
2709 	struct drm_file *file;
2710 
2711 	if (!filp)
2712 		return -EINVAL;
2713 
2714 	if (filp->f_op != &amdgpu_driver_kms_fops) {
2715 		return -EINVAL;
2716 	}
2717 
2718 	file = filp->private_data;
2719 	*fpriv = file->driver_priv;
2720 	return 0;
2721 }
2722 
2723 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2724 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2725 	DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2726 	DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2727 	DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2728 	DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2729 	DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2730 	/* KMS */
2731 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2732 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2733 	DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2734 	DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2735 	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2736 	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2737 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2738 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2739 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2740 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2741 };
2742 
2743 static const struct drm_driver amdgpu_kms_driver = {
2744 	.driver_features =
2745 	    DRIVER_ATOMIC |
2746 	    DRIVER_GEM |
2747 	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2748 	    DRIVER_SYNCOBJ_TIMELINE,
2749 	.open = amdgpu_driver_open_kms,
2750 	.postclose = amdgpu_driver_postclose_kms,
2751 	.lastclose = amdgpu_driver_lastclose_kms,
2752 	.ioctls = amdgpu_ioctls_kms,
2753 	.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2754 	.dumb_create = amdgpu_mode_dumb_create,
2755 	.dumb_map_offset = amdgpu_mode_dumb_mmap,
2756 	.fops = &amdgpu_driver_kms_fops,
2757 	.release = &amdgpu_driver_release_kms,
2758 
2759 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2760 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2761 	.gem_prime_import = amdgpu_gem_prime_import,
2762 	.gem_prime_mmap = drm_gem_prime_mmap,
2763 
2764 	.name = DRIVER_NAME,
2765 	.desc = DRIVER_DESC,
2766 	.date = DRIVER_DATE,
2767 	.major = KMS_DRIVER_MAJOR,
2768 	.minor = KMS_DRIVER_MINOR,
2769 	.patchlevel = KMS_DRIVER_PATCHLEVEL,
2770 };
2771 
2772 static struct pci_error_handlers amdgpu_pci_err_handler = {
2773 	.error_detected	= amdgpu_pci_error_detected,
2774 	.mmio_enabled	= amdgpu_pci_mmio_enabled,
2775 	.slot_reset	= amdgpu_pci_slot_reset,
2776 	.resume		= amdgpu_pci_resume,
2777 };
2778 
2779 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2780 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2781 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2782 
2783 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2784 	&amdgpu_vram_mgr_attr_group,
2785 	&amdgpu_gtt_mgr_attr_group,
2786 	&amdgpu_vbios_version_attr_group,
2787 	NULL,
2788 };
2789 
2790 
2791 static struct pci_driver amdgpu_kms_pci_driver = {
2792 	.name = DRIVER_NAME,
2793 	.id_table = pciidlist,
2794 	.probe = amdgpu_pci_probe,
2795 	.remove = amdgpu_pci_remove,
2796 	.shutdown = amdgpu_pci_shutdown,
2797 	.driver.pm = &amdgpu_pm_ops,
2798 	.err_handler = &amdgpu_pci_err_handler,
2799 	.dev_groups = amdgpu_sysfs_groups,
2800 };
2801 
2802 static int __init amdgpu_init(void)
2803 {
2804 	int r;
2805 
2806 	if (drm_firmware_drivers_only())
2807 		return -EINVAL;
2808 
2809 	r = amdgpu_sync_init();
2810 	if (r)
2811 		goto error_sync;
2812 
2813 	r = amdgpu_fence_slab_init();
2814 	if (r)
2815 		goto error_fence;
2816 
2817 	DRM_INFO("amdgpu kernel modesetting enabled.\n");
2818 	amdgpu_register_atpx_handler();
2819 	amdgpu_acpi_detect();
2820 
2821 	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2822 	amdgpu_amdkfd_init();
2823 
2824 	/* let modprobe override vga console setting */
2825 	return pci_register_driver(&amdgpu_kms_pci_driver);
2826 
2827 error_fence:
2828 	amdgpu_sync_fini();
2829 
2830 error_sync:
2831 	return r;
2832 }
2833 
2834 static void __exit amdgpu_exit(void)
2835 {
2836 	amdgpu_amdkfd_fini();
2837 	pci_unregister_driver(&amdgpu_kms_pci_driver);
2838 	amdgpu_unregister_atpx_handler();
2839 	amdgpu_sync_fini();
2840 	amdgpu_fence_slab_fini();
2841 	mmu_notifier_synchronize();
2842 }
2843 
2844 module_init(amdgpu_init);
2845 module_exit(amdgpu_exit);
2846 
2847 MODULE_AUTHOR(DRIVER_AUTHOR);
2848 MODULE_DESCRIPTION(DRIVER_DESC);
2849 MODULE_LICENSE("GPL and additional rights");
2850