1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 * - 3.42.0 - Add 16bpc fixed point display support 99 * - 3.43.0 - Add device hot plug/unplug support 100 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 101 * - 3.45.0 - Add context ioctl stable pstate interface 102 */ 103 #define KMS_DRIVER_MAJOR 3 104 #define KMS_DRIVER_MINOR 45 105 #define KMS_DRIVER_PATCHLEVEL 0 106 107 int amdgpu_vram_limit; 108 int amdgpu_vis_vram_limit; 109 int amdgpu_gart_size = -1; /* auto */ 110 int amdgpu_gtt_size = -1; /* auto */ 111 int amdgpu_moverate = -1; /* auto */ 112 int amdgpu_benchmarking; 113 int amdgpu_testing; 114 int amdgpu_audio = -1; 115 int amdgpu_disp_priority; 116 int amdgpu_hw_i2c; 117 int amdgpu_pcie_gen2 = -1; 118 int amdgpu_msi = -1; 119 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 120 int amdgpu_dpm = -1; 121 int amdgpu_fw_load_type = -1; 122 int amdgpu_aspm = -1; 123 int amdgpu_runtime_pm = -1; 124 uint amdgpu_ip_block_mask = 0xffffffff; 125 int amdgpu_bapm = -1; 126 int amdgpu_deep_color; 127 int amdgpu_vm_size = -1; 128 int amdgpu_vm_fragment_size = -1; 129 int amdgpu_vm_block_size = -1; 130 int amdgpu_vm_fault_stop; 131 int amdgpu_vm_debug; 132 int amdgpu_vm_update_mode = -1; 133 int amdgpu_exp_hw_support; 134 int amdgpu_dc = -1; 135 int amdgpu_sched_jobs = 32; 136 int amdgpu_sched_hw_submission = 2; 137 uint amdgpu_pcie_gen_cap; 138 uint amdgpu_pcie_lane_cap; 139 uint amdgpu_cg_mask = 0xffffffff; 140 uint amdgpu_pg_mask = 0xffffffff; 141 uint amdgpu_sdma_phase_quantum = 32; 142 char *amdgpu_disable_cu = NULL; 143 char *amdgpu_virtual_display = NULL; 144 145 /* 146 * OverDrive(bit 14) disabled by default 147 * GFX DCS(bit 19) disabled by default 148 */ 149 uint amdgpu_pp_feature_mask = 0xfff7bfff; 150 uint amdgpu_force_long_training; 151 int amdgpu_job_hang_limit; 152 int amdgpu_lbpw = -1; 153 int amdgpu_compute_multipipe = -1; 154 int amdgpu_gpu_recovery = -1; /* auto */ 155 int amdgpu_emu_mode; 156 uint amdgpu_smu_memory_pool_size; 157 int amdgpu_smu_pptable_id = -1; 158 /* 159 * FBC (bit 0) disabled by default 160 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 161 * - With this, for multiple monitors in sync(e.g. with the same model), 162 * mclk switching will be allowed. And the mclk will be not foced to the 163 * highest. That helps saving some idle power. 164 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 165 * PSR (bit 3) disabled by default 166 * EDP NO POWER SEQUENCING (bit 4) disabled by default 167 */ 168 uint amdgpu_dc_feature_mask = 2; 169 uint amdgpu_dc_debug_mask; 170 int amdgpu_async_gfx_ring = 1; 171 int amdgpu_mcbp; 172 int amdgpu_discovery = -1; 173 int amdgpu_mes; 174 int amdgpu_noretry = -1; 175 int amdgpu_force_asic_type = -1; 176 int amdgpu_tmz = -1; /* auto */ 177 int amdgpu_reset_method = -1; /* auto */ 178 int amdgpu_num_kcq = -1; 179 int amdgpu_smartshift_bias; 180 181 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 182 183 struct amdgpu_mgpu_info mgpu_info = { 184 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 185 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 186 mgpu_info.delayed_reset_work, 187 amdgpu_drv_delayed_reset_work_handler, 0), 188 }; 189 int amdgpu_ras_enable = -1; 190 uint amdgpu_ras_mask = 0xffffffff; 191 int amdgpu_bad_page_threshold = -1; 192 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 193 .timeout_fatal_disable = false, 194 .period = 0x0, /* default to 0x0 (timeout disable) */ 195 }; 196 197 /** 198 * DOC: vramlimit (int) 199 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 200 */ 201 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 202 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 203 204 /** 205 * DOC: vis_vramlimit (int) 206 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 207 */ 208 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 209 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 210 211 /** 212 * DOC: gartsize (uint) 213 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 214 */ 215 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 216 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 217 218 /** 219 * DOC: gttsize (int) 220 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 221 * otherwise 3/4 RAM size). 222 */ 223 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 224 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 225 226 /** 227 * DOC: moverate (int) 228 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 229 */ 230 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 231 module_param_named(moverate, amdgpu_moverate, int, 0600); 232 233 /** 234 * DOC: benchmark (int) 235 * Run benchmarks. The default is 0 (Skip benchmarks). 236 */ 237 MODULE_PARM_DESC(benchmark, "Run benchmark"); 238 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 239 240 /** 241 * DOC: test (int) 242 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 243 */ 244 MODULE_PARM_DESC(test, "Run tests"); 245 module_param_named(test, amdgpu_testing, int, 0444); 246 247 /** 248 * DOC: audio (int) 249 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 250 */ 251 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 252 module_param_named(audio, amdgpu_audio, int, 0444); 253 254 /** 255 * DOC: disp_priority (int) 256 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 257 */ 258 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 259 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 260 261 /** 262 * DOC: hw_i2c (int) 263 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 264 */ 265 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 266 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 267 268 /** 269 * DOC: pcie_gen2 (int) 270 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 271 */ 272 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 273 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 274 275 /** 276 * DOC: msi (int) 277 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 278 */ 279 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 280 module_param_named(msi, amdgpu_msi, int, 0444); 281 282 /** 283 * DOC: lockup_timeout (string) 284 * Set GPU scheduler timeout value in ms. 285 * 286 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 287 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 288 * to the default timeout. 289 * 290 * - With one value specified, the setting will apply to all non-compute jobs. 291 * - With multiple values specified, the first one will be for GFX. 292 * The second one is for Compute. The third and fourth ones are 293 * for SDMA and Video. 294 * 295 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 296 * jobs is 10000. The timeout for compute is 60000. 297 */ 298 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 299 "for passthrough or sriov, 10000 for all jobs." 300 " 0: keep default value. negative: infinity timeout), " 301 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 302 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 303 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 304 305 /** 306 * DOC: dpm (int) 307 * Override for dynamic power management setting 308 * (0 = disable, 1 = enable) 309 * The default is -1 (auto). 310 */ 311 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 312 module_param_named(dpm, amdgpu_dpm, int, 0444); 313 314 /** 315 * DOC: fw_load_type (int) 316 * Set different firmware loading type for debugging, if supported. 317 * Set to 0 to force direct loading if supported by the ASIC. Set 318 * to -1 to select the default loading mode for the ASIC, as defined 319 * by the driver. The default is -1 (auto). 320 */ 321 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)"); 322 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 323 324 /** 325 * DOC: aspm (int) 326 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 327 */ 328 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 329 module_param_named(aspm, amdgpu_aspm, int, 0444); 330 331 /** 332 * DOC: runpm (int) 333 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 334 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 335 * Setting the value to 0 disables this functionality. 336 */ 337 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 338 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 339 340 /** 341 * DOC: ip_block_mask (uint) 342 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 343 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 344 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 345 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 346 */ 347 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 348 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 349 350 /** 351 * DOC: bapm (int) 352 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 353 * The default -1 (auto, enabled) 354 */ 355 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 356 module_param_named(bapm, amdgpu_bapm, int, 0444); 357 358 /** 359 * DOC: deep_color (int) 360 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 361 */ 362 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 363 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 364 365 /** 366 * DOC: vm_size (int) 367 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 368 */ 369 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 370 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 371 372 /** 373 * DOC: vm_fragment_size (int) 374 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 375 */ 376 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 377 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 378 379 /** 380 * DOC: vm_block_size (int) 381 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 382 */ 383 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 384 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 385 386 /** 387 * DOC: vm_fault_stop (int) 388 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 389 */ 390 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 391 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 392 393 /** 394 * DOC: vm_debug (int) 395 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 396 */ 397 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 398 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 399 400 /** 401 * DOC: vm_update_mode (int) 402 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 403 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 404 */ 405 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 406 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 407 408 /** 409 * DOC: exp_hw_support (int) 410 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 411 */ 412 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 413 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 414 415 /** 416 * DOC: dc (int) 417 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 418 */ 419 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 420 module_param_named(dc, amdgpu_dc, int, 0444); 421 422 /** 423 * DOC: sched_jobs (int) 424 * Override the max number of jobs supported in the sw queue. The default is 32. 425 */ 426 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 427 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 428 429 /** 430 * DOC: sched_hw_submission (int) 431 * Override the max number of HW submissions. The default is 2. 432 */ 433 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 434 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 435 436 /** 437 * DOC: ppfeaturemask (hexint) 438 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 439 * The default is the current set of stable power features. 440 */ 441 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 442 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 443 444 /** 445 * DOC: forcelongtraining (uint) 446 * Force long memory training in resume. 447 * The default is zero, indicates short training in resume. 448 */ 449 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 450 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 451 452 /** 453 * DOC: pcie_gen_cap (uint) 454 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 455 * The default is 0 (automatic for each asic). 456 */ 457 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 458 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 459 460 /** 461 * DOC: pcie_lane_cap (uint) 462 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 463 * The default is 0 (automatic for each asic). 464 */ 465 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 466 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 467 468 /** 469 * DOC: cg_mask (uint) 470 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 471 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 472 */ 473 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 474 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 475 476 /** 477 * DOC: pg_mask (uint) 478 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 479 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 480 */ 481 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 482 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 483 484 /** 485 * DOC: sdma_phase_quantum (uint) 486 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 487 */ 488 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 489 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 490 491 /** 492 * DOC: disable_cu (charp) 493 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 494 */ 495 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 496 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 497 498 /** 499 * DOC: virtual_display (charp) 500 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 501 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 502 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 503 * device at 26:00.0. The default is NULL. 504 */ 505 MODULE_PARM_DESC(virtual_display, 506 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 507 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 508 509 /** 510 * DOC: job_hang_limit (int) 511 * Set how much time allow a job hang and not drop it. The default is 0. 512 */ 513 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 514 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 515 516 /** 517 * DOC: lbpw (int) 518 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 519 */ 520 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 521 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 522 523 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 524 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 525 526 /** 527 * DOC: gpu_recovery (int) 528 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 529 */ 530 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 532 533 /** 534 * DOC: emu_mode (int) 535 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 536 */ 537 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 538 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 539 540 /** 541 * DOC: ras_enable (int) 542 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 543 */ 544 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 545 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 546 547 /** 548 * DOC: ras_mask (uint) 549 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 550 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 551 */ 552 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 553 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 554 555 /** 556 * DOC: timeout_fatal_disable (bool) 557 * Disable Watchdog timeout fatal error event 558 */ 559 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 560 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 561 562 /** 563 * DOC: timeout_period (uint) 564 * Modify the watchdog timeout max_cycles as (1 << period) 565 */ 566 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 567 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 568 569 /** 570 * DOC: si_support (int) 571 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 572 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 573 * otherwise using amdgpu driver. 574 */ 575 #ifdef CONFIG_DRM_AMDGPU_SI 576 577 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 578 int amdgpu_si_support = 0; 579 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 580 #else 581 int amdgpu_si_support = 1; 582 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 583 #endif 584 585 module_param_named(si_support, amdgpu_si_support, int, 0444); 586 #endif 587 588 /** 589 * DOC: cik_support (int) 590 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 591 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 592 * otherwise using amdgpu driver. 593 */ 594 #ifdef CONFIG_DRM_AMDGPU_CIK 595 596 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 597 int amdgpu_cik_support = 0; 598 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 599 #else 600 int amdgpu_cik_support = 1; 601 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 602 #endif 603 604 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 605 #endif 606 607 /** 608 * DOC: smu_memory_pool_size (uint) 609 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 610 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 611 */ 612 MODULE_PARM_DESC(smu_memory_pool_size, 613 "reserve gtt for smu debug usage, 0 = disable," 614 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 615 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 616 617 /** 618 * DOC: async_gfx_ring (int) 619 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 620 */ 621 MODULE_PARM_DESC(async_gfx_ring, 622 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 623 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 624 625 /** 626 * DOC: mcbp (int) 627 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 628 */ 629 MODULE_PARM_DESC(mcbp, 630 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 631 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 632 633 /** 634 * DOC: discovery (int) 635 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 636 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 637 */ 638 MODULE_PARM_DESC(discovery, 639 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 640 module_param_named(discovery, amdgpu_discovery, int, 0444); 641 642 /** 643 * DOC: mes (int) 644 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 645 * (0 = disabled (default), 1 = enabled) 646 */ 647 MODULE_PARM_DESC(mes, 648 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 649 module_param_named(mes, amdgpu_mes, int, 0444); 650 651 /** 652 * DOC: noretry (int) 653 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 654 * do not support per-process XNACK this also disables retry page faults. 655 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 656 */ 657 MODULE_PARM_DESC(noretry, 658 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 659 module_param_named(noretry, amdgpu_noretry, int, 0644); 660 661 /** 662 * DOC: force_asic_type (int) 663 * A non negative value used to specify the asic type for all supported GPUs. 664 */ 665 MODULE_PARM_DESC(force_asic_type, 666 "A non negative value used to specify the asic type for all supported GPUs"); 667 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 668 669 670 671 #ifdef CONFIG_HSA_AMD 672 /** 673 * DOC: sched_policy (int) 674 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 675 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 676 * assigns queues to HQDs. 677 */ 678 int sched_policy = KFD_SCHED_POLICY_HWS; 679 module_param(sched_policy, int, 0444); 680 MODULE_PARM_DESC(sched_policy, 681 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 682 683 /** 684 * DOC: hws_max_conc_proc (int) 685 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 686 * number of VMIDs assigned to the HWS, which is also the default. 687 */ 688 int hws_max_conc_proc = 8; 689 module_param(hws_max_conc_proc, int, 0444); 690 MODULE_PARM_DESC(hws_max_conc_proc, 691 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 692 693 /** 694 * DOC: cwsr_enable (int) 695 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 696 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 697 * disables it. 698 */ 699 int cwsr_enable = 1; 700 module_param(cwsr_enable, int, 0444); 701 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 702 703 /** 704 * DOC: max_num_of_queues_per_device (int) 705 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 706 * is 4096. 707 */ 708 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 709 module_param(max_num_of_queues_per_device, int, 0444); 710 MODULE_PARM_DESC(max_num_of_queues_per_device, 711 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 712 713 /** 714 * DOC: send_sigterm (int) 715 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 716 * but just print errors on dmesg. Setting 1 enables sending sigterm. 717 */ 718 int send_sigterm; 719 module_param(send_sigterm, int, 0444); 720 MODULE_PARM_DESC(send_sigterm, 721 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 722 723 /** 724 * DOC: debug_largebar (int) 725 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 726 * system. This limits the VRAM size reported to ROCm applications to the visible 727 * size, usually 256MB. 728 * Default value is 0, diabled. 729 */ 730 int debug_largebar; 731 module_param(debug_largebar, int, 0444); 732 MODULE_PARM_DESC(debug_largebar, 733 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 734 735 /** 736 * DOC: ignore_crat (int) 737 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 738 * table to get information about AMD APUs. This option can serve as a workaround on 739 * systems with a broken CRAT table. 740 * 741 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 742 * whehter use CRAT) 743 */ 744 int ignore_crat; 745 module_param(ignore_crat, int, 0444); 746 MODULE_PARM_DESC(ignore_crat, 747 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 748 749 /** 750 * DOC: halt_if_hws_hang (int) 751 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 752 * Setting 1 enables halt on hang. 753 */ 754 int halt_if_hws_hang; 755 module_param(halt_if_hws_hang, int, 0644); 756 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 757 758 /** 759 * DOC: hws_gws_support(bool) 760 * Assume that HWS supports GWS barriers regardless of what firmware version 761 * check says. Default value: false (rely on MEC2 firmware version check). 762 */ 763 bool hws_gws_support; 764 module_param(hws_gws_support, bool, 0444); 765 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 766 767 /** 768 * DOC: queue_preemption_timeout_ms (int) 769 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 770 */ 771 int queue_preemption_timeout_ms = 9000; 772 module_param(queue_preemption_timeout_ms, int, 0644); 773 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 774 775 /** 776 * DOC: debug_evictions(bool) 777 * Enable extra debug messages to help determine the cause of evictions 778 */ 779 bool debug_evictions; 780 module_param(debug_evictions, bool, 0644); 781 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 782 783 /** 784 * DOC: no_system_mem_limit(bool) 785 * Disable system memory limit, to support multiple process shared memory 786 */ 787 bool no_system_mem_limit; 788 module_param(no_system_mem_limit, bool, 0644); 789 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 790 791 /** 792 * DOC: no_queue_eviction_on_vm_fault (int) 793 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 794 */ 795 int amdgpu_no_queue_eviction_on_vm_fault = 0; 796 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 797 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 798 #endif 799 800 /** 801 * DOC: dcfeaturemask (uint) 802 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 803 * The default is the current set of stable display features. 804 */ 805 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 806 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 807 808 /** 809 * DOC: dcdebugmask (uint) 810 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 811 */ 812 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 813 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 814 815 /** 816 * DOC: abmlevel (uint) 817 * Override the default ABM (Adaptive Backlight Management) level used for DC 818 * enabled hardware. Requires DMCU to be supported and loaded. 819 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 820 * default. Values 1-4 control the maximum allowable brightness reduction via 821 * the ABM algorithm, with 1 being the least reduction and 4 being the most 822 * reduction. 823 * 824 * Defaults to 0, or disabled. Userspace can still override this level later 825 * after boot. 826 */ 827 uint amdgpu_dm_abm_level; 828 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 829 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 830 831 int amdgpu_backlight = -1; 832 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 833 module_param_named(backlight, amdgpu_backlight, bint, 0444); 834 835 /** 836 * DOC: tmz (int) 837 * Trusted Memory Zone (TMZ) is a method to protect data being written 838 * to or read from memory. 839 * 840 * The default value: 0 (off). TODO: change to auto till it is completed. 841 */ 842 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 843 module_param_named(tmz, amdgpu_tmz, int, 0444); 844 845 /** 846 * DOC: reset_method (int) 847 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 848 */ 849 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 850 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 851 852 /** 853 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 854 * threshold value of faulty pages detected by RAS ECC, which may 855 * result in the GPU entering bad status when the number of total 856 * faulty pages by ECC exceeds the threshold value. 857 */ 858 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 859 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 860 861 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 862 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 863 864 /** 865 * DOC: smu_pptable_id (int) 866 * Used to override pptable id. id = 0 use VBIOS pptable. 867 * id > 0 use the soft pptable with specicfied id. 868 */ 869 MODULE_PARM_DESC(smu_pptable_id, 870 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 871 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 872 873 /* These devices are not supported by amdgpu. 874 * They are supported by the mach64, r128, radeon drivers 875 */ 876 static const u16 amdgpu_unsupported_pciidlist[] = { 877 /* mach64 */ 878 0x4354, 879 0x4358, 880 0x4554, 881 0x4742, 882 0x4744, 883 0x4749, 884 0x474C, 885 0x474D, 886 0x474E, 887 0x474F, 888 0x4750, 889 0x4751, 890 0x4752, 891 0x4753, 892 0x4754, 893 0x4755, 894 0x4756, 895 0x4757, 896 0x4758, 897 0x4759, 898 0x475A, 899 0x4C42, 900 0x4C44, 901 0x4C47, 902 0x4C49, 903 0x4C4D, 904 0x4C4E, 905 0x4C50, 906 0x4C51, 907 0x4C52, 908 0x4C53, 909 0x5654, 910 0x5655, 911 0x5656, 912 /* r128 */ 913 0x4c45, 914 0x4c46, 915 0x4d46, 916 0x4d4c, 917 0x5041, 918 0x5042, 919 0x5043, 920 0x5044, 921 0x5045, 922 0x5046, 923 0x5047, 924 0x5048, 925 0x5049, 926 0x504A, 927 0x504B, 928 0x504C, 929 0x504D, 930 0x504E, 931 0x504F, 932 0x5050, 933 0x5051, 934 0x5052, 935 0x5053, 936 0x5054, 937 0x5055, 938 0x5056, 939 0x5057, 940 0x5058, 941 0x5245, 942 0x5246, 943 0x5247, 944 0x524b, 945 0x524c, 946 0x534d, 947 0x5446, 948 0x544C, 949 0x5452, 950 /* radeon */ 951 0x3150, 952 0x3151, 953 0x3152, 954 0x3154, 955 0x3155, 956 0x3E50, 957 0x3E54, 958 0x4136, 959 0x4137, 960 0x4144, 961 0x4145, 962 0x4146, 963 0x4147, 964 0x4148, 965 0x4149, 966 0x414A, 967 0x414B, 968 0x4150, 969 0x4151, 970 0x4152, 971 0x4153, 972 0x4154, 973 0x4155, 974 0x4156, 975 0x4237, 976 0x4242, 977 0x4336, 978 0x4337, 979 0x4437, 980 0x4966, 981 0x4967, 982 0x4A48, 983 0x4A49, 984 0x4A4A, 985 0x4A4B, 986 0x4A4C, 987 0x4A4D, 988 0x4A4E, 989 0x4A4F, 990 0x4A50, 991 0x4A54, 992 0x4B48, 993 0x4B49, 994 0x4B4A, 995 0x4B4B, 996 0x4B4C, 997 0x4C57, 998 0x4C58, 999 0x4C59, 1000 0x4C5A, 1001 0x4C64, 1002 0x4C66, 1003 0x4C67, 1004 0x4E44, 1005 0x4E45, 1006 0x4E46, 1007 0x4E47, 1008 0x4E48, 1009 0x4E49, 1010 0x4E4A, 1011 0x4E4B, 1012 0x4E50, 1013 0x4E51, 1014 0x4E52, 1015 0x4E53, 1016 0x4E54, 1017 0x4E56, 1018 0x5144, 1019 0x5145, 1020 0x5146, 1021 0x5147, 1022 0x5148, 1023 0x514C, 1024 0x514D, 1025 0x5157, 1026 0x5158, 1027 0x5159, 1028 0x515A, 1029 0x515E, 1030 0x5460, 1031 0x5462, 1032 0x5464, 1033 0x5548, 1034 0x5549, 1035 0x554A, 1036 0x554B, 1037 0x554C, 1038 0x554D, 1039 0x554E, 1040 0x554F, 1041 0x5550, 1042 0x5551, 1043 0x5552, 1044 0x5554, 1045 0x564A, 1046 0x564B, 1047 0x564F, 1048 0x5652, 1049 0x5653, 1050 0x5657, 1051 0x5834, 1052 0x5835, 1053 0x5954, 1054 0x5955, 1055 0x5974, 1056 0x5975, 1057 0x5960, 1058 0x5961, 1059 0x5962, 1060 0x5964, 1061 0x5965, 1062 0x5969, 1063 0x5a41, 1064 0x5a42, 1065 0x5a61, 1066 0x5a62, 1067 0x5b60, 1068 0x5b62, 1069 0x5b63, 1070 0x5b64, 1071 0x5b65, 1072 0x5c61, 1073 0x5c63, 1074 0x5d48, 1075 0x5d49, 1076 0x5d4a, 1077 0x5d4c, 1078 0x5d4d, 1079 0x5d4e, 1080 0x5d4f, 1081 0x5d50, 1082 0x5d52, 1083 0x5d57, 1084 0x5e48, 1085 0x5e4a, 1086 0x5e4b, 1087 0x5e4c, 1088 0x5e4d, 1089 0x5e4f, 1090 0x6700, 1091 0x6701, 1092 0x6702, 1093 0x6703, 1094 0x6704, 1095 0x6705, 1096 0x6706, 1097 0x6707, 1098 0x6708, 1099 0x6709, 1100 0x6718, 1101 0x6719, 1102 0x671c, 1103 0x671d, 1104 0x671f, 1105 0x6720, 1106 0x6721, 1107 0x6722, 1108 0x6723, 1109 0x6724, 1110 0x6725, 1111 0x6726, 1112 0x6727, 1113 0x6728, 1114 0x6729, 1115 0x6738, 1116 0x6739, 1117 0x673e, 1118 0x6740, 1119 0x6741, 1120 0x6742, 1121 0x6743, 1122 0x6744, 1123 0x6745, 1124 0x6746, 1125 0x6747, 1126 0x6748, 1127 0x6749, 1128 0x674A, 1129 0x6750, 1130 0x6751, 1131 0x6758, 1132 0x6759, 1133 0x675B, 1134 0x675D, 1135 0x675F, 1136 0x6760, 1137 0x6761, 1138 0x6762, 1139 0x6763, 1140 0x6764, 1141 0x6765, 1142 0x6766, 1143 0x6767, 1144 0x6768, 1145 0x6770, 1146 0x6771, 1147 0x6772, 1148 0x6778, 1149 0x6779, 1150 0x677B, 1151 0x6840, 1152 0x6841, 1153 0x6842, 1154 0x6843, 1155 0x6849, 1156 0x684C, 1157 0x6850, 1158 0x6858, 1159 0x6859, 1160 0x6880, 1161 0x6888, 1162 0x6889, 1163 0x688A, 1164 0x688C, 1165 0x688D, 1166 0x6898, 1167 0x6899, 1168 0x689b, 1169 0x689c, 1170 0x689d, 1171 0x689e, 1172 0x68a0, 1173 0x68a1, 1174 0x68a8, 1175 0x68a9, 1176 0x68b0, 1177 0x68b8, 1178 0x68b9, 1179 0x68ba, 1180 0x68be, 1181 0x68bf, 1182 0x68c0, 1183 0x68c1, 1184 0x68c7, 1185 0x68c8, 1186 0x68c9, 1187 0x68d8, 1188 0x68d9, 1189 0x68da, 1190 0x68de, 1191 0x68e0, 1192 0x68e1, 1193 0x68e4, 1194 0x68e5, 1195 0x68e8, 1196 0x68e9, 1197 0x68f1, 1198 0x68f2, 1199 0x68f8, 1200 0x68f9, 1201 0x68fa, 1202 0x68fe, 1203 0x7100, 1204 0x7101, 1205 0x7102, 1206 0x7103, 1207 0x7104, 1208 0x7105, 1209 0x7106, 1210 0x7108, 1211 0x7109, 1212 0x710A, 1213 0x710B, 1214 0x710C, 1215 0x710E, 1216 0x710F, 1217 0x7140, 1218 0x7141, 1219 0x7142, 1220 0x7143, 1221 0x7144, 1222 0x7145, 1223 0x7146, 1224 0x7147, 1225 0x7149, 1226 0x714A, 1227 0x714B, 1228 0x714C, 1229 0x714D, 1230 0x714E, 1231 0x714F, 1232 0x7151, 1233 0x7152, 1234 0x7153, 1235 0x715E, 1236 0x715F, 1237 0x7180, 1238 0x7181, 1239 0x7183, 1240 0x7186, 1241 0x7187, 1242 0x7188, 1243 0x718A, 1244 0x718B, 1245 0x718C, 1246 0x718D, 1247 0x718F, 1248 0x7193, 1249 0x7196, 1250 0x719B, 1251 0x719F, 1252 0x71C0, 1253 0x71C1, 1254 0x71C2, 1255 0x71C3, 1256 0x71C4, 1257 0x71C5, 1258 0x71C6, 1259 0x71C7, 1260 0x71CD, 1261 0x71CE, 1262 0x71D2, 1263 0x71D4, 1264 0x71D5, 1265 0x71D6, 1266 0x71DA, 1267 0x71DE, 1268 0x7200, 1269 0x7210, 1270 0x7211, 1271 0x7240, 1272 0x7243, 1273 0x7244, 1274 0x7245, 1275 0x7246, 1276 0x7247, 1277 0x7248, 1278 0x7249, 1279 0x724A, 1280 0x724B, 1281 0x724C, 1282 0x724D, 1283 0x724E, 1284 0x724F, 1285 0x7280, 1286 0x7281, 1287 0x7283, 1288 0x7284, 1289 0x7287, 1290 0x7288, 1291 0x7289, 1292 0x728B, 1293 0x728C, 1294 0x7290, 1295 0x7291, 1296 0x7293, 1297 0x7297, 1298 0x7834, 1299 0x7835, 1300 0x791e, 1301 0x791f, 1302 0x793f, 1303 0x7941, 1304 0x7942, 1305 0x796c, 1306 0x796d, 1307 0x796e, 1308 0x796f, 1309 0x9400, 1310 0x9401, 1311 0x9402, 1312 0x9403, 1313 0x9405, 1314 0x940A, 1315 0x940B, 1316 0x940F, 1317 0x94A0, 1318 0x94A1, 1319 0x94A3, 1320 0x94B1, 1321 0x94B3, 1322 0x94B4, 1323 0x94B5, 1324 0x94B9, 1325 0x9440, 1326 0x9441, 1327 0x9442, 1328 0x9443, 1329 0x9444, 1330 0x9446, 1331 0x944A, 1332 0x944B, 1333 0x944C, 1334 0x944E, 1335 0x9450, 1336 0x9452, 1337 0x9456, 1338 0x945A, 1339 0x945B, 1340 0x945E, 1341 0x9460, 1342 0x9462, 1343 0x946A, 1344 0x946B, 1345 0x947A, 1346 0x947B, 1347 0x9480, 1348 0x9487, 1349 0x9488, 1350 0x9489, 1351 0x948A, 1352 0x948F, 1353 0x9490, 1354 0x9491, 1355 0x9495, 1356 0x9498, 1357 0x949C, 1358 0x949E, 1359 0x949F, 1360 0x94C0, 1361 0x94C1, 1362 0x94C3, 1363 0x94C4, 1364 0x94C5, 1365 0x94C6, 1366 0x94C7, 1367 0x94C8, 1368 0x94C9, 1369 0x94CB, 1370 0x94CC, 1371 0x94CD, 1372 0x9500, 1373 0x9501, 1374 0x9504, 1375 0x9505, 1376 0x9506, 1377 0x9507, 1378 0x9508, 1379 0x9509, 1380 0x950F, 1381 0x9511, 1382 0x9515, 1383 0x9517, 1384 0x9519, 1385 0x9540, 1386 0x9541, 1387 0x9542, 1388 0x954E, 1389 0x954F, 1390 0x9552, 1391 0x9553, 1392 0x9555, 1393 0x9557, 1394 0x955f, 1395 0x9580, 1396 0x9581, 1397 0x9583, 1398 0x9586, 1399 0x9587, 1400 0x9588, 1401 0x9589, 1402 0x958A, 1403 0x958B, 1404 0x958C, 1405 0x958D, 1406 0x958E, 1407 0x958F, 1408 0x9590, 1409 0x9591, 1410 0x9593, 1411 0x9595, 1412 0x9596, 1413 0x9597, 1414 0x9598, 1415 0x9599, 1416 0x959B, 1417 0x95C0, 1418 0x95C2, 1419 0x95C4, 1420 0x95C5, 1421 0x95C6, 1422 0x95C7, 1423 0x95C9, 1424 0x95CC, 1425 0x95CD, 1426 0x95CE, 1427 0x95CF, 1428 0x9610, 1429 0x9611, 1430 0x9612, 1431 0x9613, 1432 0x9614, 1433 0x9615, 1434 0x9616, 1435 0x9640, 1436 0x9641, 1437 0x9642, 1438 0x9643, 1439 0x9644, 1440 0x9645, 1441 0x9647, 1442 0x9648, 1443 0x9649, 1444 0x964a, 1445 0x964b, 1446 0x964c, 1447 0x964e, 1448 0x964f, 1449 0x9710, 1450 0x9711, 1451 0x9712, 1452 0x9713, 1453 0x9714, 1454 0x9715, 1455 0x9802, 1456 0x9803, 1457 0x9804, 1458 0x9805, 1459 0x9806, 1460 0x9807, 1461 0x9808, 1462 0x9809, 1463 0x980A, 1464 0x9900, 1465 0x9901, 1466 0x9903, 1467 0x9904, 1468 0x9905, 1469 0x9906, 1470 0x9907, 1471 0x9908, 1472 0x9909, 1473 0x990A, 1474 0x990B, 1475 0x990C, 1476 0x990D, 1477 0x990E, 1478 0x990F, 1479 0x9910, 1480 0x9913, 1481 0x9917, 1482 0x9918, 1483 0x9919, 1484 0x9990, 1485 0x9991, 1486 0x9992, 1487 0x9993, 1488 0x9994, 1489 0x9995, 1490 0x9996, 1491 0x9997, 1492 0x9998, 1493 0x9999, 1494 0x999A, 1495 0x999B, 1496 0x999C, 1497 0x999D, 1498 0x99A0, 1499 0x99A2, 1500 0x99A4, 1501 /* radeon secondary ids */ 1502 0x3171, 1503 0x3e70, 1504 0x4164, 1505 0x4165, 1506 0x4166, 1507 0x4168, 1508 0x4170, 1509 0x4171, 1510 0x4172, 1511 0x4173, 1512 0x496e, 1513 0x4a69, 1514 0x4a6a, 1515 0x4a6b, 1516 0x4a70, 1517 0x4a74, 1518 0x4b69, 1519 0x4b6b, 1520 0x4b6c, 1521 0x4c6e, 1522 0x4e64, 1523 0x4e65, 1524 0x4e66, 1525 0x4e67, 1526 0x4e68, 1527 0x4e69, 1528 0x4e6a, 1529 0x4e71, 1530 0x4f73, 1531 0x5569, 1532 0x556b, 1533 0x556d, 1534 0x556f, 1535 0x5571, 1536 0x5854, 1537 0x5874, 1538 0x5940, 1539 0x5941, 1540 0x5b72, 1541 0x5b73, 1542 0x5b74, 1543 0x5b75, 1544 0x5d44, 1545 0x5d45, 1546 0x5d6d, 1547 0x5d6f, 1548 0x5d72, 1549 0x5d77, 1550 0x5e6b, 1551 0x5e6d, 1552 0x7120, 1553 0x7124, 1554 0x7129, 1555 0x712e, 1556 0x712f, 1557 0x7162, 1558 0x7163, 1559 0x7166, 1560 0x7167, 1561 0x7172, 1562 0x7173, 1563 0x71a0, 1564 0x71a1, 1565 0x71a3, 1566 0x71a7, 1567 0x71bb, 1568 0x71e0, 1569 0x71e1, 1570 0x71e2, 1571 0x71e6, 1572 0x71e7, 1573 0x71f2, 1574 0x7269, 1575 0x726b, 1576 0x726e, 1577 0x72a0, 1578 0x72a8, 1579 0x72b1, 1580 0x72b3, 1581 0x793f, 1582 }; 1583 1584 static const struct pci_device_id pciidlist[] = { 1585 #ifdef CONFIG_DRM_AMDGPU_SI 1586 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1587 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1588 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1589 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1590 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1591 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1592 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1593 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1594 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1595 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1596 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1597 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1598 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1599 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1600 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1601 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1602 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1603 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1604 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1605 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1606 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1607 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1608 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1609 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1610 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1611 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1612 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1613 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1614 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1615 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1616 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1617 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1618 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1619 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1620 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1621 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1622 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1623 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1624 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1625 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1626 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1627 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1628 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1630 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1631 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1632 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1633 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1634 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1635 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1636 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1637 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1638 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1639 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1640 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1641 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1642 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1643 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1644 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1646 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1647 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1648 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1649 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1650 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1651 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1652 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1653 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1654 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1657 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1658 #endif 1659 #ifdef CONFIG_DRM_AMDGPU_CIK 1660 /* Kaveri */ 1661 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1662 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1663 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1664 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1665 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1666 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1667 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1668 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1669 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1670 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1671 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1672 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1673 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1674 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1675 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1676 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1677 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1678 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1679 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1680 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1681 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1682 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1683 /* Bonaire */ 1684 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1685 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1689 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1690 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1691 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1692 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1693 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1694 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1695 /* Hawaii */ 1696 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1697 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1698 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1699 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1700 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1701 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1702 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1703 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1704 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1705 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1706 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1707 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1708 /* Kabini */ 1709 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1710 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1711 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1713 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1714 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1715 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1716 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1717 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1718 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1719 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1720 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1721 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1722 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1723 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1724 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1725 /* mullins */ 1726 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1727 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1728 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1729 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1730 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1731 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1733 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1735 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1736 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1737 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 #endif 1743 /* topaz */ 1744 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1745 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1746 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1747 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1748 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1749 /* tonga */ 1750 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1751 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1752 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1753 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1754 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1755 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1756 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1757 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1758 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1759 /* fiji */ 1760 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1761 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1762 /* carrizo */ 1763 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1764 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1765 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1766 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1767 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1768 /* stoney */ 1769 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1770 /* Polaris11 */ 1771 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1772 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1773 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1774 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1775 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1776 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1777 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1778 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1779 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1780 /* Polaris10 */ 1781 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1782 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1783 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1784 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1785 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1786 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1787 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1788 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1789 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1790 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1791 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1792 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1793 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1794 /* Polaris12 */ 1795 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1796 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1797 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1798 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1799 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1800 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1801 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1802 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1803 /* VEGAM */ 1804 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1805 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1806 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1807 /* Vega 10 */ 1808 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1809 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1810 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1811 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1812 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1813 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1814 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1815 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1816 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1817 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1818 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1819 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1820 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1821 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1822 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1823 /* Vega 12 */ 1824 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1825 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1826 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1827 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1828 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1829 /* Vega 20 */ 1830 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1831 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1832 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1833 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1834 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1835 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1836 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1837 /* Raven */ 1838 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1839 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1840 /* Arcturus */ 1841 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1842 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1843 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1844 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1845 /* Navi10 */ 1846 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1847 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1848 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1849 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1850 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1851 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1852 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1853 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1854 /* Navi14 */ 1855 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1856 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1857 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1858 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1859 1860 /* Renoir */ 1861 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1862 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1863 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1864 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1865 1866 /* Navi12 */ 1867 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1868 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1869 1870 /* Sienna_Cichlid */ 1871 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1872 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1873 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1874 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1875 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1876 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1877 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1878 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1879 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1880 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1881 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1882 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1883 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1884 1885 /* Van Gogh */ 1886 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1887 1888 /* Yellow Carp */ 1889 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1890 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1891 1892 /* Navy_Flounder */ 1893 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1894 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1895 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1896 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1897 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1898 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1899 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1900 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1901 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1902 1903 /* DIMGREY_CAVEFISH */ 1904 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1905 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1906 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1907 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1908 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1909 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1910 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1911 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1912 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1913 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1914 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1915 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1916 1917 /* Aldebaran */ 1918 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1919 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1920 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1921 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1922 1923 /* CYAN_SKILLFISH */ 1924 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1925 1926 /* BEIGE_GOBY */ 1927 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1928 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1929 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1930 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1931 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1932 1933 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1934 .class = PCI_CLASS_DISPLAY_VGA << 8, 1935 .class_mask = 0xffffff, 1936 .driver_data = CHIP_IP_DISCOVERY }, 1937 1938 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1939 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1940 .class_mask = 0xffffff, 1941 .driver_data = CHIP_IP_DISCOVERY }, 1942 1943 {0, 0, 0} 1944 }; 1945 1946 MODULE_DEVICE_TABLE(pci, pciidlist); 1947 1948 static const struct drm_driver amdgpu_kms_driver; 1949 1950 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1951 { 1952 struct pci_dev *p = NULL; 1953 int i; 1954 1955 /* 0 - GPU 1956 * 1 - audio 1957 * 2 - USB 1958 * 3 - UCSI 1959 */ 1960 for (i = 1; i < 4; i++) { 1961 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1962 adev->pdev->bus->number, i); 1963 if (p) { 1964 pm_runtime_get_sync(&p->dev); 1965 pm_runtime_mark_last_busy(&p->dev); 1966 pm_runtime_put_autosuspend(&p->dev); 1967 pci_dev_put(p); 1968 } 1969 } 1970 } 1971 1972 static int amdgpu_pci_probe(struct pci_dev *pdev, 1973 const struct pci_device_id *ent) 1974 { 1975 struct drm_device *ddev; 1976 struct amdgpu_device *adev; 1977 unsigned long flags = ent->driver_data; 1978 int ret, retry = 0, i; 1979 bool supports_atomic = false; 1980 1981 /* skip devices which are owned by radeon */ 1982 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1983 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 1984 return -ENODEV; 1985 } 1986 1987 if (amdgpu_virtual_display || 1988 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1989 supports_atomic = true; 1990 1991 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1992 DRM_INFO("This hardware requires experimental hardware support.\n" 1993 "See modparam exp_hw_support\n"); 1994 return -ENODEV; 1995 } 1996 1997 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1998 * however, SME requires an indirect IOMMU mapping because the encryption 1999 * bit is beyond the DMA mask of the chip. 2000 */ 2001 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2002 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2003 dev_info(&pdev->dev, 2004 "SME is not compatible with RAVEN\n"); 2005 return -ENOTSUPP; 2006 } 2007 2008 #ifdef CONFIG_DRM_AMDGPU_SI 2009 if (!amdgpu_si_support) { 2010 switch (flags & AMD_ASIC_MASK) { 2011 case CHIP_TAHITI: 2012 case CHIP_PITCAIRN: 2013 case CHIP_VERDE: 2014 case CHIP_OLAND: 2015 case CHIP_HAINAN: 2016 dev_info(&pdev->dev, 2017 "SI support provided by radeon.\n"); 2018 dev_info(&pdev->dev, 2019 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2020 ); 2021 return -ENODEV; 2022 } 2023 } 2024 #endif 2025 #ifdef CONFIG_DRM_AMDGPU_CIK 2026 if (!amdgpu_cik_support) { 2027 switch (flags & AMD_ASIC_MASK) { 2028 case CHIP_KAVERI: 2029 case CHIP_BONAIRE: 2030 case CHIP_HAWAII: 2031 case CHIP_KABINI: 2032 case CHIP_MULLINS: 2033 dev_info(&pdev->dev, 2034 "CIK support provided by radeon.\n"); 2035 dev_info(&pdev->dev, 2036 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2037 ); 2038 return -ENODEV; 2039 } 2040 } 2041 #endif 2042 2043 /* Get rid of things like offb */ 2044 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2045 if (ret) 2046 return ret; 2047 2048 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2049 if (IS_ERR(adev)) 2050 return PTR_ERR(adev); 2051 2052 adev->dev = &pdev->dev; 2053 adev->pdev = pdev; 2054 ddev = adev_to_drm(adev); 2055 2056 if (!supports_atomic) 2057 ddev->driver_features &= ~DRIVER_ATOMIC; 2058 2059 ret = pci_enable_device(pdev); 2060 if (ret) 2061 return ret; 2062 2063 pci_set_drvdata(pdev, ddev); 2064 2065 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2066 if (ret) 2067 goto err_pci; 2068 2069 retry_init: 2070 ret = drm_dev_register(ddev, ent->driver_data); 2071 if (ret == -EAGAIN && ++retry <= 3) { 2072 DRM_INFO("retry init %d\n", retry); 2073 /* Don't request EX mode too frequently which is attacking */ 2074 msleep(5000); 2075 goto retry_init; 2076 } else if (ret) { 2077 goto err_pci; 2078 } 2079 2080 /* 2081 * 1. don't init fbdev on hw without DCE 2082 * 2. don't init fbdev if there are no connectors 2083 */ 2084 if (adev->mode_info.mode_config_initialized && 2085 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2086 /* select 8 bpp console on low vram cards */ 2087 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2088 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2089 else 2090 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2091 } 2092 2093 ret = amdgpu_debugfs_init(adev); 2094 if (ret) 2095 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2096 2097 if (adev->runpm) { 2098 /* only need to skip on ATPX */ 2099 if (amdgpu_device_supports_px(ddev)) 2100 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2101 /* we want direct complete for BOCO */ 2102 if (amdgpu_device_supports_boco(ddev)) 2103 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2104 DPM_FLAG_SMART_SUSPEND | 2105 DPM_FLAG_MAY_SKIP_RESUME); 2106 pm_runtime_use_autosuspend(ddev->dev); 2107 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2108 2109 pm_runtime_allow(ddev->dev); 2110 2111 pm_runtime_mark_last_busy(ddev->dev); 2112 pm_runtime_put_autosuspend(ddev->dev); 2113 2114 /* 2115 * For runpm implemented via BACO, PMFW will handle the 2116 * timing for BACO in and out: 2117 * - put ASIC into BACO state only when both video and 2118 * audio functions are in D3 state. 2119 * - pull ASIC out of BACO state when either video or 2120 * audio function is in D0 state. 2121 * Also, at startup, PMFW assumes both functions are in 2122 * D0 state. 2123 * 2124 * So if snd driver was loaded prior to amdgpu driver 2125 * and audio function was put into D3 state, there will 2126 * be no PMFW-aware D-state transition(D0->D3) on runpm 2127 * suspend. Thus the BACO will be not correctly kicked in. 2128 * 2129 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2130 * into D0 state. Then there will be a PMFW-aware D-state 2131 * transition(D0->D3) on runpm suspend. 2132 */ 2133 if (amdgpu_device_supports_baco(ddev) && 2134 !(adev->flags & AMD_IS_APU) && 2135 (adev->asic_type >= CHIP_NAVI10)) 2136 amdgpu_get_secondary_funcs(adev); 2137 } 2138 2139 return 0; 2140 2141 err_pci: 2142 pci_disable_device(pdev); 2143 return ret; 2144 } 2145 2146 static void 2147 amdgpu_pci_remove(struct pci_dev *pdev) 2148 { 2149 struct drm_device *dev = pci_get_drvdata(pdev); 2150 struct amdgpu_device *adev = drm_to_adev(dev); 2151 2152 drm_dev_unplug(dev); 2153 2154 if (adev->runpm) { 2155 pm_runtime_get_sync(dev->dev); 2156 pm_runtime_forbid(dev->dev); 2157 } 2158 2159 amdgpu_driver_unload_kms(dev); 2160 2161 /* 2162 * Flush any in flight DMA operations from device. 2163 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2164 * StatusTransactions Pending bit. 2165 */ 2166 pci_disable_device(pdev); 2167 pci_wait_for_pending_transaction(pdev); 2168 } 2169 2170 static void 2171 amdgpu_pci_shutdown(struct pci_dev *pdev) 2172 { 2173 struct drm_device *dev = pci_get_drvdata(pdev); 2174 struct amdgpu_device *adev = drm_to_adev(dev); 2175 2176 if (amdgpu_ras_intr_triggered()) 2177 return; 2178 2179 /* if we are running in a VM, make sure the device 2180 * torn down properly on reboot/shutdown. 2181 * unfortunately we can't detect certain 2182 * hypervisors so just do this all the time. 2183 */ 2184 if (!amdgpu_passthrough(adev)) 2185 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2186 amdgpu_device_ip_suspend(adev); 2187 adev->mp1_state = PP_MP1_STATE_NONE; 2188 } 2189 2190 /** 2191 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2192 * 2193 * @work: work_struct. 2194 */ 2195 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2196 { 2197 struct list_head device_list; 2198 struct amdgpu_device *adev; 2199 int i, r; 2200 struct amdgpu_reset_context reset_context; 2201 2202 memset(&reset_context, 0, sizeof(reset_context)); 2203 2204 mutex_lock(&mgpu_info.mutex); 2205 if (mgpu_info.pending_reset == true) { 2206 mutex_unlock(&mgpu_info.mutex); 2207 return; 2208 } 2209 mgpu_info.pending_reset = true; 2210 mutex_unlock(&mgpu_info.mutex); 2211 2212 /* Use a common context, just need to make sure full reset is done */ 2213 reset_context.method = AMD_RESET_METHOD_NONE; 2214 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2215 2216 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2217 adev = mgpu_info.gpu_ins[i].adev; 2218 reset_context.reset_req_dev = adev; 2219 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2220 if (r) { 2221 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2222 r, adev_to_drm(adev)->unique); 2223 } 2224 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2225 r = -EALREADY; 2226 } 2227 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2228 adev = mgpu_info.gpu_ins[i].adev; 2229 flush_work(&adev->xgmi_reset_work); 2230 adev->gmc.xgmi.pending_reset = false; 2231 } 2232 2233 /* reset function will rebuild the xgmi hive info , clear it now */ 2234 for (i = 0; i < mgpu_info.num_dgpu; i++) 2235 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2236 2237 INIT_LIST_HEAD(&device_list); 2238 2239 for (i = 0; i < mgpu_info.num_dgpu; i++) 2240 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2241 2242 /* unregister the GPU first, reset function will add them back */ 2243 list_for_each_entry(adev, &device_list, reset_list) 2244 amdgpu_unregister_gpu_instance(adev); 2245 2246 /* Use a common context, just need to make sure full reset is done */ 2247 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2248 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2249 2250 if (r) { 2251 DRM_ERROR("reinit gpus failure"); 2252 return; 2253 } 2254 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2255 adev = mgpu_info.gpu_ins[i].adev; 2256 if (!adev->kfd.init_complete) 2257 amdgpu_amdkfd_device_init(adev); 2258 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2259 } 2260 return; 2261 } 2262 2263 static int amdgpu_pmops_prepare(struct device *dev) 2264 { 2265 struct drm_device *drm_dev = dev_get_drvdata(dev); 2266 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2267 2268 /* Return a positive number here so 2269 * DPM_FLAG_SMART_SUSPEND works properly 2270 */ 2271 if (amdgpu_device_supports_boco(drm_dev)) 2272 return pm_runtime_suspended(dev) && 2273 pm_suspend_via_firmware(); 2274 2275 /* if we will not support s3 or s2i for the device 2276 * then skip suspend 2277 */ 2278 if (!amdgpu_acpi_is_s0ix_active(adev) && 2279 !amdgpu_acpi_is_s3_active(adev)) 2280 return 1; 2281 2282 return 0; 2283 } 2284 2285 static void amdgpu_pmops_complete(struct device *dev) 2286 { 2287 /* nothing to do */ 2288 } 2289 2290 static int amdgpu_pmops_suspend(struct device *dev) 2291 { 2292 struct drm_device *drm_dev = dev_get_drvdata(dev); 2293 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2294 int r; 2295 2296 if (amdgpu_acpi_is_s0ix_active(adev)) 2297 adev->in_s0ix = true; 2298 else 2299 adev->in_s3 = true; 2300 r = amdgpu_device_suspend(drm_dev, true); 2301 if (r) 2302 return r; 2303 if (!adev->in_s0ix) 2304 r = amdgpu_asic_reset(adev); 2305 return r; 2306 } 2307 2308 static int amdgpu_pmops_resume(struct device *dev) 2309 { 2310 struct drm_device *drm_dev = dev_get_drvdata(dev); 2311 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2312 int r; 2313 2314 /* Avoids registers access if device is physically gone */ 2315 if (!pci_device_is_present(adev->pdev)) 2316 adev->no_hw_access = true; 2317 2318 r = amdgpu_device_resume(drm_dev, true); 2319 if (amdgpu_acpi_is_s0ix_active(adev)) 2320 adev->in_s0ix = false; 2321 else 2322 adev->in_s3 = false; 2323 return r; 2324 } 2325 2326 static int amdgpu_pmops_freeze(struct device *dev) 2327 { 2328 struct drm_device *drm_dev = dev_get_drvdata(dev); 2329 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2330 int r; 2331 2332 adev->in_s4 = true; 2333 r = amdgpu_device_suspend(drm_dev, true); 2334 adev->in_s4 = false; 2335 if (r) 2336 return r; 2337 return amdgpu_asic_reset(adev); 2338 } 2339 2340 static int amdgpu_pmops_thaw(struct device *dev) 2341 { 2342 struct drm_device *drm_dev = dev_get_drvdata(dev); 2343 2344 return amdgpu_device_resume(drm_dev, true); 2345 } 2346 2347 static int amdgpu_pmops_poweroff(struct device *dev) 2348 { 2349 struct drm_device *drm_dev = dev_get_drvdata(dev); 2350 2351 return amdgpu_device_suspend(drm_dev, true); 2352 } 2353 2354 static int amdgpu_pmops_restore(struct device *dev) 2355 { 2356 struct drm_device *drm_dev = dev_get_drvdata(dev); 2357 2358 return amdgpu_device_resume(drm_dev, true); 2359 } 2360 2361 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2362 { 2363 struct pci_dev *pdev = to_pci_dev(dev); 2364 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2365 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2366 int ret, i; 2367 2368 if (!adev->runpm) { 2369 pm_runtime_forbid(dev); 2370 return -EBUSY; 2371 } 2372 2373 /* wait for all rings to drain before suspending */ 2374 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2375 struct amdgpu_ring *ring = adev->rings[i]; 2376 if (ring && ring->sched.ready) { 2377 ret = amdgpu_fence_wait_empty(ring); 2378 if (ret) 2379 return -EBUSY; 2380 } 2381 } 2382 2383 adev->in_runpm = true; 2384 if (amdgpu_device_supports_px(drm_dev)) 2385 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2386 2387 /* 2388 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2389 * proper cleanups and put itself into a state ready for PNP. That 2390 * can address some random resuming failure observed on BOCO capable 2391 * platforms. 2392 * TODO: this may be also needed for PX capable platform. 2393 */ 2394 if (amdgpu_device_supports_boco(drm_dev)) 2395 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2396 2397 ret = amdgpu_device_suspend(drm_dev, false); 2398 if (ret) { 2399 adev->in_runpm = false; 2400 if (amdgpu_device_supports_boco(drm_dev)) 2401 adev->mp1_state = PP_MP1_STATE_NONE; 2402 return ret; 2403 } 2404 2405 if (amdgpu_device_supports_boco(drm_dev)) 2406 adev->mp1_state = PP_MP1_STATE_NONE; 2407 2408 if (amdgpu_device_supports_px(drm_dev)) { 2409 /* Only need to handle PCI state in the driver for ATPX 2410 * PCI core handles it for _PR3. 2411 */ 2412 amdgpu_device_cache_pci_state(pdev); 2413 pci_disable_device(pdev); 2414 pci_ignore_hotplug(pdev); 2415 pci_set_power_state(pdev, PCI_D3cold); 2416 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2417 } else if (amdgpu_device_supports_boco(drm_dev)) { 2418 /* nothing to do */ 2419 } else if (amdgpu_device_supports_baco(drm_dev)) { 2420 amdgpu_device_baco_enter(drm_dev); 2421 } 2422 2423 return 0; 2424 } 2425 2426 static int amdgpu_pmops_runtime_resume(struct device *dev) 2427 { 2428 struct pci_dev *pdev = to_pci_dev(dev); 2429 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2430 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2431 int ret; 2432 2433 if (!adev->runpm) 2434 return -EINVAL; 2435 2436 /* Avoids registers access if device is physically gone */ 2437 if (!pci_device_is_present(adev->pdev)) 2438 adev->no_hw_access = true; 2439 2440 if (amdgpu_device_supports_px(drm_dev)) { 2441 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2442 2443 /* Only need to handle PCI state in the driver for ATPX 2444 * PCI core handles it for _PR3. 2445 */ 2446 pci_set_power_state(pdev, PCI_D0); 2447 amdgpu_device_load_pci_state(pdev); 2448 ret = pci_enable_device(pdev); 2449 if (ret) 2450 return ret; 2451 pci_set_master(pdev); 2452 } else if (amdgpu_device_supports_boco(drm_dev)) { 2453 /* Only need to handle PCI state in the driver for ATPX 2454 * PCI core handles it for _PR3. 2455 */ 2456 pci_set_master(pdev); 2457 } else if (amdgpu_device_supports_baco(drm_dev)) { 2458 amdgpu_device_baco_exit(drm_dev); 2459 } 2460 ret = amdgpu_device_resume(drm_dev, false); 2461 if (ret) 2462 return ret; 2463 2464 if (amdgpu_device_supports_px(drm_dev)) 2465 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2466 adev->in_runpm = false; 2467 return 0; 2468 } 2469 2470 static int amdgpu_pmops_runtime_idle(struct device *dev) 2471 { 2472 struct drm_device *drm_dev = dev_get_drvdata(dev); 2473 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2474 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2475 int ret = 1; 2476 2477 if (!adev->runpm) { 2478 pm_runtime_forbid(dev); 2479 return -EBUSY; 2480 } 2481 2482 if (amdgpu_device_has_dc_support(adev)) { 2483 struct drm_crtc *crtc; 2484 2485 drm_for_each_crtc(crtc, drm_dev) { 2486 drm_modeset_lock(&crtc->mutex, NULL); 2487 if (crtc->state->active) 2488 ret = -EBUSY; 2489 drm_modeset_unlock(&crtc->mutex); 2490 if (ret < 0) 2491 break; 2492 } 2493 2494 } else { 2495 struct drm_connector *list_connector; 2496 struct drm_connector_list_iter iter; 2497 2498 mutex_lock(&drm_dev->mode_config.mutex); 2499 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2500 2501 drm_connector_list_iter_begin(drm_dev, &iter); 2502 drm_for_each_connector_iter(list_connector, &iter) { 2503 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2504 ret = -EBUSY; 2505 break; 2506 } 2507 } 2508 2509 drm_connector_list_iter_end(&iter); 2510 2511 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2512 mutex_unlock(&drm_dev->mode_config.mutex); 2513 } 2514 2515 if (ret == -EBUSY) 2516 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2517 2518 pm_runtime_mark_last_busy(dev); 2519 pm_runtime_autosuspend(dev); 2520 return ret; 2521 } 2522 2523 long amdgpu_drm_ioctl(struct file *filp, 2524 unsigned int cmd, unsigned long arg) 2525 { 2526 struct drm_file *file_priv = filp->private_data; 2527 struct drm_device *dev; 2528 long ret; 2529 dev = file_priv->minor->dev; 2530 ret = pm_runtime_get_sync(dev->dev); 2531 if (ret < 0) 2532 goto out; 2533 2534 ret = drm_ioctl(filp, cmd, arg); 2535 2536 pm_runtime_mark_last_busy(dev->dev); 2537 out: 2538 pm_runtime_put_autosuspend(dev->dev); 2539 return ret; 2540 } 2541 2542 static const struct dev_pm_ops amdgpu_pm_ops = { 2543 .prepare = amdgpu_pmops_prepare, 2544 .complete = amdgpu_pmops_complete, 2545 .suspend = amdgpu_pmops_suspend, 2546 .resume = amdgpu_pmops_resume, 2547 .freeze = amdgpu_pmops_freeze, 2548 .thaw = amdgpu_pmops_thaw, 2549 .poweroff = amdgpu_pmops_poweroff, 2550 .restore = amdgpu_pmops_restore, 2551 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2552 .runtime_resume = amdgpu_pmops_runtime_resume, 2553 .runtime_idle = amdgpu_pmops_runtime_idle, 2554 }; 2555 2556 static int amdgpu_flush(struct file *f, fl_owner_t id) 2557 { 2558 struct drm_file *file_priv = f->private_data; 2559 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2560 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2561 2562 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2563 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2564 2565 return timeout >= 0 ? 0 : timeout; 2566 } 2567 2568 static const struct file_operations amdgpu_driver_kms_fops = { 2569 .owner = THIS_MODULE, 2570 .open = drm_open, 2571 .flush = amdgpu_flush, 2572 .release = drm_release, 2573 .unlocked_ioctl = amdgpu_drm_ioctl, 2574 .mmap = drm_gem_mmap, 2575 .poll = drm_poll, 2576 .read = drm_read, 2577 #ifdef CONFIG_COMPAT 2578 .compat_ioctl = amdgpu_kms_compat_ioctl, 2579 #endif 2580 #ifdef CONFIG_PROC_FS 2581 .show_fdinfo = amdgpu_show_fdinfo 2582 #endif 2583 }; 2584 2585 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2586 { 2587 struct drm_file *file; 2588 2589 if (!filp) 2590 return -EINVAL; 2591 2592 if (filp->f_op != &amdgpu_driver_kms_fops) { 2593 return -EINVAL; 2594 } 2595 2596 file = filp->private_data; 2597 *fpriv = file->driver_priv; 2598 return 0; 2599 } 2600 2601 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2602 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2603 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2604 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2605 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2606 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2607 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2608 /* KMS */ 2609 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2610 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2611 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2612 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2613 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2614 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2615 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2616 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2617 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2618 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2619 }; 2620 2621 static const struct drm_driver amdgpu_kms_driver = { 2622 .driver_features = 2623 DRIVER_ATOMIC | 2624 DRIVER_GEM | 2625 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2626 DRIVER_SYNCOBJ_TIMELINE, 2627 .open = amdgpu_driver_open_kms, 2628 .postclose = amdgpu_driver_postclose_kms, 2629 .lastclose = amdgpu_driver_lastclose_kms, 2630 .ioctls = amdgpu_ioctls_kms, 2631 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2632 .dumb_create = amdgpu_mode_dumb_create, 2633 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2634 .fops = &amdgpu_driver_kms_fops, 2635 .release = &amdgpu_driver_release_kms, 2636 2637 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2638 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2639 .gem_prime_import = amdgpu_gem_prime_import, 2640 .gem_prime_mmap = drm_gem_prime_mmap, 2641 2642 .name = DRIVER_NAME, 2643 .desc = DRIVER_DESC, 2644 .date = DRIVER_DATE, 2645 .major = KMS_DRIVER_MAJOR, 2646 .minor = KMS_DRIVER_MINOR, 2647 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2648 }; 2649 2650 static struct pci_error_handlers amdgpu_pci_err_handler = { 2651 .error_detected = amdgpu_pci_error_detected, 2652 .mmio_enabled = amdgpu_pci_mmio_enabled, 2653 .slot_reset = amdgpu_pci_slot_reset, 2654 .resume = amdgpu_pci_resume, 2655 }; 2656 2657 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2658 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2659 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2660 2661 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2662 &amdgpu_vram_mgr_attr_group, 2663 &amdgpu_gtt_mgr_attr_group, 2664 &amdgpu_vbios_version_attr_group, 2665 NULL, 2666 }; 2667 2668 2669 static struct pci_driver amdgpu_kms_pci_driver = { 2670 .name = DRIVER_NAME, 2671 .id_table = pciidlist, 2672 .probe = amdgpu_pci_probe, 2673 .remove = amdgpu_pci_remove, 2674 .shutdown = amdgpu_pci_shutdown, 2675 .driver.pm = &amdgpu_pm_ops, 2676 .err_handler = &amdgpu_pci_err_handler, 2677 .dev_groups = amdgpu_sysfs_groups, 2678 }; 2679 2680 static int __init amdgpu_init(void) 2681 { 2682 int r; 2683 2684 if (drm_firmware_drivers_only()) 2685 return -EINVAL; 2686 2687 r = amdgpu_sync_init(); 2688 if (r) 2689 goto error_sync; 2690 2691 r = amdgpu_fence_slab_init(); 2692 if (r) 2693 goto error_fence; 2694 2695 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2696 amdgpu_register_atpx_handler(); 2697 amdgpu_acpi_detect(); 2698 2699 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2700 amdgpu_amdkfd_init(); 2701 2702 /* let modprobe override vga console setting */ 2703 return pci_register_driver(&amdgpu_kms_pci_driver); 2704 2705 error_fence: 2706 amdgpu_sync_fini(); 2707 2708 error_sync: 2709 return r; 2710 } 2711 2712 static void __exit amdgpu_exit(void) 2713 { 2714 amdgpu_amdkfd_fini(); 2715 pci_unregister_driver(&amdgpu_kms_pci_driver); 2716 amdgpu_unregister_atpx_handler(); 2717 amdgpu_sync_fini(); 2718 amdgpu_fence_slab_fini(); 2719 mmu_notifier_synchronize(); 2720 } 2721 2722 module_init(amdgpu_init); 2723 module_exit(amdgpu_exit); 2724 2725 MODULE_AUTHOR(DRIVER_AUTHOR); 2726 MODULE_DESCRIPTION(DRIVER_DESC); 2727 MODULE_LICENSE("GPL and additional rights"); 2728