1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include "amdgpu_drv.h" 30 31 #include <drm/drm_pciids.h> 32 #include <linux/console.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "amdgpu.h" 40 #include "amdgpu_irq.h" 41 #include "amdgpu_dma_buf.h" 42 43 #include "amdgpu_amdkfd.h" 44 45 /* 46 * KMS wrapper. 47 * - 3.0.0 - initial driver 48 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 49 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 50 * at the end of IBs. 51 * - 3.3.0 - Add VM support for UVD on supported hardware. 52 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 53 * - 3.5.0 - Add support for new UVD_NO_OP register. 54 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 55 * - 3.7.0 - Add support for VCE clock list packet 56 * - 3.8.0 - Add support raster config init in the kernel 57 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 58 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 59 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 60 * - 3.12.0 - Add query for double offchip LDS buffers 61 * - 3.13.0 - Add PRT support 62 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 63 * - 3.15.0 - Export more gpu info for gfx9 64 * - 3.16.0 - Add reserved vmid support 65 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 66 * - 3.18.0 - Export gpu always on cu bitmap 67 * - 3.19.0 - Add support for UVD MJPEG decode 68 * - 3.20.0 - Add support for local BOs 69 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 70 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 71 * - 3.23.0 - Add query for VRAM lost counter 72 * - 3.24.0 - Add high priority compute support for gfx9 73 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 74 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 75 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 76 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 77 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 78 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 79 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 80 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 81 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 82 */ 83 #define KMS_DRIVER_MAJOR 3 84 #define KMS_DRIVER_MINOR 33 85 #define KMS_DRIVER_PATCHLEVEL 0 86 87 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 88 89 int amdgpu_vram_limit = 0; 90 int amdgpu_vis_vram_limit = 0; 91 int amdgpu_gart_size = -1; /* auto */ 92 int amdgpu_gtt_size = -1; /* auto */ 93 int amdgpu_moverate = -1; /* auto */ 94 int amdgpu_benchmarking = 0; 95 int amdgpu_testing = 0; 96 int amdgpu_audio = -1; 97 int amdgpu_disp_priority = 0; 98 int amdgpu_hw_i2c = 0; 99 int amdgpu_pcie_gen2 = -1; 100 int amdgpu_msi = -1; 101 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 102 int amdgpu_dpm = -1; 103 int amdgpu_fw_load_type = -1; 104 int amdgpu_aspm = -1; 105 int amdgpu_runtime_pm = -1; 106 uint amdgpu_ip_block_mask = 0xffffffff; 107 int amdgpu_bapm = -1; 108 int amdgpu_deep_color = 0; 109 int amdgpu_vm_size = -1; 110 int amdgpu_vm_fragment_size = -1; 111 int amdgpu_vm_block_size = -1; 112 int amdgpu_vm_fault_stop = 0; 113 int amdgpu_vm_debug = 0; 114 int amdgpu_vm_update_mode = -1; 115 int amdgpu_exp_hw_support = 0; 116 int amdgpu_dc = -1; 117 int amdgpu_sched_jobs = 32; 118 int amdgpu_sched_hw_submission = 2; 119 uint amdgpu_pcie_gen_cap = 0; 120 uint amdgpu_pcie_lane_cap = 0; 121 uint amdgpu_cg_mask = 0xffffffff; 122 uint amdgpu_pg_mask = 0xffffffff; 123 uint amdgpu_sdma_phase_quantum = 32; 124 char *amdgpu_disable_cu = NULL; 125 char *amdgpu_virtual_display = NULL; 126 /* OverDrive(bit 14) disabled by default*/ 127 uint amdgpu_pp_feature_mask = 0xffffbfff; 128 int amdgpu_ngg = 0; 129 int amdgpu_prim_buf_per_se = 0; 130 int amdgpu_pos_buf_per_se = 0; 131 int amdgpu_cntl_sb_buf_per_se = 0; 132 int amdgpu_param_buf_per_se = 0; 133 int amdgpu_job_hang_limit = 0; 134 int amdgpu_lbpw = -1; 135 int amdgpu_compute_multipipe = -1; 136 int amdgpu_gpu_recovery = -1; /* auto */ 137 int amdgpu_emu_mode = 0; 138 uint amdgpu_smu_memory_pool_size = 0; 139 /* FBC (bit 0) disabled by default*/ 140 uint amdgpu_dc_feature_mask = 0; 141 int amdgpu_async_gfx_ring = 1; 142 int amdgpu_mcbp = 0; 143 int amdgpu_discovery = 0; 144 int amdgpu_mes = 0; 145 146 struct amdgpu_mgpu_info mgpu_info = { 147 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 148 }; 149 int amdgpu_ras_enable = -1; 150 uint amdgpu_ras_mask = 0xffffffff; 151 152 /** 153 * DOC: vramlimit (int) 154 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 155 */ 156 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 157 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 158 159 /** 160 * DOC: vis_vramlimit (int) 161 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 162 */ 163 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 164 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 165 166 /** 167 * DOC: gartsize (uint) 168 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 169 */ 170 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 171 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 172 173 /** 174 * DOC: gttsize (int) 175 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 176 * otherwise 3/4 RAM size). 177 */ 178 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 179 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 180 181 /** 182 * DOC: moverate (int) 183 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 184 */ 185 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 186 module_param_named(moverate, amdgpu_moverate, int, 0600); 187 188 /** 189 * DOC: benchmark (int) 190 * Run benchmarks. The default is 0 (Skip benchmarks). 191 */ 192 MODULE_PARM_DESC(benchmark, "Run benchmark"); 193 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 194 195 /** 196 * DOC: test (int) 197 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 198 */ 199 MODULE_PARM_DESC(test, "Run tests"); 200 module_param_named(test, amdgpu_testing, int, 0444); 201 202 /** 203 * DOC: audio (int) 204 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 205 */ 206 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 207 module_param_named(audio, amdgpu_audio, int, 0444); 208 209 /** 210 * DOC: disp_priority (int) 211 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 212 */ 213 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 214 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 215 216 /** 217 * DOC: hw_i2c (int) 218 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 219 */ 220 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 221 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 222 223 /** 224 * DOC: pcie_gen2 (int) 225 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 226 */ 227 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 228 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 229 230 /** 231 * DOC: msi (int) 232 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 233 */ 234 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 235 module_param_named(msi, amdgpu_msi, int, 0444); 236 237 /** 238 * DOC: lockup_timeout (string) 239 * Set GPU scheduler timeout value in ms. 240 * 241 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 242 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 243 * to default timeout. 244 * - With one value specified, the setting will apply to all non-compute jobs. 245 * - With multiple values specified, the first one will be for GFX. The second one is for Compute. 246 * And the third and fourth ones are for SDMA and Video. 247 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 248 * jobs is 10000. And there is no timeout enforced on compute jobs. 249 */ 250 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs." 251 " 0: keep default value. negative: infinity timeout), " 252 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); 253 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 254 255 /** 256 * DOC: dpm (int) 257 * Override for dynamic power management setting 258 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 259 * The default is -1 (auto). 260 */ 261 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 262 module_param_named(dpm, amdgpu_dpm, int, 0444); 263 264 /** 265 * DOC: fw_load_type (int) 266 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 267 */ 268 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 269 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 270 271 /** 272 * DOC: aspm (int) 273 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 274 */ 275 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 276 module_param_named(aspm, amdgpu_aspm, int, 0444); 277 278 /** 279 * DOC: runpm (int) 280 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 281 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 282 */ 283 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 284 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 285 286 /** 287 * DOC: ip_block_mask (uint) 288 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 289 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 290 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 291 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 292 */ 293 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 294 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 295 296 /** 297 * DOC: bapm (int) 298 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 299 * The default -1 (auto, enabled) 300 */ 301 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 302 module_param_named(bapm, amdgpu_bapm, int, 0444); 303 304 /** 305 * DOC: deep_color (int) 306 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 307 */ 308 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 309 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 310 311 /** 312 * DOC: vm_size (int) 313 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 314 */ 315 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 316 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 317 318 /** 319 * DOC: vm_fragment_size (int) 320 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 321 */ 322 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 323 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 324 325 /** 326 * DOC: vm_block_size (int) 327 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 328 */ 329 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 330 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 331 332 /** 333 * DOC: vm_fault_stop (int) 334 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 335 */ 336 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 337 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 338 339 /** 340 * DOC: vm_debug (int) 341 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 342 */ 343 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 344 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 345 346 /** 347 * DOC: vm_update_mode (int) 348 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 349 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 350 */ 351 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 352 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 353 354 /** 355 * DOC: exp_hw_support (int) 356 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 357 */ 358 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 359 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 360 361 /** 362 * DOC: dc (int) 363 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 364 */ 365 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 366 module_param_named(dc, amdgpu_dc, int, 0444); 367 368 /** 369 * DOC: sched_jobs (int) 370 * Override the max number of jobs supported in the sw queue. The default is 32. 371 */ 372 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 373 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 374 375 /** 376 * DOC: sched_hw_submission (int) 377 * Override the max number of HW submissions. The default is 2. 378 */ 379 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 380 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 381 382 /** 383 * DOC: ppfeaturemask (uint) 384 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 385 * The default is the current set of stable power features. 386 */ 387 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 388 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 389 390 /** 391 * DOC: pcie_gen_cap (uint) 392 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 393 * The default is 0 (automatic for each asic). 394 */ 395 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 396 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 397 398 /** 399 * DOC: pcie_lane_cap (uint) 400 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 401 * The default is 0 (automatic for each asic). 402 */ 403 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 404 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 405 406 /** 407 * DOC: cg_mask (uint) 408 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 409 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 410 */ 411 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 412 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 413 414 /** 415 * DOC: pg_mask (uint) 416 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 417 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 418 */ 419 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 420 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 421 422 /** 423 * DOC: sdma_phase_quantum (uint) 424 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 425 */ 426 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 427 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 428 429 /** 430 * DOC: disable_cu (charp) 431 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 432 */ 433 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 434 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 435 436 /** 437 * DOC: virtual_display (charp) 438 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 439 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 440 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 441 * device at 26:00.0. The default is NULL. 442 */ 443 MODULE_PARM_DESC(virtual_display, 444 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 445 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 446 447 /** 448 * DOC: ngg (int) 449 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 450 */ 451 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 452 module_param_named(ngg, amdgpu_ngg, int, 0444); 453 454 /** 455 * DOC: prim_buf_per_se (int) 456 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 457 */ 458 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 459 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 460 461 /** 462 * DOC: pos_buf_per_se (int) 463 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 464 */ 465 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 466 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 467 468 /** 469 * DOC: cntl_sb_buf_per_se (int) 470 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 471 */ 472 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 473 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 474 475 /** 476 * DOC: param_buf_per_se (int) 477 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 478 * The default is 0 (depending on gfx). 479 */ 480 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 481 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 482 483 /** 484 * DOC: job_hang_limit (int) 485 * Set how much time allow a job hang and not drop it. The default is 0. 486 */ 487 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 488 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 489 490 /** 491 * DOC: lbpw (int) 492 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 493 */ 494 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 495 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 496 497 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 498 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 499 500 /** 501 * DOC: gpu_recovery (int) 502 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 503 */ 504 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 505 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 506 507 /** 508 * DOC: emu_mode (int) 509 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 510 */ 511 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 512 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 513 514 /** 515 * DOC: ras_enable (int) 516 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 517 */ 518 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 519 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 520 521 /** 522 * DOC: ras_mask (uint) 523 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 524 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 525 */ 526 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 527 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 528 529 /** 530 * DOC: si_support (int) 531 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 532 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 533 * otherwise using amdgpu driver. 534 */ 535 #ifdef CONFIG_DRM_AMDGPU_SI 536 537 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 538 int amdgpu_si_support = 0; 539 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 540 #else 541 int amdgpu_si_support = 1; 542 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 543 #endif 544 545 module_param_named(si_support, amdgpu_si_support, int, 0444); 546 #endif 547 548 /** 549 * DOC: cik_support (int) 550 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 551 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 552 * otherwise using amdgpu driver. 553 */ 554 #ifdef CONFIG_DRM_AMDGPU_CIK 555 556 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 557 int amdgpu_cik_support = 0; 558 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 559 #else 560 int amdgpu_cik_support = 1; 561 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 562 #endif 563 564 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 565 #endif 566 567 /** 568 * DOC: smu_memory_pool_size (uint) 569 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 570 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 571 */ 572 MODULE_PARM_DESC(smu_memory_pool_size, 573 "reserve gtt for smu debug usage, 0 = disable," 574 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 575 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 576 577 /** 578 * DOC: async_gfx_ring (int) 579 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 580 */ 581 MODULE_PARM_DESC(async_gfx_ring, 582 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 583 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 584 585 /** 586 * DOC: mcbp (int) 587 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 588 */ 589 MODULE_PARM_DESC(mcbp, 590 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 591 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 592 593 /** 594 * DOC: discovery (int) 595 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 596 */ 597 MODULE_PARM_DESC(discovery, 598 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 599 module_param_named(discovery, amdgpu_discovery, int, 0444); 600 601 /** 602 * DOC: mes (int) 603 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 604 * (0 = disabled (default), 1 = enabled) 605 */ 606 MODULE_PARM_DESC(mes, 607 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 608 module_param_named(mes, amdgpu_mes, int, 0444); 609 610 #ifdef CONFIG_HSA_AMD 611 /** 612 * DOC: sched_policy (int) 613 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 614 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 615 * assigns queues to HQDs. 616 */ 617 int sched_policy = KFD_SCHED_POLICY_HWS; 618 module_param(sched_policy, int, 0444); 619 MODULE_PARM_DESC(sched_policy, 620 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 621 622 /** 623 * DOC: hws_max_conc_proc (int) 624 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 625 * number of VMIDs assigned to the HWS, which is also the default. 626 */ 627 int hws_max_conc_proc = 8; 628 module_param(hws_max_conc_proc, int, 0444); 629 MODULE_PARM_DESC(hws_max_conc_proc, 630 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 631 632 /** 633 * DOC: cwsr_enable (int) 634 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 635 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 636 * disables it. 637 */ 638 int cwsr_enable = 1; 639 module_param(cwsr_enable, int, 0444); 640 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 641 642 /** 643 * DOC: max_num_of_queues_per_device (int) 644 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 645 * is 4096. 646 */ 647 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 648 module_param(max_num_of_queues_per_device, int, 0444); 649 MODULE_PARM_DESC(max_num_of_queues_per_device, 650 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 651 652 /** 653 * DOC: send_sigterm (int) 654 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 655 * but just print errors on dmesg. Setting 1 enables sending sigterm. 656 */ 657 int send_sigterm; 658 module_param(send_sigterm, int, 0444); 659 MODULE_PARM_DESC(send_sigterm, 660 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 661 662 /** 663 * DOC: debug_largebar (int) 664 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 665 * system. This limits the VRAM size reported to ROCm applications to the visible 666 * size, usually 256MB. 667 * Default value is 0, diabled. 668 */ 669 int debug_largebar; 670 module_param(debug_largebar, int, 0444); 671 MODULE_PARM_DESC(debug_largebar, 672 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 673 674 /** 675 * DOC: ignore_crat (int) 676 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 677 * table to get information about AMD APUs. This option can serve as a workaround on 678 * systems with a broken CRAT table. 679 */ 680 int ignore_crat; 681 module_param(ignore_crat, int, 0444); 682 MODULE_PARM_DESC(ignore_crat, 683 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 684 685 /** 686 * DOC: noretry (int) 687 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry. 688 * Setting 1 disables retry. 689 * Retry is needed for recoverable page faults. 690 */ 691 int noretry; 692 module_param(noretry, int, 0644); 693 MODULE_PARM_DESC(noretry, 694 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); 695 696 /** 697 * DOC: halt_if_hws_hang (int) 698 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 699 * Setting 1 enables halt on hang. 700 */ 701 int halt_if_hws_hang; 702 module_param(halt_if_hws_hang, int, 0644); 703 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 704 705 /** 706 * DOC: hws_gws_support(bool) 707 * Whether HWS support gws barriers. Default value: false (not supported) 708 * This will be replaced with a MEC firmware version check once firmware 709 * is ready 710 */ 711 bool hws_gws_support; 712 module_param(hws_gws_support, bool, 0444); 713 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 714 715 /** 716 * DOC: queue_preemption_timeout_ms (int) 717 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 718 */ 719 int queue_preemption_timeout_ms = 9000; 720 module_param(queue_preemption_timeout_ms, int, 0644); 721 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 722 #endif 723 724 /** 725 * DOC: dcfeaturemask (uint) 726 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 727 * The default is the current set of stable display features. 728 */ 729 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 730 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 731 732 /** 733 * DOC: abmlevel (uint) 734 * Override the default ABM (Adaptive Backlight Management) level used for DC 735 * enabled hardware. Requires DMCU to be supported and loaded. 736 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 737 * default. Values 1-4 control the maximum allowable brightness reduction via 738 * the ABM algorithm, with 1 being the least reduction and 4 being the most 739 * reduction. 740 * 741 * Defaults to 0, or disabled. Userspace can still override this level later 742 * after boot. 743 */ 744 uint amdgpu_dm_abm_level = 0; 745 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 746 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 747 748 static const struct pci_device_id pciidlist[] = { 749 #ifdef CONFIG_DRM_AMDGPU_SI 750 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 751 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 752 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 753 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 754 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 755 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 756 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 757 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 758 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 759 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 760 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 761 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 762 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 763 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 764 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 765 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 766 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 767 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 768 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 769 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 770 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 771 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 772 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 773 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 774 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 775 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 776 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 777 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 778 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 779 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 780 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 781 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 782 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 783 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 784 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 785 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 786 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 787 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 788 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 789 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 790 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 791 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 792 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 793 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 794 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 795 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 796 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 797 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 798 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 799 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 800 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 801 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 802 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 803 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 804 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 805 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 806 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 807 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 808 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 809 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 810 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 811 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 812 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 813 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 814 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 815 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 816 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 817 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 818 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 819 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 820 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 821 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 822 #endif 823 #ifdef CONFIG_DRM_AMDGPU_CIK 824 /* Kaveri */ 825 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 826 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 827 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 828 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 829 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 830 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 831 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 832 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 833 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 834 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 835 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 836 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 837 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 838 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 839 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 840 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 841 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 842 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 843 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 844 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 845 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 846 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 847 /* Bonaire */ 848 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 849 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 850 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 851 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 852 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 853 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 854 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 855 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 856 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 857 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 858 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 859 /* Hawaii */ 860 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 861 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 862 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 863 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 864 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 865 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 866 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 867 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 868 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 869 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 870 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 871 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 872 /* Kabini */ 873 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 874 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 875 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 876 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 877 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 878 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 879 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 880 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 881 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 882 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 884 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 886 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 887 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 888 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 889 /* mullins */ 890 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 891 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 892 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 893 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 894 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 895 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 896 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 897 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 898 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 899 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 900 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 901 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 902 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 903 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 904 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 905 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 906 #endif 907 /* topaz */ 908 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 909 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 910 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 911 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 912 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 913 /* tonga */ 914 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 915 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 916 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 917 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 918 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 919 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 920 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 921 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 922 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 923 /* fiji */ 924 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 925 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 926 /* carrizo */ 927 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 928 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 929 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 930 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 931 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 932 /* stoney */ 933 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 934 /* Polaris11 */ 935 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 936 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 937 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 938 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 939 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 940 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 941 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 942 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 943 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 944 /* Polaris10 */ 945 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 946 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 947 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 948 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 949 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 950 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 951 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 952 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 953 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 954 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 955 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 956 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 957 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 958 /* Polaris12 */ 959 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 960 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 961 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 962 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 963 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 964 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 965 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 966 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 967 /* VEGAM */ 968 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 969 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 970 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 971 /* Vega 10 */ 972 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 973 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 974 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 975 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 976 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 977 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 978 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 979 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 980 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 981 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 982 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 983 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 984 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 985 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 986 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 987 /* Vega 12 */ 988 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 989 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 990 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 991 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 992 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 993 /* Vega 20 */ 994 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 995 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 996 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 997 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 998 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 999 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1000 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1001 /* Raven */ 1002 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1003 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1004 /* Navi10 */ 1005 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1006 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1007 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1008 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1009 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1010 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1011 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1012 1013 {0, 0, 0} 1014 }; 1015 1016 MODULE_DEVICE_TABLE(pci, pciidlist); 1017 1018 static struct drm_driver kms_driver; 1019 1020 static int amdgpu_pci_probe(struct pci_dev *pdev, 1021 const struct pci_device_id *ent) 1022 { 1023 struct drm_device *dev; 1024 unsigned long flags = ent->driver_data; 1025 int ret, retry = 0; 1026 bool supports_atomic = false; 1027 1028 if (!amdgpu_virtual_display && 1029 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1030 supports_atomic = true; 1031 1032 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1033 DRM_INFO("This hardware requires experimental hardware support.\n" 1034 "See modparam exp_hw_support\n"); 1035 return -ENODEV; 1036 } 1037 1038 /* Get rid of things like offb */ 1039 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 1040 if (ret) 1041 return ret; 1042 1043 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1044 if (IS_ERR(dev)) 1045 return PTR_ERR(dev); 1046 1047 if (!supports_atomic) 1048 dev->driver_features &= ~DRIVER_ATOMIC; 1049 1050 ret = pci_enable_device(pdev); 1051 if (ret) 1052 goto err_free; 1053 1054 dev->pdev = pdev; 1055 1056 pci_set_drvdata(pdev, dev); 1057 1058 retry_init: 1059 ret = drm_dev_register(dev, ent->driver_data); 1060 if (ret == -EAGAIN && ++retry <= 3) { 1061 DRM_INFO("retry init %d\n", retry); 1062 /* Don't request EX mode too frequently which is attacking */ 1063 msleep(5000); 1064 goto retry_init; 1065 } else if (ret) 1066 goto err_pci; 1067 1068 return 0; 1069 1070 err_pci: 1071 pci_disable_device(pdev); 1072 err_free: 1073 drm_dev_put(dev); 1074 return ret; 1075 } 1076 1077 static void 1078 amdgpu_pci_remove(struct pci_dev *pdev) 1079 { 1080 struct drm_device *dev = pci_get_drvdata(pdev); 1081 1082 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 1083 drm_dev_unplug(dev); 1084 drm_dev_put(dev); 1085 pci_disable_device(pdev); 1086 pci_set_drvdata(pdev, NULL); 1087 } 1088 1089 static void 1090 amdgpu_pci_shutdown(struct pci_dev *pdev) 1091 { 1092 struct drm_device *dev = pci_get_drvdata(pdev); 1093 struct amdgpu_device *adev = dev->dev_private; 1094 1095 /* if we are running in a VM, make sure the device 1096 * torn down properly on reboot/shutdown. 1097 * unfortunately we can't detect certain 1098 * hypervisors so just do this all the time. 1099 */ 1100 amdgpu_device_ip_suspend(adev); 1101 } 1102 1103 static int amdgpu_pmops_suspend(struct device *dev) 1104 { 1105 struct pci_dev *pdev = to_pci_dev(dev); 1106 1107 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1108 return amdgpu_device_suspend(drm_dev, true, true); 1109 } 1110 1111 static int amdgpu_pmops_resume(struct device *dev) 1112 { 1113 struct pci_dev *pdev = to_pci_dev(dev); 1114 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1115 1116 /* GPU comes up enabled by the bios on resume */ 1117 if (amdgpu_device_is_px(drm_dev)) { 1118 pm_runtime_disable(dev); 1119 pm_runtime_set_active(dev); 1120 pm_runtime_enable(dev); 1121 } 1122 1123 return amdgpu_device_resume(drm_dev, true, true); 1124 } 1125 1126 static int amdgpu_pmops_freeze(struct device *dev) 1127 { 1128 struct pci_dev *pdev = to_pci_dev(dev); 1129 1130 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1131 return amdgpu_device_suspend(drm_dev, false, true); 1132 } 1133 1134 static int amdgpu_pmops_thaw(struct device *dev) 1135 { 1136 struct pci_dev *pdev = to_pci_dev(dev); 1137 1138 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1139 return amdgpu_device_resume(drm_dev, false, true); 1140 } 1141 1142 static int amdgpu_pmops_poweroff(struct device *dev) 1143 { 1144 struct pci_dev *pdev = to_pci_dev(dev); 1145 1146 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1147 return amdgpu_device_suspend(drm_dev, true, true); 1148 } 1149 1150 static int amdgpu_pmops_restore(struct device *dev) 1151 { 1152 struct pci_dev *pdev = to_pci_dev(dev); 1153 1154 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1155 return amdgpu_device_resume(drm_dev, false, true); 1156 } 1157 1158 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1159 { 1160 struct pci_dev *pdev = to_pci_dev(dev); 1161 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1162 int ret; 1163 1164 if (!amdgpu_device_is_px(drm_dev)) { 1165 pm_runtime_forbid(dev); 1166 return -EBUSY; 1167 } 1168 1169 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1170 drm_kms_helper_poll_disable(drm_dev); 1171 1172 ret = amdgpu_device_suspend(drm_dev, false, false); 1173 pci_save_state(pdev); 1174 pci_disable_device(pdev); 1175 pci_ignore_hotplug(pdev); 1176 if (amdgpu_is_atpx_hybrid()) 1177 pci_set_power_state(pdev, PCI_D3cold); 1178 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1179 pci_set_power_state(pdev, PCI_D3hot); 1180 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1181 1182 return 0; 1183 } 1184 1185 static int amdgpu_pmops_runtime_resume(struct device *dev) 1186 { 1187 struct pci_dev *pdev = to_pci_dev(dev); 1188 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1189 int ret; 1190 1191 if (!amdgpu_device_is_px(drm_dev)) 1192 return -EINVAL; 1193 1194 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1195 1196 if (amdgpu_is_atpx_hybrid() || 1197 !amdgpu_has_atpx_dgpu_power_cntl()) 1198 pci_set_power_state(pdev, PCI_D0); 1199 pci_restore_state(pdev); 1200 ret = pci_enable_device(pdev); 1201 if (ret) 1202 return ret; 1203 pci_set_master(pdev); 1204 1205 ret = amdgpu_device_resume(drm_dev, false, false); 1206 drm_kms_helper_poll_enable(drm_dev); 1207 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1208 return 0; 1209 } 1210 1211 static int amdgpu_pmops_runtime_idle(struct device *dev) 1212 { 1213 struct pci_dev *pdev = to_pci_dev(dev); 1214 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1215 struct drm_crtc *crtc; 1216 1217 if (!amdgpu_device_is_px(drm_dev)) { 1218 pm_runtime_forbid(dev); 1219 return -EBUSY; 1220 } 1221 1222 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1223 if (crtc->enabled) { 1224 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1225 return -EBUSY; 1226 } 1227 } 1228 1229 pm_runtime_mark_last_busy(dev); 1230 pm_runtime_autosuspend(dev); 1231 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1232 return 1; 1233 } 1234 1235 long amdgpu_drm_ioctl(struct file *filp, 1236 unsigned int cmd, unsigned long arg) 1237 { 1238 struct drm_file *file_priv = filp->private_data; 1239 struct drm_device *dev; 1240 long ret; 1241 dev = file_priv->minor->dev; 1242 ret = pm_runtime_get_sync(dev->dev); 1243 if (ret < 0) 1244 return ret; 1245 1246 ret = drm_ioctl(filp, cmd, arg); 1247 1248 pm_runtime_mark_last_busy(dev->dev); 1249 pm_runtime_put_autosuspend(dev->dev); 1250 return ret; 1251 } 1252 1253 static const struct dev_pm_ops amdgpu_pm_ops = { 1254 .suspend = amdgpu_pmops_suspend, 1255 .resume = amdgpu_pmops_resume, 1256 .freeze = amdgpu_pmops_freeze, 1257 .thaw = amdgpu_pmops_thaw, 1258 .poweroff = amdgpu_pmops_poweroff, 1259 .restore = amdgpu_pmops_restore, 1260 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1261 .runtime_resume = amdgpu_pmops_runtime_resume, 1262 .runtime_idle = amdgpu_pmops_runtime_idle, 1263 }; 1264 1265 static int amdgpu_flush(struct file *f, fl_owner_t id) 1266 { 1267 struct drm_file *file_priv = f->private_data; 1268 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1269 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1270 1271 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1272 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1273 1274 return timeout >= 0 ? 0 : timeout; 1275 } 1276 1277 static const struct file_operations amdgpu_driver_kms_fops = { 1278 .owner = THIS_MODULE, 1279 .open = drm_open, 1280 .flush = amdgpu_flush, 1281 .release = drm_release, 1282 .unlocked_ioctl = amdgpu_drm_ioctl, 1283 .mmap = amdgpu_mmap, 1284 .poll = drm_poll, 1285 .read = drm_read, 1286 #ifdef CONFIG_COMPAT 1287 .compat_ioctl = amdgpu_kms_compat_ioctl, 1288 #endif 1289 }; 1290 1291 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1292 { 1293 struct drm_file *file; 1294 1295 if (!filp) 1296 return -EINVAL; 1297 1298 if (filp->f_op != &amdgpu_driver_kms_fops) { 1299 return -EINVAL; 1300 } 1301 1302 file = filp->private_data; 1303 *fpriv = file->driver_priv; 1304 return 0; 1305 } 1306 1307 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 1308 { 1309 char *input = amdgpu_lockup_timeout; 1310 char *timeout_setting = NULL; 1311 int index = 0; 1312 long timeout; 1313 int ret = 0; 1314 1315 /* 1316 * By default timeout for non compute jobs is 10000. 1317 * And there is no timeout enforced on compute jobs. 1318 */ 1319 adev->gfx_timeout = msecs_to_jiffies(10000); 1320 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1321 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; 1322 1323 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1324 while ((timeout_setting = strsep(&input, ",")) && 1325 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1326 ret = kstrtol(timeout_setting, 0, &timeout); 1327 if (ret) 1328 return ret; 1329 1330 if (timeout == 0) { 1331 index++; 1332 continue; 1333 } else if (timeout < 0) { 1334 timeout = MAX_SCHEDULE_TIMEOUT; 1335 } else { 1336 timeout = msecs_to_jiffies(timeout); 1337 } 1338 1339 switch (index++) { 1340 case 0: 1341 adev->gfx_timeout = timeout; 1342 break; 1343 case 1: 1344 adev->compute_timeout = timeout; 1345 break; 1346 case 2: 1347 adev->sdma_timeout = timeout; 1348 break; 1349 case 3: 1350 adev->video_timeout = timeout; 1351 break; 1352 default: 1353 break; 1354 } 1355 } 1356 /* 1357 * There is only one value specified and 1358 * it should apply to all non-compute jobs. 1359 */ 1360 if (index == 1) 1361 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1362 } 1363 1364 return ret; 1365 } 1366 1367 static bool 1368 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1369 bool in_vblank_irq, int *vpos, int *hpos, 1370 ktime_t *stime, ktime_t *etime, 1371 const struct drm_display_mode *mode) 1372 { 1373 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1374 stime, etime, mode); 1375 } 1376 1377 static struct drm_driver kms_driver = { 1378 .driver_features = 1379 DRIVER_USE_AGP | DRIVER_ATOMIC | 1380 DRIVER_GEM | 1381 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1382 .load = amdgpu_driver_load_kms, 1383 .open = amdgpu_driver_open_kms, 1384 .postclose = amdgpu_driver_postclose_kms, 1385 .lastclose = amdgpu_driver_lastclose_kms, 1386 .unload = amdgpu_driver_unload_kms, 1387 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1388 .enable_vblank = amdgpu_enable_vblank_kms, 1389 .disable_vblank = amdgpu_disable_vblank_kms, 1390 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1391 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1392 .irq_handler = amdgpu_irq_handler, 1393 .ioctls = amdgpu_ioctls_kms, 1394 .gem_free_object_unlocked = amdgpu_gem_object_free, 1395 .gem_open_object = amdgpu_gem_object_open, 1396 .gem_close_object = amdgpu_gem_object_close, 1397 .dumb_create = amdgpu_mode_dumb_create, 1398 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1399 .fops = &amdgpu_driver_kms_fops, 1400 1401 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1402 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1403 .gem_prime_export = amdgpu_gem_prime_export, 1404 .gem_prime_import = amdgpu_gem_prime_import, 1405 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1406 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1407 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1408 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1409 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1410 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1411 1412 .name = DRIVER_NAME, 1413 .desc = DRIVER_DESC, 1414 .date = DRIVER_DATE, 1415 .major = KMS_DRIVER_MAJOR, 1416 .minor = KMS_DRIVER_MINOR, 1417 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1418 }; 1419 1420 static struct pci_driver amdgpu_kms_pci_driver = { 1421 .name = DRIVER_NAME, 1422 .id_table = pciidlist, 1423 .probe = amdgpu_pci_probe, 1424 .remove = amdgpu_pci_remove, 1425 .shutdown = amdgpu_pci_shutdown, 1426 .driver.pm = &amdgpu_pm_ops, 1427 }; 1428 1429 1430 1431 static int __init amdgpu_init(void) 1432 { 1433 int r; 1434 1435 if (vgacon_text_force()) { 1436 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1437 return -EINVAL; 1438 } 1439 1440 r = amdgpu_sync_init(); 1441 if (r) 1442 goto error_sync; 1443 1444 r = amdgpu_fence_slab_init(); 1445 if (r) 1446 goto error_fence; 1447 1448 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1449 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1450 amdgpu_register_atpx_handler(); 1451 1452 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1453 amdgpu_amdkfd_init(); 1454 1455 /* let modprobe override vga console setting */ 1456 return pci_register_driver(&amdgpu_kms_pci_driver); 1457 1458 error_fence: 1459 amdgpu_sync_fini(); 1460 1461 error_sync: 1462 return r; 1463 } 1464 1465 static void __exit amdgpu_exit(void) 1466 { 1467 amdgpu_amdkfd_fini(); 1468 pci_unregister_driver(&amdgpu_kms_pci_driver); 1469 amdgpu_unregister_atpx_handler(); 1470 amdgpu_sync_fini(); 1471 amdgpu_fence_slab_fini(); 1472 } 1473 1474 module_init(amdgpu_init); 1475 module_exit(amdgpu_exit); 1476 1477 MODULE_AUTHOR(DRIVER_AUTHOR); 1478 MODULE_DESCRIPTION(DRIVER_DESC); 1479 MODULE_LICENSE("GPL and additional rights"); 1480