1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/console.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 41 #include "amdgpu.h" 42 #include "amdgpu_irq.h" 43 #include "amdgpu_dma_buf.h" 44 #include "amdgpu_sched.h" 45 46 #include "amdgpu_amdkfd.h" 47 48 #include "amdgpu_ras.h" 49 #include "amdgpu_xgmi.h" 50 51 /* 52 * KMS wrapper. 53 * - 3.0.0 - initial driver 54 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 55 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 56 * at the end of IBs. 57 * - 3.3.0 - Add VM support for UVD on supported hardware. 58 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 59 * - 3.5.0 - Add support for new UVD_NO_OP register. 60 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 61 * - 3.7.0 - Add support for VCE clock list packet 62 * - 3.8.0 - Add support raster config init in the kernel 63 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 64 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 65 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 66 * - 3.12.0 - Add query for double offchip LDS buffers 67 * - 3.13.0 - Add PRT support 68 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 69 * - 3.15.0 - Export more gpu info for gfx9 70 * - 3.16.0 - Add reserved vmid support 71 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 72 * - 3.18.0 - Export gpu always on cu bitmap 73 * - 3.19.0 - Add support for UVD MJPEG decode 74 * - 3.20.0 - Add support for local BOs 75 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 76 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 77 * - 3.23.0 - Add query for VRAM lost counter 78 * - 3.24.0 - Add high priority compute support for gfx9 79 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 80 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 81 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 82 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 83 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 84 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 85 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 86 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 87 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 88 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 89 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 90 * - 3.36.0 - Allow reading more status registers on si/cik 91 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 92 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 93 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 94 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 95 * - 3.41.0 - Add video codec query 96 */ 97 #define KMS_DRIVER_MAJOR 3 98 #define KMS_DRIVER_MINOR 41 99 #define KMS_DRIVER_PATCHLEVEL 0 100 101 int amdgpu_vram_limit; 102 int amdgpu_vis_vram_limit; 103 int amdgpu_gart_size = -1; /* auto */ 104 int amdgpu_gtt_size = -1; /* auto */ 105 int amdgpu_moverate = -1; /* auto */ 106 int amdgpu_benchmarking; 107 int amdgpu_testing; 108 int amdgpu_audio = -1; 109 int amdgpu_disp_priority; 110 int amdgpu_hw_i2c; 111 int amdgpu_pcie_gen2 = -1; 112 int amdgpu_msi = -1; 113 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 114 int amdgpu_dpm = -1; 115 int amdgpu_fw_load_type = -1; 116 int amdgpu_aspm = -1; 117 int amdgpu_runtime_pm = -1; 118 uint amdgpu_ip_block_mask = 0xffffffff; 119 int amdgpu_bapm = -1; 120 int amdgpu_deep_color; 121 int amdgpu_vm_size = -1; 122 int amdgpu_vm_fragment_size = -1; 123 int amdgpu_vm_block_size = -1; 124 int amdgpu_vm_fault_stop; 125 int amdgpu_vm_debug; 126 int amdgpu_vm_update_mode = -1; 127 int amdgpu_exp_hw_support; 128 int amdgpu_dc = -1; 129 int amdgpu_sched_jobs = 32; 130 int amdgpu_sched_hw_submission = 2; 131 uint amdgpu_pcie_gen_cap; 132 uint amdgpu_pcie_lane_cap; 133 uint amdgpu_cg_mask = 0xffffffff; 134 uint amdgpu_pg_mask = 0xffffffff; 135 uint amdgpu_sdma_phase_quantum = 32; 136 char *amdgpu_disable_cu = NULL; 137 char *amdgpu_virtual_display = NULL; 138 139 /* 140 * OverDrive(bit 14) disabled by default 141 * GFX DCS(bit 19) disabled by default 142 */ 143 uint amdgpu_pp_feature_mask = 0xfff7bfff; 144 uint amdgpu_force_long_training; 145 int amdgpu_job_hang_limit; 146 int amdgpu_lbpw = -1; 147 int amdgpu_compute_multipipe = -1; 148 int amdgpu_gpu_recovery = -1; /* auto */ 149 int amdgpu_emu_mode; 150 uint amdgpu_smu_memory_pool_size; 151 int amdgpu_smu_pptable_id = -1; 152 /* 153 * FBC (bit 0) disabled by default 154 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 155 * - With this, for multiple monitors in sync(e.g. with the same model), 156 * mclk switching will be allowed. And the mclk will be not foced to the 157 * highest. That helps saving some idle power. 158 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 159 * PSR (bit 3) disabled by default 160 */ 161 uint amdgpu_dc_feature_mask = 2; 162 uint amdgpu_dc_debug_mask; 163 int amdgpu_async_gfx_ring = 1; 164 int amdgpu_mcbp; 165 int amdgpu_discovery = -1; 166 int amdgpu_mes; 167 int amdgpu_noretry = -1; 168 int amdgpu_force_asic_type = -1; 169 int amdgpu_tmz = -1; /* auto */ 170 uint amdgpu_freesync_vid_mode; 171 int amdgpu_reset_method = -1; /* auto */ 172 int amdgpu_num_kcq = -1; 173 174 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 175 176 struct amdgpu_mgpu_info mgpu_info = { 177 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 178 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 179 mgpu_info.delayed_reset_work, 180 amdgpu_drv_delayed_reset_work_handler, 0), 181 }; 182 int amdgpu_ras_enable = -1; 183 uint amdgpu_ras_mask = 0xffffffff; 184 int amdgpu_bad_page_threshold = -1; 185 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 186 .timeout_fatal_disable = false, 187 .period = 0x23, /* default to max. timeout = 1 << 0x23 cycles */ 188 }; 189 190 /** 191 * DOC: vramlimit (int) 192 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 193 */ 194 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 195 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 196 197 /** 198 * DOC: vis_vramlimit (int) 199 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 200 */ 201 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 202 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 203 204 /** 205 * DOC: gartsize (uint) 206 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 207 */ 208 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 209 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 210 211 /** 212 * DOC: gttsize (int) 213 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 214 * otherwise 3/4 RAM size). 215 */ 216 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 217 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 218 219 /** 220 * DOC: moverate (int) 221 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 222 */ 223 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 224 module_param_named(moverate, amdgpu_moverate, int, 0600); 225 226 /** 227 * DOC: benchmark (int) 228 * Run benchmarks. The default is 0 (Skip benchmarks). 229 */ 230 MODULE_PARM_DESC(benchmark, "Run benchmark"); 231 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 232 233 /** 234 * DOC: test (int) 235 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 236 */ 237 MODULE_PARM_DESC(test, "Run tests"); 238 module_param_named(test, amdgpu_testing, int, 0444); 239 240 /** 241 * DOC: audio (int) 242 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 243 */ 244 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 245 module_param_named(audio, amdgpu_audio, int, 0444); 246 247 /** 248 * DOC: disp_priority (int) 249 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 250 */ 251 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 252 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 253 254 /** 255 * DOC: hw_i2c (int) 256 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 257 */ 258 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 259 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 260 261 /** 262 * DOC: pcie_gen2 (int) 263 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 264 */ 265 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 266 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 267 268 /** 269 * DOC: msi (int) 270 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 271 */ 272 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 273 module_param_named(msi, amdgpu_msi, int, 0444); 274 275 /** 276 * DOC: lockup_timeout (string) 277 * Set GPU scheduler timeout value in ms. 278 * 279 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 280 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 281 * to the default timeout. 282 * 283 * - With one value specified, the setting will apply to all non-compute jobs. 284 * - With multiple values specified, the first one will be for GFX. 285 * The second one is for Compute. The third and fourth ones are 286 * for SDMA and Video. 287 * 288 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 289 * jobs is 10000. And there is no timeout enforced on compute jobs. 290 */ 291 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 292 "for passthrough or sriov, 10000 for all jobs." 293 " 0: keep default value. negative: infinity timeout), " 294 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 295 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 296 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 297 298 /** 299 * DOC: dpm (int) 300 * Override for dynamic power management setting 301 * (0 = disable, 1 = enable) 302 * The default is -1 (auto). 303 */ 304 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 305 module_param_named(dpm, amdgpu_dpm, int, 0444); 306 307 /** 308 * DOC: fw_load_type (int) 309 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 310 */ 311 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 312 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 313 314 /** 315 * DOC: aspm (int) 316 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 317 */ 318 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 319 module_param_named(aspm, amdgpu_aspm, int, 0444); 320 321 /** 322 * DOC: runpm (int) 323 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 324 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 325 */ 326 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 327 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 328 329 /** 330 * DOC: ip_block_mask (uint) 331 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 332 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 333 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 334 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 335 */ 336 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 337 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 338 339 /** 340 * DOC: bapm (int) 341 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 342 * The default -1 (auto, enabled) 343 */ 344 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 345 module_param_named(bapm, amdgpu_bapm, int, 0444); 346 347 /** 348 * DOC: deep_color (int) 349 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 350 */ 351 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 352 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 353 354 /** 355 * DOC: vm_size (int) 356 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 357 */ 358 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 359 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 360 361 /** 362 * DOC: vm_fragment_size (int) 363 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 364 */ 365 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 366 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 367 368 /** 369 * DOC: vm_block_size (int) 370 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 371 */ 372 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 373 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 374 375 /** 376 * DOC: vm_fault_stop (int) 377 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 378 */ 379 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 380 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 381 382 /** 383 * DOC: vm_debug (int) 384 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 385 */ 386 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 387 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 388 389 /** 390 * DOC: vm_update_mode (int) 391 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 392 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 393 */ 394 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 395 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 396 397 /** 398 * DOC: exp_hw_support (int) 399 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 400 */ 401 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 402 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 403 404 /** 405 * DOC: dc (int) 406 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 407 */ 408 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 409 module_param_named(dc, amdgpu_dc, int, 0444); 410 411 /** 412 * DOC: sched_jobs (int) 413 * Override the max number of jobs supported in the sw queue. The default is 32. 414 */ 415 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 416 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 417 418 /** 419 * DOC: sched_hw_submission (int) 420 * Override the max number of HW submissions. The default is 2. 421 */ 422 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 423 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 424 425 /** 426 * DOC: ppfeaturemask (hexint) 427 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 428 * The default is the current set of stable power features. 429 */ 430 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 431 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 432 433 /** 434 * DOC: forcelongtraining (uint) 435 * Force long memory training in resume. 436 * The default is zero, indicates short training in resume. 437 */ 438 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 439 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 440 441 /** 442 * DOC: pcie_gen_cap (uint) 443 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 444 * The default is 0 (automatic for each asic). 445 */ 446 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 447 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 448 449 /** 450 * DOC: pcie_lane_cap (uint) 451 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 452 * The default is 0 (automatic for each asic). 453 */ 454 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 455 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 456 457 /** 458 * DOC: cg_mask (uint) 459 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 460 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 461 */ 462 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 463 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 464 465 /** 466 * DOC: pg_mask (uint) 467 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 468 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 469 */ 470 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 471 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 472 473 /** 474 * DOC: sdma_phase_quantum (uint) 475 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 476 */ 477 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 478 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 479 480 /** 481 * DOC: disable_cu (charp) 482 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 483 */ 484 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 485 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 486 487 /** 488 * DOC: virtual_display (charp) 489 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 490 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 491 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 492 * device at 26:00.0. The default is NULL. 493 */ 494 MODULE_PARM_DESC(virtual_display, 495 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 496 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 497 498 /** 499 * DOC: job_hang_limit (int) 500 * Set how much time allow a job hang and not drop it. The default is 0. 501 */ 502 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 503 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 504 505 /** 506 * DOC: lbpw (int) 507 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 508 */ 509 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 510 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 511 512 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 513 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 514 515 /** 516 * DOC: gpu_recovery (int) 517 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 518 */ 519 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 520 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 521 522 /** 523 * DOC: emu_mode (int) 524 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 525 */ 526 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 527 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 528 529 /** 530 * DOC: ras_enable (int) 531 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 532 */ 533 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 534 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 535 536 /** 537 * DOC: ras_mask (uint) 538 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 539 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 540 */ 541 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 542 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 543 544 /** 545 * DOC: timeout_fatal_disable (bool) 546 * Disable Watchdog timeout fatal error event 547 */ 548 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 549 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 550 551 /** 552 * DOC: timeout_period (uint) 553 * Modify the watchdog timeout max_cycles as (1 << period) 554 */ 555 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (1 to 0x23(default), timeout maxCycles = (1 << period)"); 556 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 557 558 /** 559 * DOC: si_support (int) 560 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 561 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 562 * otherwise using amdgpu driver. 563 */ 564 #ifdef CONFIG_DRM_AMDGPU_SI 565 566 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 567 int amdgpu_si_support = 0; 568 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 569 #else 570 int amdgpu_si_support = 1; 571 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 572 #endif 573 574 module_param_named(si_support, amdgpu_si_support, int, 0444); 575 #endif 576 577 /** 578 * DOC: cik_support (int) 579 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 581 * otherwise using amdgpu driver. 582 */ 583 #ifdef CONFIG_DRM_AMDGPU_CIK 584 585 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 586 int amdgpu_cik_support = 0; 587 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 588 #else 589 int amdgpu_cik_support = 1; 590 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 591 #endif 592 593 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 594 #endif 595 596 /** 597 * DOC: smu_memory_pool_size (uint) 598 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 599 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 600 */ 601 MODULE_PARM_DESC(smu_memory_pool_size, 602 "reserve gtt for smu debug usage, 0 = disable," 603 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 604 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 605 606 /** 607 * DOC: async_gfx_ring (int) 608 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 609 */ 610 MODULE_PARM_DESC(async_gfx_ring, 611 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 612 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 613 614 /** 615 * DOC: mcbp (int) 616 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 617 */ 618 MODULE_PARM_DESC(mcbp, 619 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 620 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 621 622 /** 623 * DOC: discovery (int) 624 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 625 * (-1 = auto (default), 0 = disabled, 1 = enabled) 626 */ 627 MODULE_PARM_DESC(discovery, 628 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 629 module_param_named(discovery, amdgpu_discovery, int, 0444); 630 631 /** 632 * DOC: mes (int) 633 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 634 * (0 = disabled (default), 1 = enabled) 635 */ 636 MODULE_PARM_DESC(mes, 637 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 638 module_param_named(mes, amdgpu_mes, int, 0444); 639 640 /** 641 * DOC: noretry (int) 642 * Disable retry faults in the GPU memory controller. 643 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 644 */ 645 MODULE_PARM_DESC(noretry, 646 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 647 module_param_named(noretry, amdgpu_noretry, int, 0644); 648 649 /** 650 * DOC: force_asic_type (int) 651 * A non negative value used to specify the asic type for all supported GPUs. 652 */ 653 MODULE_PARM_DESC(force_asic_type, 654 "A non negative value used to specify the asic type for all supported GPUs"); 655 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 656 657 658 659 #ifdef CONFIG_HSA_AMD 660 /** 661 * DOC: sched_policy (int) 662 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 663 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 664 * assigns queues to HQDs. 665 */ 666 int sched_policy = KFD_SCHED_POLICY_HWS; 667 module_param(sched_policy, int, 0444); 668 MODULE_PARM_DESC(sched_policy, 669 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 670 671 /** 672 * DOC: hws_max_conc_proc (int) 673 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 674 * number of VMIDs assigned to the HWS, which is also the default. 675 */ 676 int hws_max_conc_proc = 8; 677 module_param(hws_max_conc_proc, int, 0444); 678 MODULE_PARM_DESC(hws_max_conc_proc, 679 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 680 681 /** 682 * DOC: cwsr_enable (int) 683 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 684 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 685 * disables it. 686 */ 687 int cwsr_enable = 1; 688 module_param(cwsr_enable, int, 0444); 689 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 690 691 /** 692 * DOC: max_num_of_queues_per_device (int) 693 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 694 * is 4096. 695 */ 696 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 697 module_param(max_num_of_queues_per_device, int, 0444); 698 MODULE_PARM_DESC(max_num_of_queues_per_device, 699 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 700 701 /** 702 * DOC: send_sigterm (int) 703 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 704 * but just print errors on dmesg. Setting 1 enables sending sigterm. 705 */ 706 int send_sigterm; 707 module_param(send_sigterm, int, 0444); 708 MODULE_PARM_DESC(send_sigterm, 709 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 710 711 /** 712 * DOC: debug_largebar (int) 713 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 714 * system. This limits the VRAM size reported to ROCm applications to the visible 715 * size, usually 256MB. 716 * Default value is 0, diabled. 717 */ 718 int debug_largebar; 719 module_param(debug_largebar, int, 0444); 720 MODULE_PARM_DESC(debug_largebar, 721 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 722 723 /** 724 * DOC: ignore_crat (int) 725 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 726 * table to get information about AMD APUs. This option can serve as a workaround on 727 * systems with a broken CRAT table. 728 * 729 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 730 * whehter use CRAT) 731 */ 732 int ignore_crat; 733 module_param(ignore_crat, int, 0444); 734 MODULE_PARM_DESC(ignore_crat, 735 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 736 737 /** 738 * DOC: halt_if_hws_hang (int) 739 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 740 * Setting 1 enables halt on hang. 741 */ 742 int halt_if_hws_hang; 743 module_param(halt_if_hws_hang, int, 0644); 744 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 745 746 /** 747 * DOC: hws_gws_support(bool) 748 * Assume that HWS supports GWS barriers regardless of what firmware version 749 * check says. Default value: false (rely on MEC2 firmware version check). 750 */ 751 bool hws_gws_support; 752 module_param(hws_gws_support, bool, 0444); 753 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 754 755 /** 756 * DOC: queue_preemption_timeout_ms (int) 757 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 758 */ 759 int queue_preemption_timeout_ms = 9000; 760 module_param(queue_preemption_timeout_ms, int, 0644); 761 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 762 763 /** 764 * DOC: debug_evictions(bool) 765 * Enable extra debug messages to help determine the cause of evictions 766 */ 767 bool debug_evictions; 768 module_param(debug_evictions, bool, 0644); 769 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 770 771 /** 772 * DOC: no_system_mem_limit(bool) 773 * Disable system memory limit, to support multiple process shared memory 774 */ 775 bool no_system_mem_limit; 776 module_param(no_system_mem_limit, bool, 0644); 777 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 778 779 /** 780 * DOC: no_queue_eviction_on_vm_fault (int) 781 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 782 */ 783 int amdgpu_no_queue_eviction_on_vm_fault = 0; 784 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 785 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 786 #endif 787 788 /** 789 * DOC: dcfeaturemask (uint) 790 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 791 * The default is the current set of stable display features. 792 */ 793 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 794 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 795 796 /** 797 * DOC: dcdebugmask (uint) 798 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 799 */ 800 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 801 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 802 803 /** 804 * DOC: abmlevel (uint) 805 * Override the default ABM (Adaptive Backlight Management) level used for DC 806 * enabled hardware. Requires DMCU to be supported and loaded. 807 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 808 * default. Values 1-4 control the maximum allowable brightness reduction via 809 * the ABM algorithm, with 1 being the least reduction and 4 being the most 810 * reduction. 811 * 812 * Defaults to 0, or disabled. Userspace can still override this level later 813 * after boot. 814 */ 815 uint amdgpu_dm_abm_level; 816 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 817 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 818 819 int amdgpu_backlight = -1; 820 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 821 module_param_named(backlight, amdgpu_backlight, bint, 0444); 822 823 /** 824 * DOC: tmz (int) 825 * Trusted Memory Zone (TMZ) is a method to protect data being written 826 * to or read from memory. 827 * 828 * The default value: 0 (off). TODO: change to auto till it is completed. 829 */ 830 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 831 module_param_named(tmz, amdgpu_tmz, int, 0444); 832 833 /** 834 * DOC: freesync_video (uint) 835 * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience 836 * when setting a freesync supported mode for which full modeset is not needed. 837 * The default value: 0 (off). 838 */ 839 MODULE_PARM_DESC( 840 freesync_video, 841 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 842 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 843 844 /** 845 * DOC: reset_method (int) 846 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 847 */ 848 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 849 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 850 851 /** 852 * DOC: bad_page_threshold (int) 853 * Bad page threshold is to specify the threshold value of faulty pages 854 * detected by RAS ECC, that may result in GPU entering bad status if total 855 * faulty pages by ECC exceed threshold value and leave it for user's further 856 * check. 857 */ 858 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 859 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 860 861 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 862 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 863 864 /** 865 * DOC: smu_pptable_id (int) 866 * Used to override pptable id. id = 0 use VBIOS pptable. 867 * id > 0 use the soft pptable with specicfied id. 868 */ 869 MODULE_PARM_DESC(smu_pptable_id, 870 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 871 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 872 873 static const struct pci_device_id pciidlist[] = { 874 #ifdef CONFIG_DRM_AMDGPU_SI 875 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 876 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 877 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 878 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 879 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 880 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 881 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 882 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 883 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 884 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 885 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 886 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 887 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 888 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 889 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 890 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 891 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 892 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 893 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 894 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 895 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 896 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 897 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 898 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 899 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 900 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 901 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 902 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 903 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 904 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 905 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 906 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 907 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 908 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 909 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 910 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 911 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 912 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 913 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 914 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 915 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 916 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 917 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 918 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 919 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 920 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 921 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 922 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 923 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 924 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 925 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 926 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 927 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 928 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 929 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 930 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 931 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 932 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 933 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 934 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 935 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 936 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 937 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 938 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 939 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 940 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 941 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 942 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 943 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 944 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 945 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 946 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 947 #endif 948 #ifdef CONFIG_DRM_AMDGPU_CIK 949 /* Kaveri */ 950 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 951 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 952 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 953 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 954 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 955 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 956 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 957 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 958 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 959 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 960 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 961 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 962 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 963 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 964 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 965 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 966 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 967 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 968 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 969 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 970 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 971 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 972 /* Bonaire */ 973 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 974 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 975 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 976 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 977 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 978 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 979 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 980 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 981 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 982 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 983 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 984 /* Hawaii */ 985 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 986 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 987 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 988 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 989 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 990 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 991 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 992 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 993 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 994 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 995 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 996 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 997 /* Kabini */ 998 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 999 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1000 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1001 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1002 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1003 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1004 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1005 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1006 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1007 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1008 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1009 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1010 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1011 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1012 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1013 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1014 /* mullins */ 1015 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1016 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1017 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1018 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1019 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1020 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1021 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1022 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1023 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1024 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1025 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1026 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1027 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1028 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1029 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1030 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1031 #endif 1032 /* topaz */ 1033 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1034 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1035 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1036 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1037 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1038 /* tonga */ 1039 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1040 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1041 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1042 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1043 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1044 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1045 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1046 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1047 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1048 /* fiji */ 1049 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1050 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1051 /* carrizo */ 1052 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1053 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1054 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1055 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1056 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1057 /* stoney */ 1058 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1059 /* Polaris11 */ 1060 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1061 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1062 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1063 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1064 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1065 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1066 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1067 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1068 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1069 /* Polaris10 */ 1070 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1071 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1072 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1073 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1074 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1075 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1076 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1077 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1078 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1079 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1080 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1081 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1082 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1083 /* Polaris12 */ 1084 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1085 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1086 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1087 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1088 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1089 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1090 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1091 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1092 /* VEGAM */ 1093 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1094 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1095 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1096 /* Vega 10 */ 1097 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1098 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1099 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1100 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1101 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1102 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1103 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1104 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1105 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1106 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1107 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1108 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1109 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1110 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1111 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1112 /* Vega 12 */ 1113 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1114 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1115 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1116 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1117 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1118 /* Vega 20 */ 1119 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1120 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1121 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1122 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1123 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1124 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1125 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1126 /* Raven */ 1127 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1128 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1129 /* Arcturus */ 1130 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1131 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1132 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1133 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1134 /* Navi10 */ 1135 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1136 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1137 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1138 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1139 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1140 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1141 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1142 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1143 /* Navi14 */ 1144 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1145 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1146 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1147 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1148 1149 /* Renoir */ 1150 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1151 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1152 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1153 1154 /* Navi12 */ 1155 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1156 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1157 1158 /* Sienna_Cichlid */ 1159 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1160 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1161 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1162 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1163 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1164 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1165 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1166 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1167 1168 /* Van Gogh */ 1169 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1170 1171 /* Navy_Flounder */ 1172 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1173 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1174 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1175 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1176 1177 /* DIMGREY_CAVEFISH */ 1178 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1179 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1180 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1181 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1182 1183 /* Aldebaran */ 1184 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1185 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1186 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1187 1188 {0, 0, 0} 1189 }; 1190 1191 MODULE_DEVICE_TABLE(pci, pciidlist); 1192 1193 static const struct drm_driver amdgpu_kms_driver; 1194 1195 static int amdgpu_pci_probe(struct pci_dev *pdev, 1196 const struct pci_device_id *ent) 1197 { 1198 struct drm_device *ddev; 1199 struct amdgpu_device *adev; 1200 unsigned long flags = ent->driver_data; 1201 int ret, retry = 0; 1202 bool supports_atomic = false; 1203 1204 if (!amdgpu_virtual_display && 1205 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1206 supports_atomic = true; 1207 1208 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1209 DRM_INFO("This hardware requires experimental hardware support.\n" 1210 "See modparam exp_hw_support\n"); 1211 return -ENODEV; 1212 } 1213 1214 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1215 * however, SME requires an indirect IOMMU mapping because the encryption 1216 * bit is beyond the DMA mask of the chip. 1217 */ 1218 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1219 dev_info(&pdev->dev, 1220 "SME is not compatible with RAVEN\n"); 1221 return -ENOTSUPP; 1222 } 1223 1224 #ifdef CONFIG_DRM_AMDGPU_SI 1225 if (!amdgpu_si_support) { 1226 switch (flags & AMD_ASIC_MASK) { 1227 case CHIP_TAHITI: 1228 case CHIP_PITCAIRN: 1229 case CHIP_VERDE: 1230 case CHIP_OLAND: 1231 case CHIP_HAINAN: 1232 dev_info(&pdev->dev, 1233 "SI support provided by radeon.\n"); 1234 dev_info(&pdev->dev, 1235 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1236 ); 1237 return -ENODEV; 1238 } 1239 } 1240 #endif 1241 #ifdef CONFIG_DRM_AMDGPU_CIK 1242 if (!amdgpu_cik_support) { 1243 switch (flags & AMD_ASIC_MASK) { 1244 case CHIP_KAVERI: 1245 case CHIP_BONAIRE: 1246 case CHIP_HAWAII: 1247 case CHIP_KABINI: 1248 case CHIP_MULLINS: 1249 dev_info(&pdev->dev, 1250 "CIK support provided by radeon.\n"); 1251 dev_info(&pdev->dev, 1252 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1253 ); 1254 return -ENODEV; 1255 } 1256 } 1257 #endif 1258 1259 /* Get rid of things like offb */ 1260 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1261 if (ret) 1262 return ret; 1263 1264 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1265 if (IS_ERR(adev)) 1266 return PTR_ERR(adev); 1267 1268 adev->dev = &pdev->dev; 1269 adev->pdev = pdev; 1270 ddev = adev_to_drm(adev); 1271 1272 if (!supports_atomic) 1273 ddev->driver_features &= ~DRIVER_ATOMIC; 1274 1275 ret = pci_enable_device(pdev); 1276 if (ret) 1277 return ret; 1278 1279 pci_set_drvdata(pdev, ddev); 1280 1281 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1282 if (ret) 1283 goto err_pci; 1284 1285 retry_init: 1286 ret = drm_dev_register(ddev, ent->driver_data); 1287 if (ret == -EAGAIN && ++retry <= 3) { 1288 DRM_INFO("retry init %d\n", retry); 1289 /* Don't request EX mode too frequently which is attacking */ 1290 msleep(5000); 1291 goto retry_init; 1292 } else if (ret) { 1293 goto err_pci; 1294 } 1295 1296 ret = amdgpu_debugfs_init(adev); 1297 if (ret) 1298 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1299 1300 return 0; 1301 1302 err_pci: 1303 pci_disable_device(pdev); 1304 return ret; 1305 } 1306 1307 static void 1308 amdgpu_pci_remove(struct pci_dev *pdev) 1309 { 1310 struct drm_device *dev = pci_get_drvdata(pdev); 1311 1312 #ifdef MODULE 1313 if (THIS_MODULE->state != MODULE_STATE_GOING) 1314 #endif 1315 DRM_ERROR("Hotplug removal is not supported\n"); 1316 drm_dev_unplug(dev); 1317 amdgpu_driver_unload_kms(dev); 1318 pci_disable_device(pdev); 1319 pci_set_drvdata(pdev, NULL); 1320 } 1321 1322 static void 1323 amdgpu_pci_shutdown(struct pci_dev *pdev) 1324 { 1325 struct drm_device *dev = pci_get_drvdata(pdev); 1326 struct amdgpu_device *adev = drm_to_adev(dev); 1327 1328 if (amdgpu_ras_intr_triggered()) 1329 return; 1330 1331 /* if we are running in a VM, make sure the device 1332 * torn down properly on reboot/shutdown. 1333 * unfortunately we can't detect certain 1334 * hypervisors so just do this all the time. 1335 */ 1336 if (!amdgpu_passthrough(adev)) 1337 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1338 amdgpu_device_ip_suspend(adev); 1339 adev->mp1_state = PP_MP1_STATE_NONE; 1340 } 1341 1342 /** 1343 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 1344 * 1345 * @work: work_struct. 1346 */ 1347 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 1348 { 1349 struct list_head device_list; 1350 struct amdgpu_device *adev; 1351 int i, r; 1352 bool need_full_reset = true; 1353 1354 mutex_lock(&mgpu_info.mutex); 1355 if (mgpu_info.pending_reset == true) { 1356 mutex_unlock(&mgpu_info.mutex); 1357 return; 1358 } 1359 mgpu_info.pending_reset = true; 1360 mutex_unlock(&mgpu_info.mutex); 1361 1362 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1363 adev = mgpu_info.gpu_ins[i].adev; 1364 r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset); 1365 if (r) { 1366 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 1367 r, adev_to_drm(adev)->unique); 1368 } 1369 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 1370 r = -EALREADY; 1371 } 1372 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1373 adev = mgpu_info.gpu_ins[i].adev; 1374 flush_work(&adev->xgmi_reset_work); 1375 adev->gmc.xgmi.pending_reset = false; 1376 } 1377 1378 /* reset function will rebuild the xgmi hive info , clear it now */ 1379 for (i = 0; i < mgpu_info.num_dgpu; i++) 1380 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 1381 1382 INIT_LIST_HEAD(&device_list); 1383 1384 for (i = 0; i < mgpu_info.num_dgpu; i++) 1385 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 1386 1387 /* unregister the GPU first, reset function will add them back */ 1388 list_for_each_entry(adev, &device_list, reset_list) 1389 amdgpu_unregister_gpu_instance(adev); 1390 1391 r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true); 1392 if (r) { 1393 DRM_ERROR("reinit gpus failure"); 1394 return; 1395 } 1396 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1397 adev = mgpu_info.gpu_ins[i].adev; 1398 if (!adev->kfd.init_complete) 1399 amdgpu_amdkfd_device_init(adev); 1400 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1401 } 1402 return; 1403 } 1404 1405 static int amdgpu_pmops_prepare(struct device *dev) 1406 { 1407 struct drm_device *drm_dev = dev_get_drvdata(dev); 1408 1409 /* Return a positive number here so 1410 * DPM_FLAG_SMART_SUSPEND works properly 1411 */ 1412 if (amdgpu_device_supports_boco(drm_dev)) 1413 return pm_runtime_suspended(dev) && 1414 pm_suspend_via_firmware(); 1415 1416 return 0; 1417 } 1418 1419 static void amdgpu_pmops_complete(struct device *dev) 1420 { 1421 /* nothing to do */ 1422 } 1423 1424 static int amdgpu_pmops_suspend(struct device *dev) 1425 { 1426 struct drm_device *drm_dev = dev_get_drvdata(dev); 1427 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1428 int r; 1429 1430 if (amdgpu_acpi_is_s0ix_supported(adev)) 1431 adev->in_s0ix = true; 1432 adev->in_s3 = true; 1433 r = amdgpu_device_suspend(drm_dev, true); 1434 adev->in_s3 = false; 1435 1436 return r; 1437 } 1438 1439 static int amdgpu_pmops_resume(struct device *dev) 1440 { 1441 struct drm_device *drm_dev = dev_get_drvdata(dev); 1442 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1443 int r; 1444 1445 r = amdgpu_device_resume(drm_dev, true); 1446 if (amdgpu_acpi_is_s0ix_supported(adev)) 1447 adev->in_s0ix = false; 1448 return r; 1449 } 1450 1451 static int amdgpu_pmops_freeze(struct device *dev) 1452 { 1453 struct drm_device *drm_dev = dev_get_drvdata(dev); 1454 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1455 int r; 1456 1457 adev->in_s4 = true; 1458 r = amdgpu_device_suspend(drm_dev, true); 1459 adev->in_s4 = false; 1460 if (r) 1461 return r; 1462 return amdgpu_asic_reset(adev); 1463 } 1464 1465 static int amdgpu_pmops_thaw(struct device *dev) 1466 { 1467 struct drm_device *drm_dev = dev_get_drvdata(dev); 1468 1469 return amdgpu_device_resume(drm_dev, true); 1470 } 1471 1472 static int amdgpu_pmops_poweroff(struct device *dev) 1473 { 1474 struct drm_device *drm_dev = dev_get_drvdata(dev); 1475 1476 return amdgpu_device_suspend(drm_dev, true); 1477 } 1478 1479 static int amdgpu_pmops_restore(struct device *dev) 1480 { 1481 struct drm_device *drm_dev = dev_get_drvdata(dev); 1482 1483 return amdgpu_device_resume(drm_dev, true); 1484 } 1485 1486 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1487 { 1488 struct pci_dev *pdev = to_pci_dev(dev); 1489 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1490 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1491 int ret, i; 1492 1493 if (!adev->runpm) { 1494 pm_runtime_forbid(dev); 1495 return -EBUSY; 1496 } 1497 1498 /* wait for all rings to drain before suspending */ 1499 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1500 struct amdgpu_ring *ring = adev->rings[i]; 1501 if (ring && ring->sched.ready) { 1502 ret = amdgpu_fence_wait_empty(ring); 1503 if (ret) 1504 return -EBUSY; 1505 } 1506 } 1507 1508 adev->in_runpm = true; 1509 if (amdgpu_device_supports_px(drm_dev)) 1510 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1511 1512 ret = amdgpu_device_suspend(drm_dev, false); 1513 if (ret) { 1514 adev->in_runpm = false; 1515 return ret; 1516 } 1517 1518 if (amdgpu_device_supports_px(drm_dev)) { 1519 /* Only need to handle PCI state in the driver for ATPX 1520 * PCI core handles it for _PR3. 1521 */ 1522 amdgpu_device_cache_pci_state(pdev); 1523 pci_disable_device(pdev); 1524 pci_ignore_hotplug(pdev); 1525 pci_set_power_state(pdev, PCI_D3cold); 1526 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1527 } else if (amdgpu_device_supports_baco(drm_dev)) { 1528 amdgpu_device_baco_enter(drm_dev); 1529 } 1530 1531 return 0; 1532 } 1533 1534 static int amdgpu_pmops_runtime_resume(struct device *dev) 1535 { 1536 struct pci_dev *pdev = to_pci_dev(dev); 1537 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1538 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1539 int ret; 1540 1541 if (!adev->runpm) 1542 return -EINVAL; 1543 1544 if (amdgpu_device_supports_px(drm_dev)) { 1545 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1546 1547 /* Only need to handle PCI state in the driver for ATPX 1548 * PCI core handles it for _PR3. 1549 */ 1550 pci_set_power_state(pdev, PCI_D0); 1551 amdgpu_device_load_pci_state(pdev); 1552 ret = pci_enable_device(pdev); 1553 if (ret) 1554 return ret; 1555 pci_set_master(pdev); 1556 } else if (amdgpu_device_supports_boco(drm_dev)) { 1557 /* Only need to handle PCI state in the driver for ATPX 1558 * PCI core handles it for _PR3. 1559 */ 1560 pci_set_master(pdev); 1561 } else if (amdgpu_device_supports_baco(drm_dev)) { 1562 amdgpu_device_baco_exit(drm_dev); 1563 } 1564 ret = amdgpu_device_resume(drm_dev, false); 1565 if (amdgpu_device_supports_px(drm_dev)) 1566 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1567 adev->in_runpm = false; 1568 return 0; 1569 } 1570 1571 static int amdgpu_pmops_runtime_idle(struct device *dev) 1572 { 1573 struct drm_device *drm_dev = dev_get_drvdata(dev); 1574 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1575 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1576 int ret = 1; 1577 1578 if (!adev->runpm) { 1579 pm_runtime_forbid(dev); 1580 return -EBUSY; 1581 } 1582 1583 if (amdgpu_device_has_dc_support(adev)) { 1584 struct drm_crtc *crtc; 1585 1586 drm_modeset_lock_all(drm_dev); 1587 1588 drm_for_each_crtc(crtc, drm_dev) { 1589 if (crtc->state->active) { 1590 ret = -EBUSY; 1591 break; 1592 } 1593 } 1594 1595 drm_modeset_unlock_all(drm_dev); 1596 1597 } else { 1598 struct drm_connector *list_connector; 1599 struct drm_connector_list_iter iter; 1600 1601 mutex_lock(&drm_dev->mode_config.mutex); 1602 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1603 1604 drm_connector_list_iter_begin(drm_dev, &iter); 1605 drm_for_each_connector_iter(list_connector, &iter) { 1606 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1607 ret = -EBUSY; 1608 break; 1609 } 1610 } 1611 1612 drm_connector_list_iter_end(&iter); 1613 1614 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1615 mutex_unlock(&drm_dev->mode_config.mutex); 1616 } 1617 1618 if (ret == -EBUSY) 1619 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1620 1621 pm_runtime_mark_last_busy(dev); 1622 pm_runtime_autosuspend(dev); 1623 return ret; 1624 } 1625 1626 long amdgpu_drm_ioctl(struct file *filp, 1627 unsigned int cmd, unsigned long arg) 1628 { 1629 struct drm_file *file_priv = filp->private_data; 1630 struct drm_device *dev; 1631 long ret; 1632 dev = file_priv->minor->dev; 1633 ret = pm_runtime_get_sync(dev->dev); 1634 if (ret < 0) 1635 goto out; 1636 1637 ret = drm_ioctl(filp, cmd, arg); 1638 1639 pm_runtime_mark_last_busy(dev->dev); 1640 out: 1641 pm_runtime_put_autosuspend(dev->dev); 1642 return ret; 1643 } 1644 1645 static const struct dev_pm_ops amdgpu_pm_ops = { 1646 .prepare = amdgpu_pmops_prepare, 1647 .complete = amdgpu_pmops_complete, 1648 .suspend = amdgpu_pmops_suspend, 1649 .resume = amdgpu_pmops_resume, 1650 .freeze = amdgpu_pmops_freeze, 1651 .thaw = amdgpu_pmops_thaw, 1652 .poweroff = amdgpu_pmops_poweroff, 1653 .restore = amdgpu_pmops_restore, 1654 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1655 .runtime_resume = amdgpu_pmops_runtime_resume, 1656 .runtime_idle = amdgpu_pmops_runtime_idle, 1657 }; 1658 1659 static int amdgpu_flush(struct file *f, fl_owner_t id) 1660 { 1661 struct drm_file *file_priv = f->private_data; 1662 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1663 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1664 1665 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1666 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1667 1668 return timeout >= 0 ? 0 : timeout; 1669 } 1670 1671 static const struct file_operations amdgpu_driver_kms_fops = { 1672 .owner = THIS_MODULE, 1673 .open = drm_open, 1674 .flush = amdgpu_flush, 1675 .release = drm_release, 1676 .unlocked_ioctl = amdgpu_drm_ioctl, 1677 .mmap = amdgpu_mmap, 1678 .poll = drm_poll, 1679 .read = drm_read, 1680 #ifdef CONFIG_COMPAT 1681 .compat_ioctl = amdgpu_kms_compat_ioctl, 1682 #endif 1683 }; 1684 1685 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1686 { 1687 struct drm_file *file; 1688 1689 if (!filp) 1690 return -EINVAL; 1691 1692 if (filp->f_op != &amdgpu_driver_kms_fops) { 1693 return -EINVAL; 1694 } 1695 1696 file = filp->private_data; 1697 *fpriv = file->driver_priv; 1698 return 0; 1699 } 1700 1701 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1702 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1703 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1704 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1705 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1706 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1707 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1708 /* KMS */ 1709 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1710 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1711 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1712 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1713 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1714 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1715 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1716 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1717 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1718 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1719 }; 1720 1721 static const struct drm_driver amdgpu_kms_driver = { 1722 .driver_features = 1723 DRIVER_ATOMIC | 1724 DRIVER_GEM | 1725 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1726 DRIVER_SYNCOBJ_TIMELINE, 1727 .open = amdgpu_driver_open_kms, 1728 .postclose = amdgpu_driver_postclose_kms, 1729 .lastclose = amdgpu_driver_lastclose_kms, 1730 .irq_handler = amdgpu_irq_handler, 1731 .ioctls = amdgpu_ioctls_kms, 1732 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1733 .dumb_create = amdgpu_mode_dumb_create, 1734 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1735 .fops = &amdgpu_driver_kms_fops, 1736 1737 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1738 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1739 .gem_prime_import = amdgpu_gem_prime_import, 1740 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1741 1742 .name = DRIVER_NAME, 1743 .desc = DRIVER_DESC, 1744 .date = DRIVER_DATE, 1745 .major = KMS_DRIVER_MAJOR, 1746 .minor = KMS_DRIVER_MINOR, 1747 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1748 }; 1749 1750 static struct pci_error_handlers amdgpu_pci_err_handler = { 1751 .error_detected = amdgpu_pci_error_detected, 1752 .mmio_enabled = amdgpu_pci_mmio_enabled, 1753 .slot_reset = amdgpu_pci_slot_reset, 1754 .resume = amdgpu_pci_resume, 1755 }; 1756 1757 static struct pci_driver amdgpu_kms_pci_driver = { 1758 .name = DRIVER_NAME, 1759 .id_table = pciidlist, 1760 .probe = amdgpu_pci_probe, 1761 .remove = amdgpu_pci_remove, 1762 .shutdown = amdgpu_pci_shutdown, 1763 .driver.pm = &amdgpu_pm_ops, 1764 .err_handler = &amdgpu_pci_err_handler, 1765 }; 1766 1767 static int __init amdgpu_init(void) 1768 { 1769 int r; 1770 1771 if (vgacon_text_force()) { 1772 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1773 return -EINVAL; 1774 } 1775 1776 r = amdgpu_sync_init(); 1777 if (r) 1778 goto error_sync; 1779 1780 r = amdgpu_fence_slab_init(); 1781 if (r) 1782 goto error_fence; 1783 1784 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1785 amdgpu_register_atpx_handler(); 1786 1787 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1788 amdgpu_amdkfd_init(); 1789 1790 /* let modprobe override vga console setting */ 1791 return pci_register_driver(&amdgpu_kms_pci_driver); 1792 1793 error_fence: 1794 amdgpu_sync_fini(); 1795 1796 error_sync: 1797 return r; 1798 } 1799 1800 static void __exit amdgpu_exit(void) 1801 { 1802 amdgpu_amdkfd_fini(); 1803 pci_unregister_driver(&amdgpu_kms_pci_driver); 1804 amdgpu_unregister_atpx_handler(); 1805 amdgpu_sync_fini(); 1806 amdgpu_fence_slab_fini(); 1807 mmu_notifier_synchronize(); 1808 } 1809 1810 module_init(amdgpu_init); 1811 module_exit(amdgpu_exit); 1812 1813 MODULE_AUTHOR(DRIVER_AUTHOR); 1814 MODULE_DESCRIPTION(DRIVER_DESC); 1815 MODULE_LICENSE("GPL and additional rights"); 1816