1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/fb.h> 42 #include <linux/dynamic_debug.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 #include "amdgpu_dma_buf.h" 47 #include "amdgpu_sched.h" 48 #include "amdgpu_fdinfo.h" 49 #include "amdgpu_amdkfd.h" 50 51 #include "amdgpu_ras.h" 52 #include "amdgpu_xgmi.h" 53 #include "amdgpu_reset.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * 3.49.0 - Add gang submit into CS IOCTL 108 */ 109 #define KMS_DRIVER_MAJOR 3 110 #define KMS_DRIVER_MINOR 49 111 #define KMS_DRIVER_PATCHLEVEL 0 112 113 int amdgpu_vram_limit; 114 int amdgpu_vis_vram_limit; 115 int amdgpu_gart_size = -1; /* auto */ 116 int amdgpu_gtt_size = -1; /* auto */ 117 int amdgpu_moverate = -1; /* auto */ 118 int amdgpu_audio = -1; 119 int amdgpu_disp_priority; 120 int amdgpu_hw_i2c; 121 int amdgpu_pcie_gen2 = -1; 122 int amdgpu_msi = -1; 123 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 124 int amdgpu_dpm = -1; 125 int amdgpu_fw_load_type = -1; 126 int amdgpu_aspm = -1; 127 int amdgpu_runtime_pm = -1; 128 uint amdgpu_ip_block_mask = 0xffffffff; 129 int amdgpu_bapm = -1; 130 int amdgpu_deep_color; 131 int amdgpu_vm_size = -1; 132 int amdgpu_vm_fragment_size = -1; 133 int amdgpu_vm_block_size = -1; 134 int amdgpu_vm_fault_stop; 135 int amdgpu_vm_debug; 136 int amdgpu_vm_update_mode = -1; 137 int amdgpu_exp_hw_support; 138 int amdgpu_dc = -1; 139 int amdgpu_sched_jobs = 32; 140 int amdgpu_sched_hw_submission = 2; 141 uint amdgpu_pcie_gen_cap; 142 uint amdgpu_pcie_lane_cap; 143 u64 amdgpu_cg_mask = 0xffffffffffffffff; 144 uint amdgpu_pg_mask = 0xffffffff; 145 uint amdgpu_sdma_phase_quantum = 32; 146 char *amdgpu_disable_cu = NULL; 147 char *amdgpu_virtual_display = NULL; 148 149 /* 150 * OverDrive(bit 14) disabled by default 151 * GFX DCS(bit 19) disabled by default 152 */ 153 uint amdgpu_pp_feature_mask = 0xfff7bfff; 154 uint amdgpu_force_long_training; 155 int amdgpu_job_hang_limit; 156 int amdgpu_lbpw = -1; 157 int amdgpu_compute_multipipe = -1; 158 int amdgpu_gpu_recovery = -1; /* auto */ 159 int amdgpu_emu_mode; 160 uint amdgpu_smu_memory_pool_size; 161 int amdgpu_smu_pptable_id = -1; 162 /* 163 * FBC (bit 0) disabled by default 164 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 165 * - With this, for multiple monitors in sync(e.g. with the same model), 166 * mclk switching will be allowed. And the mclk will be not foced to the 167 * highest. That helps saving some idle power. 168 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 169 * PSR (bit 3) disabled by default 170 * EDP NO POWER SEQUENCING (bit 4) disabled by default 171 */ 172 uint amdgpu_dc_feature_mask = 2; 173 uint amdgpu_dc_debug_mask; 174 uint amdgpu_dc_visual_confirm; 175 int amdgpu_async_gfx_ring = 1; 176 int amdgpu_mcbp; 177 int amdgpu_discovery = -1; 178 int amdgpu_mes; 179 int amdgpu_mes_kiq; 180 int amdgpu_noretry = -1; 181 int amdgpu_force_asic_type = -1; 182 int amdgpu_tmz = -1; /* auto */ 183 uint amdgpu_freesync_vid_mode; 184 int amdgpu_reset_method = -1; /* auto */ 185 int amdgpu_num_kcq = -1; 186 int amdgpu_smartshift_bias; 187 int amdgpu_use_xgmi_p2p = 1; 188 int amdgpu_vcnfw_log; 189 190 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 191 192 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 193 "DRM_UT_CORE", 194 "DRM_UT_DRIVER", 195 "DRM_UT_KMS", 196 "DRM_UT_PRIME", 197 "DRM_UT_ATOMIC", 198 "DRM_UT_VBL", 199 "DRM_UT_STATE", 200 "DRM_UT_LEASE", 201 "DRM_UT_DP", 202 "DRM_UT_DRMRES"); 203 204 struct amdgpu_mgpu_info mgpu_info = { 205 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 206 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 207 mgpu_info.delayed_reset_work, 208 amdgpu_drv_delayed_reset_work_handler, 0), 209 }; 210 int amdgpu_ras_enable = -1; 211 uint amdgpu_ras_mask = 0xffffffff; 212 int amdgpu_bad_page_threshold = -1; 213 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 214 .timeout_fatal_disable = false, 215 .period = 0x0, /* default to 0x0 (timeout disable) */ 216 }; 217 218 /** 219 * DOC: vramlimit (int) 220 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 221 */ 222 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 223 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 224 225 /** 226 * DOC: vis_vramlimit (int) 227 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 228 */ 229 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 230 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 231 232 /** 233 * DOC: gartsize (uint) 234 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 235 * The default is -1 (The size depends on asic). 236 */ 237 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 238 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 239 240 /** 241 * DOC: gttsize (int) 242 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 243 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 244 */ 245 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 246 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 247 248 /** 249 * DOC: moverate (int) 250 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 251 */ 252 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 253 module_param_named(moverate, amdgpu_moverate, int, 0600); 254 255 /** 256 * DOC: audio (int) 257 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 258 */ 259 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 260 module_param_named(audio, amdgpu_audio, int, 0444); 261 262 /** 263 * DOC: disp_priority (int) 264 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 265 */ 266 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 267 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 268 269 /** 270 * DOC: hw_i2c (int) 271 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 272 */ 273 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 274 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 275 276 /** 277 * DOC: pcie_gen2 (int) 278 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 279 */ 280 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 281 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 282 283 /** 284 * DOC: msi (int) 285 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 286 */ 287 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 288 module_param_named(msi, amdgpu_msi, int, 0444); 289 290 /** 291 * DOC: lockup_timeout (string) 292 * Set GPU scheduler timeout value in ms. 293 * 294 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 295 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 296 * to the default timeout. 297 * 298 * - With one value specified, the setting will apply to all non-compute jobs. 299 * - With multiple values specified, the first one will be for GFX. 300 * The second one is for Compute. The third and fourth ones are 301 * for SDMA and Video. 302 * 303 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 304 * jobs is 10000. The timeout for compute is 60000. 305 */ 306 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 307 "for passthrough or sriov, 10000 for all jobs." 308 " 0: keep default value. negative: infinity timeout), " 309 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 310 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 311 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 312 313 /** 314 * DOC: dpm (int) 315 * Override for dynamic power management setting 316 * (0 = disable, 1 = enable) 317 * The default is -1 (auto). 318 */ 319 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 320 module_param_named(dpm, amdgpu_dpm, int, 0444); 321 322 /** 323 * DOC: fw_load_type (int) 324 * Set different firmware loading type for debugging, if supported. 325 * Set to 0 to force direct loading if supported by the ASIC. Set 326 * to -1 to select the default loading mode for the ASIC, as defined 327 * by the driver. The default is -1 (auto). 328 */ 329 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 330 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 331 332 /** 333 * DOC: aspm (int) 334 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 335 */ 336 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 337 module_param_named(aspm, amdgpu_aspm, int, 0444); 338 339 /** 340 * DOC: runpm (int) 341 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 342 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 343 * Setting the value to 0 disables this functionality. 344 */ 345 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 346 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 347 348 /** 349 * DOC: ip_block_mask (uint) 350 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 351 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 352 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 353 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 354 */ 355 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 356 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 357 358 /** 359 * DOC: bapm (int) 360 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 361 * The default -1 (auto, enabled) 362 */ 363 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 364 module_param_named(bapm, amdgpu_bapm, int, 0444); 365 366 /** 367 * DOC: deep_color (int) 368 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 369 */ 370 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 371 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 372 373 /** 374 * DOC: vm_size (int) 375 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 376 */ 377 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 378 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 379 380 /** 381 * DOC: vm_fragment_size (int) 382 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 383 */ 384 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 385 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 386 387 /** 388 * DOC: vm_block_size (int) 389 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 390 */ 391 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 392 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 393 394 /** 395 * DOC: vm_fault_stop (int) 396 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 397 */ 398 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 399 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 400 401 /** 402 * DOC: vm_debug (int) 403 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 404 */ 405 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 406 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 407 408 /** 409 * DOC: vm_update_mode (int) 410 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 411 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 412 */ 413 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 414 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 415 416 /** 417 * DOC: exp_hw_support (int) 418 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 419 */ 420 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 421 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 422 423 /** 424 * DOC: dc (int) 425 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 426 */ 427 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 428 module_param_named(dc, amdgpu_dc, int, 0444); 429 430 /** 431 * DOC: sched_jobs (int) 432 * Override the max number of jobs supported in the sw queue. The default is 32. 433 */ 434 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 435 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 436 437 /** 438 * DOC: sched_hw_submission (int) 439 * Override the max number of HW submissions. The default is 2. 440 */ 441 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 442 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 443 444 /** 445 * DOC: ppfeaturemask (hexint) 446 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 447 * The default is the current set of stable power features. 448 */ 449 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 450 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 451 452 /** 453 * DOC: forcelongtraining (uint) 454 * Force long memory training in resume. 455 * The default is zero, indicates short training in resume. 456 */ 457 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 458 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 459 460 /** 461 * DOC: pcie_gen_cap (uint) 462 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 463 * The default is 0 (automatic for each asic). 464 */ 465 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 466 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 467 468 /** 469 * DOC: pcie_lane_cap (uint) 470 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 471 * The default is 0 (automatic for each asic). 472 */ 473 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 474 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 475 476 /** 477 * DOC: cg_mask (ullong) 478 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 479 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 480 */ 481 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 482 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 483 484 /** 485 * DOC: pg_mask (uint) 486 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 487 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 488 */ 489 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 490 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 491 492 /** 493 * DOC: sdma_phase_quantum (uint) 494 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 495 */ 496 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 497 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 498 499 /** 500 * DOC: disable_cu (charp) 501 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 502 */ 503 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 504 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 505 506 /** 507 * DOC: virtual_display (charp) 508 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 509 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 510 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 511 * device at 26:00.0. The default is NULL. 512 */ 513 MODULE_PARM_DESC(virtual_display, 514 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 515 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 516 517 /** 518 * DOC: job_hang_limit (int) 519 * Set how much time allow a job hang and not drop it. The default is 0. 520 */ 521 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 522 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 523 524 /** 525 * DOC: lbpw (int) 526 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 527 */ 528 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 529 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 530 531 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 532 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 533 534 /** 535 * DOC: gpu_recovery (int) 536 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 537 */ 538 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 539 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 540 541 /** 542 * DOC: emu_mode (int) 543 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 544 */ 545 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 546 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 547 548 /** 549 * DOC: ras_enable (int) 550 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 551 */ 552 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 553 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 554 555 /** 556 * DOC: ras_mask (uint) 557 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 558 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 559 */ 560 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 561 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 562 563 /** 564 * DOC: timeout_fatal_disable (bool) 565 * Disable Watchdog timeout fatal error event 566 */ 567 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 568 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 569 570 /** 571 * DOC: timeout_period (uint) 572 * Modify the watchdog timeout max_cycles as (1 << period) 573 */ 574 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 575 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 576 577 /** 578 * DOC: si_support (int) 579 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 581 * otherwise using amdgpu driver. 582 */ 583 #ifdef CONFIG_DRM_AMDGPU_SI 584 585 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 586 int amdgpu_si_support = 0; 587 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 588 #else 589 int amdgpu_si_support = 1; 590 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 591 #endif 592 593 module_param_named(si_support, amdgpu_si_support, int, 0444); 594 #endif 595 596 /** 597 * DOC: cik_support (int) 598 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 599 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 600 * otherwise using amdgpu driver. 601 */ 602 #ifdef CONFIG_DRM_AMDGPU_CIK 603 604 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 605 int amdgpu_cik_support = 0; 606 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 607 #else 608 int amdgpu_cik_support = 1; 609 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 610 #endif 611 612 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 613 #endif 614 615 /** 616 * DOC: smu_memory_pool_size (uint) 617 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 618 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 619 */ 620 MODULE_PARM_DESC(smu_memory_pool_size, 621 "reserve gtt for smu debug usage, 0 = disable," 622 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 623 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 624 625 /** 626 * DOC: async_gfx_ring (int) 627 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 628 */ 629 MODULE_PARM_DESC(async_gfx_ring, 630 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 631 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 632 633 /** 634 * DOC: mcbp (int) 635 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 636 */ 637 MODULE_PARM_DESC(mcbp, 638 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 639 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 640 641 /** 642 * DOC: discovery (int) 643 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 644 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 645 */ 646 MODULE_PARM_DESC(discovery, 647 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 648 module_param_named(discovery, amdgpu_discovery, int, 0444); 649 650 /** 651 * DOC: mes (int) 652 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 653 * (0 = disabled (default), 1 = enabled) 654 */ 655 MODULE_PARM_DESC(mes, 656 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 657 module_param_named(mes, amdgpu_mes, int, 0444); 658 659 /** 660 * DOC: mes_kiq (int) 661 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 662 * (0 = disabled (default), 1 = enabled) 663 */ 664 MODULE_PARM_DESC(mes_kiq, 665 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 666 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 667 668 /** 669 * DOC: noretry (int) 670 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 671 * do not support per-process XNACK this also disables retry page faults. 672 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 673 */ 674 MODULE_PARM_DESC(noretry, 675 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 676 module_param_named(noretry, amdgpu_noretry, int, 0644); 677 678 /** 679 * DOC: force_asic_type (int) 680 * A non negative value used to specify the asic type for all supported GPUs. 681 */ 682 MODULE_PARM_DESC(force_asic_type, 683 "A non negative value used to specify the asic type for all supported GPUs"); 684 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 685 686 /** 687 * DOC: use_xgmi_p2p (int) 688 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 689 */ 690 MODULE_PARM_DESC(use_xgmi_p2p, 691 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 692 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 693 694 695 #ifdef CONFIG_HSA_AMD 696 /** 697 * DOC: sched_policy (int) 698 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 699 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 700 * assigns queues to HQDs. 701 */ 702 int sched_policy = KFD_SCHED_POLICY_HWS; 703 module_param(sched_policy, int, 0444); 704 MODULE_PARM_DESC(sched_policy, 705 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 706 707 /** 708 * DOC: hws_max_conc_proc (int) 709 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 710 * number of VMIDs assigned to the HWS, which is also the default. 711 */ 712 int hws_max_conc_proc = -1; 713 module_param(hws_max_conc_proc, int, 0444); 714 MODULE_PARM_DESC(hws_max_conc_proc, 715 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 716 717 /** 718 * DOC: cwsr_enable (int) 719 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 720 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 721 * disables it. 722 */ 723 int cwsr_enable = 1; 724 module_param(cwsr_enable, int, 0444); 725 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 726 727 /** 728 * DOC: max_num_of_queues_per_device (int) 729 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 730 * is 4096. 731 */ 732 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 733 module_param(max_num_of_queues_per_device, int, 0444); 734 MODULE_PARM_DESC(max_num_of_queues_per_device, 735 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 736 737 /** 738 * DOC: send_sigterm (int) 739 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 740 * but just print errors on dmesg. Setting 1 enables sending sigterm. 741 */ 742 int send_sigterm; 743 module_param(send_sigterm, int, 0444); 744 MODULE_PARM_DESC(send_sigterm, 745 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 746 747 /** 748 * DOC: debug_largebar (int) 749 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 750 * system. This limits the VRAM size reported to ROCm applications to the visible 751 * size, usually 256MB. 752 * Default value is 0, diabled. 753 */ 754 int debug_largebar; 755 module_param(debug_largebar, int, 0444); 756 MODULE_PARM_DESC(debug_largebar, 757 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 758 759 /** 760 * DOC: ignore_crat (int) 761 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 762 * table to get information about AMD APUs. This option can serve as a workaround on 763 * systems with a broken CRAT table. 764 * 765 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 766 * whether use CRAT) 767 */ 768 int ignore_crat; 769 module_param(ignore_crat, int, 0444); 770 MODULE_PARM_DESC(ignore_crat, 771 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 772 773 /** 774 * DOC: halt_if_hws_hang (int) 775 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 776 * Setting 1 enables halt on hang. 777 */ 778 int halt_if_hws_hang; 779 module_param(halt_if_hws_hang, int, 0644); 780 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 781 782 /** 783 * DOC: hws_gws_support(bool) 784 * Assume that HWS supports GWS barriers regardless of what firmware version 785 * check says. Default value: false (rely on MEC2 firmware version check). 786 */ 787 bool hws_gws_support; 788 module_param(hws_gws_support, bool, 0444); 789 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 790 791 /** 792 * DOC: queue_preemption_timeout_ms (int) 793 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 794 */ 795 int queue_preemption_timeout_ms = 9000; 796 module_param(queue_preemption_timeout_ms, int, 0644); 797 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 798 799 /** 800 * DOC: debug_evictions(bool) 801 * Enable extra debug messages to help determine the cause of evictions 802 */ 803 bool debug_evictions; 804 module_param(debug_evictions, bool, 0644); 805 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 806 807 /** 808 * DOC: no_system_mem_limit(bool) 809 * Disable system memory limit, to support multiple process shared memory 810 */ 811 bool no_system_mem_limit; 812 module_param(no_system_mem_limit, bool, 0644); 813 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 814 815 /** 816 * DOC: no_queue_eviction_on_vm_fault (int) 817 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 818 */ 819 int amdgpu_no_queue_eviction_on_vm_fault = 0; 820 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 821 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 822 #endif 823 824 /** 825 * DOC: pcie_p2p (bool) 826 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 827 */ 828 #ifdef CONFIG_HSA_AMD_P2P 829 bool pcie_p2p = true; 830 module_param(pcie_p2p, bool, 0444); 831 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 832 #endif 833 834 /** 835 * DOC: dcfeaturemask (uint) 836 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 837 * The default is the current set of stable display features. 838 */ 839 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 840 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 841 842 /** 843 * DOC: dcdebugmask (uint) 844 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 845 */ 846 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 847 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 848 849 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 850 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 851 852 /** 853 * DOC: abmlevel (uint) 854 * Override the default ABM (Adaptive Backlight Management) level used for DC 855 * enabled hardware. Requires DMCU to be supported and loaded. 856 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 857 * default. Values 1-4 control the maximum allowable brightness reduction via 858 * the ABM algorithm, with 1 being the least reduction and 4 being the most 859 * reduction. 860 * 861 * Defaults to 0, or disabled. Userspace can still override this level later 862 * after boot. 863 */ 864 uint amdgpu_dm_abm_level; 865 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 866 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 867 868 int amdgpu_backlight = -1; 869 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 870 module_param_named(backlight, amdgpu_backlight, bint, 0444); 871 872 /** 873 * DOC: tmz (int) 874 * Trusted Memory Zone (TMZ) is a method to protect data being written 875 * to or read from memory. 876 * 877 * The default value: 0 (off). TODO: change to auto till it is completed. 878 */ 879 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 880 module_param_named(tmz, amdgpu_tmz, int, 0444); 881 882 /** 883 * DOC: freesync_video (uint) 884 * Enable the optimization to adjust front porch timing to achieve seamless 885 * mode change experience when setting a freesync supported mode for which full 886 * modeset is not needed. 887 * 888 * The Display Core will add a set of modes derived from the base FreeSync 889 * video mode into the corresponding connector's mode list based on commonly 890 * used refresh rates and VRR range of the connected display, when users enable 891 * this feature. From the userspace perspective, they can see a seamless mode 892 * change experience when the change between different refresh rates under the 893 * same resolution. Additionally, userspace applications such as Video playback 894 * can read this modeset list and change the refresh rate based on the video 895 * frame rate. Finally, the userspace can also derive an appropriate mode for a 896 * particular refresh rate based on the FreeSync Mode and add it to the 897 * connector's mode list. 898 * 899 * Note: This is an experimental feature. 900 * 901 * The default value: 0 (off). 902 */ 903 MODULE_PARM_DESC( 904 freesync_video, 905 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 906 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 907 908 /** 909 * DOC: reset_method (int) 910 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 911 */ 912 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 913 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 914 915 /** 916 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 917 * threshold value of faulty pages detected by RAS ECC, which may 918 * result in the GPU entering bad status when the number of total 919 * faulty pages by ECC exceeds the threshold value. 920 */ 921 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 922 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 923 924 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 925 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 926 927 /** 928 * DOC: vcnfw_log (int) 929 * Enable vcnfw log output for debugging, the default is disabled. 930 */ 931 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 932 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 933 934 /** 935 * DOC: smu_pptable_id (int) 936 * Used to override pptable id. id = 0 use VBIOS pptable. 937 * id > 0 use the soft pptable with specicfied id. 938 */ 939 MODULE_PARM_DESC(smu_pptable_id, 940 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 941 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 942 943 /* These devices are not supported by amdgpu. 944 * They are supported by the mach64, r128, radeon drivers 945 */ 946 static const u16 amdgpu_unsupported_pciidlist[] = { 947 /* mach64 */ 948 0x4354, 949 0x4358, 950 0x4554, 951 0x4742, 952 0x4744, 953 0x4749, 954 0x474C, 955 0x474D, 956 0x474E, 957 0x474F, 958 0x4750, 959 0x4751, 960 0x4752, 961 0x4753, 962 0x4754, 963 0x4755, 964 0x4756, 965 0x4757, 966 0x4758, 967 0x4759, 968 0x475A, 969 0x4C42, 970 0x4C44, 971 0x4C47, 972 0x4C49, 973 0x4C4D, 974 0x4C4E, 975 0x4C50, 976 0x4C51, 977 0x4C52, 978 0x4C53, 979 0x5654, 980 0x5655, 981 0x5656, 982 /* r128 */ 983 0x4c45, 984 0x4c46, 985 0x4d46, 986 0x4d4c, 987 0x5041, 988 0x5042, 989 0x5043, 990 0x5044, 991 0x5045, 992 0x5046, 993 0x5047, 994 0x5048, 995 0x5049, 996 0x504A, 997 0x504B, 998 0x504C, 999 0x504D, 1000 0x504E, 1001 0x504F, 1002 0x5050, 1003 0x5051, 1004 0x5052, 1005 0x5053, 1006 0x5054, 1007 0x5055, 1008 0x5056, 1009 0x5057, 1010 0x5058, 1011 0x5245, 1012 0x5246, 1013 0x5247, 1014 0x524b, 1015 0x524c, 1016 0x534d, 1017 0x5446, 1018 0x544C, 1019 0x5452, 1020 /* radeon */ 1021 0x3150, 1022 0x3151, 1023 0x3152, 1024 0x3154, 1025 0x3155, 1026 0x3E50, 1027 0x3E54, 1028 0x4136, 1029 0x4137, 1030 0x4144, 1031 0x4145, 1032 0x4146, 1033 0x4147, 1034 0x4148, 1035 0x4149, 1036 0x414A, 1037 0x414B, 1038 0x4150, 1039 0x4151, 1040 0x4152, 1041 0x4153, 1042 0x4154, 1043 0x4155, 1044 0x4156, 1045 0x4237, 1046 0x4242, 1047 0x4336, 1048 0x4337, 1049 0x4437, 1050 0x4966, 1051 0x4967, 1052 0x4A48, 1053 0x4A49, 1054 0x4A4A, 1055 0x4A4B, 1056 0x4A4C, 1057 0x4A4D, 1058 0x4A4E, 1059 0x4A4F, 1060 0x4A50, 1061 0x4A54, 1062 0x4B48, 1063 0x4B49, 1064 0x4B4A, 1065 0x4B4B, 1066 0x4B4C, 1067 0x4C57, 1068 0x4C58, 1069 0x4C59, 1070 0x4C5A, 1071 0x4C64, 1072 0x4C66, 1073 0x4C67, 1074 0x4E44, 1075 0x4E45, 1076 0x4E46, 1077 0x4E47, 1078 0x4E48, 1079 0x4E49, 1080 0x4E4A, 1081 0x4E4B, 1082 0x4E50, 1083 0x4E51, 1084 0x4E52, 1085 0x4E53, 1086 0x4E54, 1087 0x4E56, 1088 0x5144, 1089 0x5145, 1090 0x5146, 1091 0x5147, 1092 0x5148, 1093 0x514C, 1094 0x514D, 1095 0x5157, 1096 0x5158, 1097 0x5159, 1098 0x515A, 1099 0x515E, 1100 0x5460, 1101 0x5462, 1102 0x5464, 1103 0x5548, 1104 0x5549, 1105 0x554A, 1106 0x554B, 1107 0x554C, 1108 0x554D, 1109 0x554E, 1110 0x554F, 1111 0x5550, 1112 0x5551, 1113 0x5552, 1114 0x5554, 1115 0x564A, 1116 0x564B, 1117 0x564F, 1118 0x5652, 1119 0x5653, 1120 0x5657, 1121 0x5834, 1122 0x5835, 1123 0x5954, 1124 0x5955, 1125 0x5974, 1126 0x5975, 1127 0x5960, 1128 0x5961, 1129 0x5962, 1130 0x5964, 1131 0x5965, 1132 0x5969, 1133 0x5a41, 1134 0x5a42, 1135 0x5a61, 1136 0x5a62, 1137 0x5b60, 1138 0x5b62, 1139 0x5b63, 1140 0x5b64, 1141 0x5b65, 1142 0x5c61, 1143 0x5c63, 1144 0x5d48, 1145 0x5d49, 1146 0x5d4a, 1147 0x5d4c, 1148 0x5d4d, 1149 0x5d4e, 1150 0x5d4f, 1151 0x5d50, 1152 0x5d52, 1153 0x5d57, 1154 0x5e48, 1155 0x5e4a, 1156 0x5e4b, 1157 0x5e4c, 1158 0x5e4d, 1159 0x5e4f, 1160 0x6700, 1161 0x6701, 1162 0x6702, 1163 0x6703, 1164 0x6704, 1165 0x6705, 1166 0x6706, 1167 0x6707, 1168 0x6708, 1169 0x6709, 1170 0x6718, 1171 0x6719, 1172 0x671c, 1173 0x671d, 1174 0x671f, 1175 0x6720, 1176 0x6721, 1177 0x6722, 1178 0x6723, 1179 0x6724, 1180 0x6725, 1181 0x6726, 1182 0x6727, 1183 0x6728, 1184 0x6729, 1185 0x6738, 1186 0x6739, 1187 0x673e, 1188 0x6740, 1189 0x6741, 1190 0x6742, 1191 0x6743, 1192 0x6744, 1193 0x6745, 1194 0x6746, 1195 0x6747, 1196 0x6748, 1197 0x6749, 1198 0x674A, 1199 0x6750, 1200 0x6751, 1201 0x6758, 1202 0x6759, 1203 0x675B, 1204 0x675D, 1205 0x675F, 1206 0x6760, 1207 0x6761, 1208 0x6762, 1209 0x6763, 1210 0x6764, 1211 0x6765, 1212 0x6766, 1213 0x6767, 1214 0x6768, 1215 0x6770, 1216 0x6771, 1217 0x6772, 1218 0x6778, 1219 0x6779, 1220 0x677B, 1221 0x6840, 1222 0x6841, 1223 0x6842, 1224 0x6843, 1225 0x6849, 1226 0x684C, 1227 0x6850, 1228 0x6858, 1229 0x6859, 1230 0x6880, 1231 0x6888, 1232 0x6889, 1233 0x688A, 1234 0x688C, 1235 0x688D, 1236 0x6898, 1237 0x6899, 1238 0x689b, 1239 0x689c, 1240 0x689d, 1241 0x689e, 1242 0x68a0, 1243 0x68a1, 1244 0x68a8, 1245 0x68a9, 1246 0x68b0, 1247 0x68b8, 1248 0x68b9, 1249 0x68ba, 1250 0x68be, 1251 0x68bf, 1252 0x68c0, 1253 0x68c1, 1254 0x68c7, 1255 0x68c8, 1256 0x68c9, 1257 0x68d8, 1258 0x68d9, 1259 0x68da, 1260 0x68de, 1261 0x68e0, 1262 0x68e1, 1263 0x68e4, 1264 0x68e5, 1265 0x68e8, 1266 0x68e9, 1267 0x68f1, 1268 0x68f2, 1269 0x68f8, 1270 0x68f9, 1271 0x68fa, 1272 0x68fe, 1273 0x7100, 1274 0x7101, 1275 0x7102, 1276 0x7103, 1277 0x7104, 1278 0x7105, 1279 0x7106, 1280 0x7108, 1281 0x7109, 1282 0x710A, 1283 0x710B, 1284 0x710C, 1285 0x710E, 1286 0x710F, 1287 0x7140, 1288 0x7141, 1289 0x7142, 1290 0x7143, 1291 0x7144, 1292 0x7145, 1293 0x7146, 1294 0x7147, 1295 0x7149, 1296 0x714A, 1297 0x714B, 1298 0x714C, 1299 0x714D, 1300 0x714E, 1301 0x714F, 1302 0x7151, 1303 0x7152, 1304 0x7153, 1305 0x715E, 1306 0x715F, 1307 0x7180, 1308 0x7181, 1309 0x7183, 1310 0x7186, 1311 0x7187, 1312 0x7188, 1313 0x718A, 1314 0x718B, 1315 0x718C, 1316 0x718D, 1317 0x718F, 1318 0x7193, 1319 0x7196, 1320 0x719B, 1321 0x719F, 1322 0x71C0, 1323 0x71C1, 1324 0x71C2, 1325 0x71C3, 1326 0x71C4, 1327 0x71C5, 1328 0x71C6, 1329 0x71C7, 1330 0x71CD, 1331 0x71CE, 1332 0x71D2, 1333 0x71D4, 1334 0x71D5, 1335 0x71D6, 1336 0x71DA, 1337 0x71DE, 1338 0x7200, 1339 0x7210, 1340 0x7211, 1341 0x7240, 1342 0x7243, 1343 0x7244, 1344 0x7245, 1345 0x7246, 1346 0x7247, 1347 0x7248, 1348 0x7249, 1349 0x724A, 1350 0x724B, 1351 0x724C, 1352 0x724D, 1353 0x724E, 1354 0x724F, 1355 0x7280, 1356 0x7281, 1357 0x7283, 1358 0x7284, 1359 0x7287, 1360 0x7288, 1361 0x7289, 1362 0x728B, 1363 0x728C, 1364 0x7290, 1365 0x7291, 1366 0x7293, 1367 0x7297, 1368 0x7834, 1369 0x7835, 1370 0x791e, 1371 0x791f, 1372 0x793f, 1373 0x7941, 1374 0x7942, 1375 0x796c, 1376 0x796d, 1377 0x796e, 1378 0x796f, 1379 0x9400, 1380 0x9401, 1381 0x9402, 1382 0x9403, 1383 0x9405, 1384 0x940A, 1385 0x940B, 1386 0x940F, 1387 0x94A0, 1388 0x94A1, 1389 0x94A3, 1390 0x94B1, 1391 0x94B3, 1392 0x94B4, 1393 0x94B5, 1394 0x94B9, 1395 0x9440, 1396 0x9441, 1397 0x9442, 1398 0x9443, 1399 0x9444, 1400 0x9446, 1401 0x944A, 1402 0x944B, 1403 0x944C, 1404 0x944E, 1405 0x9450, 1406 0x9452, 1407 0x9456, 1408 0x945A, 1409 0x945B, 1410 0x945E, 1411 0x9460, 1412 0x9462, 1413 0x946A, 1414 0x946B, 1415 0x947A, 1416 0x947B, 1417 0x9480, 1418 0x9487, 1419 0x9488, 1420 0x9489, 1421 0x948A, 1422 0x948F, 1423 0x9490, 1424 0x9491, 1425 0x9495, 1426 0x9498, 1427 0x949C, 1428 0x949E, 1429 0x949F, 1430 0x94C0, 1431 0x94C1, 1432 0x94C3, 1433 0x94C4, 1434 0x94C5, 1435 0x94C6, 1436 0x94C7, 1437 0x94C8, 1438 0x94C9, 1439 0x94CB, 1440 0x94CC, 1441 0x94CD, 1442 0x9500, 1443 0x9501, 1444 0x9504, 1445 0x9505, 1446 0x9506, 1447 0x9507, 1448 0x9508, 1449 0x9509, 1450 0x950F, 1451 0x9511, 1452 0x9515, 1453 0x9517, 1454 0x9519, 1455 0x9540, 1456 0x9541, 1457 0x9542, 1458 0x954E, 1459 0x954F, 1460 0x9552, 1461 0x9553, 1462 0x9555, 1463 0x9557, 1464 0x955f, 1465 0x9580, 1466 0x9581, 1467 0x9583, 1468 0x9586, 1469 0x9587, 1470 0x9588, 1471 0x9589, 1472 0x958A, 1473 0x958B, 1474 0x958C, 1475 0x958D, 1476 0x958E, 1477 0x958F, 1478 0x9590, 1479 0x9591, 1480 0x9593, 1481 0x9595, 1482 0x9596, 1483 0x9597, 1484 0x9598, 1485 0x9599, 1486 0x959B, 1487 0x95C0, 1488 0x95C2, 1489 0x95C4, 1490 0x95C5, 1491 0x95C6, 1492 0x95C7, 1493 0x95C9, 1494 0x95CC, 1495 0x95CD, 1496 0x95CE, 1497 0x95CF, 1498 0x9610, 1499 0x9611, 1500 0x9612, 1501 0x9613, 1502 0x9614, 1503 0x9615, 1504 0x9616, 1505 0x9640, 1506 0x9641, 1507 0x9642, 1508 0x9643, 1509 0x9644, 1510 0x9645, 1511 0x9647, 1512 0x9648, 1513 0x9649, 1514 0x964a, 1515 0x964b, 1516 0x964c, 1517 0x964e, 1518 0x964f, 1519 0x9710, 1520 0x9711, 1521 0x9712, 1522 0x9713, 1523 0x9714, 1524 0x9715, 1525 0x9802, 1526 0x9803, 1527 0x9804, 1528 0x9805, 1529 0x9806, 1530 0x9807, 1531 0x9808, 1532 0x9809, 1533 0x980A, 1534 0x9900, 1535 0x9901, 1536 0x9903, 1537 0x9904, 1538 0x9905, 1539 0x9906, 1540 0x9907, 1541 0x9908, 1542 0x9909, 1543 0x990A, 1544 0x990B, 1545 0x990C, 1546 0x990D, 1547 0x990E, 1548 0x990F, 1549 0x9910, 1550 0x9913, 1551 0x9917, 1552 0x9918, 1553 0x9919, 1554 0x9990, 1555 0x9991, 1556 0x9992, 1557 0x9993, 1558 0x9994, 1559 0x9995, 1560 0x9996, 1561 0x9997, 1562 0x9998, 1563 0x9999, 1564 0x999A, 1565 0x999B, 1566 0x999C, 1567 0x999D, 1568 0x99A0, 1569 0x99A2, 1570 0x99A4, 1571 /* radeon secondary ids */ 1572 0x3171, 1573 0x3e70, 1574 0x4164, 1575 0x4165, 1576 0x4166, 1577 0x4168, 1578 0x4170, 1579 0x4171, 1580 0x4172, 1581 0x4173, 1582 0x496e, 1583 0x4a69, 1584 0x4a6a, 1585 0x4a6b, 1586 0x4a70, 1587 0x4a74, 1588 0x4b69, 1589 0x4b6b, 1590 0x4b6c, 1591 0x4c6e, 1592 0x4e64, 1593 0x4e65, 1594 0x4e66, 1595 0x4e67, 1596 0x4e68, 1597 0x4e69, 1598 0x4e6a, 1599 0x4e71, 1600 0x4f73, 1601 0x5569, 1602 0x556b, 1603 0x556d, 1604 0x556f, 1605 0x5571, 1606 0x5854, 1607 0x5874, 1608 0x5940, 1609 0x5941, 1610 0x5b72, 1611 0x5b73, 1612 0x5b74, 1613 0x5b75, 1614 0x5d44, 1615 0x5d45, 1616 0x5d6d, 1617 0x5d6f, 1618 0x5d72, 1619 0x5d77, 1620 0x5e6b, 1621 0x5e6d, 1622 0x7120, 1623 0x7124, 1624 0x7129, 1625 0x712e, 1626 0x712f, 1627 0x7162, 1628 0x7163, 1629 0x7166, 1630 0x7167, 1631 0x7172, 1632 0x7173, 1633 0x71a0, 1634 0x71a1, 1635 0x71a3, 1636 0x71a7, 1637 0x71bb, 1638 0x71e0, 1639 0x71e1, 1640 0x71e2, 1641 0x71e6, 1642 0x71e7, 1643 0x71f2, 1644 0x7269, 1645 0x726b, 1646 0x726e, 1647 0x72a0, 1648 0x72a8, 1649 0x72b1, 1650 0x72b3, 1651 0x793f, 1652 }; 1653 1654 static const struct pci_device_id pciidlist[] = { 1655 #ifdef CONFIG_DRM_AMDGPU_SI 1656 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1657 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1658 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1659 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1660 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1661 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1662 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1663 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1664 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1665 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1666 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1668 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1669 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1670 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1671 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1673 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1674 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1675 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1676 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1677 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1678 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1679 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1680 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1681 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1682 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1683 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1684 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1685 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1689 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1690 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1691 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1692 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1693 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1694 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1698 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1700 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1701 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1707 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1708 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1709 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1710 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1711 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1716 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1717 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1718 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1719 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1720 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1721 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1722 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1727 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1728 #endif 1729 #ifdef CONFIG_DRM_AMDGPU_CIK 1730 /* Kaveri */ 1731 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1733 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1735 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1736 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1737 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1742 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1743 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1744 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1745 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1746 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1747 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1748 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1751 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1752 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1753 /* Bonaire */ 1754 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1755 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1757 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1758 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1759 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1760 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1761 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1762 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1763 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1764 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1765 /* Hawaii */ 1766 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1767 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1768 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1769 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1770 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1771 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1772 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1773 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1774 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1775 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1776 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1777 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1778 /* Kabini */ 1779 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1781 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1783 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1784 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1785 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1786 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1787 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1788 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1789 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1790 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1791 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1792 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1793 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1794 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1795 /* mullins */ 1796 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1797 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1798 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1800 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1801 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1802 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1803 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1804 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1805 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1806 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 #endif 1813 /* topaz */ 1814 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1815 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1816 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1817 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1818 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1819 /* tonga */ 1820 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1821 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1822 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1823 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1824 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1825 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1826 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1827 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1828 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1829 /* fiji */ 1830 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1831 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1832 /* carrizo */ 1833 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1834 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1835 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1836 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1837 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1838 /* stoney */ 1839 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1840 /* Polaris11 */ 1841 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1842 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1843 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1844 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1845 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1846 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1847 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1848 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1849 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1850 /* Polaris10 */ 1851 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1852 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1853 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1854 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1855 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1856 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1857 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1858 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1859 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1860 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1861 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1863 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1864 /* Polaris12 */ 1865 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1866 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1867 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1868 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1869 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1870 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1871 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1872 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1873 /* VEGAM */ 1874 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1875 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1876 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1877 /* Vega 10 */ 1878 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1879 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1880 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1881 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1882 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1883 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1884 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1885 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1886 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1887 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1888 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1893 /* Vega 12 */ 1894 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1895 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1896 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1897 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1898 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1899 /* Vega 20 */ 1900 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1901 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1902 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1903 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1904 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1905 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1906 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1907 /* Raven */ 1908 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1909 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1910 /* Arcturus */ 1911 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1912 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1913 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1914 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1915 /* Navi10 */ 1916 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1917 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1918 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1919 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1920 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1921 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1922 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1923 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1924 /* Navi14 */ 1925 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1926 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1927 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1928 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1929 1930 /* Renoir */ 1931 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1932 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1933 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1934 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1935 1936 /* Navi12 */ 1937 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1938 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1939 1940 /* Sienna_Cichlid */ 1941 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1942 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1943 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1944 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1945 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1946 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1947 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1948 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1949 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1950 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1951 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1953 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1954 1955 /* Yellow Carp */ 1956 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1957 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1958 1959 /* Navy_Flounder */ 1960 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1961 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1962 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1963 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1964 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1965 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1966 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1967 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1968 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1969 1970 /* DIMGREY_CAVEFISH */ 1971 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1972 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1973 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1974 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1975 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1976 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1977 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1978 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1979 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1980 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1981 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1982 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1983 1984 /* Aldebaran */ 1985 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1986 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1987 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1988 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1989 1990 /* CYAN_SKILLFISH */ 1991 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1992 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1993 1994 /* BEIGE_GOBY */ 1995 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1996 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1997 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1998 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1999 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2000 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2001 2002 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2003 .class = PCI_CLASS_DISPLAY_VGA << 8, 2004 .class_mask = 0xffffff, 2005 .driver_data = CHIP_IP_DISCOVERY }, 2006 2007 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2008 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2009 .class_mask = 0xffffff, 2010 .driver_data = CHIP_IP_DISCOVERY }, 2011 2012 {0, 0, 0} 2013 }; 2014 2015 MODULE_DEVICE_TABLE(pci, pciidlist); 2016 2017 static const struct drm_driver amdgpu_kms_driver; 2018 2019 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2020 { 2021 struct pci_dev *p = NULL; 2022 int i; 2023 2024 /* 0 - GPU 2025 * 1 - audio 2026 * 2 - USB 2027 * 3 - UCSI 2028 */ 2029 for (i = 1; i < 4; i++) { 2030 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2031 adev->pdev->bus->number, i); 2032 if (p) { 2033 pm_runtime_get_sync(&p->dev); 2034 pm_runtime_mark_last_busy(&p->dev); 2035 pm_runtime_put_autosuspend(&p->dev); 2036 pci_dev_put(p); 2037 } 2038 } 2039 } 2040 2041 static int amdgpu_pci_probe(struct pci_dev *pdev, 2042 const struct pci_device_id *ent) 2043 { 2044 struct drm_device *ddev; 2045 struct amdgpu_device *adev; 2046 unsigned long flags = ent->driver_data; 2047 int ret, retry = 0, i; 2048 bool supports_atomic = false; 2049 2050 /* skip devices which are owned by radeon */ 2051 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2052 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2053 return -ENODEV; 2054 } 2055 2056 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2057 amdgpu_aspm = 0; 2058 2059 if (amdgpu_virtual_display || 2060 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2061 supports_atomic = true; 2062 2063 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2064 DRM_INFO("This hardware requires experimental hardware support.\n" 2065 "See modparam exp_hw_support\n"); 2066 return -ENODEV; 2067 } 2068 /* differentiate between P10 and P11 asics with the same DID */ 2069 if (pdev->device == 0x67FF && 2070 (pdev->revision == 0xE3 || 2071 pdev->revision == 0xE7 || 2072 pdev->revision == 0xF3 || 2073 pdev->revision == 0xF7)) { 2074 flags &= ~AMD_ASIC_MASK; 2075 flags |= CHIP_POLARIS10; 2076 } 2077 2078 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2079 * however, SME requires an indirect IOMMU mapping because the encryption 2080 * bit is beyond the DMA mask of the chip. 2081 */ 2082 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2083 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2084 dev_info(&pdev->dev, 2085 "SME is not compatible with RAVEN\n"); 2086 return -ENOTSUPP; 2087 } 2088 2089 #ifdef CONFIG_DRM_AMDGPU_SI 2090 if (!amdgpu_si_support) { 2091 switch (flags & AMD_ASIC_MASK) { 2092 case CHIP_TAHITI: 2093 case CHIP_PITCAIRN: 2094 case CHIP_VERDE: 2095 case CHIP_OLAND: 2096 case CHIP_HAINAN: 2097 dev_info(&pdev->dev, 2098 "SI support provided by radeon.\n"); 2099 dev_info(&pdev->dev, 2100 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2101 ); 2102 return -ENODEV; 2103 } 2104 } 2105 #endif 2106 #ifdef CONFIG_DRM_AMDGPU_CIK 2107 if (!amdgpu_cik_support) { 2108 switch (flags & AMD_ASIC_MASK) { 2109 case CHIP_KAVERI: 2110 case CHIP_BONAIRE: 2111 case CHIP_HAWAII: 2112 case CHIP_KABINI: 2113 case CHIP_MULLINS: 2114 dev_info(&pdev->dev, 2115 "CIK support provided by radeon.\n"); 2116 dev_info(&pdev->dev, 2117 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2118 ); 2119 return -ENODEV; 2120 } 2121 } 2122 #endif 2123 2124 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2125 if (IS_ERR(adev)) 2126 return PTR_ERR(adev); 2127 2128 adev->dev = &pdev->dev; 2129 adev->pdev = pdev; 2130 ddev = adev_to_drm(adev); 2131 2132 if (!supports_atomic) 2133 ddev->driver_features &= ~DRIVER_ATOMIC; 2134 2135 ret = pci_enable_device(pdev); 2136 if (ret) 2137 return ret; 2138 2139 pci_set_drvdata(pdev, ddev); 2140 2141 ret = amdgpu_driver_load_kms(adev, flags); 2142 if (ret) 2143 goto err_pci; 2144 2145 retry_init: 2146 ret = drm_dev_register(ddev, flags); 2147 if (ret == -EAGAIN && ++retry <= 3) { 2148 DRM_INFO("retry init %d\n", retry); 2149 /* Don't request EX mode too frequently which is attacking */ 2150 msleep(5000); 2151 goto retry_init; 2152 } else if (ret) { 2153 goto err_pci; 2154 } 2155 2156 /* 2157 * 1. don't init fbdev on hw without DCE 2158 * 2. don't init fbdev if there are no connectors 2159 */ 2160 if (adev->mode_info.mode_config_initialized && 2161 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2162 /* select 8 bpp console on low vram cards */ 2163 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2164 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2165 else 2166 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2167 } 2168 2169 ret = amdgpu_debugfs_init(adev); 2170 if (ret) 2171 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2172 2173 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2174 /* only need to skip on ATPX */ 2175 if (amdgpu_device_supports_px(ddev)) 2176 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2177 /* we want direct complete for BOCO */ 2178 if (amdgpu_device_supports_boco(ddev)) 2179 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2180 DPM_FLAG_SMART_SUSPEND | 2181 DPM_FLAG_MAY_SKIP_RESUME); 2182 pm_runtime_use_autosuspend(ddev->dev); 2183 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2184 2185 pm_runtime_allow(ddev->dev); 2186 2187 pm_runtime_mark_last_busy(ddev->dev); 2188 pm_runtime_put_autosuspend(ddev->dev); 2189 2190 /* 2191 * For runpm implemented via BACO, PMFW will handle the 2192 * timing for BACO in and out: 2193 * - put ASIC into BACO state only when both video and 2194 * audio functions are in D3 state. 2195 * - pull ASIC out of BACO state when either video or 2196 * audio function is in D0 state. 2197 * Also, at startup, PMFW assumes both functions are in 2198 * D0 state. 2199 * 2200 * So if snd driver was loaded prior to amdgpu driver 2201 * and audio function was put into D3 state, there will 2202 * be no PMFW-aware D-state transition(D0->D3) on runpm 2203 * suspend. Thus the BACO will be not correctly kicked in. 2204 * 2205 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2206 * into D0 state. Then there will be a PMFW-aware D-state 2207 * transition(D0->D3) on runpm suspend. 2208 */ 2209 if (amdgpu_device_supports_baco(ddev) && 2210 !(adev->flags & AMD_IS_APU) && 2211 (adev->asic_type >= CHIP_NAVI10)) 2212 amdgpu_get_secondary_funcs(adev); 2213 } 2214 2215 return 0; 2216 2217 err_pci: 2218 pci_disable_device(pdev); 2219 return ret; 2220 } 2221 2222 static void 2223 amdgpu_pci_remove(struct pci_dev *pdev) 2224 { 2225 struct drm_device *dev = pci_get_drvdata(pdev); 2226 struct amdgpu_device *adev = drm_to_adev(dev); 2227 2228 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2229 pm_runtime_get_sync(dev->dev); 2230 pm_runtime_forbid(dev->dev); 2231 } 2232 2233 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2234 !amdgpu_sriov_vf(adev)) { 2235 bool need_to_reset_gpu = false; 2236 2237 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2238 struct amdgpu_hive_info *hive; 2239 2240 hive = amdgpu_get_xgmi_hive(adev); 2241 if (hive->device_remove_count == 0) 2242 need_to_reset_gpu = true; 2243 hive->device_remove_count++; 2244 amdgpu_put_xgmi_hive(hive); 2245 } else { 2246 need_to_reset_gpu = true; 2247 } 2248 2249 /* Workaround for ASICs need to reset SMU. 2250 * Called only when the first device is removed. 2251 */ 2252 if (need_to_reset_gpu) { 2253 struct amdgpu_reset_context reset_context; 2254 2255 adev->shutdown = true; 2256 memset(&reset_context, 0, sizeof(reset_context)); 2257 reset_context.method = AMD_RESET_METHOD_NONE; 2258 reset_context.reset_req_dev = adev; 2259 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2260 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2261 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2262 } 2263 } 2264 2265 amdgpu_driver_unload_kms(dev); 2266 2267 drm_dev_unplug(dev); 2268 2269 /* 2270 * Flush any in flight DMA operations from device. 2271 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2272 * StatusTransactions Pending bit. 2273 */ 2274 pci_disable_device(pdev); 2275 pci_wait_for_pending_transaction(pdev); 2276 } 2277 2278 static void 2279 amdgpu_pci_shutdown(struct pci_dev *pdev) 2280 { 2281 struct drm_device *dev = pci_get_drvdata(pdev); 2282 struct amdgpu_device *adev = drm_to_adev(dev); 2283 2284 if (amdgpu_ras_intr_triggered()) 2285 return; 2286 2287 /* if we are running in a VM, make sure the device 2288 * torn down properly on reboot/shutdown. 2289 * unfortunately we can't detect certain 2290 * hypervisors so just do this all the time. 2291 */ 2292 if (!amdgpu_passthrough(adev)) 2293 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2294 amdgpu_device_ip_suspend(adev); 2295 adev->mp1_state = PP_MP1_STATE_NONE; 2296 } 2297 2298 /** 2299 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2300 * 2301 * @work: work_struct. 2302 */ 2303 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2304 { 2305 struct list_head device_list; 2306 struct amdgpu_device *adev; 2307 int i, r; 2308 struct amdgpu_reset_context reset_context; 2309 2310 memset(&reset_context, 0, sizeof(reset_context)); 2311 2312 mutex_lock(&mgpu_info.mutex); 2313 if (mgpu_info.pending_reset == true) { 2314 mutex_unlock(&mgpu_info.mutex); 2315 return; 2316 } 2317 mgpu_info.pending_reset = true; 2318 mutex_unlock(&mgpu_info.mutex); 2319 2320 /* Use a common context, just need to make sure full reset is done */ 2321 reset_context.method = AMD_RESET_METHOD_NONE; 2322 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2323 2324 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2325 adev = mgpu_info.gpu_ins[i].adev; 2326 reset_context.reset_req_dev = adev; 2327 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2328 if (r) { 2329 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2330 r, adev_to_drm(adev)->unique); 2331 } 2332 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2333 r = -EALREADY; 2334 } 2335 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2336 adev = mgpu_info.gpu_ins[i].adev; 2337 flush_work(&adev->xgmi_reset_work); 2338 adev->gmc.xgmi.pending_reset = false; 2339 } 2340 2341 /* reset function will rebuild the xgmi hive info , clear it now */ 2342 for (i = 0; i < mgpu_info.num_dgpu; i++) 2343 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2344 2345 INIT_LIST_HEAD(&device_list); 2346 2347 for (i = 0; i < mgpu_info.num_dgpu; i++) 2348 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2349 2350 /* unregister the GPU first, reset function will add them back */ 2351 list_for_each_entry(adev, &device_list, reset_list) 2352 amdgpu_unregister_gpu_instance(adev); 2353 2354 /* Use a common context, just need to make sure full reset is done */ 2355 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2356 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2357 2358 if (r) { 2359 DRM_ERROR("reinit gpus failure"); 2360 return; 2361 } 2362 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2363 adev = mgpu_info.gpu_ins[i].adev; 2364 if (!adev->kfd.init_complete) 2365 amdgpu_amdkfd_device_init(adev); 2366 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2367 } 2368 return; 2369 } 2370 2371 static int amdgpu_pmops_prepare(struct device *dev) 2372 { 2373 struct drm_device *drm_dev = dev_get_drvdata(dev); 2374 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2375 2376 /* Return a positive number here so 2377 * DPM_FLAG_SMART_SUSPEND works properly 2378 */ 2379 if (amdgpu_device_supports_boco(drm_dev)) 2380 return pm_runtime_suspended(dev); 2381 2382 /* if we will not support s3 or s2i for the device 2383 * then skip suspend 2384 */ 2385 if (!amdgpu_acpi_is_s0ix_active(adev) && 2386 !amdgpu_acpi_is_s3_active(adev)) 2387 return 1; 2388 2389 return 0; 2390 } 2391 2392 static void amdgpu_pmops_complete(struct device *dev) 2393 { 2394 /* nothing to do */ 2395 } 2396 2397 static int amdgpu_pmops_suspend(struct device *dev) 2398 { 2399 struct drm_device *drm_dev = dev_get_drvdata(dev); 2400 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2401 2402 if (amdgpu_acpi_is_s0ix_active(adev)) 2403 adev->in_s0ix = true; 2404 else 2405 adev->in_s3 = true; 2406 return amdgpu_device_suspend(drm_dev, true); 2407 } 2408 2409 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2410 { 2411 struct drm_device *drm_dev = dev_get_drvdata(dev); 2412 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2413 2414 if (amdgpu_acpi_should_gpu_reset(adev)) 2415 return amdgpu_asic_reset(adev); 2416 2417 return 0; 2418 } 2419 2420 static int amdgpu_pmops_resume(struct device *dev) 2421 { 2422 struct drm_device *drm_dev = dev_get_drvdata(dev); 2423 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2424 int r; 2425 2426 /* Avoids registers access if device is physically gone */ 2427 if (!pci_device_is_present(adev->pdev)) 2428 adev->no_hw_access = true; 2429 2430 r = amdgpu_device_resume(drm_dev, true); 2431 if (amdgpu_acpi_is_s0ix_active(adev)) 2432 adev->in_s0ix = false; 2433 else 2434 adev->in_s3 = false; 2435 return r; 2436 } 2437 2438 static int amdgpu_pmops_freeze(struct device *dev) 2439 { 2440 struct drm_device *drm_dev = dev_get_drvdata(dev); 2441 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2442 int r; 2443 2444 adev->in_s4 = true; 2445 r = amdgpu_device_suspend(drm_dev, true); 2446 adev->in_s4 = false; 2447 if (r) 2448 return r; 2449 return amdgpu_asic_reset(adev); 2450 } 2451 2452 static int amdgpu_pmops_thaw(struct device *dev) 2453 { 2454 struct drm_device *drm_dev = dev_get_drvdata(dev); 2455 2456 return amdgpu_device_resume(drm_dev, true); 2457 } 2458 2459 static int amdgpu_pmops_poweroff(struct device *dev) 2460 { 2461 struct drm_device *drm_dev = dev_get_drvdata(dev); 2462 2463 return amdgpu_device_suspend(drm_dev, true); 2464 } 2465 2466 static int amdgpu_pmops_restore(struct device *dev) 2467 { 2468 struct drm_device *drm_dev = dev_get_drvdata(dev); 2469 2470 return amdgpu_device_resume(drm_dev, true); 2471 } 2472 2473 static int amdgpu_runtime_idle_check_display(struct device *dev) 2474 { 2475 struct pci_dev *pdev = to_pci_dev(dev); 2476 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2477 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2478 2479 if (adev->mode_info.num_crtc) { 2480 struct drm_connector *list_connector; 2481 struct drm_connector_list_iter iter; 2482 int ret = 0; 2483 2484 /* XXX: Return busy if any displays are connected to avoid 2485 * possible display wakeups after runtime resume due to 2486 * hotplug events in case any displays were connected while 2487 * the GPU was in suspend. Remove this once that is fixed. 2488 */ 2489 mutex_lock(&drm_dev->mode_config.mutex); 2490 drm_connector_list_iter_begin(drm_dev, &iter); 2491 drm_for_each_connector_iter(list_connector, &iter) { 2492 if (list_connector->status == connector_status_connected) { 2493 ret = -EBUSY; 2494 break; 2495 } 2496 } 2497 drm_connector_list_iter_end(&iter); 2498 mutex_unlock(&drm_dev->mode_config.mutex); 2499 2500 if (ret) 2501 return ret; 2502 2503 if (adev->dc_enabled) { 2504 struct drm_crtc *crtc; 2505 2506 drm_for_each_crtc(crtc, drm_dev) { 2507 drm_modeset_lock(&crtc->mutex, NULL); 2508 if (crtc->state->active) 2509 ret = -EBUSY; 2510 drm_modeset_unlock(&crtc->mutex); 2511 if (ret < 0) 2512 break; 2513 } 2514 } else { 2515 mutex_lock(&drm_dev->mode_config.mutex); 2516 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2517 2518 drm_connector_list_iter_begin(drm_dev, &iter); 2519 drm_for_each_connector_iter(list_connector, &iter) { 2520 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2521 ret = -EBUSY; 2522 break; 2523 } 2524 } 2525 2526 drm_connector_list_iter_end(&iter); 2527 2528 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2529 mutex_unlock(&drm_dev->mode_config.mutex); 2530 } 2531 if (ret) 2532 return ret; 2533 } 2534 2535 return 0; 2536 } 2537 2538 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2539 { 2540 struct pci_dev *pdev = to_pci_dev(dev); 2541 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2542 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2543 int ret, i; 2544 2545 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2546 pm_runtime_forbid(dev); 2547 return -EBUSY; 2548 } 2549 2550 ret = amdgpu_runtime_idle_check_display(dev); 2551 if (ret) 2552 return ret; 2553 2554 /* wait for all rings to drain before suspending */ 2555 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2556 struct amdgpu_ring *ring = adev->rings[i]; 2557 if (ring && ring->sched.ready) { 2558 ret = amdgpu_fence_wait_empty(ring); 2559 if (ret) 2560 return -EBUSY; 2561 } 2562 } 2563 2564 adev->in_runpm = true; 2565 if (amdgpu_device_supports_px(drm_dev)) 2566 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2567 2568 /* 2569 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2570 * proper cleanups and put itself into a state ready for PNP. That 2571 * can address some random resuming failure observed on BOCO capable 2572 * platforms. 2573 * TODO: this may be also needed for PX capable platform. 2574 */ 2575 if (amdgpu_device_supports_boco(drm_dev)) 2576 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2577 2578 ret = amdgpu_device_suspend(drm_dev, false); 2579 if (ret) { 2580 adev->in_runpm = false; 2581 if (amdgpu_device_supports_boco(drm_dev)) 2582 adev->mp1_state = PP_MP1_STATE_NONE; 2583 return ret; 2584 } 2585 2586 if (amdgpu_device_supports_boco(drm_dev)) 2587 adev->mp1_state = PP_MP1_STATE_NONE; 2588 2589 if (amdgpu_device_supports_px(drm_dev)) { 2590 /* Only need to handle PCI state in the driver for ATPX 2591 * PCI core handles it for _PR3. 2592 */ 2593 amdgpu_device_cache_pci_state(pdev); 2594 pci_disable_device(pdev); 2595 pci_ignore_hotplug(pdev); 2596 pci_set_power_state(pdev, PCI_D3cold); 2597 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2598 } else if (amdgpu_device_supports_boco(drm_dev)) { 2599 /* nothing to do */ 2600 } else if (amdgpu_device_supports_baco(drm_dev)) { 2601 amdgpu_device_baco_enter(drm_dev); 2602 } 2603 2604 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2605 2606 return 0; 2607 } 2608 2609 static int amdgpu_pmops_runtime_resume(struct device *dev) 2610 { 2611 struct pci_dev *pdev = to_pci_dev(dev); 2612 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2613 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2614 int ret; 2615 2616 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2617 return -EINVAL; 2618 2619 /* Avoids registers access if device is physically gone */ 2620 if (!pci_device_is_present(adev->pdev)) 2621 adev->no_hw_access = true; 2622 2623 if (amdgpu_device_supports_px(drm_dev)) { 2624 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2625 2626 /* Only need to handle PCI state in the driver for ATPX 2627 * PCI core handles it for _PR3. 2628 */ 2629 pci_set_power_state(pdev, PCI_D0); 2630 amdgpu_device_load_pci_state(pdev); 2631 ret = pci_enable_device(pdev); 2632 if (ret) 2633 return ret; 2634 pci_set_master(pdev); 2635 } else if (amdgpu_device_supports_boco(drm_dev)) { 2636 /* Only need to handle PCI state in the driver for ATPX 2637 * PCI core handles it for _PR3. 2638 */ 2639 pci_set_master(pdev); 2640 } else if (amdgpu_device_supports_baco(drm_dev)) { 2641 amdgpu_device_baco_exit(drm_dev); 2642 } 2643 ret = amdgpu_device_resume(drm_dev, false); 2644 if (ret) { 2645 if (amdgpu_device_supports_px(drm_dev)) 2646 pci_disable_device(pdev); 2647 return ret; 2648 } 2649 2650 if (amdgpu_device_supports_px(drm_dev)) 2651 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2652 adev->in_runpm = false; 2653 return 0; 2654 } 2655 2656 static int amdgpu_pmops_runtime_idle(struct device *dev) 2657 { 2658 struct drm_device *drm_dev = dev_get_drvdata(dev); 2659 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2660 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2661 int ret = 1; 2662 2663 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2664 pm_runtime_forbid(dev); 2665 return -EBUSY; 2666 } 2667 2668 ret = amdgpu_runtime_idle_check_display(dev); 2669 2670 pm_runtime_mark_last_busy(dev); 2671 pm_runtime_autosuspend(dev); 2672 return ret; 2673 } 2674 2675 long amdgpu_drm_ioctl(struct file *filp, 2676 unsigned int cmd, unsigned long arg) 2677 { 2678 struct drm_file *file_priv = filp->private_data; 2679 struct drm_device *dev; 2680 long ret; 2681 dev = file_priv->minor->dev; 2682 ret = pm_runtime_get_sync(dev->dev); 2683 if (ret < 0) 2684 goto out; 2685 2686 ret = drm_ioctl(filp, cmd, arg); 2687 2688 pm_runtime_mark_last_busy(dev->dev); 2689 out: 2690 pm_runtime_put_autosuspend(dev->dev); 2691 return ret; 2692 } 2693 2694 static const struct dev_pm_ops amdgpu_pm_ops = { 2695 .prepare = amdgpu_pmops_prepare, 2696 .complete = amdgpu_pmops_complete, 2697 .suspend = amdgpu_pmops_suspend, 2698 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2699 .resume = amdgpu_pmops_resume, 2700 .freeze = amdgpu_pmops_freeze, 2701 .thaw = amdgpu_pmops_thaw, 2702 .poweroff = amdgpu_pmops_poweroff, 2703 .restore = amdgpu_pmops_restore, 2704 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2705 .runtime_resume = amdgpu_pmops_runtime_resume, 2706 .runtime_idle = amdgpu_pmops_runtime_idle, 2707 }; 2708 2709 static int amdgpu_flush(struct file *f, fl_owner_t id) 2710 { 2711 struct drm_file *file_priv = f->private_data; 2712 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2713 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2714 2715 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2716 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2717 2718 return timeout >= 0 ? 0 : timeout; 2719 } 2720 2721 static const struct file_operations amdgpu_driver_kms_fops = { 2722 .owner = THIS_MODULE, 2723 .open = drm_open, 2724 .flush = amdgpu_flush, 2725 .release = drm_release, 2726 .unlocked_ioctl = amdgpu_drm_ioctl, 2727 .mmap = drm_gem_mmap, 2728 .poll = drm_poll, 2729 .read = drm_read, 2730 #ifdef CONFIG_COMPAT 2731 .compat_ioctl = amdgpu_kms_compat_ioctl, 2732 #endif 2733 #ifdef CONFIG_PROC_FS 2734 .show_fdinfo = amdgpu_show_fdinfo 2735 #endif 2736 }; 2737 2738 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2739 { 2740 struct drm_file *file; 2741 2742 if (!filp) 2743 return -EINVAL; 2744 2745 if (filp->f_op != &amdgpu_driver_kms_fops) { 2746 return -EINVAL; 2747 } 2748 2749 file = filp->private_data; 2750 *fpriv = file->driver_priv; 2751 return 0; 2752 } 2753 2754 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2755 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2756 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2757 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2758 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2759 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2760 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2761 /* KMS */ 2762 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2763 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2764 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2765 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2766 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2767 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2768 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2769 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2770 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2771 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2772 }; 2773 2774 static const struct drm_driver amdgpu_kms_driver = { 2775 .driver_features = 2776 DRIVER_ATOMIC | 2777 DRIVER_GEM | 2778 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2779 DRIVER_SYNCOBJ_TIMELINE, 2780 .open = amdgpu_driver_open_kms, 2781 .postclose = amdgpu_driver_postclose_kms, 2782 .lastclose = amdgpu_driver_lastclose_kms, 2783 .ioctls = amdgpu_ioctls_kms, 2784 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2785 .dumb_create = amdgpu_mode_dumb_create, 2786 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2787 .fops = &amdgpu_driver_kms_fops, 2788 .release = &amdgpu_driver_release_kms, 2789 2790 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2791 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2792 .gem_prime_import = amdgpu_gem_prime_import, 2793 .gem_prime_mmap = drm_gem_prime_mmap, 2794 2795 .name = DRIVER_NAME, 2796 .desc = DRIVER_DESC, 2797 .date = DRIVER_DATE, 2798 .major = KMS_DRIVER_MAJOR, 2799 .minor = KMS_DRIVER_MINOR, 2800 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2801 }; 2802 2803 static struct pci_error_handlers amdgpu_pci_err_handler = { 2804 .error_detected = amdgpu_pci_error_detected, 2805 .mmio_enabled = amdgpu_pci_mmio_enabled, 2806 .slot_reset = amdgpu_pci_slot_reset, 2807 .resume = amdgpu_pci_resume, 2808 }; 2809 2810 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2811 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2812 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2813 2814 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2815 &amdgpu_vram_mgr_attr_group, 2816 &amdgpu_gtt_mgr_attr_group, 2817 &amdgpu_vbios_version_attr_group, 2818 NULL, 2819 }; 2820 2821 2822 static struct pci_driver amdgpu_kms_pci_driver = { 2823 .name = DRIVER_NAME, 2824 .id_table = pciidlist, 2825 .probe = amdgpu_pci_probe, 2826 .remove = amdgpu_pci_remove, 2827 .shutdown = amdgpu_pci_shutdown, 2828 .driver.pm = &amdgpu_pm_ops, 2829 .err_handler = &amdgpu_pci_err_handler, 2830 .dev_groups = amdgpu_sysfs_groups, 2831 }; 2832 2833 static int __init amdgpu_init(void) 2834 { 2835 int r; 2836 2837 if (drm_firmware_drivers_only()) 2838 return -EINVAL; 2839 2840 r = amdgpu_sync_init(); 2841 if (r) 2842 goto error_sync; 2843 2844 r = amdgpu_fence_slab_init(); 2845 if (r) 2846 goto error_fence; 2847 2848 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2849 amdgpu_register_atpx_handler(); 2850 amdgpu_acpi_detect(); 2851 2852 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2853 amdgpu_amdkfd_init(); 2854 2855 /* let modprobe override vga console setting */ 2856 return pci_register_driver(&amdgpu_kms_pci_driver); 2857 2858 error_fence: 2859 amdgpu_sync_fini(); 2860 2861 error_sync: 2862 return r; 2863 } 2864 2865 static void __exit amdgpu_exit(void) 2866 { 2867 amdgpu_amdkfd_fini(); 2868 pci_unregister_driver(&amdgpu_kms_pci_driver); 2869 amdgpu_unregister_atpx_handler(); 2870 amdgpu_sync_fini(); 2871 amdgpu_fence_slab_fini(); 2872 mmu_notifier_synchronize(); 2873 } 2874 2875 module_init(amdgpu_init); 2876 module_exit(amdgpu_exit); 2877 2878 MODULE_AUTHOR(DRIVER_AUTHOR); 2879 MODULE_DESCRIPTION(DRIVER_DESC); 2880 MODULE_LICENSE("GPL and additional rights"); 2881