1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_generic.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_vblank.h> 31 #include <drm/drm_managed.h> 32 #include "amdgpu_drv.h" 33 34 #include <drm/drm_pciids.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/cc_platform.h> 42 #include <linux/fb.h> 43 #include <linux/dynamic_debug.h> 44 45 #include "amdgpu.h" 46 #include "amdgpu_irq.h" 47 #include "amdgpu_dma_buf.h" 48 #include "amdgpu_sched.h" 49 #include "amdgpu_fdinfo.h" 50 #include "amdgpu_amdkfd.h" 51 52 #include "amdgpu_ras.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_reset.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * 3.49.0 - Add gang submit into CS IOCTL 109 */ 110 #define KMS_DRIVER_MAJOR 3 111 #define KMS_DRIVER_MINOR 49 112 #define KMS_DRIVER_PATCHLEVEL 0 113 114 int amdgpu_vram_limit; 115 int amdgpu_vis_vram_limit; 116 int amdgpu_gart_size = -1; /* auto */ 117 int amdgpu_gtt_size = -1; /* auto */ 118 int amdgpu_moverate = -1; /* auto */ 119 int amdgpu_audio = -1; 120 int amdgpu_disp_priority; 121 int amdgpu_hw_i2c; 122 int amdgpu_pcie_gen2 = -1; 123 int amdgpu_msi = -1; 124 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 125 int amdgpu_dpm = -1; 126 int amdgpu_fw_load_type = -1; 127 int amdgpu_aspm = -1; 128 int amdgpu_runtime_pm = -1; 129 uint amdgpu_ip_block_mask = 0xffffffff; 130 int amdgpu_bapm = -1; 131 int amdgpu_deep_color; 132 int amdgpu_vm_size = -1; 133 int amdgpu_vm_fragment_size = -1; 134 int amdgpu_vm_block_size = -1; 135 int amdgpu_vm_fault_stop; 136 int amdgpu_vm_debug; 137 int amdgpu_vm_update_mode = -1; 138 int amdgpu_exp_hw_support; 139 int amdgpu_dc = -1; 140 int amdgpu_sched_jobs = 32; 141 int amdgpu_sched_hw_submission = 2; 142 uint amdgpu_pcie_gen_cap; 143 uint amdgpu_pcie_lane_cap; 144 u64 amdgpu_cg_mask = 0xffffffffffffffff; 145 uint amdgpu_pg_mask = 0xffffffff; 146 uint amdgpu_sdma_phase_quantum = 32; 147 char *amdgpu_disable_cu = NULL; 148 char *amdgpu_virtual_display = NULL; 149 150 /* 151 * OverDrive(bit 14) disabled by default 152 * GFX DCS(bit 19) disabled by default 153 */ 154 uint amdgpu_pp_feature_mask = 0xfff7bfff; 155 uint amdgpu_force_long_training; 156 int amdgpu_job_hang_limit; 157 int amdgpu_lbpw = -1; 158 int amdgpu_compute_multipipe = -1; 159 int amdgpu_gpu_recovery = -1; /* auto */ 160 int amdgpu_emu_mode; 161 uint amdgpu_smu_memory_pool_size; 162 int amdgpu_smu_pptable_id = -1; 163 /* 164 * FBC (bit 0) disabled by default 165 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 166 * - With this, for multiple monitors in sync(e.g. with the same model), 167 * mclk switching will be allowed. And the mclk will be not foced to the 168 * highest. That helps saving some idle power. 169 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 170 * PSR (bit 3) disabled by default 171 * EDP NO POWER SEQUENCING (bit 4) disabled by default 172 */ 173 uint amdgpu_dc_feature_mask = 2; 174 uint amdgpu_dc_debug_mask; 175 uint amdgpu_dc_visual_confirm; 176 int amdgpu_async_gfx_ring = 1; 177 int amdgpu_mcbp; 178 int amdgpu_discovery = -1; 179 int amdgpu_mes; 180 int amdgpu_mes_kiq; 181 int amdgpu_noretry = -1; 182 int amdgpu_force_asic_type = -1; 183 int amdgpu_tmz = -1; /* auto */ 184 uint amdgpu_freesync_vid_mode; 185 int amdgpu_reset_method = -1; /* auto */ 186 int amdgpu_num_kcq = -1; 187 int amdgpu_smartshift_bias; 188 int amdgpu_use_xgmi_p2p = 1; 189 int amdgpu_vcnfw_log; 190 191 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 192 193 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 194 "DRM_UT_CORE", 195 "DRM_UT_DRIVER", 196 "DRM_UT_KMS", 197 "DRM_UT_PRIME", 198 "DRM_UT_ATOMIC", 199 "DRM_UT_VBL", 200 "DRM_UT_STATE", 201 "DRM_UT_LEASE", 202 "DRM_UT_DP", 203 "DRM_UT_DRMRES"); 204 205 struct amdgpu_mgpu_info mgpu_info = { 206 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 207 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 208 mgpu_info.delayed_reset_work, 209 amdgpu_drv_delayed_reset_work_handler, 0), 210 }; 211 int amdgpu_ras_enable = -1; 212 uint amdgpu_ras_mask = 0xffffffff; 213 int amdgpu_bad_page_threshold = -1; 214 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 215 .timeout_fatal_disable = false, 216 .period = 0x0, /* default to 0x0 (timeout disable) */ 217 }; 218 219 /** 220 * DOC: vramlimit (int) 221 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 222 */ 223 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 224 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 225 226 /** 227 * DOC: vis_vramlimit (int) 228 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 229 */ 230 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 231 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 232 233 /** 234 * DOC: gartsize (uint) 235 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 236 * The default is -1 (The size depends on asic). 237 */ 238 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 239 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 240 241 /** 242 * DOC: gttsize (int) 243 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 244 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 245 */ 246 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 247 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 248 249 /** 250 * DOC: moverate (int) 251 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 252 */ 253 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 254 module_param_named(moverate, amdgpu_moverate, int, 0600); 255 256 /** 257 * DOC: audio (int) 258 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 259 */ 260 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 261 module_param_named(audio, amdgpu_audio, int, 0444); 262 263 /** 264 * DOC: disp_priority (int) 265 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 266 */ 267 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 268 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 269 270 /** 271 * DOC: hw_i2c (int) 272 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 273 */ 274 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 275 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 276 277 /** 278 * DOC: pcie_gen2 (int) 279 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 280 */ 281 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 282 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 283 284 /** 285 * DOC: msi (int) 286 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 287 */ 288 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 289 module_param_named(msi, amdgpu_msi, int, 0444); 290 291 /** 292 * DOC: lockup_timeout (string) 293 * Set GPU scheduler timeout value in ms. 294 * 295 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 296 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 297 * to the default timeout. 298 * 299 * - With one value specified, the setting will apply to all non-compute jobs. 300 * - With multiple values specified, the first one will be for GFX. 301 * The second one is for Compute. The third and fourth ones are 302 * for SDMA and Video. 303 * 304 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 305 * jobs is 10000. The timeout for compute is 60000. 306 */ 307 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 308 "for passthrough or sriov, 10000 for all jobs." 309 " 0: keep default value. negative: infinity timeout), " 310 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 311 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 312 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 313 314 /** 315 * DOC: dpm (int) 316 * Override for dynamic power management setting 317 * (0 = disable, 1 = enable) 318 * The default is -1 (auto). 319 */ 320 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 321 module_param_named(dpm, amdgpu_dpm, int, 0444); 322 323 /** 324 * DOC: fw_load_type (int) 325 * Set different firmware loading type for debugging, if supported. 326 * Set to 0 to force direct loading if supported by the ASIC. Set 327 * to -1 to select the default loading mode for the ASIC, as defined 328 * by the driver. The default is -1 (auto). 329 */ 330 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 331 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 332 333 /** 334 * DOC: aspm (int) 335 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 336 */ 337 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 338 module_param_named(aspm, amdgpu_aspm, int, 0444); 339 340 /** 341 * DOC: runpm (int) 342 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 343 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 344 * Setting the value to 0 disables this functionality. 345 */ 346 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 347 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 348 349 /** 350 * DOC: ip_block_mask (uint) 351 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 352 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 353 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 354 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 355 */ 356 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 357 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 358 359 /** 360 * DOC: bapm (int) 361 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 362 * The default -1 (auto, enabled) 363 */ 364 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 365 module_param_named(bapm, amdgpu_bapm, int, 0444); 366 367 /** 368 * DOC: deep_color (int) 369 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 370 */ 371 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 372 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 373 374 /** 375 * DOC: vm_size (int) 376 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 377 */ 378 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 379 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 380 381 /** 382 * DOC: vm_fragment_size (int) 383 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 384 */ 385 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 386 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 387 388 /** 389 * DOC: vm_block_size (int) 390 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 391 */ 392 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 393 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 394 395 /** 396 * DOC: vm_fault_stop (int) 397 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 398 */ 399 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 400 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 401 402 /** 403 * DOC: vm_debug (int) 404 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 405 */ 406 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 407 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 408 409 /** 410 * DOC: vm_update_mode (int) 411 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 412 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 413 */ 414 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 415 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 416 417 /** 418 * DOC: exp_hw_support (int) 419 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 420 */ 421 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 422 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 423 424 /** 425 * DOC: dc (int) 426 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 427 */ 428 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 429 module_param_named(dc, amdgpu_dc, int, 0444); 430 431 /** 432 * DOC: sched_jobs (int) 433 * Override the max number of jobs supported in the sw queue. The default is 32. 434 */ 435 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 436 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 437 438 /** 439 * DOC: sched_hw_submission (int) 440 * Override the max number of HW submissions. The default is 2. 441 */ 442 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 443 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 444 445 /** 446 * DOC: ppfeaturemask (hexint) 447 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 448 * The default is the current set of stable power features. 449 */ 450 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 451 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 452 453 /** 454 * DOC: forcelongtraining (uint) 455 * Force long memory training in resume. 456 * The default is zero, indicates short training in resume. 457 */ 458 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 459 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 460 461 /** 462 * DOC: pcie_gen_cap (uint) 463 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 464 * The default is 0 (automatic for each asic). 465 */ 466 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 467 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 468 469 /** 470 * DOC: pcie_lane_cap (uint) 471 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 472 * The default is 0 (automatic for each asic). 473 */ 474 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 475 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 476 477 /** 478 * DOC: cg_mask (ullong) 479 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 480 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 481 */ 482 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 483 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 484 485 /** 486 * DOC: pg_mask (uint) 487 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 488 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 489 */ 490 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 491 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 492 493 /** 494 * DOC: sdma_phase_quantum (uint) 495 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 496 */ 497 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 498 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 499 500 /** 501 * DOC: disable_cu (charp) 502 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 503 */ 504 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 505 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 506 507 /** 508 * DOC: virtual_display (charp) 509 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 510 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 511 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 512 * device at 26:00.0. The default is NULL. 513 */ 514 MODULE_PARM_DESC(virtual_display, 515 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 516 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 517 518 /** 519 * DOC: job_hang_limit (int) 520 * Set how much time allow a job hang and not drop it. The default is 0. 521 */ 522 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 523 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 524 525 /** 526 * DOC: lbpw (int) 527 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 528 */ 529 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 530 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 531 532 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 533 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 534 535 /** 536 * DOC: gpu_recovery (int) 537 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 538 */ 539 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 540 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 541 542 /** 543 * DOC: emu_mode (int) 544 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 545 */ 546 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 547 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 548 549 /** 550 * DOC: ras_enable (int) 551 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 552 */ 553 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 554 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 555 556 /** 557 * DOC: ras_mask (uint) 558 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 559 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 560 */ 561 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 562 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 563 564 /** 565 * DOC: timeout_fatal_disable (bool) 566 * Disable Watchdog timeout fatal error event 567 */ 568 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 569 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 570 571 /** 572 * DOC: timeout_period (uint) 573 * Modify the watchdog timeout max_cycles as (1 << period) 574 */ 575 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 576 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 577 578 /** 579 * DOC: si_support (int) 580 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 581 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 582 * otherwise using amdgpu driver. 583 */ 584 #ifdef CONFIG_DRM_AMDGPU_SI 585 586 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 587 int amdgpu_si_support = 0; 588 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 589 #else 590 int amdgpu_si_support = 1; 591 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 592 #endif 593 594 module_param_named(si_support, amdgpu_si_support, int, 0444); 595 #endif 596 597 /** 598 * DOC: cik_support (int) 599 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 600 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 601 * otherwise using amdgpu driver. 602 */ 603 #ifdef CONFIG_DRM_AMDGPU_CIK 604 605 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 606 int amdgpu_cik_support = 0; 607 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 608 #else 609 int amdgpu_cik_support = 1; 610 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 611 #endif 612 613 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 614 #endif 615 616 /** 617 * DOC: smu_memory_pool_size (uint) 618 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 619 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 620 */ 621 MODULE_PARM_DESC(smu_memory_pool_size, 622 "reserve gtt for smu debug usage, 0 = disable," 623 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 624 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 625 626 /** 627 * DOC: async_gfx_ring (int) 628 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 629 */ 630 MODULE_PARM_DESC(async_gfx_ring, 631 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 632 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 633 634 /** 635 * DOC: mcbp (int) 636 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 637 */ 638 MODULE_PARM_DESC(mcbp, 639 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 640 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 641 642 /** 643 * DOC: discovery (int) 644 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 645 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 646 */ 647 MODULE_PARM_DESC(discovery, 648 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 649 module_param_named(discovery, amdgpu_discovery, int, 0444); 650 651 /** 652 * DOC: mes (int) 653 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 654 * (0 = disabled (default), 1 = enabled) 655 */ 656 MODULE_PARM_DESC(mes, 657 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 658 module_param_named(mes, amdgpu_mes, int, 0444); 659 660 /** 661 * DOC: mes_kiq (int) 662 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 663 * (0 = disabled (default), 1 = enabled) 664 */ 665 MODULE_PARM_DESC(mes_kiq, 666 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 667 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 668 669 /** 670 * DOC: noretry (int) 671 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 672 * do not support per-process XNACK this also disables retry page faults. 673 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 674 */ 675 MODULE_PARM_DESC(noretry, 676 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 677 module_param_named(noretry, amdgpu_noretry, int, 0644); 678 679 /** 680 * DOC: force_asic_type (int) 681 * A non negative value used to specify the asic type for all supported GPUs. 682 */ 683 MODULE_PARM_DESC(force_asic_type, 684 "A non negative value used to specify the asic type for all supported GPUs"); 685 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 686 687 /** 688 * DOC: use_xgmi_p2p (int) 689 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 690 */ 691 MODULE_PARM_DESC(use_xgmi_p2p, 692 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 693 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 694 695 696 #ifdef CONFIG_HSA_AMD 697 /** 698 * DOC: sched_policy (int) 699 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 700 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 701 * assigns queues to HQDs. 702 */ 703 int sched_policy = KFD_SCHED_POLICY_HWS; 704 module_param(sched_policy, int, 0444); 705 MODULE_PARM_DESC(sched_policy, 706 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 707 708 /** 709 * DOC: hws_max_conc_proc (int) 710 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 711 * number of VMIDs assigned to the HWS, which is also the default. 712 */ 713 int hws_max_conc_proc = -1; 714 module_param(hws_max_conc_proc, int, 0444); 715 MODULE_PARM_DESC(hws_max_conc_proc, 716 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 717 718 /** 719 * DOC: cwsr_enable (int) 720 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 721 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 722 * disables it. 723 */ 724 int cwsr_enable = 1; 725 module_param(cwsr_enable, int, 0444); 726 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 727 728 /** 729 * DOC: max_num_of_queues_per_device (int) 730 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 731 * is 4096. 732 */ 733 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 734 module_param(max_num_of_queues_per_device, int, 0444); 735 MODULE_PARM_DESC(max_num_of_queues_per_device, 736 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 737 738 /** 739 * DOC: send_sigterm (int) 740 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 741 * but just print errors on dmesg. Setting 1 enables sending sigterm. 742 */ 743 int send_sigterm; 744 module_param(send_sigterm, int, 0444); 745 MODULE_PARM_DESC(send_sigterm, 746 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 747 748 /** 749 * DOC: debug_largebar (int) 750 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 751 * system. This limits the VRAM size reported to ROCm applications to the visible 752 * size, usually 256MB. 753 * Default value is 0, diabled. 754 */ 755 int debug_largebar; 756 module_param(debug_largebar, int, 0444); 757 MODULE_PARM_DESC(debug_largebar, 758 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 759 760 /** 761 * DOC: ignore_crat (int) 762 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 763 * table to get information about AMD APUs. This option can serve as a workaround on 764 * systems with a broken CRAT table. 765 * 766 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 767 * whether use CRAT) 768 */ 769 int ignore_crat; 770 module_param(ignore_crat, int, 0444); 771 MODULE_PARM_DESC(ignore_crat, 772 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 773 774 /** 775 * DOC: halt_if_hws_hang (int) 776 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 777 * Setting 1 enables halt on hang. 778 */ 779 int halt_if_hws_hang; 780 module_param(halt_if_hws_hang, int, 0644); 781 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 782 783 /** 784 * DOC: hws_gws_support(bool) 785 * Assume that HWS supports GWS barriers regardless of what firmware version 786 * check says. Default value: false (rely on MEC2 firmware version check). 787 */ 788 bool hws_gws_support; 789 module_param(hws_gws_support, bool, 0444); 790 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 791 792 /** 793 * DOC: queue_preemption_timeout_ms (int) 794 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 795 */ 796 int queue_preemption_timeout_ms = 9000; 797 module_param(queue_preemption_timeout_ms, int, 0644); 798 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 799 800 /** 801 * DOC: debug_evictions(bool) 802 * Enable extra debug messages to help determine the cause of evictions 803 */ 804 bool debug_evictions; 805 module_param(debug_evictions, bool, 0644); 806 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 807 808 /** 809 * DOC: no_system_mem_limit(bool) 810 * Disable system memory limit, to support multiple process shared memory 811 */ 812 bool no_system_mem_limit; 813 module_param(no_system_mem_limit, bool, 0644); 814 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 815 816 /** 817 * DOC: no_queue_eviction_on_vm_fault (int) 818 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 819 */ 820 int amdgpu_no_queue_eviction_on_vm_fault = 0; 821 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 822 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 823 #endif 824 825 /** 826 * DOC: pcie_p2p (bool) 827 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 828 */ 829 #ifdef CONFIG_HSA_AMD_P2P 830 bool pcie_p2p = true; 831 module_param(pcie_p2p, bool, 0444); 832 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 833 #endif 834 835 /** 836 * DOC: dcfeaturemask (uint) 837 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 838 * The default is the current set of stable display features. 839 */ 840 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 841 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 842 843 /** 844 * DOC: dcdebugmask (uint) 845 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 846 */ 847 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 848 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 849 850 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 851 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 852 853 /** 854 * DOC: abmlevel (uint) 855 * Override the default ABM (Adaptive Backlight Management) level used for DC 856 * enabled hardware. Requires DMCU to be supported and loaded. 857 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 858 * default. Values 1-4 control the maximum allowable brightness reduction via 859 * the ABM algorithm, with 1 being the least reduction and 4 being the most 860 * reduction. 861 * 862 * Defaults to 0, or disabled. Userspace can still override this level later 863 * after boot. 864 */ 865 uint amdgpu_dm_abm_level; 866 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 867 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 868 869 int amdgpu_backlight = -1; 870 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 871 module_param_named(backlight, amdgpu_backlight, bint, 0444); 872 873 /** 874 * DOC: tmz (int) 875 * Trusted Memory Zone (TMZ) is a method to protect data being written 876 * to or read from memory. 877 * 878 * The default value: 0 (off). TODO: change to auto till it is completed. 879 */ 880 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 881 module_param_named(tmz, amdgpu_tmz, int, 0444); 882 883 /** 884 * DOC: freesync_video (uint) 885 * Enable the optimization to adjust front porch timing to achieve seamless 886 * mode change experience when setting a freesync supported mode for which full 887 * modeset is not needed. 888 * 889 * The Display Core will add a set of modes derived from the base FreeSync 890 * video mode into the corresponding connector's mode list based on commonly 891 * used refresh rates and VRR range of the connected display, when users enable 892 * this feature. From the userspace perspective, they can see a seamless mode 893 * change experience when the change between different refresh rates under the 894 * same resolution. Additionally, userspace applications such as Video playback 895 * can read this modeset list and change the refresh rate based on the video 896 * frame rate. Finally, the userspace can also derive an appropriate mode for a 897 * particular refresh rate based on the FreeSync Mode and add it to the 898 * connector's mode list. 899 * 900 * Note: This is an experimental feature. 901 * 902 * The default value: 0 (off). 903 */ 904 MODULE_PARM_DESC( 905 freesync_video, 906 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 907 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 908 909 /** 910 * DOC: reset_method (int) 911 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 912 */ 913 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 914 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 915 916 /** 917 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 918 * threshold value of faulty pages detected by RAS ECC, which may 919 * result in the GPU entering bad status when the number of total 920 * faulty pages by ECC exceeds the threshold value. 921 */ 922 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 923 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 924 925 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 926 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 927 928 /** 929 * DOC: vcnfw_log (int) 930 * Enable vcnfw log output for debugging, the default is disabled. 931 */ 932 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 933 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 934 935 /** 936 * DOC: smu_pptable_id (int) 937 * Used to override pptable id. id = 0 use VBIOS pptable. 938 * id > 0 use the soft pptable with specicfied id. 939 */ 940 MODULE_PARM_DESC(smu_pptable_id, 941 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 942 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 943 944 /* These devices are not supported by amdgpu. 945 * They are supported by the mach64, r128, radeon drivers 946 */ 947 static const u16 amdgpu_unsupported_pciidlist[] = { 948 /* mach64 */ 949 0x4354, 950 0x4358, 951 0x4554, 952 0x4742, 953 0x4744, 954 0x4749, 955 0x474C, 956 0x474D, 957 0x474E, 958 0x474F, 959 0x4750, 960 0x4751, 961 0x4752, 962 0x4753, 963 0x4754, 964 0x4755, 965 0x4756, 966 0x4757, 967 0x4758, 968 0x4759, 969 0x475A, 970 0x4C42, 971 0x4C44, 972 0x4C47, 973 0x4C49, 974 0x4C4D, 975 0x4C4E, 976 0x4C50, 977 0x4C51, 978 0x4C52, 979 0x4C53, 980 0x5654, 981 0x5655, 982 0x5656, 983 /* r128 */ 984 0x4c45, 985 0x4c46, 986 0x4d46, 987 0x4d4c, 988 0x5041, 989 0x5042, 990 0x5043, 991 0x5044, 992 0x5045, 993 0x5046, 994 0x5047, 995 0x5048, 996 0x5049, 997 0x504A, 998 0x504B, 999 0x504C, 1000 0x504D, 1001 0x504E, 1002 0x504F, 1003 0x5050, 1004 0x5051, 1005 0x5052, 1006 0x5053, 1007 0x5054, 1008 0x5055, 1009 0x5056, 1010 0x5057, 1011 0x5058, 1012 0x5245, 1013 0x5246, 1014 0x5247, 1015 0x524b, 1016 0x524c, 1017 0x534d, 1018 0x5446, 1019 0x544C, 1020 0x5452, 1021 /* radeon */ 1022 0x3150, 1023 0x3151, 1024 0x3152, 1025 0x3154, 1026 0x3155, 1027 0x3E50, 1028 0x3E54, 1029 0x4136, 1030 0x4137, 1031 0x4144, 1032 0x4145, 1033 0x4146, 1034 0x4147, 1035 0x4148, 1036 0x4149, 1037 0x414A, 1038 0x414B, 1039 0x4150, 1040 0x4151, 1041 0x4152, 1042 0x4153, 1043 0x4154, 1044 0x4155, 1045 0x4156, 1046 0x4237, 1047 0x4242, 1048 0x4336, 1049 0x4337, 1050 0x4437, 1051 0x4966, 1052 0x4967, 1053 0x4A48, 1054 0x4A49, 1055 0x4A4A, 1056 0x4A4B, 1057 0x4A4C, 1058 0x4A4D, 1059 0x4A4E, 1060 0x4A4F, 1061 0x4A50, 1062 0x4A54, 1063 0x4B48, 1064 0x4B49, 1065 0x4B4A, 1066 0x4B4B, 1067 0x4B4C, 1068 0x4C57, 1069 0x4C58, 1070 0x4C59, 1071 0x4C5A, 1072 0x4C64, 1073 0x4C66, 1074 0x4C67, 1075 0x4E44, 1076 0x4E45, 1077 0x4E46, 1078 0x4E47, 1079 0x4E48, 1080 0x4E49, 1081 0x4E4A, 1082 0x4E4B, 1083 0x4E50, 1084 0x4E51, 1085 0x4E52, 1086 0x4E53, 1087 0x4E54, 1088 0x4E56, 1089 0x5144, 1090 0x5145, 1091 0x5146, 1092 0x5147, 1093 0x5148, 1094 0x514C, 1095 0x514D, 1096 0x5157, 1097 0x5158, 1098 0x5159, 1099 0x515A, 1100 0x515E, 1101 0x5460, 1102 0x5462, 1103 0x5464, 1104 0x5548, 1105 0x5549, 1106 0x554A, 1107 0x554B, 1108 0x554C, 1109 0x554D, 1110 0x554E, 1111 0x554F, 1112 0x5550, 1113 0x5551, 1114 0x5552, 1115 0x5554, 1116 0x564A, 1117 0x564B, 1118 0x564F, 1119 0x5652, 1120 0x5653, 1121 0x5657, 1122 0x5834, 1123 0x5835, 1124 0x5954, 1125 0x5955, 1126 0x5974, 1127 0x5975, 1128 0x5960, 1129 0x5961, 1130 0x5962, 1131 0x5964, 1132 0x5965, 1133 0x5969, 1134 0x5a41, 1135 0x5a42, 1136 0x5a61, 1137 0x5a62, 1138 0x5b60, 1139 0x5b62, 1140 0x5b63, 1141 0x5b64, 1142 0x5b65, 1143 0x5c61, 1144 0x5c63, 1145 0x5d48, 1146 0x5d49, 1147 0x5d4a, 1148 0x5d4c, 1149 0x5d4d, 1150 0x5d4e, 1151 0x5d4f, 1152 0x5d50, 1153 0x5d52, 1154 0x5d57, 1155 0x5e48, 1156 0x5e4a, 1157 0x5e4b, 1158 0x5e4c, 1159 0x5e4d, 1160 0x5e4f, 1161 0x6700, 1162 0x6701, 1163 0x6702, 1164 0x6703, 1165 0x6704, 1166 0x6705, 1167 0x6706, 1168 0x6707, 1169 0x6708, 1170 0x6709, 1171 0x6718, 1172 0x6719, 1173 0x671c, 1174 0x671d, 1175 0x671f, 1176 0x6720, 1177 0x6721, 1178 0x6722, 1179 0x6723, 1180 0x6724, 1181 0x6725, 1182 0x6726, 1183 0x6727, 1184 0x6728, 1185 0x6729, 1186 0x6738, 1187 0x6739, 1188 0x673e, 1189 0x6740, 1190 0x6741, 1191 0x6742, 1192 0x6743, 1193 0x6744, 1194 0x6745, 1195 0x6746, 1196 0x6747, 1197 0x6748, 1198 0x6749, 1199 0x674A, 1200 0x6750, 1201 0x6751, 1202 0x6758, 1203 0x6759, 1204 0x675B, 1205 0x675D, 1206 0x675F, 1207 0x6760, 1208 0x6761, 1209 0x6762, 1210 0x6763, 1211 0x6764, 1212 0x6765, 1213 0x6766, 1214 0x6767, 1215 0x6768, 1216 0x6770, 1217 0x6771, 1218 0x6772, 1219 0x6778, 1220 0x6779, 1221 0x677B, 1222 0x6840, 1223 0x6841, 1224 0x6842, 1225 0x6843, 1226 0x6849, 1227 0x684C, 1228 0x6850, 1229 0x6858, 1230 0x6859, 1231 0x6880, 1232 0x6888, 1233 0x6889, 1234 0x688A, 1235 0x688C, 1236 0x688D, 1237 0x6898, 1238 0x6899, 1239 0x689b, 1240 0x689c, 1241 0x689d, 1242 0x689e, 1243 0x68a0, 1244 0x68a1, 1245 0x68a8, 1246 0x68a9, 1247 0x68b0, 1248 0x68b8, 1249 0x68b9, 1250 0x68ba, 1251 0x68be, 1252 0x68bf, 1253 0x68c0, 1254 0x68c1, 1255 0x68c7, 1256 0x68c8, 1257 0x68c9, 1258 0x68d8, 1259 0x68d9, 1260 0x68da, 1261 0x68de, 1262 0x68e0, 1263 0x68e1, 1264 0x68e4, 1265 0x68e5, 1266 0x68e8, 1267 0x68e9, 1268 0x68f1, 1269 0x68f2, 1270 0x68f8, 1271 0x68f9, 1272 0x68fa, 1273 0x68fe, 1274 0x7100, 1275 0x7101, 1276 0x7102, 1277 0x7103, 1278 0x7104, 1279 0x7105, 1280 0x7106, 1281 0x7108, 1282 0x7109, 1283 0x710A, 1284 0x710B, 1285 0x710C, 1286 0x710E, 1287 0x710F, 1288 0x7140, 1289 0x7141, 1290 0x7142, 1291 0x7143, 1292 0x7144, 1293 0x7145, 1294 0x7146, 1295 0x7147, 1296 0x7149, 1297 0x714A, 1298 0x714B, 1299 0x714C, 1300 0x714D, 1301 0x714E, 1302 0x714F, 1303 0x7151, 1304 0x7152, 1305 0x7153, 1306 0x715E, 1307 0x715F, 1308 0x7180, 1309 0x7181, 1310 0x7183, 1311 0x7186, 1312 0x7187, 1313 0x7188, 1314 0x718A, 1315 0x718B, 1316 0x718C, 1317 0x718D, 1318 0x718F, 1319 0x7193, 1320 0x7196, 1321 0x719B, 1322 0x719F, 1323 0x71C0, 1324 0x71C1, 1325 0x71C2, 1326 0x71C3, 1327 0x71C4, 1328 0x71C5, 1329 0x71C6, 1330 0x71C7, 1331 0x71CD, 1332 0x71CE, 1333 0x71D2, 1334 0x71D4, 1335 0x71D5, 1336 0x71D6, 1337 0x71DA, 1338 0x71DE, 1339 0x7200, 1340 0x7210, 1341 0x7211, 1342 0x7240, 1343 0x7243, 1344 0x7244, 1345 0x7245, 1346 0x7246, 1347 0x7247, 1348 0x7248, 1349 0x7249, 1350 0x724A, 1351 0x724B, 1352 0x724C, 1353 0x724D, 1354 0x724E, 1355 0x724F, 1356 0x7280, 1357 0x7281, 1358 0x7283, 1359 0x7284, 1360 0x7287, 1361 0x7288, 1362 0x7289, 1363 0x728B, 1364 0x728C, 1365 0x7290, 1366 0x7291, 1367 0x7293, 1368 0x7297, 1369 0x7834, 1370 0x7835, 1371 0x791e, 1372 0x791f, 1373 0x793f, 1374 0x7941, 1375 0x7942, 1376 0x796c, 1377 0x796d, 1378 0x796e, 1379 0x796f, 1380 0x9400, 1381 0x9401, 1382 0x9402, 1383 0x9403, 1384 0x9405, 1385 0x940A, 1386 0x940B, 1387 0x940F, 1388 0x94A0, 1389 0x94A1, 1390 0x94A3, 1391 0x94B1, 1392 0x94B3, 1393 0x94B4, 1394 0x94B5, 1395 0x94B9, 1396 0x9440, 1397 0x9441, 1398 0x9442, 1399 0x9443, 1400 0x9444, 1401 0x9446, 1402 0x944A, 1403 0x944B, 1404 0x944C, 1405 0x944E, 1406 0x9450, 1407 0x9452, 1408 0x9456, 1409 0x945A, 1410 0x945B, 1411 0x945E, 1412 0x9460, 1413 0x9462, 1414 0x946A, 1415 0x946B, 1416 0x947A, 1417 0x947B, 1418 0x9480, 1419 0x9487, 1420 0x9488, 1421 0x9489, 1422 0x948A, 1423 0x948F, 1424 0x9490, 1425 0x9491, 1426 0x9495, 1427 0x9498, 1428 0x949C, 1429 0x949E, 1430 0x949F, 1431 0x94C0, 1432 0x94C1, 1433 0x94C3, 1434 0x94C4, 1435 0x94C5, 1436 0x94C6, 1437 0x94C7, 1438 0x94C8, 1439 0x94C9, 1440 0x94CB, 1441 0x94CC, 1442 0x94CD, 1443 0x9500, 1444 0x9501, 1445 0x9504, 1446 0x9505, 1447 0x9506, 1448 0x9507, 1449 0x9508, 1450 0x9509, 1451 0x950F, 1452 0x9511, 1453 0x9515, 1454 0x9517, 1455 0x9519, 1456 0x9540, 1457 0x9541, 1458 0x9542, 1459 0x954E, 1460 0x954F, 1461 0x9552, 1462 0x9553, 1463 0x9555, 1464 0x9557, 1465 0x955f, 1466 0x9580, 1467 0x9581, 1468 0x9583, 1469 0x9586, 1470 0x9587, 1471 0x9588, 1472 0x9589, 1473 0x958A, 1474 0x958B, 1475 0x958C, 1476 0x958D, 1477 0x958E, 1478 0x958F, 1479 0x9590, 1480 0x9591, 1481 0x9593, 1482 0x9595, 1483 0x9596, 1484 0x9597, 1485 0x9598, 1486 0x9599, 1487 0x959B, 1488 0x95C0, 1489 0x95C2, 1490 0x95C4, 1491 0x95C5, 1492 0x95C6, 1493 0x95C7, 1494 0x95C9, 1495 0x95CC, 1496 0x95CD, 1497 0x95CE, 1498 0x95CF, 1499 0x9610, 1500 0x9611, 1501 0x9612, 1502 0x9613, 1503 0x9614, 1504 0x9615, 1505 0x9616, 1506 0x9640, 1507 0x9641, 1508 0x9642, 1509 0x9643, 1510 0x9644, 1511 0x9645, 1512 0x9647, 1513 0x9648, 1514 0x9649, 1515 0x964a, 1516 0x964b, 1517 0x964c, 1518 0x964e, 1519 0x964f, 1520 0x9710, 1521 0x9711, 1522 0x9712, 1523 0x9713, 1524 0x9714, 1525 0x9715, 1526 0x9802, 1527 0x9803, 1528 0x9804, 1529 0x9805, 1530 0x9806, 1531 0x9807, 1532 0x9808, 1533 0x9809, 1534 0x980A, 1535 0x9900, 1536 0x9901, 1537 0x9903, 1538 0x9904, 1539 0x9905, 1540 0x9906, 1541 0x9907, 1542 0x9908, 1543 0x9909, 1544 0x990A, 1545 0x990B, 1546 0x990C, 1547 0x990D, 1548 0x990E, 1549 0x990F, 1550 0x9910, 1551 0x9913, 1552 0x9917, 1553 0x9918, 1554 0x9919, 1555 0x9990, 1556 0x9991, 1557 0x9992, 1558 0x9993, 1559 0x9994, 1560 0x9995, 1561 0x9996, 1562 0x9997, 1563 0x9998, 1564 0x9999, 1565 0x999A, 1566 0x999B, 1567 0x999C, 1568 0x999D, 1569 0x99A0, 1570 0x99A2, 1571 0x99A4, 1572 /* radeon secondary ids */ 1573 0x3171, 1574 0x3e70, 1575 0x4164, 1576 0x4165, 1577 0x4166, 1578 0x4168, 1579 0x4170, 1580 0x4171, 1581 0x4172, 1582 0x4173, 1583 0x496e, 1584 0x4a69, 1585 0x4a6a, 1586 0x4a6b, 1587 0x4a70, 1588 0x4a74, 1589 0x4b69, 1590 0x4b6b, 1591 0x4b6c, 1592 0x4c6e, 1593 0x4e64, 1594 0x4e65, 1595 0x4e66, 1596 0x4e67, 1597 0x4e68, 1598 0x4e69, 1599 0x4e6a, 1600 0x4e71, 1601 0x4f73, 1602 0x5569, 1603 0x556b, 1604 0x556d, 1605 0x556f, 1606 0x5571, 1607 0x5854, 1608 0x5874, 1609 0x5940, 1610 0x5941, 1611 0x5b72, 1612 0x5b73, 1613 0x5b74, 1614 0x5b75, 1615 0x5d44, 1616 0x5d45, 1617 0x5d6d, 1618 0x5d6f, 1619 0x5d72, 1620 0x5d77, 1621 0x5e6b, 1622 0x5e6d, 1623 0x7120, 1624 0x7124, 1625 0x7129, 1626 0x712e, 1627 0x712f, 1628 0x7162, 1629 0x7163, 1630 0x7166, 1631 0x7167, 1632 0x7172, 1633 0x7173, 1634 0x71a0, 1635 0x71a1, 1636 0x71a3, 1637 0x71a7, 1638 0x71bb, 1639 0x71e0, 1640 0x71e1, 1641 0x71e2, 1642 0x71e6, 1643 0x71e7, 1644 0x71f2, 1645 0x7269, 1646 0x726b, 1647 0x726e, 1648 0x72a0, 1649 0x72a8, 1650 0x72b1, 1651 0x72b3, 1652 0x793f, 1653 }; 1654 1655 static const struct pci_device_id pciidlist[] = { 1656 #ifdef CONFIG_DRM_AMDGPU_SI 1657 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1658 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1659 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1660 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1661 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1662 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1663 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1664 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1665 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1666 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1668 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1669 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1670 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1671 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1674 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1675 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1676 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1677 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1678 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1679 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1680 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1681 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1682 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1683 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1684 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1685 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1689 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1690 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1691 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1692 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1693 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1694 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1699 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1700 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1701 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1708 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1709 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1710 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1711 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1712 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1717 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1718 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1719 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1720 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1721 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1722 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1723 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1728 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1729 #endif 1730 #ifdef CONFIG_DRM_AMDGPU_CIK 1731 /* Kaveri */ 1732 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1733 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1734 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1735 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1736 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1737 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1743 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1744 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1745 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1746 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1747 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1748 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1749 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1752 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1753 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1754 /* Bonaire */ 1755 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1757 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1758 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1759 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1760 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1761 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1762 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1763 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1764 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1765 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1766 /* Hawaii */ 1767 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1768 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1769 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1770 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1771 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1772 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1773 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1774 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1775 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1776 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1777 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1778 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1779 /* Kabini */ 1780 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1782 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1783 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1784 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1785 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1786 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1787 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1788 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1789 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1790 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1791 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1792 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1793 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1794 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1795 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1796 /* mullins */ 1797 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1798 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1800 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1801 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1802 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1803 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1804 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1805 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1806 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 #endif 1814 /* topaz */ 1815 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1816 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1817 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1818 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1819 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1820 /* tonga */ 1821 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1822 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1823 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1824 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1825 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1826 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1827 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1828 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1829 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1830 /* fiji */ 1831 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1832 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1833 /* carrizo */ 1834 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1835 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1836 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1837 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1838 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1839 /* stoney */ 1840 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1841 /* Polaris11 */ 1842 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1843 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1844 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1845 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1846 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1847 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1848 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1849 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1850 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1851 /* Polaris10 */ 1852 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1853 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1854 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1855 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1856 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1857 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1858 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1859 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1860 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1861 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1863 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1864 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1865 /* Polaris12 */ 1866 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1867 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1868 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1869 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1870 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1871 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1872 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1873 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1874 /* VEGAM */ 1875 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1876 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1877 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1878 /* Vega 10 */ 1879 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1880 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1881 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1882 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1883 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1884 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1885 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1886 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1887 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1888 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1893 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1894 /* Vega 12 */ 1895 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1896 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1897 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1898 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1899 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1900 /* Vega 20 */ 1901 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1902 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1903 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1904 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1905 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1906 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1907 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1908 /* Raven */ 1909 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1910 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1911 /* Arcturus */ 1912 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1913 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1914 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1915 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1916 /* Navi10 */ 1917 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1918 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1919 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1920 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1921 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1922 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1923 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1924 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1925 /* Navi14 */ 1926 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1927 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1928 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1929 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1930 1931 /* Renoir */ 1932 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1933 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1934 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1935 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1936 1937 /* Navi12 */ 1938 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1939 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1940 1941 /* Sienna_Cichlid */ 1942 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1943 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1944 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1945 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1946 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1947 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1948 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1949 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1950 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1951 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1953 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1954 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1955 1956 /* Yellow Carp */ 1957 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1958 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1959 1960 /* Navy_Flounder */ 1961 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1962 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1963 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1964 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1965 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1966 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1967 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1968 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1969 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1970 1971 /* DIMGREY_CAVEFISH */ 1972 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1973 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1974 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1975 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1976 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1977 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1978 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1979 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1980 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1981 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1982 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1983 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1984 1985 /* Aldebaran */ 1986 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1987 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1988 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1989 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1990 1991 /* CYAN_SKILLFISH */ 1992 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1993 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1994 1995 /* BEIGE_GOBY */ 1996 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1997 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1998 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1999 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2000 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2001 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2002 2003 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2004 .class = PCI_CLASS_DISPLAY_VGA << 8, 2005 .class_mask = 0xffffff, 2006 .driver_data = CHIP_IP_DISCOVERY }, 2007 2008 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2009 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2010 .class_mask = 0xffffff, 2011 .driver_data = CHIP_IP_DISCOVERY }, 2012 2013 {0, 0, 0} 2014 }; 2015 2016 MODULE_DEVICE_TABLE(pci, pciidlist); 2017 2018 static const struct drm_driver amdgpu_kms_driver; 2019 2020 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2021 { 2022 struct pci_dev *p = NULL; 2023 int i; 2024 2025 /* 0 - GPU 2026 * 1 - audio 2027 * 2 - USB 2028 * 3 - UCSI 2029 */ 2030 for (i = 1; i < 4; i++) { 2031 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2032 adev->pdev->bus->number, i); 2033 if (p) { 2034 pm_runtime_get_sync(&p->dev); 2035 pm_runtime_mark_last_busy(&p->dev); 2036 pm_runtime_put_autosuspend(&p->dev); 2037 pci_dev_put(p); 2038 } 2039 } 2040 } 2041 2042 static int amdgpu_pci_probe(struct pci_dev *pdev, 2043 const struct pci_device_id *ent) 2044 { 2045 struct drm_device *ddev; 2046 struct amdgpu_device *adev; 2047 unsigned long flags = ent->driver_data; 2048 int ret, retry = 0, i; 2049 bool supports_atomic = false; 2050 2051 /* skip devices which are owned by radeon */ 2052 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2053 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2054 return -ENODEV; 2055 } 2056 2057 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2058 amdgpu_aspm = 0; 2059 2060 if (amdgpu_virtual_display || 2061 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2062 supports_atomic = true; 2063 2064 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2065 DRM_INFO("This hardware requires experimental hardware support.\n" 2066 "See modparam exp_hw_support\n"); 2067 return -ENODEV; 2068 } 2069 /* differentiate between P10 and P11 asics with the same DID */ 2070 if (pdev->device == 0x67FF && 2071 (pdev->revision == 0xE3 || 2072 pdev->revision == 0xE7 || 2073 pdev->revision == 0xF3 || 2074 pdev->revision == 0xF7)) { 2075 flags &= ~AMD_ASIC_MASK; 2076 flags |= CHIP_POLARIS10; 2077 } 2078 2079 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2080 * however, SME requires an indirect IOMMU mapping because the encryption 2081 * bit is beyond the DMA mask of the chip. 2082 */ 2083 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2084 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2085 dev_info(&pdev->dev, 2086 "SME is not compatible with RAVEN\n"); 2087 return -ENOTSUPP; 2088 } 2089 2090 #ifdef CONFIG_DRM_AMDGPU_SI 2091 if (!amdgpu_si_support) { 2092 switch (flags & AMD_ASIC_MASK) { 2093 case CHIP_TAHITI: 2094 case CHIP_PITCAIRN: 2095 case CHIP_VERDE: 2096 case CHIP_OLAND: 2097 case CHIP_HAINAN: 2098 dev_info(&pdev->dev, 2099 "SI support provided by radeon.\n"); 2100 dev_info(&pdev->dev, 2101 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2102 ); 2103 return -ENODEV; 2104 } 2105 } 2106 #endif 2107 #ifdef CONFIG_DRM_AMDGPU_CIK 2108 if (!amdgpu_cik_support) { 2109 switch (flags & AMD_ASIC_MASK) { 2110 case CHIP_KAVERI: 2111 case CHIP_BONAIRE: 2112 case CHIP_HAWAII: 2113 case CHIP_KABINI: 2114 case CHIP_MULLINS: 2115 dev_info(&pdev->dev, 2116 "CIK support provided by radeon.\n"); 2117 dev_info(&pdev->dev, 2118 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2119 ); 2120 return -ENODEV; 2121 } 2122 } 2123 #endif 2124 2125 /* Get rid of things like offb */ 2126 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2127 if (ret) 2128 return ret; 2129 2130 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2131 if (IS_ERR(adev)) 2132 return PTR_ERR(adev); 2133 2134 adev->dev = &pdev->dev; 2135 adev->pdev = pdev; 2136 ddev = adev_to_drm(adev); 2137 2138 if (!supports_atomic) 2139 ddev->driver_features &= ~DRIVER_ATOMIC; 2140 2141 ret = pci_enable_device(pdev); 2142 if (ret) 2143 return ret; 2144 2145 pci_set_drvdata(pdev, ddev); 2146 2147 ret = amdgpu_driver_load_kms(adev, flags); 2148 if (ret) 2149 goto err_pci; 2150 2151 retry_init: 2152 ret = drm_dev_register(ddev, flags); 2153 if (ret == -EAGAIN && ++retry <= 3) { 2154 DRM_INFO("retry init %d\n", retry); 2155 /* Don't request EX mode too frequently which is attacking */ 2156 msleep(5000); 2157 goto retry_init; 2158 } else if (ret) { 2159 goto err_pci; 2160 } 2161 2162 /* 2163 * 1. don't init fbdev on hw without DCE 2164 * 2. don't init fbdev if there are no connectors 2165 */ 2166 if (adev->mode_info.mode_config_initialized && 2167 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2168 /* select 8 bpp console on low vram cards */ 2169 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2170 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2171 else 2172 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2173 } 2174 2175 ret = amdgpu_debugfs_init(adev); 2176 if (ret) 2177 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2178 2179 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2180 /* only need to skip on ATPX */ 2181 if (amdgpu_device_supports_px(ddev)) 2182 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2183 /* we want direct complete for BOCO */ 2184 if (amdgpu_device_supports_boco(ddev)) 2185 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2186 DPM_FLAG_SMART_SUSPEND | 2187 DPM_FLAG_MAY_SKIP_RESUME); 2188 pm_runtime_use_autosuspend(ddev->dev); 2189 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2190 2191 pm_runtime_allow(ddev->dev); 2192 2193 pm_runtime_mark_last_busy(ddev->dev); 2194 pm_runtime_put_autosuspend(ddev->dev); 2195 2196 /* 2197 * For runpm implemented via BACO, PMFW will handle the 2198 * timing for BACO in and out: 2199 * - put ASIC into BACO state only when both video and 2200 * audio functions are in D3 state. 2201 * - pull ASIC out of BACO state when either video or 2202 * audio function is in D0 state. 2203 * Also, at startup, PMFW assumes both functions are in 2204 * D0 state. 2205 * 2206 * So if snd driver was loaded prior to amdgpu driver 2207 * and audio function was put into D3 state, there will 2208 * be no PMFW-aware D-state transition(D0->D3) on runpm 2209 * suspend. Thus the BACO will be not correctly kicked in. 2210 * 2211 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2212 * into D0 state. Then there will be a PMFW-aware D-state 2213 * transition(D0->D3) on runpm suspend. 2214 */ 2215 if (amdgpu_device_supports_baco(ddev) && 2216 !(adev->flags & AMD_IS_APU) && 2217 (adev->asic_type >= CHIP_NAVI10)) 2218 amdgpu_get_secondary_funcs(adev); 2219 } 2220 2221 return 0; 2222 2223 err_pci: 2224 pci_disable_device(pdev); 2225 return ret; 2226 } 2227 2228 static void 2229 amdgpu_pci_remove(struct pci_dev *pdev) 2230 { 2231 struct drm_device *dev = pci_get_drvdata(pdev); 2232 struct amdgpu_device *adev = drm_to_adev(dev); 2233 2234 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2235 pm_runtime_get_sync(dev->dev); 2236 pm_runtime_forbid(dev->dev); 2237 } 2238 2239 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2240 !amdgpu_sriov_vf(adev)) { 2241 bool need_to_reset_gpu = false; 2242 2243 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2244 struct amdgpu_hive_info *hive; 2245 2246 hive = amdgpu_get_xgmi_hive(adev); 2247 if (hive->device_remove_count == 0) 2248 need_to_reset_gpu = true; 2249 hive->device_remove_count++; 2250 amdgpu_put_xgmi_hive(hive); 2251 } else { 2252 need_to_reset_gpu = true; 2253 } 2254 2255 /* Workaround for ASICs need to reset SMU. 2256 * Called only when the first device is removed. 2257 */ 2258 if (need_to_reset_gpu) { 2259 struct amdgpu_reset_context reset_context; 2260 2261 adev->shutdown = true; 2262 memset(&reset_context, 0, sizeof(reset_context)); 2263 reset_context.method = AMD_RESET_METHOD_NONE; 2264 reset_context.reset_req_dev = adev; 2265 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2266 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2267 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2268 } 2269 } 2270 2271 amdgpu_driver_unload_kms(dev); 2272 2273 drm_dev_unplug(dev); 2274 2275 /* 2276 * Flush any in flight DMA operations from device. 2277 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2278 * StatusTransactions Pending bit. 2279 */ 2280 pci_disable_device(pdev); 2281 pci_wait_for_pending_transaction(pdev); 2282 } 2283 2284 static void 2285 amdgpu_pci_shutdown(struct pci_dev *pdev) 2286 { 2287 struct drm_device *dev = pci_get_drvdata(pdev); 2288 struct amdgpu_device *adev = drm_to_adev(dev); 2289 2290 if (amdgpu_ras_intr_triggered()) 2291 return; 2292 2293 /* if we are running in a VM, make sure the device 2294 * torn down properly on reboot/shutdown. 2295 * unfortunately we can't detect certain 2296 * hypervisors so just do this all the time. 2297 */ 2298 if (!amdgpu_passthrough(adev)) 2299 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2300 amdgpu_device_ip_suspend(adev); 2301 adev->mp1_state = PP_MP1_STATE_NONE; 2302 } 2303 2304 /** 2305 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2306 * 2307 * @work: work_struct. 2308 */ 2309 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2310 { 2311 struct list_head device_list; 2312 struct amdgpu_device *adev; 2313 int i, r; 2314 struct amdgpu_reset_context reset_context; 2315 2316 memset(&reset_context, 0, sizeof(reset_context)); 2317 2318 mutex_lock(&mgpu_info.mutex); 2319 if (mgpu_info.pending_reset == true) { 2320 mutex_unlock(&mgpu_info.mutex); 2321 return; 2322 } 2323 mgpu_info.pending_reset = true; 2324 mutex_unlock(&mgpu_info.mutex); 2325 2326 /* Use a common context, just need to make sure full reset is done */ 2327 reset_context.method = AMD_RESET_METHOD_NONE; 2328 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2329 2330 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2331 adev = mgpu_info.gpu_ins[i].adev; 2332 reset_context.reset_req_dev = adev; 2333 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2334 if (r) { 2335 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2336 r, adev_to_drm(adev)->unique); 2337 } 2338 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2339 r = -EALREADY; 2340 } 2341 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2342 adev = mgpu_info.gpu_ins[i].adev; 2343 flush_work(&adev->xgmi_reset_work); 2344 adev->gmc.xgmi.pending_reset = false; 2345 } 2346 2347 /* reset function will rebuild the xgmi hive info , clear it now */ 2348 for (i = 0; i < mgpu_info.num_dgpu; i++) 2349 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2350 2351 INIT_LIST_HEAD(&device_list); 2352 2353 for (i = 0; i < mgpu_info.num_dgpu; i++) 2354 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2355 2356 /* unregister the GPU first, reset function will add them back */ 2357 list_for_each_entry(adev, &device_list, reset_list) 2358 amdgpu_unregister_gpu_instance(adev); 2359 2360 /* Use a common context, just need to make sure full reset is done */ 2361 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2362 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2363 2364 if (r) { 2365 DRM_ERROR("reinit gpus failure"); 2366 return; 2367 } 2368 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2369 adev = mgpu_info.gpu_ins[i].adev; 2370 if (!adev->kfd.init_complete) 2371 amdgpu_amdkfd_device_init(adev); 2372 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2373 } 2374 return; 2375 } 2376 2377 static int amdgpu_pmops_prepare(struct device *dev) 2378 { 2379 struct drm_device *drm_dev = dev_get_drvdata(dev); 2380 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2381 2382 /* Return a positive number here so 2383 * DPM_FLAG_SMART_SUSPEND works properly 2384 */ 2385 if (amdgpu_device_supports_boco(drm_dev)) 2386 return pm_runtime_suspended(dev); 2387 2388 /* if we will not support s3 or s2i for the device 2389 * then skip suspend 2390 */ 2391 if (!amdgpu_acpi_is_s0ix_active(adev) && 2392 !amdgpu_acpi_is_s3_active(adev)) 2393 return 1; 2394 2395 return 0; 2396 } 2397 2398 static void amdgpu_pmops_complete(struct device *dev) 2399 { 2400 /* nothing to do */ 2401 } 2402 2403 static int amdgpu_pmops_suspend(struct device *dev) 2404 { 2405 struct drm_device *drm_dev = dev_get_drvdata(dev); 2406 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2407 2408 if (amdgpu_acpi_is_s0ix_active(adev)) 2409 adev->in_s0ix = true; 2410 else 2411 adev->in_s3 = true; 2412 return amdgpu_device_suspend(drm_dev, true); 2413 } 2414 2415 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2416 { 2417 struct drm_device *drm_dev = dev_get_drvdata(dev); 2418 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2419 2420 if (amdgpu_acpi_should_gpu_reset(adev)) 2421 return amdgpu_asic_reset(adev); 2422 2423 return 0; 2424 } 2425 2426 static int amdgpu_pmops_resume(struct device *dev) 2427 { 2428 struct drm_device *drm_dev = dev_get_drvdata(dev); 2429 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2430 int r; 2431 2432 /* Avoids registers access if device is physically gone */ 2433 if (!pci_device_is_present(adev->pdev)) 2434 adev->no_hw_access = true; 2435 2436 r = amdgpu_device_resume(drm_dev, true); 2437 if (amdgpu_acpi_is_s0ix_active(adev)) 2438 adev->in_s0ix = false; 2439 else 2440 adev->in_s3 = false; 2441 return r; 2442 } 2443 2444 static int amdgpu_pmops_freeze(struct device *dev) 2445 { 2446 struct drm_device *drm_dev = dev_get_drvdata(dev); 2447 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2448 int r; 2449 2450 adev->in_s4 = true; 2451 r = amdgpu_device_suspend(drm_dev, true); 2452 adev->in_s4 = false; 2453 if (r) 2454 return r; 2455 return amdgpu_asic_reset(adev); 2456 } 2457 2458 static int amdgpu_pmops_thaw(struct device *dev) 2459 { 2460 struct drm_device *drm_dev = dev_get_drvdata(dev); 2461 2462 return amdgpu_device_resume(drm_dev, true); 2463 } 2464 2465 static int amdgpu_pmops_poweroff(struct device *dev) 2466 { 2467 struct drm_device *drm_dev = dev_get_drvdata(dev); 2468 2469 return amdgpu_device_suspend(drm_dev, true); 2470 } 2471 2472 static int amdgpu_pmops_restore(struct device *dev) 2473 { 2474 struct drm_device *drm_dev = dev_get_drvdata(dev); 2475 2476 return amdgpu_device_resume(drm_dev, true); 2477 } 2478 2479 static int amdgpu_runtime_idle_check_display(struct device *dev) 2480 { 2481 struct pci_dev *pdev = to_pci_dev(dev); 2482 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2483 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2484 2485 if (adev->mode_info.num_crtc) { 2486 struct drm_connector *list_connector; 2487 struct drm_connector_list_iter iter; 2488 int ret = 0; 2489 2490 /* XXX: Return busy if any displays are connected to avoid 2491 * possible display wakeups after runtime resume due to 2492 * hotplug events in case any displays were connected while 2493 * the GPU was in suspend. Remove this once that is fixed. 2494 */ 2495 mutex_lock(&drm_dev->mode_config.mutex); 2496 drm_connector_list_iter_begin(drm_dev, &iter); 2497 drm_for_each_connector_iter(list_connector, &iter) { 2498 if (list_connector->status == connector_status_connected) { 2499 ret = -EBUSY; 2500 break; 2501 } 2502 } 2503 drm_connector_list_iter_end(&iter); 2504 mutex_unlock(&drm_dev->mode_config.mutex); 2505 2506 if (ret) 2507 return ret; 2508 2509 if (adev->dc_enabled) { 2510 struct drm_crtc *crtc; 2511 2512 drm_for_each_crtc(crtc, drm_dev) { 2513 drm_modeset_lock(&crtc->mutex, NULL); 2514 if (crtc->state->active) 2515 ret = -EBUSY; 2516 drm_modeset_unlock(&crtc->mutex); 2517 if (ret < 0) 2518 break; 2519 } 2520 } else { 2521 mutex_lock(&drm_dev->mode_config.mutex); 2522 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2523 2524 drm_connector_list_iter_begin(drm_dev, &iter); 2525 drm_for_each_connector_iter(list_connector, &iter) { 2526 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2527 ret = -EBUSY; 2528 break; 2529 } 2530 } 2531 2532 drm_connector_list_iter_end(&iter); 2533 2534 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2535 mutex_unlock(&drm_dev->mode_config.mutex); 2536 } 2537 if (ret) 2538 return ret; 2539 } 2540 2541 return 0; 2542 } 2543 2544 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2545 { 2546 struct pci_dev *pdev = to_pci_dev(dev); 2547 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2548 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2549 int ret, i; 2550 2551 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2552 pm_runtime_forbid(dev); 2553 return -EBUSY; 2554 } 2555 2556 ret = amdgpu_runtime_idle_check_display(dev); 2557 if (ret) 2558 return ret; 2559 2560 /* wait for all rings to drain before suspending */ 2561 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2562 struct amdgpu_ring *ring = adev->rings[i]; 2563 if (ring && ring->sched.ready) { 2564 ret = amdgpu_fence_wait_empty(ring); 2565 if (ret) 2566 return -EBUSY; 2567 } 2568 } 2569 2570 adev->in_runpm = true; 2571 if (amdgpu_device_supports_px(drm_dev)) 2572 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2573 2574 /* 2575 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2576 * proper cleanups and put itself into a state ready for PNP. That 2577 * can address some random resuming failure observed on BOCO capable 2578 * platforms. 2579 * TODO: this may be also needed for PX capable platform. 2580 */ 2581 if (amdgpu_device_supports_boco(drm_dev)) 2582 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2583 2584 ret = amdgpu_device_suspend(drm_dev, false); 2585 if (ret) { 2586 adev->in_runpm = false; 2587 if (amdgpu_device_supports_boco(drm_dev)) 2588 adev->mp1_state = PP_MP1_STATE_NONE; 2589 return ret; 2590 } 2591 2592 if (amdgpu_device_supports_boco(drm_dev)) 2593 adev->mp1_state = PP_MP1_STATE_NONE; 2594 2595 if (amdgpu_device_supports_px(drm_dev)) { 2596 /* Only need to handle PCI state in the driver for ATPX 2597 * PCI core handles it for _PR3. 2598 */ 2599 amdgpu_device_cache_pci_state(pdev); 2600 pci_disable_device(pdev); 2601 pci_ignore_hotplug(pdev); 2602 pci_set_power_state(pdev, PCI_D3cold); 2603 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2604 } else if (amdgpu_device_supports_boco(drm_dev)) { 2605 /* nothing to do */ 2606 } else if (amdgpu_device_supports_baco(drm_dev)) { 2607 amdgpu_device_baco_enter(drm_dev); 2608 } 2609 2610 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2611 2612 return 0; 2613 } 2614 2615 static int amdgpu_pmops_runtime_resume(struct device *dev) 2616 { 2617 struct pci_dev *pdev = to_pci_dev(dev); 2618 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2619 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2620 int ret; 2621 2622 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2623 return -EINVAL; 2624 2625 /* Avoids registers access if device is physically gone */ 2626 if (!pci_device_is_present(adev->pdev)) 2627 adev->no_hw_access = true; 2628 2629 if (amdgpu_device_supports_px(drm_dev)) { 2630 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2631 2632 /* Only need to handle PCI state in the driver for ATPX 2633 * PCI core handles it for _PR3. 2634 */ 2635 pci_set_power_state(pdev, PCI_D0); 2636 amdgpu_device_load_pci_state(pdev); 2637 ret = pci_enable_device(pdev); 2638 if (ret) 2639 return ret; 2640 pci_set_master(pdev); 2641 } else if (amdgpu_device_supports_boco(drm_dev)) { 2642 /* Only need to handle PCI state in the driver for ATPX 2643 * PCI core handles it for _PR3. 2644 */ 2645 pci_set_master(pdev); 2646 } else if (amdgpu_device_supports_baco(drm_dev)) { 2647 amdgpu_device_baco_exit(drm_dev); 2648 } 2649 ret = amdgpu_device_resume(drm_dev, false); 2650 if (ret) { 2651 if (amdgpu_device_supports_px(drm_dev)) 2652 pci_disable_device(pdev); 2653 return ret; 2654 } 2655 2656 if (amdgpu_device_supports_px(drm_dev)) 2657 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2658 adev->in_runpm = false; 2659 return 0; 2660 } 2661 2662 static int amdgpu_pmops_runtime_idle(struct device *dev) 2663 { 2664 struct drm_device *drm_dev = dev_get_drvdata(dev); 2665 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2666 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2667 int ret = 1; 2668 2669 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2670 pm_runtime_forbid(dev); 2671 return -EBUSY; 2672 } 2673 2674 ret = amdgpu_runtime_idle_check_display(dev); 2675 2676 pm_runtime_mark_last_busy(dev); 2677 pm_runtime_autosuspend(dev); 2678 return ret; 2679 } 2680 2681 long amdgpu_drm_ioctl(struct file *filp, 2682 unsigned int cmd, unsigned long arg) 2683 { 2684 struct drm_file *file_priv = filp->private_data; 2685 struct drm_device *dev; 2686 long ret; 2687 dev = file_priv->minor->dev; 2688 ret = pm_runtime_get_sync(dev->dev); 2689 if (ret < 0) 2690 goto out; 2691 2692 ret = drm_ioctl(filp, cmd, arg); 2693 2694 pm_runtime_mark_last_busy(dev->dev); 2695 out: 2696 pm_runtime_put_autosuspend(dev->dev); 2697 return ret; 2698 } 2699 2700 static const struct dev_pm_ops amdgpu_pm_ops = { 2701 .prepare = amdgpu_pmops_prepare, 2702 .complete = amdgpu_pmops_complete, 2703 .suspend = amdgpu_pmops_suspend, 2704 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2705 .resume = amdgpu_pmops_resume, 2706 .freeze = amdgpu_pmops_freeze, 2707 .thaw = amdgpu_pmops_thaw, 2708 .poweroff = amdgpu_pmops_poweroff, 2709 .restore = amdgpu_pmops_restore, 2710 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2711 .runtime_resume = amdgpu_pmops_runtime_resume, 2712 .runtime_idle = amdgpu_pmops_runtime_idle, 2713 }; 2714 2715 static int amdgpu_flush(struct file *f, fl_owner_t id) 2716 { 2717 struct drm_file *file_priv = f->private_data; 2718 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2719 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2720 2721 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2722 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2723 2724 return timeout >= 0 ? 0 : timeout; 2725 } 2726 2727 static const struct file_operations amdgpu_driver_kms_fops = { 2728 .owner = THIS_MODULE, 2729 .open = drm_open, 2730 .flush = amdgpu_flush, 2731 .release = drm_release, 2732 .unlocked_ioctl = amdgpu_drm_ioctl, 2733 .mmap = drm_gem_mmap, 2734 .poll = drm_poll, 2735 .read = drm_read, 2736 #ifdef CONFIG_COMPAT 2737 .compat_ioctl = amdgpu_kms_compat_ioctl, 2738 #endif 2739 #ifdef CONFIG_PROC_FS 2740 .show_fdinfo = amdgpu_show_fdinfo 2741 #endif 2742 }; 2743 2744 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2745 { 2746 struct drm_file *file; 2747 2748 if (!filp) 2749 return -EINVAL; 2750 2751 if (filp->f_op != &amdgpu_driver_kms_fops) { 2752 return -EINVAL; 2753 } 2754 2755 file = filp->private_data; 2756 *fpriv = file->driver_priv; 2757 return 0; 2758 } 2759 2760 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2761 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2762 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2763 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2764 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2765 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2766 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2767 /* KMS */ 2768 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2769 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2770 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2771 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2772 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2773 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2774 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2775 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2776 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2777 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2778 }; 2779 2780 static const struct drm_driver amdgpu_kms_driver = { 2781 .driver_features = 2782 DRIVER_ATOMIC | 2783 DRIVER_GEM | 2784 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2785 DRIVER_SYNCOBJ_TIMELINE, 2786 .open = amdgpu_driver_open_kms, 2787 .postclose = amdgpu_driver_postclose_kms, 2788 .lastclose = amdgpu_driver_lastclose_kms, 2789 .ioctls = amdgpu_ioctls_kms, 2790 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2791 .dumb_create = amdgpu_mode_dumb_create, 2792 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2793 .fops = &amdgpu_driver_kms_fops, 2794 .release = &amdgpu_driver_release_kms, 2795 2796 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2797 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2798 .gem_prime_import = amdgpu_gem_prime_import, 2799 .gem_prime_mmap = drm_gem_prime_mmap, 2800 2801 .name = DRIVER_NAME, 2802 .desc = DRIVER_DESC, 2803 .date = DRIVER_DATE, 2804 .major = KMS_DRIVER_MAJOR, 2805 .minor = KMS_DRIVER_MINOR, 2806 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2807 }; 2808 2809 static struct pci_error_handlers amdgpu_pci_err_handler = { 2810 .error_detected = amdgpu_pci_error_detected, 2811 .mmio_enabled = amdgpu_pci_mmio_enabled, 2812 .slot_reset = amdgpu_pci_slot_reset, 2813 .resume = amdgpu_pci_resume, 2814 }; 2815 2816 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2817 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2818 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2819 2820 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2821 &amdgpu_vram_mgr_attr_group, 2822 &amdgpu_gtt_mgr_attr_group, 2823 &amdgpu_vbios_version_attr_group, 2824 NULL, 2825 }; 2826 2827 2828 static struct pci_driver amdgpu_kms_pci_driver = { 2829 .name = DRIVER_NAME, 2830 .id_table = pciidlist, 2831 .probe = amdgpu_pci_probe, 2832 .remove = amdgpu_pci_remove, 2833 .shutdown = amdgpu_pci_shutdown, 2834 .driver.pm = &amdgpu_pm_ops, 2835 .err_handler = &amdgpu_pci_err_handler, 2836 .dev_groups = amdgpu_sysfs_groups, 2837 }; 2838 2839 static int __init amdgpu_init(void) 2840 { 2841 int r; 2842 2843 if (drm_firmware_drivers_only()) 2844 return -EINVAL; 2845 2846 r = amdgpu_sync_init(); 2847 if (r) 2848 goto error_sync; 2849 2850 r = amdgpu_fence_slab_init(); 2851 if (r) 2852 goto error_fence; 2853 2854 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2855 amdgpu_register_atpx_handler(); 2856 amdgpu_acpi_detect(); 2857 2858 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2859 amdgpu_amdkfd_init(); 2860 2861 /* let modprobe override vga console setting */ 2862 return pci_register_driver(&amdgpu_kms_pci_driver); 2863 2864 error_fence: 2865 amdgpu_sync_fini(); 2866 2867 error_sync: 2868 return r; 2869 } 2870 2871 static void __exit amdgpu_exit(void) 2872 { 2873 amdgpu_amdkfd_fini(); 2874 pci_unregister_driver(&amdgpu_kms_pci_driver); 2875 amdgpu_unregister_atpx_handler(); 2876 amdgpu_sync_fini(); 2877 amdgpu_fence_slab_fini(); 2878 mmu_notifier_synchronize(); 2879 } 2880 2881 module_init(amdgpu_init); 2882 module_exit(amdgpu_exit); 2883 2884 MODULE_AUTHOR(DRIVER_AUTHOR); 2885 MODULE_DESCRIPTION(DRIVER_DESC); 2886 MODULE_LICENSE("GPL and additional rights"); 2887