1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 * - 3.42.0 - Add 16bpc fixed point display support 99 * - 3.43.0 - Add device hot plug/unplug support 100 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 101 * - 3.45.0 - Add context ioctl stable pstate interface 102 * * 3.46.0 - To enable hot plug amdgpu tests in libdrm 103 */ 104 #define KMS_DRIVER_MAJOR 3 105 #define KMS_DRIVER_MINOR 46 106 #define KMS_DRIVER_PATCHLEVEL 0 107 108 int amdgpu_vram_limit; 109 int amdgpu_vis_vram_limit; 110 int amdgpu_gart_size = -1; /* auto */ 111 int amdgpu_gtt_size = -1; /* auto */ 112 int amdgpu_moverate = -1; /* auto */ 113 int amdgpu_audio = -1; 114 int amdgpu_disp_priority; 115 int amdgpu_hw_i2c; 116 int amdgpu_pcie_gen2 = -1; 117 int amdgpu_msi = -1; 118 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 119 int amdgpu_dpm = -1; 120 int amdgpu_fw_load_type = -1; 121 int amdgpu_aspm = -1; 122 int amdgpu_runtime_pm = -1; 123 uint amdgpu_ip_block_mask = 0xffffffff; 124 int amdgpu_bapm = -1; 125 int amdgpu_deep_color; 126 int amdgpu_vm_size = -1; 127 int amdgpu_vm_fragment_size = -1; 128 int amdgpu_vm_block_size = -1; 129 int amdgpu_vm_fault_stop; 130 int amdgpu_vm_debug; 131 int amdgpu_vm_update_mode = -1; 132 int amdgpu_exp_hw_support; 133 int amdgpu_dc = -1; 134 int amdgpu_sched_jobs = 32; 135 int amdgpu_sched_hw_submission = 2; 136 uint amdgpu_pcie_gen_cap; 137 uint amdgpu_pcie_lane_cap; 138 u64 amdgpu_cg_mask = 0xffffffffffffffff; 139 uint amdgpu_pg_mask = 0xffffffff; 140 uint amdgpu_sdma_phase_quantum = 32; 141 char *amdgpu_disable_cu = NULL; 142 char *amdgpu_virtual_display = NULL; 143 144 /* 145 * OverDrive(bit 14) disabled by default 146 * GFX DCS(bit 19) disabled by default 147 */ 148 uint amdgpu_pp_feature_mask = 0xfff7bfff; 149 uint amdgpu_force_long_training; 150 int amdgpu_job_hang_limit; 151 int amdgpu_lbpw = -1; 152 int amdgpu_compute_multipipe = -1; 153 int amdgpu_gpu_recovery = -1; /* auto */ 154 int amdgpu_emu_mode; 155 uint amdgpu_smu_memory_pool_size; 156 int amdgpu_smu_pptable_id = -1; 157 /* 158 * FBC (bit 0) disabled by default 159 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 160 * - With this, for multiple monitors in sync(e.g. with the same model), 161 * mclk switching will be allowed. And the mclk will be not foced to the 162 * highest. That helps saving some idle power. 163 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 164 * PSR (bit 3) disabled by default 165 * EDP NO POWER SEQUENCING (bit 4) disabled by default 166 */ 167 uint amdgpu_dc_feature_mask = 2; 168 uint amdgpu_dc_debug_mask; 169 int amdgpu_async_gfx_ring = 1; 170 int amdgpu_mcbp; 171 int amdgpu_discovery = -1; 172 int amdgpu_mes; 173 int amdgpu_mes_kiq; 174 int amdgpu_noretry = -1; 175 int amdgpu_force_asic_type = -1; 176 int amdgpu_tmz = -1; /* auto */ 177 int amdgpu_reset_method = -1; /* auto */ 178 int amdgpu_num_kcq = -1; 179 int amdgpu_smartshift_bias; 180 int amdgpu_use_xgmi_p2p = 1; 181 int amdgpu_vcnfw_log; 182 183 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 184 185 struct amdgpu_mgpu_info mgpu_info = { 186 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 187 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 188 mgpu_info.delayed_reset_work, 189 amdgpu_drv_delayed_reset_work_handler, 0), 190 }; 191 int amdgpu_ras_enable = -1; 192 uint amdgpu_ras_mask = 0xffffffff; 193 int amdgpu_bad_page_threshold = -1; 194 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 195 .timeout_fatal_disable = false, 196 .period = 0x0, /* default to 0x0 (timeout disable) */ 197 }; 198 199 /** 200 * DOC: vramlimit (int) 201 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 202 */ 203 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 204 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 205 206 /** 207 * DOC: vis_vramlimit (int) 208 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 209 */ 210 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 211 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 212 213 /** 214 * DOC: gartsize (uint) 215 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 216 */ 217 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 218 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 219 220 /** 221 * DOC: gttsize (int) 222 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 223 * otherwise 3/4 RAM size). 224 */ 225 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 226 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 227 228 /** 229 * DOC: moverate (int) 230 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 231 */ 232 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 233 module_param_named(moverate, amdgpu_moverate, int, 0600); 234 235 /** 236 * DOC: audio (int) 237 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 238 */ 239 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 240 module_param_named(audio, amdgpu_audio, int, 0444); 241 242 /** 243 * DOC: disp_priority (int) 244 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 245 */ 246 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 247 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 248 249 /** 250 * DOC: hw_i2c (int) 251 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 252 */ 253 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 254 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 255 256 /** 257 * DOC: pcie_gen2 (int) 258 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 259 */ 260 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 261 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 262 263 /** 264 * DOC: msi (int) 265 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 266 */ 267 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 268 module_param_named(msi, amdgpu_msi, int, 0444); 269 270 /** 271 * DOC: lockup_timeout (string) 272 * Set GPU scheduler timeout value in ms. 273 * 274 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 275 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 276 * to the default timeout. 277 * 278 * - With one value specified, the setting will apply to all non-compute jobs. 279 * - With multiple values specified, the first one will be for GFX. 280 * The second one is for Compute. The third and fourth ones are 281 * for SDMA and Video. 282 * 283 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 284 * jobs is 10000. The timeout for compute is 60000. 285 */ 286 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 287 "for passthrough or sriov, 10000 for all jobs." 288 " 0: keep default value. negative: infinity timeout), " 289 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 290 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 291 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 292 293 /** 294 * DOC: dpm (int) 295 * Override for dynamic power management setting 296 * (0 = disable, 1 = enable) 297 * The default is -1 (auto). 298 */ 299 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 300 module_param_named(dpm, amdgpu_dpm, int, 0444); 301 302 /** 303 * DOC: fw_load_type (int) 304 * Set different firmware loading type for debugging, if supported. 305 * Set to 0 to force direct loading if supported by the ASIC. Set 306 * to -1 to select the default loading mode for the ASIC, as defined 307 * by the driver. The default is -1 (auto). 308 */ 309 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 310 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 311 312 /** 313 * DOC: aspm (int) 314 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 315 */ 316 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 317 module_param_named(aspm, amdgpu_aspm, int, 0444); 318 319 /** 320 * DOC: runpm (int) 321 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 322 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 323 * Setting the value to 0 disables this functionality. 324 */ 325 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 326 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 327 328 /** 329 * DOC: ip_block_mask (uint) 330 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 331 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 332 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 333 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 334 */ 335 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 336 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 337 338 /** 339 * DOC: bapm (int) 340 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 341 * The default -1 (auto, enabled) 342 */ 343 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 344 module_param_named(bapm, amdgpu_bapm, int, 0444); 345 346 /** 347 * DOC: deep_color (int) 348 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 349 */ 350 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 351 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 352 353 /** 354 * DOC: vm_size (int) 355 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 356 */ 357 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 358 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 359 360 /** 361 * DOC: vm_fragment_size (int) 362 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 363 */ 364 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 365 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 366 367 /** 368 * DOC: vm_block_size (int) 369 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 370 */ 371 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 372 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 373 374 /** 375 * DOC: vm_fault_stop (int) 376 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 377 */ 378 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 379 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 380 381 /** 382 * DOC: vm_debug (int) 383 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 384 */ 385 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 386 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 387 388 /** 389 * DOC: vm_update_mode (int) 390 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 391 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 392 */ 393 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 394 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 395 396 /** 397 * DOC: exp_hw_support (int) 398 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 399 */ 400 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 401 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 402 403 /** 404 * DOC: dc (int) 405 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 406 */ 407 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 408 module_param_named(dc, amdgpu_dc, int, 0444); 409 410 /** 411 * DOC: sched_jobs (int) 412 * Override the max number of jobs supported in the sw queue. The default is 32. 413 */ 414 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 415 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 416 417 /** 418 * DOC: sched_hw_submission (int) 419 * Override the max number of HW submissions. The default is 2. 420 */ 421 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 422 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 423 424 /** 425 * DOC: ppfeaturemask (hexint) 426 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 427 * The default is the current set of stable power features. 428 */ 429 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 430 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 431 432 /** 433 * DOC: forcelongtraining (uint) 434 * Force long memory training in resume. 435 * The default is zero, indicates short training in resume. 436 */ 437 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 438 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 439 440 /** 441 * DOC: pcie_gen_cap (uint) 442 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 443 * The default is 0 (automatic for each asic). 444 */ 445 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 446 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 447 448 /** 449 * DOC: pcie_lane_cap (uint) 450 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 451 * The default is 0 (automatic for each asic). 452 */ 453 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 454 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 455 456 /** 457 * DOC: cg_mask (ullong) 458 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 459 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 460 */ 461 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 462 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 463 464 /** 465 * DOC: pg_mask (uint) 466 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 467 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 468 */ 469 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 470 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 471 472 /** 473 * DOC: sdma_phase_quantum (uint) 474 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 475 */ 476 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 477 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 478 479 /** 480 * DOC: disable_cu (charp) 481 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 482 */ 483 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 484 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 485 486 /** 487 * DOC: virtual_display (charp) 488 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 489 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 490 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 491 * device at 26:00.0. The default is NULL. 492 */ 493 MODULE_PARM_DESC(virtual_display, 494 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 495 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 496 497 /** 498 * DOC: job_hang_limit (int) 499 * Set how much time allow a job hang and not drop it. The default is 0. 500 */ 501 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 502 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 503 504 /** 505 * DOC: lbpw (int) 506 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 507 */ 508 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 509 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 510 511 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 512 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 513 514 /** 515 * DOC: gpu_recovery (int) 516 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 517 */ 518 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 519 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 520 521 /** 522 * DOC: emu_mode (int) 523 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 524 */ 525 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 526 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 527 528 /** 529 * DOC: ras_enable (int) 530 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 531 */ 532 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 533 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 534 535 /** 536 * DOC: ras_mask (uint) 537 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 538 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 539 */ 540 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 541 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 542 543 /** 544 * DOC: timeout_fatal_disable (bool) 545 * Disable Watchdog timeout fatal error event 546 */ 547 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 548 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 549 550 /** 551 * DOC: timeout_period (uint) 552 * Modify the watchdog timeout max_cycles as (1 << period) 553 */ 554 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 555 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 556 557 /** 558 * DOC: si_support (int) 559 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 560 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 561 * otherwise using amdgpu driver. 562 */ 563 #ifdef CONFIG_DRM_AMDGPU_SI 564 565 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 566 int amdgpu_si_support = 0; 567 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 568 #else 569 int amdgpu_si_support = 1; 570 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 571 #endif 572 573 module_param_named(si_support, amdgpu_si_support, int, 0444); 574 #endif 575 576 /** 577 * DOC: cik_support (int) 578 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 580 * otherwise using amdgpu driver. 581 */ 582 #ifdef CONFIG_DRM_AMDGPU_CIK 583 584 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 585 int amdgpu_cik_support = 0; 586 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 587 #else 588 int amdgpu_cik_support = 1; 589 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 590 #endif 591 592 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 593 #endif 594 595 /** 596 * DOC: smu_memory_pool_size (uint) 597 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 598 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 599 */ 600 MODULE_PARM_DESC(smu_memory_pool_size, 601 "reserve gtt for smu debug usage, 0 = disable," 602 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 603 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 604 605 /** 606 * DOC: async_gfx_ring (int) 607 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 608 */ 609 MODULE_PARM_DESC(async_gfx_ring, 610 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 611 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 612 613 /** 614 * DOC: mcbp (int) 615 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 616 */ 617 MODULE_PARM_DESC(mcbp, 618 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 619 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 620 621 /** 622 * DOC: discovery (int) 623 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 624 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 625 */ 626 MODULE_PARM_DESC(discovery, 627 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 628 module_param_named(discovery, amdgpu_discovery, int, 0444); 629 630 /** 631 * DOC: mes (int) 632 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 633 * (0 = disabled (default), 1 = enabled) 634 */ 635 MODULE_PARM_DESC(mes, 636 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 637 module_param_named(mes, amdgpu_mes, int, 0444); 638 639 /** 640 * DOC: mes_kiq (int) 641 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 642 * (0 = disabled (default), 1 = enabled) 643 */ 644 MODULE_PARM_DESC(mes_kiq, 645 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 646 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 647 648 /** 649 * DOC: noretry (int) 650 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 651 * do not support per-process XNACK this also disables retry page faults. 652 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 653 */ 654 MODULE_PARM_DESC(noretry, 655 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 656 module_param_named(noretry, amdgpu_noretry, int, 0644); 657 658 /** 659 * DOC: force_asic_type (int) 660 * A non negative value used to specify the asic type for all supported GPUs. 661 */ 662 MODULE_PARM_DESC(force_asic_type, 663 "A non negative value used to specify the asic type for all supported GPUs"); 664 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 665 666 /** 667 * DOC: use_xgmi_p2p (int) 668 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 669 */ 670 MODULE_PARM_DESC(use_xgmi_p2p, 671 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 672 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 673 674 675 #ifdef CONFIG_HSA_AMD 676 /** 677 * DOC: sched_policy (int) 678 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 679 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 680 * assigns queues to HQDs. 681 */ 682 int sched_policy = KFD_SCHED_POLICY_HWS; 683 module_param(sched_policy, int, 0444); 684 MODULE_PARM_DESC(sched_policy, 685 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 686 687 /** 688 * DOC: hws_max_conc_proc (int) 689 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 690 * number of VMIDs assigned to the HWS, which is also the default. 691 */ 692 int hws_max_conc_proc = -1; 693 module_param(hws_max_conc_proc, int, 0444); 694 MODULE_PARM_DESC(hws_max_conc_proc, 695 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 696 697 /** 698 * DOC: cwsr_enable (int) 699 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 700 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 701 * disables it. 702 */ 703 int cwsr_enable = 1; 704 module_param(cwsr_enable, int, 0444); 705 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 706 707 /** 708 * DOC: max_num_of_queues_per_device (int) 709 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 710 * is 4096. 711 */ 712 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 713 module_param(max_num_of_queues_per_device, int, 0444); 714 MODULE_PARM_DESC(max_num_of_queues_per_device, 715 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 716 717 /** 718 * DOC: send_sigterm (int) 719 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 720 * but just print errors on dmesg. Setting 1 enables sending sigterm. 721 */ 722 int send_sigterm; 723 module_param(send_sigterm, int, 0444); 724 MODULE_PARM_DESC(send_sigterm, 725 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 726 727 /** 728 * DOC: debug_largebar (int) 729 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 730 * system. This limits the VRAM size reported to ROCm applications to the visible 731 * size, usually 256MB. 732 * Default value is 0, diabled. 733 */ 734 int debug_largebar; 735 module_param(debug_largebar, int, 0444); 736 MODULE_PARM_DESC(debug_largebar, 737 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 738 739 /** 740 * DOC: ignore_crat (int) 741 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 742 * table to get information about AMD APUs. This option can serve as a workaround on 743 * systems with a broken CRAT table. 744 * 745 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 746 * whether use CRAT) 747 */ 748 int ignore_crat; 749 module_param(ignore_crat, int, 0444); 750 MODULE_PARM_DESC(ignore_crat, 751 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 752 753 /** 754 * DOC: halt_if_hws_hang (int) 755 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 756 * Setting 1 enables halt on hang. 757 */ 758 int halt_if_hws_hang; 759 module_param(halt_if_hws_hang, int, 0644); 760 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 761 762 /** 763 * DOC: hws_gws_support(bool) 764 * Assume that HWS supports GWS barriers regardless of what firmware version 765 * check says. Default value: false (rely on MEC2 firmware version check). 766 */ 767 bool hws_gws_support; 768 module_param(hws_gws_support, bool, 0444); 769 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 770 771 /** 772 * DOC: queue_preemption_timeout_ms (int) 773 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 774 */ 775 int queue_preemption_timeout_ms = 9000; 776 module_param(queue_preemption_timeout_ms, int, 0644); 777 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 778 779 /** 780 * DOC: debug_evictions(bool) 781 * Enable extra debug messages to help determine the cause of evictions 782 */ 783 bool debug_evictions; 784 module_param(debug_evictions, bool, 0644); 785 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 786 787 /** 788 * DOC: no_system_mem_limit(bool) 789 * Disable system memory limit, to support multiple process shared memory 790 */ 791 bool no_system_mem_limit; 792 module_param(no_system_mem_limit, bool, 0644); 793 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 794 795 /** 796 * DOC: no_queue_eviction_on_vm_fault (int) 797 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 798 */ 799 int amdgpu_no_queue_eviction_on_vm_fault = 0; 800 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 801 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 802 #endif 803 804 /** 805 * DOC: dcfeaturemask (uint) 806 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 807 * The default is the current set of stable display features. 808 */ 809 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 810 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 811 812 /** 813 * DOC: dcdebugmask (uint) 814 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 815 */ 816 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 817 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 818 819 /** 820 * DOC: abmlevel (uint) 821 * Override the default ABM (Adaptive Backlight Management) level used for DC 822 * enabled hardware. Requires DMCU to be supported and loaded. 823 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 824 * default. Values 1-4 control the maximum allowable brightness reduction via 825 * the ABM algorithm, with 1 being the least reduction and 4 being the most 826 * reduction. 827 * 828 * Defaults to 0, or disabled. Userspace can still override this level later 829 * after boot. 830 */ 831 uint amdgpu_dm_abm_level; 832 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 833 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 834 835 int amdgpu_backlight = -1; 836 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 837 module_param_named(backlight, amdgpu_backlight, bint, 0444); 838 839 /** 840 * DOC: tmz (int) 841 * Trusted Memory Zone (TMZ) is a method to protect data being written 842 * to or read from memory. 843 * 844 * The default value: 0 (off). TODO: change to auto till it is completed. 845 */ 846 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 847 module_param_named(tmz, amdgpu_tmz, int, 0444); 848 849 /** 850 * DOC: reset_method (int) 851 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 852 */ 853 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 854 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 855 856 /** 857 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 858 * threshold value of faulty pages detected by RAS ECC, which may 859 * result in the GPU entering bad status when the number of total 860 * faulty pages by ECC exceeds the threshold value. 861 */ 862 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 863 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 864 865 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 866 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 867 868 /** 869 * DOC: vcnfw_log (int) 870 * Enable vcnfw log output for debugging, the default is disabled. 871 */ 872 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 873 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 874 875 /** 876 * DOC: smu_pptable_id (int) 877 * Used to override pptable id. id = 0 use VBIOS pptable. 878 * id > 0 use the soft pptable with specicfied id. 879 */ 880 MODULE_PARM_DESC(smu_pptable_id, 881 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 882 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 883 884 /* These devices are not supported by amdgpu. 885 * They are supported by the mach64, r128, radeon drivers 886 */ 887 static const u16 amdgpu_unsupported_pciidlist[] = { 888 /* mach64 */ 889 0x4354, 890 0x4358, 891 0x4554, 892 0x4742, 893 0x4744, 894 0x4749, 895 0x474C, 896 0x474D, 897 0x474E, 898 0x474F, 899 0x4750, 900 0x4751, 901 0x4752, 902 0x4753, 903 0x4754, 904 0x4755, 905 0x4756, 906 0x4757, 907 0x4758, 908 0x4759, 909 0x475A, 910 0x4C42, 911 0x4C44, 912 0x4C47, 913 0x4C49, 914 0x4C4D, 915 0x4C4E, 916 0x4C50, 917 0x4C51, 918 0x4C52, 919 0x4C53, 920 0x5654, 921 0x5655, 922 0x5656, 923 /* r128 */ 924 0x4c45, 925 0x4c46, 926 0x4d46, 927 0x4d4c, 928 0x5041, 929 0x5042, 930 0x5043, 931 0x5044, 932 0x5045, 933 0x5046, 934 0x5047, 935 0x5048, 936 0x5049, 937 0x504A, 938 0x504B, 939 0x504C, 940 0x504D, 941 0x504E, 942 0x504F, 943 0x5050, 944 0x5051, 945 0x5052, 946 0x5053, 947 0x5054, 948 0x5055, 949 0x5056, 950 0x5057, 951 0x5058, 952 0x5245, 953 0x5246, 954 0x5247, 955 0x524b, 956 0x524c, 957 0x534d, 958 0x5446, 959 0x544C, 960 0x5452, 961 /* radeon */ 962 0x3150, 963 0x3151, 964 0x3152, 965 0x3154, 966 0x3155, 967 0x3E50, 968 0x3E54, 969 0x4136, 970 0x4137, 971 0x4144, 972 0x4145, 973 0x4146, 974 0x4147, 975 0x4148, 976 0x4149, 977 0x414A, 978 0x414B, 979 0x4150, 980 0x4151, 981 0x4152, 982 0x4153, 983 0x4154, 984 0x4155, 985 0x4156, 986 0x4237, 987 0x4242, 988 0x4336, 989 0x4337, 990 0x4437, 991 0x4966, 992 0x4967, 993 0x4A48, 994 0x4A49, 995 0x4A4A, 996 0x4A4B, 997 0x4A4C, 998 0x4A4D, 999 0x4A4E, 1000 0x4A4F, 1001 0x4A50, 1002 0x4A54, 1003 0x4B48, 1004 0x4B49, 1005 0x4B4A, 1006 0x4B4B, 1007 0x4B4C, 1008 0x4C57, 1009 0x4C58, 1010 0x4C59, 1011 0x4C5A, 1012 0x4C64, 1013 0x4C66, 1014 0x4C67, 1015 0x4E44, 1016 0x4E45, 1017 0x4E46, 1018 0x4E47, 1019 0x4E48, 1020 0x4E49, 1021 0x4E4A, 1022 0x4E4B, 1023 0x4E50, 1024 0x4E51, 1025 0x4E52, 1026 0x4E53, 1027 0x4E54, 1028 0x4E56, 1029 0x5144, 1030 0x5145, 1031 0x5146, 1032 0x5147, 1033 0x5148, 1034 0x514C, 1035 0x514D, 1036 0x5157, 1037 0x5158, 1038 0x5159, 1039 0x515A, 1040 0x515E, 1041 0x5460, 1042 0x5462, 1043 0x5464, 1044 0x5548, 1045 0x5549, 1046 0x554A, 1047 0x554B, 1048 0x554C, 1049 0x554D, 1050 0x554E, 1051 0x554F, 1052 0x5550, 1053 0x5551, 1054 0x5552, 1055 0x5554, 1056 0x564A, 1057 0x564B, 1058 0x564F, 1059 0x5652, 1060 0x5653, 1061 0x5657, 1062 0x5834, 1063 0x5835, 1064 0x5954, 1065 0x5955, 1066 0x5974, 1067 0x5975, 1068 0x5960, 1069 0x5961, 1070 0x5962, 1071 0x5964, 1072 0x5965, 1073 0x5969, 1074 0x5a41, 1075 0x5a42, 1076 0x5a61, 1077 0x5a62, 1078 0x5b60, 1079 0x5b62, 1080 0x5b63, 1081 0x5b64, 1082 0x5b65, 1083 0x5c61, 1084 0x5c63, 1085 0x5d48, 1086 0x5d49, 1087 0x5d4a, 1088 0x5d4c, 1089 0x5d4d, 1090 0x5d4e, 1091 0x5d4f, 1092 0x5d50, 1093 0x5d52, 1094 0x5d57, 1095 0x5e48, 1096 0x5e4a, 1097 0x5e4b, 1098 0x5e4c, 1099 0x5e4d, 1100 0x5e4f, 1101 0x6700, 1102 0x6701, 1103 0x6702, 1104 0x6703, 1105 0x6704, 1106 0x6705, 1107 0x6706, 1108 0x6707, 1109 0x6708, 1110 0x6709, 1111 0x6718, 1112 0x6719, 1113 0x671c, 1114 0x671d, 1115 0x671f, 1116 0x6720, 1117 0x6721, 1118 0x6722, 1119 0x6723, 1120 0x6724, 1121 0x6725, 1122 0x6726, 1123 0x6727, 1124 0x6728, 1125 0x6729, 1126 0x6738, 1127 0x6739, 1128 0x673e, 1129 0x6740, 1130 0x6741, 1131 0x6742, 1132 0x6743, 1133 0x6744, 1134 0x6745, 1135 0x6746, 1136 0x6747, 1137 0x6748, 1138 0x6749, 1139 0x674A, 1140 0x6750, 1141 0x6751, 1142 0x6758, 1143 0x6759, 1144 0x675B, 1145 0x675D, 1146 0x675F, 1147 0x6760, 1148 0x6761, 1149 0x6762, 1150 0x6763, 1151 0x6764, 1152 0x6765, 1153 0x6766, 1154 0x6767, 1155 0x6768, 1156 0x6770, 1157 0x6771, 1158 0x6772, 1159 0x6778, 1160 0x6779, 1161 0x677B, 1162 0x6840, 1163 0x6841, 1164 0x6842, 1165 0x6843, 1166 0x6849, 1167 0x684C, 1168 0x6850, 1169 0x6858, 1170 0x6859, 1171 0x6880, 1172 0x6888, 1173 0x6889, 1174 0x688A, 1175 0x688C, 1176 0x688D, 1177 0x6898, 1178 0x6899, 1179 0x689b, 1180 0x689c, 1181 0x689d, 1182 0x689e, 1183 0x68a0, 1184 0x68a1, 1185 0x68a8, 1186 0x68a9, 1187 0x68b0, 1188 0x68b8, 1189 0x68b9, 1190 0x68ba, 1191 0x68be, 1192 0x68bf, 1193 0x68c0, 1194 0x68c1, 1195 0x68c7, 1196 0x68c8, 1197 0x68c9, 1198 0x68d8, 1199 0x68d9, 1200 0x68da, 1201 0x68de, 1202 0x68e0, 1203 0x68e1, 1204 0x68e4, 1205 0x68e5, 1206 0x68e8, 1207 0x68e9, 1208 0x68f1, 1209 0x68f2, 1210 0x68f8, 1211 0x68f9, 1212 0x68fa, 1213 0x68fe, 1214 0x7100, 1215 0x7101, 1216 0x7102, 1217 0x7103, 1218 0x7104, 1219 0x7105, 1220 0x7106, 1221 0x7108, 1222 0x7109, 1223 0x710A, 1224 0x710B, 1225 0x710C, 1226 0x710E, 1227 0x710F, 1228 0x7140, 1229 0x7141, 1230 0x7142, 1231 0x7143, 1232 0x7144, 1233 0x7145, 1234 0x7146, 1235 0x7147, 1236 0x7149, 1237 0x714A, 1238 0x714B, 1239 0x714C, 1240 0x714D, 1241 0x714E, 1242 0x714F, 1243 0x7151, 1244 0x7152, 1245 0x7153, 1246 0x715E, 1247 0x715F, 1248 0x7180, 1249 0x7181, 1250 0x7183, 1251 0x7186, 1252 0x7187, 1253 0x7188, 1254 0x718A, 1255 0x718B, 1256 0x718C, 1257 0x718D, 1258 0x718F, 1259 0x7193, 1260 0x7196, 1261 0x719B, 1262 0x719F, 1263 0x71C0, 1264 0x71C1, 1265 0x71C2, 1266 0x71C3, 1267 0x71C4, 1268 0x71C5, 1269 0x71C6, 1270 0x71C7, 1271 0x71CD, 1272 0x71CE, 1273 0x71D2, 1274 0x71D4, 1275 0x71D5, 1276 0x71D6, 1277 0x71DA, 1278 0x71DE, 1279 0x7200, 1280 0x7210, 1281 0x7211, 1282 0x7240, 1283 0x7243, 1284 0x7244, 1285 0x7245, 1286 0x7246, 1287 0x7247, 1288 0x7248, 1289 0x7249, 1290 0x724A, 1291 0x724B, 1292 0x724C, 1293 0x724D, 1294 0x724E, 1295 0x724F, 1296 0x7280, 1297 0x7281, 1298 0x7283, 1299 0x7284, 1300 0x7287, 1301 0x7288, 1302 0x7289, 1303 0x728B, 1304 0x728C, 1305 0x7290, 1306 0x7291, 1307 0x7293, 1308 0x7297, 1309 0x7834, 1310 0x7835, 1311 0x791e, 1312 0x791f, 1313 0x793f, 1314 0x7941, 1315 0x7942, 1316 0x796c, 1317 0x796d, 1318 0x796e, 1319 0x796f, 1320 0x9400, 1321 0x9401, 1322 0x9402, 1323 0x9403, 1324 0x9405, 1325 0x940A, 1326 0x940B, 1327 0x940F, 1328 0x94A0, 1329 0x94A1, 1330 0x94A3, 1331 0x94B1, 1332 0x94B3, 1333 0x94B4, 1334 0x94B5, 1335 0x94B9, 1336 0x9440, 1337 0x9441, 1338 0x9442, 1339 0x9443, 1340 0x9444, 1341 0x9446, 1342 0x944A, 1343 0x944B, 1344 0x944C, 1345 0x944E, 1346 0x9450, 1347 0x9452, 1348 0x9456, 1349 0x945A, 1350 0x945B, 1351 0x945E, 1352 0x9460, 1353 0x9462, 1354 0x946A, 1355 0x946B, 1356 0x947A, 1357 0x947B, 1358 0x9480, 1359 0x9487, 1360 0x9488, 1361 0x9489, 1362 0x948A, 1363 0x948F, 1364 0x9490, 1365 0x9491, 1366 0x9495, 1367 0x9498, 1368 0x949C, 1369 0x949E, 1370 0x949F, 1371 0x94C0, 1372 0x94C1, 1373 0x94C3, 1374 0x94C4, 1375 0x94C5, 1376 0x94C6, 1377 0x94C7, 1378 0x94C8, 1379 0x94C9, 1380 0x94CB, 1381 0x94CC, 1382 0x94CD, 1383 0x9500, 1384 0x9501, 1385 0x9504, 1386 0x9505, 1387 0x9506, 1388 0x9507, 1389 0x9508, 1390 0x9509, 1391 0x950F, 1392 0x9511, 1393 0x9515, 1394 0x9517, 1395 0x9519, 1396 0x9540, 1397 0x9541, 1398 0x9542, 1399 0x954E, 1400 0x954F, 1401 0x9552, 1402 0x9553, 1403 0x9555, 1404 0x9557, 1405 0x955f, 1406 0x9580, 1407 0x9581, 1408 0x9583, 1409 0x9586, 1410 0x9587, 1411 0x9588, 1412 0x9589, 1413 0x958A, 1414 0x958B, 1415 0x958C, 1416 0x958D, 1417 0x958E, 1418 0x958F, 1419 0x9590, 1420 0x9591, 1421 0x9593, 1422 0x9595, 1423 0x9596, 1424 0x9597, 1425 0x9598, 1426 0x9599, 1427 0x959B, 1428 0x95C0, 1429 0x95C2, 1430 0x95C4, 1431 0x95C5, 1432 0x95C6, 1433 0x95C7, 1434 0x95C9, 1435 0x95CC, 1436 0x95CD, 1437 0x95CE, 1438 0x95CF, 1439 0x9610, 1440 0x9611, 1441 0x9612, 1442 0x9613, 1443 0x9614, 1444 0x9615, 1445 0x9616, 1446 0x9640, 1447 0x9641, 1448 0x9642, 1449 0x9643, 1450 0x9644, 1451 0x9645, 1452 0x9647, 1453 0x9648, 1454 0x9649, 1455 0x964a, 1456 0x964b, 1457 0x964c, 1458 0x964e, 1459 0x964f, 1460 0x9710, 1461 0x9711, 1462 0x9712, 1463 0x9713, 1464 0x9714, 1465 0x9715, 1466 0x9802, 1467 0x9803, 1468 0x9804, 1469 0x9805, 1470 0x9806, 1471 0x9807, 1472 0x9808, 1473 0x9809, 1474 0x980A, 1475 0x9900, 1476 0x9901, 1477 0x9903, 1478 0x9904, 1479 0x9905, 1480 0x9906, 1481 0x9907, 1482 0x9908, 1483 0x9909, 1484 0x990A, 1485 0x990B, 1486 0x990C, 1487 0x990D, 1488 0x990E, 1489 0x990F, 1490 0x9910, 1491 0x9913, 1492 0x9917, 1493 0x9918, 1494 0x9919, 1495 0x9990, 1496 0x9991, 1497 0x9992, 1498 0x9993, 1499 0x9994, 1500 0x9995, 1501 0x9996, 1502 0x9997, 1503 0x9998, 1504 0x9999, 1505 0x999A, 1506 0x999B, 1507 0x999C, 1508 0x999D, 1509 0x99A0, 1510 0x99A2, 1511 0x99A4, 1512 /* radeon secondary ids */ 1513 0x3171, 1514 0x3e70, 1515 0x4164, 1516 0x4165, 1517 0x4166, 1518 0x4168, 1519 0x4170, 1520 0x4171, 1521 0x4172, 1522 0x4173, 1523 0x496e, 1524 0x4a69, 1525 0x4a6a, 1526 0x4a6b, 1527 0x4a70, 1528 0x4a74, 1529 0x4b69, 1530 0x4b6b, 1531 0x4b6c, 1532 0x4c6e, 1533 0x4e64, 1534 0x4e65, 1535 0x4e66, 1536 0x4e67, 1537 0x4e68, 1538 0x4e69, 1539 0x4e6a, 1540 0x4e71, 1541 0x4f73, 1542 0x5569, 1543 0x556b, 1544 0x556d, 1545 0x556f, 1546 0x5571, 1547 0x5854, 1548 0x5874, 1549 0x5940, 1550 0x5941, 1551 0x5b72, 1552 0x5b73, 1553 0x5b74, 1554 0x5b75, 1555 0x5d44, 1556 0x5d45, 1557 0x5d6d, 1558 0x5d6f, 1559 0x5d72, 1560 0x5d77, 1561 0x5e6b, 1562 0x5e6d, 1563 0x7120, 1564 0x7124, 1565 0x7129, 1566 0x712e, 1567 0x712f, 1568 0x7162, 1569 0x7163, 1570 0x7166, 1571 0x7167, 1572 0x7172, 1573 0x7173, 1574 0x71a0, 1575 0x71a1, 1576 0x71a3, 1577 0x71a7, 1578 0x71bb, 1579 0x71e0, 1580 0x71e1, 1581 0x71e2, 1582 0x71e6, 1583 0x71e7, 1584 0x71f2, 1585 0x7269, 1586 0x726b, 1587 0x726e, 1588 0x72a0, 1589 0x72a8, 1590 0x72b1, 1591 0x72b3, 1592 0x793f, 1593 }; 1594 1595 static const struct pci_device_id pciidlist[] = { 1596 #ifdef CONFIG_DRM_AMDGPU_SI 1597 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1598 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1599 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1600 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1601 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1602 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1603 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1604 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1605 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1606 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1607 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1608 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1609 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1610 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1611 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1612 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1613 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1614 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1615 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1616 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1617 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1618 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1619 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1620 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1621 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1622 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1623 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1624 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1625 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1626 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1627 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1630 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1631 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1632 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1633 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1634 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1635 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1636 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1637 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1638 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1639 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1640 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1641 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1642 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1643 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1644 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1647 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1648 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1649 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1650 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1651 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1652 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1653 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1654 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1657 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1658 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1659 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1660 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1661 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1662 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1663 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1664 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1665 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1666 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1667 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1668 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1669 #endif 1670 #ifdef CONFIG_DRM_AMDGPU_CIK 1671 /* Kaveri */ 1672 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1673 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1674 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1675 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1676 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1677 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1678 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1679 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1680 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1681 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1682 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1683 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1684 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1685 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1686 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1687 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1688 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1689 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1690 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1691 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1692 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1693 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1694 /* Bonaire */ 1695 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1700 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1701 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1702 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1703 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1704 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1705 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1706 /* Hawaii */ 1707 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1708 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1709 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1710 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1711 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1712 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1713 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1714 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1715 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1716 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1717 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1718 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1719 /* Kabini */ 1720 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1721 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1722 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1723 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1724 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1725 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1726 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1727 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1728 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1729 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1730 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1731 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1733 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1734 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1735 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1736 /* mullins */ 1737 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1743 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1744 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1745 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1746 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1747 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1748 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1752 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1753 #endif 1754 /* topaz */ 1755 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1756 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1757 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1758 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1759 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1760 /* tonga */ 1761 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1762 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1763 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1764 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1765 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1766 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1767 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1768 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1769 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1770 /* fiji */ 1771 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1772 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1773 /* carrizo */ 1774 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1775 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1776 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1777 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1778 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1779 /* stoney */ 1780 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1781 /* Polaris11 */ 1782 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1783 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1784 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1785 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1786 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1787 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1788 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1789 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1790 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1791 /* Polaris10 */ 1792 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1793 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1794 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1795 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1796 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1797 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1798 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1799 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1800 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1801 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1802 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1803 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1804 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1805 /* Polaris12 */ 1806 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1807 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1808 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1809 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1810 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1811 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1812 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1813 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1814 /* VEGAM */ 1815 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1816 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1817 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1818 /* Vega 10 */ 1819 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1820 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1821 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1822 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1823 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1824 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1825 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1826 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1827 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1828 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1829 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1830 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1831 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1832 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1833 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1834 /* Vega 12 */ 1835 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1836 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1837 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1838 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1839 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1840 /* Vega 20 */ 1841 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1842 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1843 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1844 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1845 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1846 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1847 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1848 /* Raven */ 1849 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1850 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1851 /* Arcturus */ 1852 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1853 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1854 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1855 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1856 /* Navi10 */ 1857 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1858 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1859 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1860 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1861 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1862 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1863 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1864 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1865 /* Navi14 */ 1866 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1867 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1868 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1869 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1870 1871 /* Renoir */ 1872 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1873 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1874 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1875 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1876 1877 /* Navi12 */ 1878 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1879 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1880 1881 /* Sienna_Cichlid */ 1882 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1883 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1884 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1885 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1886 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1887 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1888 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1889 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1890 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1891 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1892 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1893 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1894 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1895 1896 /* Van Gogh */ 1897 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1898 1899 /* Yellow Carp */ 1900 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1901 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1902 1903 /* Navy_Flounder */ 1904 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1905 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1906 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1907 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1908 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1909 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1910 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1911 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1912 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1913 1914 /* DIMGREY_CAVEFISH */ 1915 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1916 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1917 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1918 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1919 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1920 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1921 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1922 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1923 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1924 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1925 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1926 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1927 1928 /* Aldebaran */ 1929 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1930 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1931 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1932 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1933 1934 /* CYAN_SKILLFISH */ 1935 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1936 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1937 1938 /* BEIGE_GOBY */ 1939 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1940 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1941 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1942 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1943 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1944 1945 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1946 .class = PCI_CLASS_DISPLAY_VGA << 8, 1947 .class_mask = 0xffffff, 1948 .driver_data = CHIP_IP_DISCOVERY }, 1949 1950 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1951 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1952 .class_mask = 0xffffff, 1953 .driver_data = CHIP_IP_DISCOVERY }, 1954 1955 {0, 0, 0} 1956 }; 1957 1958 MODULE_DEVICE_TABLE(pci, pciidlist); 1959 1960 static const struct drm_driver amdgpu_kms_driver; 1961 1962 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1963 { 1964 struct pci_dev *p = NULL; 1965 int i; 1966 1967 /* 0 - GPU 1968 * 1 - audio 1969 * 2 - USB 1970 * 3 - UCSI 1971 */ 1972 for (i = 1; i < 4; i++) { 1973 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1974 adev->pdev->bus->number, i); 1975 if (p) { 1976 pm_runtime_get_sync(&p->dev); 1977 pm_runtime_mark_last_busy(&p->dev); 1978 pm_runtime_put_autosuspend(&p->dev); 1979 pci_dev_put(p); 1980 } 1981 } 1982 } 1983 1984 static int amdgpu_pci_probe(struct pci_dev *pdev, 1985 const struct pci_device_id *ent) 1986 { 1987 struct drm_device *ddev; 1988 struct amdgpu_device *adev; 1989 unsigned long flags = ent->driver_data; 1990 int ret, retry = 0, i; 1991 bool supports_atomic = false; 1992 1993 /* skip devices which are owned by radeon */ 1994 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1995 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 1996 return -ENODEV; 1997 } 1998 1999 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2000 amdgpu_aspm = 0; 2001 2002 if (amdgpu_virtual_display || 2003 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2004 supports_atomic = true; 2005 2006 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2007 DRM_INFO("This hardware requires experimental hardware support.\n" 2008 "See modparam exp_hw_support\n"); 2009 return -ENODEV; 2010 } 2011 2012 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2013 * however, SME requires an indirect IOMMU mapping because the encryption 2014 * bit is beyond the DMA mask of the chip. 2015 */ 2016 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2017 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2018 dev_info(&pdev->dev, 2019 "SME is not compatible with RAVEN\n"); 2020 return -ENOTSUPP; 2021 } 2022 2023 #ifdef CONFIG_DRM_AMDGPU_SI 2024 if (!amdgpu_si_support) { 2025 switch (flags & AMD_ASIC_MASK) { 2026 case CHIP_TAHITI: 2027 case CHIP_PITCAIRN: 2028 case CHIP_VERDE: 2029 case CHIP_OLAND: 2030 case CHIP_HAINAN: 2031 dev_info(&pdev->dev, 2032 "SI support provided by radeon.\n"); 2033 dev_info(&pdev->dev, 2034 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2035 ); 2036 return -ENODEV; 2037 } 2038 } 2039 #endif 2040 #ifdef CONFIG_DRM_AMDGPU_CIK 2041 if (!amdgpu_cik_support) { 2042 switch (flags & AMD_ASIC_MASK) { 2043 case CHIP_KAVERI: 2044 case CHIP_BONAIRE: 2045 case CHIP_HAWAII: 2046 case CHIP_KABINI: 2047 case CHIP_MULLINS: 2048 dev_info(&pdev->dev, 2049 "CIK support provided by radeon.\n"); 2050 dev_info(&pdev->dev, 2051 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2052 ); 2053 return -ENODEV; 2054 } 2055 } 2056 #endif 2057 2058 /* Get rid of things like offb */ 2059 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2060 if (ret) 2061 return ret; 2062 2063 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2064 if (IS_ERR(adev)) 2065 return PTR_ERR(adev); 2066 2067 adev->dev = &pdev->dev; 2068 adev->pdev = pdev; 2069 ddev = adev_to_drm(adev); 2070 2071 if (!supports_atomic) 2072 ddev->driver_features &= ~DRIVER_ATOMIC; 2073 2074 ret = pci_enable_device(pdev); 2075 if (ret) 2076 return ret; 2077 2078 pci_set_drvdata(pdev, ddev); 2079 2080 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2081 if (ret) 2082 goto err_pci; 2083 2084 retry_init: 2085 ret = drm_dev_register(ddev, ent->driver_data); 2086 if (ret == -EAGAIN && ++retry <= 3) { 2087 DRM_INFO("retry init %d\n", retry); 2088 /* Don't request EX mode too frequently which is attacking */ 2089 msleep(5000); 2090 goto retry_init; 2091 } else if (ret) { 2092 goto err_pci; 2093 } 2094 2095 /* 2096 * 1. don't init fbdev on hw without DCE 2097 * 2. don't init fbdev if there are no connectors 2098 */ 2099 if (adev->mode_info.mode_config_initialized && 2100 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2101 /* select 8 bpp console on low vram cards */ 2102 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2103 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2104 else 2105 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2106 } 2107 2108 ret = amdgpu_debugfs_init(adev); 2109 if (ret) 2110 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2111 2112 if (adev->runpm) { 2113 /* only need to skip on ATPX */ 2114 if (amdgpu_device_supports_px(ddev)) 2115 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2116 /* we want direct complete for BOCO */ 2117 if (amdgpu_device_supports_boco(ddev)) 2118 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2119 DPM_FLAG_SMART_SUSPEND | 2120 DPM_FLAG_MAY_SKIP_RESUME); 2121 pm_runtime_use_autosuspend(ddev->dev); 2122 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2123 2124 pm_runtime_allow(ddev->dev); 2125 2126 pm_runtime_mark_last_busy(ddev->dev); 2127 pm_runtime_put_autosuspend(ddev->dev); 2128 2129 /* 2130 * For runpm implemented via BACO, PMFW will handle the 2131 * timing for BACO in and out: 2132 * - put ASIC into BACO state only when both video and 2133 * audio functions are in D3 state. 2134 * - pull ASIC out of BACO state when either video or 2135 * audio function is in D0 state. 2136 * Also, at startup, PMFW assumes both functions are in 2137 * D0 state. 2138 * 2139 * So if snd driver was loaded prior to amdgpu driver 2140 * and audio function was put into D3 state, there will 2141 * be no PMFW-aware D-state transition(D0->D3) on runpm 2142 * suspend. Thus the BACO will be not correctly kicked in. 2143 * 2144 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2145 * into D0 state. Then there will be a PMFW-aware D-state 2146 * transition(D0->D3) on runpm suspend. 2147 */ 2148 if (amdgpu_device_supports_baco(ddev) && 2149 !(adev->flags & AMD_IS_APU) && 2150 (adev->asic_type >= CHIP_NAVI10)) 2151 amdgpu_get_secondary_funcs(adev); 2152 } 2153 2154 return 0; 2155 2156 err_pci: 2157 pci_disable_device(pdev); 2158 return ret; 2159 } 2160 2161 static void 2162 amdgpu_pci_remove(struct pci_dev *pdev) 2163 { 2164 struct drm_device *dev = pci_get_drvdata(pdev); 2165 struct amdgpu_device *adev = drm_to_adev(dev); 2166 2167 drm_dev_unplug(dev); 2168 2169 if (adev->runpm) { 2170 pm_runtime_get_sync(dev->dev); 2171 pm_runtime_forbid(dev->dev); 2172 } 2173 2174 amdgpu_driver_unload_kms(dev); 2175 2176 /* 2177 * Flush any in flight DMA operations from device. 2178 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2179 * StatusTransactions Pending bit. 2180 */ 2181 pci_disable_device(pdev); 2182 pci_wait_for_pending_transaction(pdev); 2183 } 2184 2185 static void 2186 amdgpu_pci_shutdown(struct pci_dev *pdev) 2187 { 2188 struct drm_device *dev = pci_get_drvdata(pdev); 2189 struct amdgpu_device *adev = drm_to_adev(dev); 2190 2191 if (amdgpu_ras_intr_triggered()) 2192 return; 2193 2194 /* if we are running in a VM, make sure the device 2195 * torn down properly on reboot/shutdown. 2196 * unfortunately we can't detect certain 2197 * hypervisors so just do this all the time. 2198 */ 2199 if (!amdgpu_passthrough(adev)) 2200 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2201 amdgpu_device_ip_suspend(adev); 2202 adev->mp1_state = PP_MP1_STATE_NONE; 2203 } 2204 2205 /** 2206 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2207 * 2208 * @work: work_struct. 2209 */ 2210 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2211 { 2212 struct list_head device_list; 2213 struct amdgpu_device *adev; 2214 int i, r; 2215 struct amdgpu_reset_context reset_context; 2216 2217 memset(&reset_context, 0, sizeof(reset_context)); 2218 2219 mutex_lock(&mgpu_info.mutex); 2220 if (mgpu_info.pending_reset == true) { 2221 mutex_unlock(&mgpu_info.mutex); 2222 return; 2223 } 2224 mgpu_info.pending_reset = true; 2225 mutex_unlock(&mgpu_info.mutex); 2226 2227 /* Use a common context, just need to make sure full reset is done */ 2228 reset_context.method = AMD_RESET_METHOD_NONE; 2229 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2230 2231 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2232 adev = mgpu_info.gpu_ins[i].adev; 2233 reset_context.reset_req_dev = adev; 2234 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2235 if (r) { 2236 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2237 r, adev_to_drm(adev)->unique); 2238 } 2239 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2240 r = -EALREADY; 2241 } 2242 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2243 adev = mgpu_info.gpu_ins[i].adev; 2244 flush_work(&adev->xgmi_reset_work); 2245 adev->gmc.xgmi.pending_reset = false; 2246 } 2247 2248 /* reset function will rebuild the xgmi hive info , clear it now */ 2249 for (i = 0; i < mgpu_info.num_dgpu; i++) 2250 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2251 2252 INIT_LIST_HEAD(&device_list); 2253 2254 for (i = 0; i < mgpu_info.num_dgpu; i++) 2255 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2256 2257 /* unregister the GPU first, reset function will add them back */ 2258 list_for_each_entry(adev, &device_list, reset_list) 2259 amdgpu_unregister_gpu_instance(adev); 2260 2261 /* Use a common context, just need to make sure full reset is done */ 2262 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2263 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2264 2265 if (r) { 2266 DRM_ERROR("reinit gpus failure"); 2267 return; 2268 } 2269 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2270 adev = mgpu_info.gpu_ins[i].adev; 2271 if (!adev->kfd.init_complete) 2272 amdgpu_amdkfd_device_init(adev); 2273 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2274 } 2275 return; 2276 } 2277 2278 static int amdgpu_pmops_prepare(struct device *dev) 2279 { 2280 struct drm_device *drm_dev = dev_get_drvdata(dev); 2281 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2282 2283 /* Return a positive number here so 2284 * DPM_FLAG_SMART_SUSPEND works properly 2285 */ 2286 if (amdgpu_device_supports_boco(drm_dev)) 2287 return pm_runtime_suspended(dev); 2288 2289 /* if we will not support s3 or s2i for the device 2290 * then skip suspend 2291 */ 2292 if (!amdgpu_acpi_is_s0ix_active(adev) && 2293 !amdgpu_acpi_is_s3_active(adev)) 2294 return 1; 2295 2296 return 0; 2297 } 2298 2299 static void amdgpu_pmops_complete(struct device *dev) 2300 { 2301 /* nothing to do */ 2302 } 2303 2304 static int amdgpu_pmops_suspend(struct device *dev) 2305 { 2306 struct drm_device *drm_dev = dev_get_drvdata(dev); 2307 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2308 2309 if (amdgpu_acpi_is_s0ix_active(adev)) 2310 adev->in_s0ix = true; 2311 else 2312 adev->in_s3 = true; 2313 return amdgpu_device_suspend(drm_dev, true); 2314 } 2315 2316 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2317 { 2318 struct drm_device *drm_dev = dev_get_drvdata(dev); 2319 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2320 2321 if (amdgpu_acpi_should_gpu_reset(adev)) 2322 return amdgpu_asic_reset(adev); 2323 2324 return 0; 2325 } 2326 2327 static int amdgpu_pmops_resume(struct device *dev) 2328 { 2329 struct drm_device *drm_dev = dev_get_drvdata(dev); 2330 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2331 int r; 2332 2333 /* Avoids registers access if device is physically gone */ 2334 if (!pci_device_is_present(adev->pdev)) 2335 adev->no_hw_access = true; 2336 2337 r = amdgpu_device_resume(drm_dev, true); 2338 if (amdgpu_acpi_is_s0ix_active(adev)) 2339 adev->in_s0ix = false; 2340 else 2341 adev->in_s3 = false; 2342 return r; 2343 } 2344 2345 static int amdgpu_pmops_freeze(struct device *dev) 2346 { 2347 struct drm_device *drm_dev = dev_get_drvdata(dev); 2348 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2349 int r; 2350 2351 adev->in_s4 = true; 2352 r = amdgpu_device_suspend(drm_dev, true); 2353 adev->in_s4 = false; 2354 if (r) 2355 return r; 2356 return amdgpu_asic_reset(adev); 2357 } 2358 2359 static int amdgpu_pmops_thaw(struct device *dev) 2360 { 2361 struct drm_device *drm_dev = dev_get_drvdata(dev); 2362 2363 return amdgpu_device_resume(drm_dev, true); 2364 } 2365 2366 static int amdgpu_pmops_poweroff(struct device *dev) 2367 { 2368 struct drm_device *drm_dev = dev_get_drvdata(dev); 2369 2370 return amdgpu_device_suspend(drm_dev, true); 2371 } 2372 2373 static int amdgpu_pmops_restore(struct device *dev) 2374 { 2375 struct drm_device *drm_dev = dev_get_drvdata(dev); 2376 2377 return amdgpu_device_resume(drm_dev, true); 2378 } 2379 2380 static int amdgpu_runtime_idle_check_display(struct device *dev) 2381 { 2382 struct pci_dev *pdev = to_pci_dev(dev); 2383 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2384 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2385 2386 if (adev->mode_info.num_crtc) { 2387 struct drm_connector *list_connector; 2388 struct drm_connector_list_iter iter; 2389 int ret = 0; 2390 2391 /* XXX: Return busy if any displays are connected to avoid 2392 * possible display wakeups after runtime resume due to 2393 * hotplug events in case any displays were connected while 2394 * the GPU was in suspend. Remove this once that is fixed. 2395 */ 2396 mutex_lock(&drm_dev->mode_config.mutex); 2397 drm_connector_list_iter_begin(drm_dev, &iter); 2398 drm_for_each_connector_iter(list_connector, &iter) { 2399 if (list_connector->status == connector_status_connected) { 2400 ret = -EBUSY; 2401 break; 2402 } 2403 } 2404 drm_connector_list_iter_end(&iter); 2405 mutex_unlock(&drm_dev->mode_config.mutex); 2406 2407 if (ret) 2408 return ret; 2409 2410 if (amdgpu_device_has_dc_support(adev)) { 2411 struct drm_crtc *crtc; 2412 2413 drm_for_each_crtc(crtc, drm_dev) { 2414 drm_modeset_lock(&crtc->mutex, NULL); 2415 if (crtc->state->active) 2416 ret = -EBUSY; 2417 drm_modeset_unlock(&crtc->mutex); 2418 if (ret < 0) 2419 break; 2420 } 2421 } else { 2422 mutex_lock(&drm_dev->mode_config.mutex); 2423 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2424 2425 drm_connector_list_iter_begin(drm_dev, &iter); 2426 drm_for_each_connector_iter(list_connector, &iter) { 2427 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2428 ret = -EBUSY; 2429 break; 2430 } 2431 } 2432 2433 drm_connector_list_iter_end(&iter); 2434 2435 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2436 mutex_unlock(&drm_dev->mode_config.mutex); 2437 } 2438 if (ret) 2439 return ret; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2446 { 2447 struct pci_dev *pdev = to_pci_dev(dev); 2448 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2449 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2450 int ret, i; 2451 2452 if (!adev->runpm) { 2453 pm_runtime_forbid(dev); 2454 return -EBUSY; 2455 } 2456 2457 ret = amdgpu_runtime_idle_check_display(dev); 2458 if (ret) 2459 return ret; 2460 2461 /* wait for all rings to drain before suspending */ 2462 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2463 struct amdgpu_ring *ring = adev->rings[i]; 2464 if (ring && ring->sched.ready) { 2465 ret = amdgpu_fence_wait_empty(ring); 2466 if (ret) 2467 return -EBUSY; 2468 } 2469 } 2470 2471 adev->in_runpm = true; 2472 if (amdgpu_device_supports_px(drm_dev)) 2473 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2474 2475 /* 2476 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2477 * proper cleanups and put itself into a state ready for PNP. That 2478 * can address some random resuming failure observed on BOCO capable 2479 * platforms. 2480 * TODO: this may be also needed for PX capable platform. 2481 */ 2482 if (amdgpu_device_supports_boco(drm_dev)) 2483 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2484 2485 ret = amdgpu_device_suspend(drm_dev, false); 2486 if (ret) { 2487 adev->in_runpm = false; 2488 if (amdgpu_device_supports_boco(drm_dev)) 2489 adev->mp1_state = PP_MP1_STATE_NONE; 2490 return ret; 2491 } 2492 2493 if (amdgpu_device_supports_boco(drm_dev)) 2494 adev->mp1_state = PP_MP1_STATE_NONE; 2495 2496 if (amdgpu_device_supports_px(drm_dev)) { 2497 /* Only need to handle PCI state in the driver for ATPX 2498 * PCI core handles it for _PR3. 2499 */ 2500 amdgpu_device_cache_pci_state(pdev); 2501 pci_disable_device(pdev); 2502 pci_ignore_hotplug(pdev); 2503 pci_set_power_state(pdev, PCI_D3cold); 2504 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2505 } else if (amdgpu_device_supports_boco(drm_dev)) { 2506 /* nothing to do */ 2507 } else if (amdgpu_device_supports_baco(drm_dev)) { 2508 amdgpu_device_baco_enter(drm_dev); 2509 } 2510 2511 return 0; 2512 } 2513 2514 static int amdgpu_pmops_runtime_resume(struct device *dev) 2515 { 2516 struct pci_dev *pdev = to_pci_dev(dev); 2517 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2518 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2519 int ret; 2520 2521 if (!adev->runpm) 2522 return -EINVAL; 2523 2524 /* Avoids registers access if device is physically gone */ 2525 if (!pci_device_is_present(adev->pdev)) 2526 adev->no_hw_access = true; 2527 2528 if (amdgpu_device_supports_px(drm_dev)) { 2529 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2530 2531 /* Only need to handle PCI state in the driver for ATPX 2532 * PCI core handles it for _PR3. 2533 */ 2534 pci_set_power_state(pdev, PCI_D0); 2535 amdgpu_device_load_pci_state(pdev); 2536 ret = pci_enable_device(pdev); 2537 if (ret) 2538 return ret; 2539 pci_set_master(pdev); 2540 } else if (amdgpu_device_supports_boco(drm_dev)) { 2541 /* Only need to handle PCI state in the driver for ATPX 2542 * PCI core handles it for _PR3. 2543 */ 2544 pci_set_master(pdev); 2545 } else if (amdgpu_device_supports_baco(drm_dev)) { 2546 amdgpu_device_baco_exit(drm_dev); 2547 } 2548 ret = amdgpu_device_resume(drm_dev, false); 2549 if (ret) 2550 return ret; 2551 2552 if (amdgpu_device_supports_px(drm_dev)) 2553 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2554 adev->in_runpm = false; 2555 return 0; 2556 } 2557 2558 static int amdgpu_pmops_runtime_idle(struct device *dev) 2559 { 2560 struct drm_device *drm_dev = dev_get_drvdata(dev); 2561 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2562 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2563 int ret = 1; 2564 2565 if (!adev->runpm) { 2566 pm_runtime_forbid(dev); 2567 return -EBUSY; 2568 } 2569 2570 ret = amdgpu_runtime_idle_check_display(dev); 2571 2572 pm_runtime_mark_last_busy(dev); 2573 pm_runtime_autosuspend(dev); 2574 return ret; 2575 } 2576 2577 long amdgpu_drm_ioctl(struct file *filp, 2578 unsigned int cmd, unsigned long arg) 2579 { 2580 struct drm_file *file_priv = filp->private_data; 2581 struct drm_device *dev; 2582 long ret; 2583 dev = file_priv->minor->dev; 2584 ret = pm_runtime_get_sync(dev->dev); 2585 if (ret < 0) 2586 goto out; 2587 2588 ret = drm_ioctl(filp, cmd, arg); 2589 2590 pm_runtime_mark_last_busy(dev->dev); 2591 out: 2592 pm_runtime_put_autosuspend(dev->dev); 2593 return ret; 2594 } 2595 2596 static const struct dev_pm_ops amdgpu_pm_ops = { 2597 .prepare = amdgpu_pmops_prepare, 2598 .complete = amdgpu_pmops_complete, 2599 .suspend = amdgpu_pmops_suspend, 2600 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2601 .resume = amdgpu_pmops_resume, 2602 .freeze = amdgpu_pmops_freeze, 2603 .thaw = amdgpu_pmops_thaw, 2604 .poweroff = amdgpu_pmops_poweroff, 2605 .restore = amdgpu_pmops_restore, 2606 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2607 .runtime_resume = amdgpu_pmops_runtime_resume, 2608 .runtime_idle = amdgpu_pmops_runtime_idle, 2609 }; 2610 2611 static int amdgpu_flush(struct file *f, fl_owner_t id) 2612 { 2613 struct drm_file *file_priv = f->private_data; 2614 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2615 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2616 2617 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2618 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2619 2620 return timeout >= 0 ? 0 : timeout; 2621 } 2622 2623 static const struct file_operations amdgpu_driver_kms_fops = { 2624 .owner = THIS_MODULE, 2625 .open = drm_open, 2626 .flush = amdgpu_flush, 2627 .release = drm_release, 2628 .unlocked_ioctl = amdgpu_drm_ioctl, 2629 .mmap = drm_gem_mmap, 2630 .poll = drm_poll, 2631 .read = drm_read, 2632 #ifdef CONFIG_COMPAT 2633 .compat_ioctl = amdgpu_kms_compat_ioctl, 2634 #endif 2635 #ifdef CONFIG_PROC_FS 2636 .show_fdinfo = amdgpu_show_fdinfo 2637 #endif 2638 }; 2639 2640 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2641 { 2642 struct drm_file *file; 2643 2644 if (!filp) 2645 return -EINVAL; 2646 2647 if (filp->f_op != &amdgpu_driver_kms_fops) { 2648 return -EINVAL; 2649 } 2650 2651 file = filp->private_data; 2652 *fpriv = file->driver_priv; 2653 return 0; 2654 } 2655 2656 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2657 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2658 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2659 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2660 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2661 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2662 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2663 /* KMS */ 2664 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2665 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2666 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2667 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2668 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2669 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2670 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2671 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2672 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2673 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2674 }; 2675 2676 static const struct drm_driver amdgpu_kms_driver = { 2677 .driver_features = 2678 DRIVER_ATOMIC | 2679 DRIVER_GEM | 2680 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2681 DRIVER_SYNCOBJ_TIMELINE, 2682 .open = amdgpu_driver_open_kms, 2683 .postclose = amdgpu_driver_postclose_kms, 2684 .lastclose = amdgpu_driver_lastclose_kms, 2685 .ioctls = amdgpu_ioctls_kms, 2686 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2687 .dumb_create = amdgpu_mode_dumb_create, 2688 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2689 .fops = &amdgpu_driver_kms_fops, 2690 .release = &amdgpu_driver_release_kms, 2691 2692 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2693 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2694 .gem_prime_import = amdgpu_gem_prime_import, 2695 .gem_prime_mmap = drm_gem_prime_mmap, 2696 2697 .name = DRIVER_NAME, 2698 .desc = DRIVER_DESC, 2699 .date = DRIVER_DATE, 2700 .major = KMS_DRIVER_MAJOR, 2701 .minor = KMS_DRIVER_MINOR, 2702 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2703 }; 2704 2705 static struct pci_error_handlers amdgpu_pci_err_handler = { 2706 .error_detected = amdgpu_pci_error_detected, 2707 .mmio_enabled = amdgpu_pci_mmio_enabled, 2708 .slot_reset = amdgpu_pci_slot_reset, 2709 .resume = amdgpu_pci_resume, 2710 }; 2711 2712 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2713 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2714 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2715 2716 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2717 &amdgpu_vram_mgr_attr_group, 2718 &amdgpu_gtt_mgr_attr_group, 2719 &amdgpu_vbios_version_attr_group, 2720 NULL, 2721 }; 2722 2723 2724 static struct pci_driver amdgpu_kms_pci_driver = { 2725 .name = DRIVER_NAME, 2726 .id_table = pciidlist, 2727 .probe = amdgpu_pci_probe, 2728 .remove = amdgpu_pci_remove, 2729 .shutdown = amdgpu_pci_shutdown, 2730 .driver.pm = &amdgpu_pm_ops, 2731 .err_handler = &amdgpu_pci_err_handler, 2732 .dev_groups = amdgpu_sysfs_groups, 2733 }; 2734 2735 static int __init amdgpu_init(void) 2736 { 2737 int r; 2738 2739 if (drm_firmware_drivers_only()) 2740 return -EINVAL; 2741 2742 r = amdgpu_sync_init(); 2743 if (r) 2744 goto error_sync; 2745 2746 r = amdgpu_fence_slab_init(); 2747 if (r) 2748 goto error_fence; 2749 2750 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2751 amdgpu_register_atpx_handler(); 2752 amdgpu_acpi_detect(); 2753 2754 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2755 amdgpu_amdkfd_init(); 2756 2757 /* let modprobe override vga console setting */ 2758 return pci_register_driver(&amdgpu_kms_pci_driver); 2759 2760 error_fence: 2761 amdgpu_sync_fini(); 2762 2763 error_sync: 2764 return r; 2765 } 2766 2767 static void __exit amdgpu_exit(void) 2768 { 2769 amdgpu_amdkfd_fini(); 2770 pci_unregister_driver(&amdgpu_kms_pci_driver); 2771 amdgpu_unregister_atpx_handler(); 2772 amdgpu_sync_fini(); 2773 amdgpu_fence_slab_fini(); 2774 mmu_notifier_synchronize(); 2775 } 2776 2777 module_init(amdgpu_init); 2778 module_exit(amdgpu_exit); 2779 2780 MODULE_AUTHOR(DRIVER_AUTHOR); 2781 MODULE_DESCRIPTION(DRIVER_DESC); 2782 MODULE_LICENSE("GPL and additional rights"); 2783