1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/amdgpu_drm.h> 27 #include <drm/drm_gem.h> 28 #include "amdgpu_drv.h" 29 30 #include <drm/drm_pciids.h> 31 #include <linux/console.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/vga_switcheroo.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_irq.h" 39 #include "amdgpu_dma_buf.h" 40 41 #include "amdgpu_amdkfd.h" 42 43 /* 44 * KMS wrapper. 45 * - 3.0.0 - initial driver 46 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 47 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 48 * at the end of IBs. 49 * - 3.3.0 - Add VM support for UVD on supported hardware. 50 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 51 * - 3.5.0 - Add support for new UVD_NO_OP register. 52 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 53 * - 3.7.0 - Add support for VCE clock list packet 54 * - 3.8.0 - Add support raster config init in the kernel 55 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 56 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 57 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 58 * - 3.12.0 - Add query for double offchip LDS buffers 59 * - 3.13.0 - Add PRT support 60 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 61 * - 3.15.0 - Export more gpu info for gfx9 62 * - 3.16.0 - Add reserved vmid support 63 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 64 * - 3.18.0 - Export gpu always on cu bitmap 65 * - 3.19.0 - Add support for UVD MJPEG decode 66 * - 3.20.0 - Add support for local BOs 67 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 68 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 69 * - 3.23.0 - Add query for VRAM lost counter 70 * - 3.24.0 - Add high priority compute support for gfx9 71 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 72 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 73 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 74 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 75 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 76 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 77 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 78 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 79 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 80 */ 81 #define KMS_DRIVER_MAJOR 3 82 #define KMS_DRIVER_MINOR 33 83 #define KMS_DRIVER_PATCHLEVEL 0 84 85 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 86 87 int amdgpu_vram_limit = 0; 88 int amdgpu_vis_vram_limit = 0; 89 int amdgpu_gart_size = -1; /* auto */ 90 int amdgpu_gtt_size = -1; /* auto */ 91 int amdgpu_moverate = -1; /* auto */ 92 int amdgpu_benchmarking = 0; 93 int amdgpu_testing = 0; 94 int amdgpu_audio = -1; 95 int amdgpu_disp_priority = 0; 96 int amdgpu_hw_i2c = 0; 97 int amdgpu_pcie_gen2 = -1; 98 int amdgpu_msi = -1; 99 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 100 int amdgpu_dpm = -1; 101 int amdgpu_fw_load_type = -1; 102 int amdgpu_aspm = -1; 103 int amdgpu_runtime_pm = -1; 104 uint amdgpu_ip_block_mask = 0xffffffff; 105 int amdgpu_bapm = -1; 106 int amdgpu_deep_color = 0; 107 int amdgpu_vm_size = -1; 108 int amdgpu_vm_fragment_size = -1; 109 int amdgpu_vm_block_size = -1; 110 int amdgpu_vm_fault_stop = 0; 111 int amdgpu_vm_debug = 0; 112 int amdgpu_vm_update_mode = -1; 113 int amdgpu_exp_hw_support = 0; 114 int amdgpu_dc = -1; 115 int amdgpu_sched_jobs = 32; 116 int amdgpu_sched_hw_submission = 2; 117 uint amdgpu_pcie_gen_cap = 0; 118 uint amdgpu_pcie_lane_cap = 0; 119 uint amdgpu_cg_mask = 0xffffffff; 120 uint amdgpu_pg_mask = 0xffffffff; 121 uint amdgpu_sdma_phase_quantum = 32; 122 char *amdgpu_disable_cu = NULL; 123 char *amdgpu_virtual_display = NULL; 124 /* OverDrive(bit 14) disabled by default*/ 125 uint amdgpu_pp_feature_mask = 0xffffbfff; 126 int amdgpu_ngg = 0; 127 int amdgpu_prim_buf_per_se = 0; 128 int amdgpu_pos_buf_per_se = 0; 129 int amdgpu_cntl_sb_buf_per_se = 0; 130 int amdgpu_param_buf_per_se = 0; 131 int amdgpu_job_hang_limit = 0; 132 int amdgpu_lbpw = -1; 133 int amdgpu_compute_multipipe = -1; 134 int amdgpu_gpu_recovery = -1; /* auto */ 135 int amdgpu_emu_mode = 0; 136 uint amdgpu_smu_memory_pool_size = 0; 137 /* FBC (bit 0) disabled by default*/ 138 uint amdgpu_dc_feature_mask = 0; 139 int amdgpu_async_gfx_ring = 1; 140 141 struct amdgpu_mgpu_info mgpu_info = { 142 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 143 }; 144 int amdgpu_ras_enable = -1; 145 uint amdgpu_ras_mask = 0xffffffff; 146 147 /** 148 * DOC: vramlimit (int) 149 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 150 */ 151 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 152 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 153 154 /** 155 * DOC: vis_vramlimit (int) 156 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 157 */ 158 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 159 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 160 161 /** 162 * DOC: gartsize (uint) 163 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 164 */ 165 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 166 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 167 168 /** 169 * DOC: gttsize (int) 170 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 171 * otherwise 3/4 RAM size). 172 */ 173 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 174 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 175 176 /** 177 * DOC: moverate (int) 178 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 179 */ 180 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 181 module_param_named(moverate, amdgpu_moverate, int, 0600); 182 183 /** 184 * DOC: benchmark (int) 185 * Run benchmarks. The default is 0 (Skip benchmarks). 186 */ 187 MODULE_PARM_DESC(benchmark, "Run benchmark"); 188 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 189 190 /** 191 * DOC: test (int) 192 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 193 */ 194 MODULE_PARM_DESC(test, "Run tests"); 195 module_param_named(test, amdgpu_testing, int, 0444); 196 197 /** 198 * DOC: audio (int) 199 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 200 */ 201 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 202 module_param_named(audio, amdgpu_audio, int, 0444); 203 204 /** 205 * DOC: disp_priority (int) 206 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 207 */ 208 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 209 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 210 211 /** 212 * DOC: hw_i2c (int) 213 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 214 */ 215 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 216 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 217 218 /** 219 * DOC: pcie_gen2 (int) 220 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 221 */ 222 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 223 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 224 225 /** 226 * DOC: msi (int) 227 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 228 */ 229 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 230 module_param_named(msi, amdgpu_msi, int, 0444); 231 232 /** 233 * DOC: lockup_timeout (string) 234 * Set GPU scheduler timeout value in ms. 235 * 236 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 237 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 238 * to default timeout. 239 * - With one value specified, the setting will apply to all non-compute jobs. 240 * - With multiple values specified, the first one will be for GFX. The second one is for Compute. 241 * And the third and fourth ones are for SDMA and Video. 242 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 243 * jobs is 10000. And there is no timeout enforced on compute jobs. 244 */ 245 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and no timeout for compute jobs), " 246 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); 247 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 248 249 /** 250 * DOC: dpm (int) 251 * Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto). 252 */ 253 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 254 module_param_named(dpm, amdgpu_dpm, int, 0444); 255 256 /** 257 * DOC: fw_load_type (int) 258 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 259 */ 260 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 261 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 262 263 /** 264 * DOC: aspm (int) 265 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 266 */ 267 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 268 module_param_named(aspm, amdgpu_aspm, int, 0444); 269 270 /** 271 * DOC: runpm (int) 272 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 273 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 274 */ 275 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 276 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 277 278 /** 279 * DOC: ip_block_mask (uint) 280 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 281 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 282 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 283 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 284 */ 285 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 286 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 287 288 /** 289 * DOC: bapm (int) 290 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 291 * The default -1 (auto, enabled) 292 */ 293 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 294 module_param_named(bapm, amdgpu_bapm, int, 0444); 295 296 /** 297 * DOC: deep_color (int) 298 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 299 */ 300 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 301 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 302 303 /** 304 * DOC: vm_size (int) 305 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 306 */ 307 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 308 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 309 310 /** 311 * DOC: vm_fragment_size (int) 312 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 313 */ 314 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 315 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 316 317 /** 318 * DOC: vm_block_size (int) 319 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 320 */ 321 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 322 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 323 324 /** 325 * DOC: vm_fault_stop (int) 326 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 327 */ 328 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 329 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 330 331 /** 332 * DOC: vm_debug (int) 333 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 334 */ 335 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 336 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 337 338 /** 339 * DOC: vm_update_mode (int) 340 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 341 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 342 */ 343 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 344 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 345 346 /** 347 * DOC: exp_hw_support (int) 348 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 349 */ 350 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 351 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 352 353 /** 354 * DOC: dc (int) 355 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 356 */ 357 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 358 module_param_named(dc, amdgpu_dc, int, 0444); 359 360 /** 361 * DOC: sched_jobs (int) 362 * Override the max number of jobs supported in the sw queue. The default is 32. 363 */ 364 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 365 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 366 367 /** 368 * DOC: sched_hw_submission (int) 369 * Override the max number of HW submissions. The default is 2. 370 */ 371 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 372 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 373 374 /** 375 * DOC: ppfeaturemask (uint) 376 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 377 * The default is the current set of stable power features. 378 */ 379 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 380 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 381 382 /** 383 * DOC: pcie_gen_cap (uint) 384 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 385 * The default is 0 (automatic for each asic). 386 */ 387 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 388 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 389 390 /** 391 * DOC: pcie_lane_cap (uint) 392 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 393 * The default is 0 (automatic for each asic). 394 */ 395 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 396 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 397 398 /** 399 * DOC: cg_mask (uint) 400 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 401 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 402 */ 403 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 404 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 405 406 /** 407 * DOC: pg_mask (uint) 408 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 409 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 410 */ 411 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 412 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 413 414 /** 415 * DOC: sdma_phase_quantum (uint) 416 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 417 */ 418 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 419 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 420 421 /** 422 * DOC: disable_cu (charp) 423 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 424 */ 425 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 426 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 427 428 /** 429 * DOC: virtual_display (charp) 430 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 431 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 432 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 433 * device at 26:00.0. The default is NULL. 434 */ 435 MODULE_PARM_DESC(virtual_display, 436 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 437 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 438 439 /** 440 * DOC: ngg (int) 441 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 442 */ 443 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 444 module_param_named(ngg, amdgpu_ngg, int, 0444); 445 446 /** 447 * DOC: prim_buf_per_se (int) 448 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 449 */ 450 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 451 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 452 453 /** 454 * DOC: pos_buf_per_se (int) 455 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 456 */ 457 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 458 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 459 460 /** 461 * DOC: cntl_sb_buf_per_se (int) 462 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 463 */ 464 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 465 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 466 467 /** 468 * DOC: param_buf_per_se (int) 469 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 470 * The default is 0 (depending on gfx). 471 */ 472 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 473 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 474 475 /** 476 * DOC: job_hang_limit (int) 477 * Set how much time allow a job hang and not drop it. The default is 0. 478 */ 479 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 480 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 481 482 /** 483 * DOC: lbpw (int) 484 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 485 */ 486 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 487 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 488 489 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 490 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 491 492 /** 493 * DOC: gpu_recovery (int) 494 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 495 */ 496 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 497 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 498 499 /** 500 * DOC: emu_mode (int) 501 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 502 */ 503 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 504 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 505 506 /** 507 * DOC: ras_enable (int) 508 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 509 */ 510 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 511 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 512 513 /** 514 * DOC: ras_mask (uint) 515 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 516 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 517 */ 518 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 519 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 520 521 /** 522 * DOC: si_support (int) 523 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 524 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 525 * otherwise using amdgpu driver. 526 */ 527 #ifdef CONFIG_DRM_AMDGPU_SI 528 529 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 530 int amdgpu_si_support = 0; 531 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 532 #else 533 int amdgpu_si_support = 1; 534 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 535 #endif 536 537 module_param_named(si_support, amdgpu_si_support, int, 0444); 538 #endif 539 540 /** 541 * DOC: cik_support (int) 542 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 543 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 544 * otherwise using amdgpu driver. 545 */ 546 #ifdef CONFIG_DRM_AMDGPU_CIK 547 548 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 549 int amdgpu_cik_support = 0; 550 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 551 #else 552 int amdgpu_cik_support = 1; 553 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 554 #endif 555 556 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 557 #endif 558 559 /** 560 * DOC: smu_memory_pool_size (uint) 561 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 562 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 563 */ 564 MODULE_PARM_DESC(smu_memory_pool_size, 565 "reserve gtt for smu debug usage, 0 = disable," 566 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 567 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 568 569 /** 570 * DOC: async_gfx_ring (int) 571 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 572 */ 573 MODULE_PARM_DESC(async_gfx_ring, 574 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 575 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 576 577 #ifdef CONFIG_HSA_AMD 578 /** 579 * DOC: sched_policy (int) 580 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 581 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 582 * assigns queues to HQDs. 583 */ 584 int sched_policy = KFD_SCHED_POLICY_HWS; 585 module_param(sched_policy, int, 0444); 586 MODULE_PARM_DESC(sched_policy, 587 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 588 589 /** 590 * DOC: hws_max_conc_proc (int) 591 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 592 * number of VMIDs assigned to the HWS, which is also the default. 593 */ 594 int hws_max_conc_proc = 8; 595 module_param(hws_max_conc_proc, int, 0444); 596 MODULE_PARM_DESC(hws_max_conc_proc, 597 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 598 599 /** 600 * DOC: cwsr_enable (int) 601 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 602 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 603 * disables it. 604 */ 605 int cwsr_enable = 1; 606 module_param(cwsr_enable, int, 0444); 607 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 608 609 /** 610 * DOC: max_num_of_queues_per_device (int) 611 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 612 * is 4096. 613 */ 614 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 615 module_param(max_num_of_queues_per_device, int, 0444); 616 MODULE_PARM_DESC(max_num_of_queues_per_device, 617 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 618 619 /** 620 * DOC: send_sigterm (int) 621 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 622 * but just print errors on dmesg. Setting 1 enables sending sigterm. 623 */ 624 int send_sigterm; 625 module_param(send_sigterm, int, 0444); 626 MODULE_PARM_DESC(send_sigterm, 627 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 628 629 /** 630 * DOC: debug_largebar (int) 631 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 632 * system. This limits the VRAM size reported to ROCm applications to the visible 633 * size, usually 256MB. 634 * Default value is 0, diabled. 635 */ 636 int debug_largebar; 637 module_param(debug_largebar, int, 0444); 638 MODULE_PARM_DESC(debug_largebar, 639 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 640 641 /** 642 * DOC: ignore_crat (int) 643 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 644 * table to get information about AMD APUs. This option can serve as a workaround on 645 * systems with a broken CRAT table. 646 */ 647 int ignore_crat; 648 module_param(ignore_crat, int, 0444); 649 MODULE_PARM_DESC(ignore_crat, 650 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 651 652 /** 653 * DOC: noretry (int) 654 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry. 655 * Setting 1 disables retry. 656 * Retry is needed for recoverable page faults. 657 */ 658 int noretry; 659 module_param(noretry, int, 0644); 660 MODULE_PARM_DESC(noretry, 661 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); 662 663 /** 664 * DOC: halt_if_hws_hang (int) 665 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 666 * Setting 1 enables halt on hang. 667 */ 668 int halt_if_hws_hang; 669 module_param(halt_if_hws_hang, int, 0644); 670 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 671 672 /** 673 * DOC: hws_gws_support(bool) 674 * Whether HWS support gws barriers. Default value: false (not supported) 675 * This will be replaced with a MEC firmware version check once firmware 676 * is ready 677 */ 678 bool hws_gws_support; 679 module_param(hws_gws_support, bool, 0444); 680 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 681 #endif 682 683 /** 684 * DOC: dcfeaturemask (uint) 685 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 686 * The default is the current set of stable display features. 687 */ 688 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 689 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 690 691 /** 692 * DOC: abmlevel (uint) 693 * Override the default ABM (Adaptive Backlight Management) level used for DC 694 * enabled hardware. Requires DMCU to be supported and loaded. 695 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 696 * default. Values 1-4 control the maximum allowable brightness reduction via 697 * the ABM algorithm, with 1 being the least reduction and 4 being the most 698 * reduction. 699 * 700 * Defaults to 0, or disabled. Userspace can still override this level later 701 * after boot. 702 */ 703 uint amdgpu_dm_abm_level = 0; 704 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 705 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 706 707 static const struct pci_device_id pciidlist[] = { 708 #ifdef CONFIG_DRM_AMDGPU_SI 709 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 710 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 711 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 712 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 713 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 714 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 715 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 716 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 717 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 718 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 719 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 720 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 721 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 722 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 723 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 724 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 725 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 726 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 727 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 728 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 729 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 730 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 731 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 732 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 733 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 734 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 735 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 736 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 737 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 738 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 739 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 740 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 741 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 742 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 743 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 744 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 745 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 746 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 747 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 748 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 749 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 750 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 751 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 752 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 753 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 754 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 755 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 756 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 757 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 758 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 759 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 760 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 761 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 762 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 763 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 764 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 765 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 766 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 767 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 768 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 769 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 770 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 771 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 772 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 773 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 774 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 775 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 776 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 777 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 778 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 779 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 780 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 781 #endif 782 #ifdef CONFIG_DRM_AMDGPU_CIK 783 /* Kaveri */ 784 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 785 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 786 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 787 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 788 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 789 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 790 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 791 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 792 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 793 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 794 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 795 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 796 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 797 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 798 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 799 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 800 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 801 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 802 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 803 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 804 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 805 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 806 /* Bonaire */ 807 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 808 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 809 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 810 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 811 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 812 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 813 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 814 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 815 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 816 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 817 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 818 /* Hawaii */ 819 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 820 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 821 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 822 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 823 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 824 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 825 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 826 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 827 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 828 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 829 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 830 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 831 /* Kabini */ 832 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 833 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 834 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 835 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 836 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 837 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 838 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 839 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 840 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 841 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 842 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 843 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 844 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 845 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 846 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 847 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 848 /* mullins */ 849 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 850 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 851 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 852 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 853 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 854 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 855 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 856 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 857 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 858 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 859 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 860 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 861 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 862 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 863 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 864 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 865 #endif 866 /* topaz */ 867 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 868 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 869 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 870 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 871 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 872 /* tonga */ 873 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 874 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 875 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 876 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 877 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 878 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 879 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 880 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 881 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 882 /* fiji */ 883 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 884 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 885 /* carrizo */ 886 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 887 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 888 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 889 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 890 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 891 /* stoney */ 892 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 893 /* Polaris11 */ 894 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 895 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 896 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 897 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 898 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 899 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 900 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 901 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 902 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 903 /* Polaris10 */ 904 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 905 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 906 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 907 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 908 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 909 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 910 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 911 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 912 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 913 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 914 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 915 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 916 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 917 /* Polaris12 */ 918 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 919 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 920 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 921 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 922 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 923 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 924 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 925 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 926 /* VEGAM */ 927 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 928 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 929 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 930 /* Vega 10 */ 931 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 932 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 933 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 934 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 935 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 936 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 937 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 938 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 939 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 940 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 941 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 942 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 943 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 944 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 945 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 946 /* Vega 12 */ 947 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 948 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 949 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 950 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 951 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 952 /* Vega 20 */ 953 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 954 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 955 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 956 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 957 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 958 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 959 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 960 /* Raven */ 961 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 962 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 963 964 {0, 0, 0} 965 }; 966 967 MODULE_DEVICE_TABLE(pci, pciidlist); 968 969 static struct drm_driver kms_driver; 970 971 static int amdgpu_pci_probe(struct pci_dev *pdev, 972 const struct pci_device_id *ent) 973 { 974 struct drm_device *dev; 975 unsigned long flags = ent->driver_data; 976 int ret, retry = 0; 977 bool supports_atomic = false; 978 979 if (!amdgpu_virtual_display && 980 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 981 supports_atomic = true; 982 983 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 984 DRM_INFO("This hardware requires experimental hardware support.\n" 985 "See modparam exp_hw_support\n"); 986 return -ENODEV; 987 } 988 989 /* Get rid of things like offb */ 990 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 991 if (ret) 992 return ret; 993 994 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 995 if (IS_ERR(dev)) 996 return PTR_ERR(dev); 997 998 if (!supports_atomic) 999 dev->driver_features &= ~DRIVER_ATOMIC; 1000 1001 ret = pci_enable_device(pdev); 1002 if (ret) 1003 goto err_free; 1004 1005 dev->pdev = pdev; 1006 1007 pci_set_drvdata(pdev, dev); 1008 1009 retry_init: 1010 ret = drm_dev_register(dev, ent->driver_data); 1011 if (ret == -EAGAIN && ++retry <= 3) { 1012 DRM_INFO("retry init %d\n", retry); 1013 /* Don't request EX mode too frequently which is attacking */ 1014 msleep(5000); 1015 goto retry_init; 1016 } else if (ret) 1017 goto err_pci; 1018 1019 return 0; 1020 1021 err_pci: 1022 pci_disable_device(pdev); 1023 err_free: 1024 drm_dev_put(dev); 1025 return ret; 1026 } 1027 1028 static void 1029 amdgpu_pci_remove(struct pci_dev *pdev) 1030 { 1031 struct drm_device *dev = pci_get_drvdata(pdev); 1032 1033 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 1034 drm_dev_unplug(dev); 1035 drm_dev_put(dev); 1036 pci_disable_device(pdev); 1037 pci_set_drvdata(pdev, NULL); 1038 } 1039 1040 static void 1041 amdgpu_pci_shutdown(struct pci_dev *pdev) 1042 { 1043 struct drm_device *dev = pci_get_drvdata(pdev); 1044 struct amdgpu_device *adev = dev->dev_private; 1045 1046 /* if we are running in a VM, make sure the device 1047 * torn down properly on reboot/shutdown. 1048 * unfortunately we can't detect certain 1049 * hypervisors so just do this all the time. 1050 */ 1051 amdgpu_device_ip_suspend(adev); 1052 } 1053 1054 static int amdgpu_pmops_suspend(struct device *dev) 1055 { 1056 struct pci_dev *pdev = to_pci_dev(dev); 1057 1058 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1059 return amdgpu_device_suspend(drm_dev, true, true); 1060 } 1061 1062 static int amdgpu_pmops_resume(struct device *dev) 1063 { 1064 struct pci_dev *pdev = to_pci_dev(dev); 1065 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1066 1067 /* GPU comes up enabled by the bios on resume */ 1068 if (amdgpu_device_is_px(drm_dev)) { 1069 pm_runtime_disable(dev); 1070 pm_runtime_set_active(dev); 1071 pm_runtime_enable(dev); 1072 } 1073 1074 return amdgpu_device_resume(drm_dev, true, true); 1075 } 1076 1077 static int amdgpu_pmops_freeze(struct device *dev) 1078 { 1079 struct pci_dev *pdev = to_pci_dev(dev); 1080 1081 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1082 return amdgpu_device_suspend(drm_dev, false, true); 1083 } 1084 1085 static int amdgpu_pmops_thaw(struct device *dev) 1086 { 1087 struct pci_dev *pdev = to_pci_dev(dev); 1088 1089 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1090 return amdgpu_device_resume(drm_dev, false, true); 1091 } 1092 1093 static int amdgpu_pmops_poweroff(struct device *dev) 1094 { 1095 struct pci_dev *pdev = to_pci_dev(dev); 1096 1097 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1098 return amdgpu_device_suspend(drm_dev, true, true); 1099 } 1100 1101 static int amdgpu_pmops_restore(struct device *dev) 1102 { 1103 struct pci_dev *pdev = to_pci_dev(dev); 1104 1105 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1106 return amdgpu_device_resume(drm_dev, false, true); 1107 } 1108 1109 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1110 { 1111 struct pci_dev *pdev = to_pci_dev(dev); 1112 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1113 int ret; 1114 1115 if (!amdgpu_device_is_px(drm_dev)) { 1116 pm_runtime_forbid(dev); 1117 return -EBUSY; 1118 } 1119 1120 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1121 drm_kms_helper_poll_disable(drm_dev); 1122 1123 ret = amdgpu_device_suspend(drm_dev, false, false); 1124 pci_save_state(pdev); 1125 pci_disable_device(pdev); 1126 pci_ignore_hotplug(pdev); 1127 if (amdgpu_is_atpx_hybrid()) 1128 pci_set_power_state(pdev, PCI_D3cold); 1129 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1130 pci_set_power_state(pdev, PCI_D3hot); 1131 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1132 1133 return 0; 1134 } 1135 1136 static int amdgpu_pmops_runtime_resume(struct device *dev) 1137 { 1138 struct pci_dev *pdev = to_pci_dev(dev); 1139 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1140 int ret; 1141 1142 if (!amdgpu_device_is_px(drm_dev)) 1143 return -EINVAL; 1144 1145 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1146 1147 if (amdgpu_is_atpx_hybrid() || 1148 !amdgpu_has_atpx_dgpu_power_cntl()) 1149 pci_set_power_state(pdev, PCI_D0); 1150 pci_restore_state(pdev); 1151 ret = pci_enable_device(pdev); 1152 if (ret) 1153 return ret; 1154 pci_set_master(pdev); 1155 1156 ret = amdgpu_device_resume(drm_dev, false, false); 1157 drm_kms_helper_poll_enable(drm_dev); 1158 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1159 return 0; 1160 } 1161 1162 static int amdgpu_pmops_runtime_idle(struct device *dev) 1163 { 1164 struct pci_dev *pdev = to_pci_dev(dev); 1165 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1166 struct drm_crtc *crtc; 1167 1168 if (!amdgpu_device_is_px(drm_dev)) { 1169 pm_runtime_forbid(dev); 1170 return -EBUSY; 1171 } 1172 1173 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1174 if (crtc->enabled) { 1175 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1176 return -EBUSY; 1177 } 1178 } 1179 1180 pm_runtime_mark_last_busy(dev); 1181 pm_runtime_autosuspend(dev); 1182 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1183 return 1; 1184 } 1185 1186 long amdgpu_drm_ioctl(struct file *filp, 1187 unsigned int cmd, unsigned long arg) 1188 { 1189 struct drm_file *file_priv = filp->private_data; 1190 struct drm_device *dev; 1191 long ret; 1192 dev = file_priv->minor->dev; 1193 ret = pm_runtime_get_sync(dev->dev); 1194 if (ret < 0) 1195 return ret; 1196 1197 ret = drm_ioctl(filp, cmd, arg); 1198 1199 pm_runtime_mark_last_busy(dev->dev); 1200 pm_runtime_put_autosuspend(dev->dev); 1201 return ret; 1202 } 1203 1204 static const struct dev_pm_ops amdgpu_pm_ops = { 1205 .suspend = amdgpu_pmops_suspend, 1206 .resume = amdgpu_pmops_resume, 1207 .freeze = amdgpu_pmops_freeze, 1208 .thaw = amdgpu_pmops_thaw, 1209 .poweroff = amdgpu_pmops_poweroff, 1210 .restore = amdgpu_pmops_restore, 1211 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1212 .runtime_resume = amdgpu_pmops_runtime_resume, 1213 .runtime_idle = amdgpu_pmops_runtime_idle, 1214 }; 1215 1216 static int amdgpu_flush(struct file *f, fl_owner_t id) 1217 { 1218 struct drm_file *file_priv = f->private_data; 1219 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1220 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1221 1222 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1223 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1224 1225 return timeout >= 0 ? 0 : timeout; 1226 } 1227 1228 static const struct file_operations amdgpu_driver_kms_fops = { 1229 .owner = THIS_MODULE, 1230 .open = drm_open, 1231 .flush = amdgpu_flush, 1232 .release = drm_release, 1233 .unlocked_ioctl = amdgpu_drm_ioctl, 1234 .mmap = amdgpu_mmap, 1235 .poll = drm_poll, 1236 .read = drm_read, 1237 #ifdef CONFIG_COMPAT 1238 .compat_ioctl = amdgpu_kms_compat_ioctl, 1239 #endif 1240 }; 1241 1242 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1243 { 1244 struct drm_file *file; 1245 1246 if (!filp) 1247 return -EINVAL; 1248 1249 if (filp->f_op != &amdgpu_driver_kms_fops) { 1250 return -EINVAL; 1251 } 1252 1253 file = filp->private_data; 1254 *fpriv = file->driver_priv; 1255 return 0; 1256 } 1257 1258 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 1259 { 1260 char *input = amdgpu_lockup_timeout; 1261 char *timeout_setting = NULL; 1262 int index = 0; 1263 long timeout; 1264 int ret = 0; 1265 1266 /* 1267 * By default timeout for non compute jobs is 10000. 1268 * And there is no timeout enforced on compute jobs. 1269 */ 1270 adev->gfx_timeout = adev->sdma_timeout = adev->video_timeout = 10000; 1271 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; 1272 1273 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1274 while ((timeout_setting = strsep(&input, ",")) && 1275 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1276 ret = kstrtol(timeout_setting, 0, &timeout); 1277 if (ret) 1278 return ret; 1279 1280 /* Invalidate 0 and negative values */ 1281 if (timeout <= 0) { 1282 index++; 1283 continue; 1284 } 1285 1286 switch (index++) { 1287 case 0: 1288 adev->gfx_timeout = timeout; 1289 break; 1290 case 1: 1291 adev->compute_timeout = timeout; 1292 break; 1293 case 2: 1294 adev->sdma_timeout = timeout; 1295 break; 1296 case 3: 1297 adev->video_timeout = timeout; 1298 break; 1299 default: 1300 break; 1301 } 1302 } 1303 /* 1304 * There is only one value specified and 1305 * it should apply to all non-compute jobs. 1306 */ 1307 if (index == 1) 1308 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1309 } 1310 1311 return ret; 1312 } 1313 1314 static bool 1315 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1316 bool in_vblank_irq, int *vpos, int *hpos, 1317 ktime_t *stime, ktime_t *etime, 1318 const struct drm_display_mode *mode) 1319 { 1320 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1321 stime, etime, mode); 1322 } 1323 1324 static struct drm_driver kms_driver = { 1325 .driver_features = 1326 DRIVER_USE_AGP | DRIVER_ATOMIC | 1327 DRIVER_GEM | 1328 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1329 .load = amdgpu_driver_load_kms, 1330 .open = amdgpu_driver_open_kms, 1331 .postclose = amdgpu_driver_postclose_kms, 1332 .lastclose = amdgpu_driver_lastclose_kms, 1333 .unload = amdgpu_driver_unload_kms, 1334 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1335 .enable_vblank = amdgpu_enable_vblank_kms, 1336 .disable_vblank = amdgpu_disable_vblank_kms, 1337 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1338 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1339 .irq_handler = amdgpu_irq_handler, 1340 .ioctls = amdgpu_ioctls_kms, 1341 .gem_free_object_unlocked = amdgpu_gem_object_free, 1342 .gem_open_object = amdgpu_gem_object_open, 1343 .gem_close_object = amdgpu_gem_object_close, 1344 .dumb_create = amdgpu_mode_dumb_create, 1345 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1346 .fops = &amdgpu_driver_kms_fops, 1347 1348 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1349 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1350 .gem_prime_export = amdgpu_gem_prime_export, 1351 .gem_prime_import = amdgpu_gem_prime_import, 1352 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1353 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1354 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1355 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1356 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1357 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1358 1359 .name = DRIVER_NAME, 1360 .desc = DRIVER_DESC, 1361 .date = DRIVER_DATE, 1362 .major = KMS_DRIVER_MAJOR, 1363 .minor = KMS_DRIVER_MINOR, 1364 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1365 }; 1366 1367 static struct pci_driver amdgpu_kms_pci_driver = { 1368 .name = DRIVER_NAME, 1369 .id_table = pciidlist, 1370 .probe = amdgpu_pci_probe, 1371 .remove = amdgpu_pci_remove, 1372 .shutdown = amdgpu_pci_shutdown, 1373 .driver.pm = &amdgpu_pm_ops, 1374 }; 1375 1376 1377 1378 static int __init amdgpu_init(void) 1379 { 1380 int r; 1381 1382 if (vgacon_text_force()) { 1383 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1384 return -EINVAL; 1385 } 1386 1387 r = amdgpu_sync_init(); 1388 if (r) 1389 goto error_sync; 1390 1391 r = amdgpu_fence_slab_init(); 1392 if (r) 1393 goto error_fence; 1394 1395 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1396 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1397 amdgpu_register_atpx_handler(); 1398 1399 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1400 amdgpu_amdkfd_init(); 1401 1402 /* let modprobe override vga console setting */ 1403 return pci_register_driver(&amdgpu_kms_pci_driver); 1404 1405 error_fence: 1406 amdgpu_sync_fini(); 1407 1408 error_sync: 1409 return r; 1410 } 1411 1412 static void __exit amdgpu_exit(void) 1413 { 1414 amdgpu_amdkfd_fini(); 1415 pci_unregister_driver(&amdgpu_kms_pci_driver); 1416 amdgpu_unregister_atpx_handler(); 1417 amdgpu_sync_fini(); 1418 amdgpu_fence_slab_fini(); 1419 } 1420 1421 module_init(amdgpu_init); 1422 module_exit(amdgpu_exit); 1423 1424 MODULE_AUTHOR(DRIVER_AUTHOR); 1425 MODULE_DESCRIPTION(DRIVER_DESC); 1426 MODULE_LICENSE("GPL and additional rights"); 1427