1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 */ 63 #define KMS_DRIVER_MAJOR 3 64 #define KMS_DRIVER_MINOR 9 65 #define KMS_DRIVER_PATCHLEVEL 0 66 67 int amdgpu_vram_limit = 0; 68 int amdgpu_gart_size = -1; /* auto */ 69 int amdgpu_moverate = -1; /* auto */ 70 int amdgpu_benchmarking = 0; 71 int amdgpu_testing = 0; 72 int amdgpu_audio = -1; 73 int amdgpu_disp_priority = 0; 74 int amdgpu_hw_i2c = 0; 75 int amdgpu_pcie_gen2 = -1; 76 int amdgpu_msi = -1; 77 int amdgpu_lockup_timeout = 0; 78 int amdgpu_dpm = -1; 79 int amdgpu_smc_load_fw = 1; 80 int amdgpu_aspm = -1; 81 int amdgpu_runtime_pm = -1; 82 unsigned amdgpu_ip_block_mask = 0xffffffff; 83 int amdgpu_bapm = -1; 84 int amdgpu_deep_color = 0; 85 int amdgpu_vm_size = 64; 86 int amdgpu_vm_block_size = -1; 87 int amdgpu_vm_fault_stop = 0; 88 int amdgpu_vm_debug = 0; 89 int amdgpu_vram_page_split = 1024; 90 int amdgpu_exp_hw_support = 0; 91 int amdgpu_sched_jobs = 32; 92 int amdgpu_sched_hw_submission = 2; 93 int amdgpu_no_evict = 0; 94 int amdgpu_direct_gma_size = 0; 95 unsigned amdgpu_pcie_gen_cap = 0; 96 unsigned amdgpu_pcie_lane_cap = 0; 97 unsigned amdgpu_cg_mask = 0xffffffff; 98 unsigned amdgpu_pg_mask = 0xffffffff; 99 char *amdgpu_disable_cu = NULL; 100 char *amdgpu_virtual_display = NULL; 101 unsigned amdgpu_pp_feature_mask = 0xffffffff; 102 103 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 104 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 105 106 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 107 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 108 109 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 110 module_param_named(moverate, amdgpu_moverate, int, 0600); 111 112 MODULE_PARM_DESC(benchmark, "Run benchmark"); 113 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 114 115 MODULE_PARM_DESC(test, "Run tests"); 116 module_param_named(test, amdgpu_testing, int, 0444); 117 118 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 119 module_param_named(audio, amdgpu_audio, int, 0444); 120 121 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 122 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 123 124 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 125 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 126 127 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 128 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 129 130 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 131 module_param_named(msi, amdgpu_msi, int, 0444); 132 133 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 134 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 135 136 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 137 module_param_named(dpm, amdgpu_dpm, int, 0444); 138 139 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 140 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 141 142 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 143 module_param_named(aspm, amdgpu_aspm, int, 0444); 144 145 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 146 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 147 148 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 149 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 150 151 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 152 module_param_named(bapm, amdgpu_bapm, int, 0444); 153 154 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 155 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 156 157 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 158 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 159 160 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 161 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 162 163 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 164 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 165 166 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 167 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 168 169 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); 170 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 171 172 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 173 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 174 175 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 176 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 177 178 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 179 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 180 181 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 182 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); 183 184 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); 185 module_param_named(no_evict, amdgpu_no_evict, int, 0444); 186 187 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); 188 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); 189 190 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 191 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 192 193 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 194 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 195 196 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 197 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 198 199 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 200 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 201 202 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 203 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 204 205 MODULE_PARM_DESC(virtual_display, 206 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 207 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 208 209 static const struct pci_device_id pciidlist[] = { 210 #ifdef CONFIG_DRM_AMDGPU_SI 211 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 212 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 213 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 214 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 215 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 216 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 217 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 218 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 219 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 220 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 221 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 222 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 223 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 224 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 225 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 226 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 227 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 228 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 229 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 230 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 231 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 232 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 233 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 234 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 235 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 236 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 237 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 238 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 239 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 240 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 241 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 242 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 243 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 244 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 245 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 246 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 247 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 248 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 249 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 250 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 251 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 252 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 253 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 254 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 255 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 256 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 257 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 258 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 259 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 260 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 261 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 262 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 263 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 264 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 265 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 266 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 267 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 268 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 269 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 270 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 271 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 272 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 273 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 274 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 275 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 276 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 277 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 278 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 279 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 280 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 281 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 282 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 283 #endif 284 #ifdef CONFIG_DRM_AMDGPU_CIK 285 /* Kaveri */ 286 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 287 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 288 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 289 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 290 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 291 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 292 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 293 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 294 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 295 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 296 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 297 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 298 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 299 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 300 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 301 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 302 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 303 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 304 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 305 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 306 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 307 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 308 /* Bonaire */ 309 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 310 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 311 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 312 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 313 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 314 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 315 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 316 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 317 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 318 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 319 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 320 /* Hawaii */ 321 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 322 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 323 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 324 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 325 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 326 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 327 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 328 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 329 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 330 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 331 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 332 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 333 /* Kabini */ 334 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 335 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 336 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 337 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 338 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 339 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 340 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 341 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 342 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 343 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 344 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 345 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 346 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 347 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 348 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 349 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 350 /* mullins */ 351 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 352 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 353 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 354 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 355 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 356 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 357 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 358 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 359 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 360 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 361 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 362 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 363 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 364 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 365 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 366 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 367 #endif 368 /* topaz */ 369 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 370 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 371 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 372 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 373 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 374 /* tonga */ 375 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 376 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 377 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 378 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 379 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 380 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 381 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 382 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 383 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 384 /* fiji */ 385 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 386 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 387 /* carrizo */ 388 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 389 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 390 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 391 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 392 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 393 /* stoney */ 394 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 395 /* Polaris11 */ 396 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 397 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 398 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 399 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 400 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 401 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 402 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 403 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 404 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 405 /* Polaris10 */ 406 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 407 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 408 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 409 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 410 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 411 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 412 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 413 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 414 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 415 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 416 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 417 /* Polaris12 */ 418 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 419 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 420 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 421 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 422 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 423 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 424 425 {0, 0, 0} 426 }; 427 428 MODULE_DEVICE_TABLE(pci, pciidlist); 429 430 static struct drm_driver kms_driver; 431 432 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 433 { 434 struct apertures_struct *ap; 435 bool primary = false; 436 437 ap = alloc_apertures(1); 438 if (!ap) 439 return -ENOMEM; 440 441 ap->ranges[0].base = pci_resource_start(pdev, 0); 442 ap->ranges[0].size = pci_resource_len(pdev, 0); 443 444 #ifdef CONFIG_X86 445 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 446 #endif 447 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 448 kfree(ap); 449 450 return 0; 451 } 452 453 static int amdgpu_pci_probe(struct pci_dev *pdev, 454 const struct pci_device_id *ent) 455 { 456 unsigned long flags = ent->driver_data; 457 int ret; 458 459 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 460 DRM_INFO("This hardware requires experimental hardware support.\n" 461 "See modparam exp_hw_support\n"); 462 return -ENODEV; 463 } 464 465 /* 466 * Initialize amdkfd before starting radeon. If it was not loaded yet, 467 * defer radeon probing 468 */ 469 ret = amdgpu_amdkfd_init(); 470 if (ret == -EPROBE_DEFER) 471 return ret; 472 473 /* Get rid of things like offb */ 474 ret = amdgpu_kick_out_firmware_fb(pdev); 475 if (ret) 476 return ret; 477 478 return drm_get_pci_dev(pdev, ent, &kms_driver); 479 } 480 481 static void 482 amdgpu_pci_remove(struct pci_dev *pdev) 483 { 484 struct drm_device *dev = pci_get_drvdata(pdev); 485 486 drm_put_dev(dev); 487 } 488 489 static void 490 amdgpu_pci_shutdown(struct pci_dev *pdev) 491 { 492 struct drm_device *dev = pci_get_drvdata(pdev); 493 struct amdgpu_device *adev = dev->dev_private; 494 495 /* if we are running in a VM, make sure the device 496 * torn down properly on reboot/shutdown. 497 * unfortunately we can't detect certain 498 * hypervisors so just do this all the time. 499 */ 500 amdgpu_suspend(adev); 501 } 502 503 static int amdgpu_pmops_suspend(struct device *dev) 504 { 505 struct pci_dev *pdev = to_pci_dev(dev); 506 507 struct drm_device *drm_dev = pci_get_drvdata(pdev); 508 return amdgpu_device_suspend(drm_dev, true, true); 509 } 510 511 static int amdgpu_pmops_resume(struct device *dev) 512 { 513 struct pci_dev *pdev = to_pci_dev(dev); 514 struct drm_device *drm_dev = pci_get_drvdata(pdev); 515 516 /* GPU comes up enabled by the bios on resume */ 517 if (amdgpu_device_is_px(drm_dev)) { 518 pm_runtime_disable(dev); 519 pm_runtime_set_active(dev); 520 pm_runtime_enable(dev); 521 } 522 523 return amdgpu_device_resume(drm_dev, true, true); 524 } 525 526 static int amdgpu_pmops_freeze(struct device *dev) 527 { 528 struct pci_dev *pdev = to_pci_dev(dev); 529 530 struct drm_device *drm_dev = pci_get_drvdata(pdev); 531 return amdgpu_device_suspend(drm_dev, false, true); 532 } 533 534 static int amdgpu_pmops_thaw(struct device *dev) 535 { 536 struct pci_dev *pdev = to_pci_dev(dev); 537 538 struct drm_device *drm_dev = pci_get_drvdata(pdev); 539 return amdgpu_device_resume(drm_dev, false, true); 540 } 541 542 static int amdgpu_pmops_poweroff(struct device *dev) 543 { 544 struct pci_dev *pdev = to_pci_dev(dev); 545 546 struct drm_device *drm_dev = pci_get_drvdata(pdev); 547 return amdgpu_device_suspend(drm_dev, true, true); 548 } 549 550 static int amdgpu_pmops_restore(struct device *dev) 551 { 552 struct pci_dev *pdev = to_pci_dev(dev); 553 554 struct drm_device *drm_dev = pci_get_drvdata(pdev); 555 return amdgpu_device_resume(drm_dev, false, true); 556 } 557 558 static int amdgpu_pmops_runtime_suspend(struct device *dev) 559 { 560 struct pci_dev *pdev = to_pci_dev(dev); 561 struct drm_device *drm_dev = pci_get_drvdata(pdev); 562 int ret; 563 564 if (!amdgpu_device_is_px(drm_dev)) { 565 pm_runtime_forbid(dev); 566 return -EBUSY; 567 } 568 569 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 570 drm_kms_helper_poll_disable(drm_dev); 571 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 572 573 ret = amdgpu_device_suspend(drm_dev, false, false); 574 pci_save_state(pdev); 575 pci_disable_device(pdev); 576 pci_ignore_hotplug(pdev); 577 if (amdgpu_is_atpx_hybrid()) 578 pci_set_power_state(pdev, PCI_D3cold); 579 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 580 pci_set_power_state(pdev, PCI_D3hot); 581 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 582 583 return 0; 584 } 585 586 static int amdgpu_pmops_runtime_resume(struct device *dev) 587 { 588 struct pci_dev *pdev = to_pci_dev(dev); 589 struct drm_device *drm_dev = pci_get_drvdata(pdev); 590 int ret; 591 592 if (!amdgpu_device_is_px(drm_dev)) 593 return -EINVAL; 594 595 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 596 597 if (amdgpu_is_atpx_hybrid() || 598 !amdgpu_has_atpx_dgpu_power_cntl()) 599 pci_set_power_state(pdev, PCI_D0); 600 pci_restore_state(pdev); 601 ret = pci_enable_device(pdev); 602 if (ret) 603 return ret; 604 pci_set_master(pdev); 605 606 ret = amdgpu_device_resume(drm_dev, false, false); 607 drm_kms_helper_poll_enable(drm_dev); 608 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 609 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 610 return 0; 611 } 612 613 static int amdgpu_pmops_runtime_idle(struct device *dev) 614 { 615 struct pci_dev *pdev = to_pci_dev(dev); 616 struct drm_device *drm_dev = pci_get_drvdata(pdev); 617 struct drm_crtc *crtc; 618 619 if (!amdgpu_device_is_px(drm_dev)) { 620 pm_runtime_forbid(dev); 621 return -EBUSY; 622 } 623 624 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 625 if (crtc->enabled) { 626 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 627 return -EBUSY; 628 } 629 } 630 631 pm_runtime_mark_last_busy(dev); 632 pm_runtime_autosuspend(dev); 633 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 634 return 1; 635 } 636 637 long amdgpu_drm_ioctl(struct file *filp, 638 unsigned int cmd, unsigned long arg) 639 { 640 struct drm_file *file_priv = filp->private_data; 641 struct drm_device *dev; 642 long ret; 643 dev = file_priv->minor->dev; 644 ret = pm_runtime_get_sync(dev->dev); 645 if (ret < 0) 646 return ret; 647 648 ret = drm_ioctl(filp, cmd, arg); 649 650 pm_runtime_mark_last_busy(dev->dev); 651 pm_runtime_put_autosuspend(dev->dev); 652 return ret; 653 } 654 655 static const struct dev_pm_ops amdgpu_pm_ops = { 656 .suspend = amdgpu_pmops_suspend, 657 .resume = amdgpu_pmops_resume, 658 .freeze = amdgpu_pmops_freeze, 659 .thaw = amdgpu_pmops_thaw, 660 .poweroff = amdgpu_pmops_poweroff, 661 .restore = amdgpu_pmops_restore, 662 .runtime_suspend = amdgpu_pmops_runtime_suspend, 663 .runtime_resume = amdgpu_pmops_runtime_resume, 664 .runtime_idle = amdgpu_pmops_runtime_idle, 665 }; 666 667 static const struct file_operations amdgpu_driver_kms_fops = { 668 .owner = THIS_MODULE, 669 .open = drm_open, 670 .release = drm_release, 671 .unlocked_ioctl = amdgpu_drm_ioctl, 672 .mmap = amdgpu_mmap, 673 .poll = drm_poll, 674 .read = drm_read, 675 #ifdef CONFIG_COMPAT 676 .compat_ioctl = amdgpu_kms_compat_ioctl, 677 #endif 678 }; 679 680 static struct drm_driver kms_driver = { 681 .driver_features = 682 DRIVER_USE_AGP | 683 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 684 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, 685 .load = amdgpu_driver_load_kms, 686 .open = amdgpu_driver_open_kms, 687 .preclose = amdgpu_driver_preclose_kms, 688 .postclose = amdgpu_driver_postclose_kms, 689 .lastclose = amdgpu_driver_lastclose_kms, 690 .set_busid = drm_pci_set_busid, 691 .unload = amdgpu_driver_unload_kms, 692 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 693 .enable_vblank = amdgpu_enable_vblank_kms, 694 .disable_vblank = amdgpu_disable_vblank_kms, 695 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 696 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 697 #if defined(CONFIG_DEBUG_FS) 698 .debugfs_init = amdgpu_debugfs_init, 699 #endif 700 .irq_preinstall = amdgpu_irq_preinstall, 701 .irq_postinstall = amdgpu_irq_postinstall, 702 .irq_uninstall = amdgpu_irq_uninstall, 703 .irq_handler = amdgpu_irq_handler, 704 .ioctls = amdgpu_ioctls_kms, 705 .gem_free_object_unlocked = amdgpu_gem_object_free, 706 .gem_open_object = amdgpu_gem_object_open, 707 .gem_close_object = amdgpu_gem_object_close, 708 .dumb_create = amdgpu_mode_dumb_create, 709 .dumb_map_offset = amdgpu_mode_dumb_mmap, 710 .dumb_destroy = drm_gem_dumb_destroy, 711 .fops = &amdgpu_driver_kms_fops, 712 713 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 714 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 715 .gem_prime_export = amdgpu_gem_prime_export, 716 .gem_prime_import = drm_gem_prime_import, 717 .gem_prime_pin = amdgpu_gem_prime_pin, 718 .gem_prime_unpin = amdgpu_gem_prime_unpin, 719 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 720 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 721 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 722 .gem_prime_vmap = amdgpu_gem_prime_vmap, 723 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 724 725 .name = DRIVER_NAME, 726 .desc = DRIVER_DESC, 727 .date = DRIVER_DATE, 728 .major = KMS_DRIVER_MAJOR, 729 .minor = KMS_DRIVER_MINOR, 730 .patchlevel = KMS_DRIVER_PATCHLEVEL, 731 }; 732 733 static struct drm_driver *driver; 734 static struct pci_driver *pdriver; 735 736 static struct pci_driver amdgpu_kms_pci_driver = { 737 .name = DRIVER_NAME, 738 .id_table = pciidlist, 739 .probe = amdgpu_pci_probe, 740 .remove = amdgpu_pci_remove, 741 .shutdown = amdgpu_pci_shutdown, 742 .driver.pm = &amdgpu_pm_ops, 743 }; 744 745 746 747 static int __init amdgpu_init(void) 748 { 749 int r; 750 751 r = amdgpu_sync_init(); 752 if (r) 753 goto error_sync; 754 755 r = amdgpu_fence_slab_init(); 756 if (r) 757 goto error_fence; 758 759 r = amd_sched_fence_slab_init(); 760 if (r) 761 goto error_sched; 762 763 if (vgacon_text_force()) { 764 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 765 return -EINVAL; 766 } 767 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 768 driver = &kms_driver; 769 pdriver = &amdgpu_kms_pci_driver; 770 driver->num_ioctls = amdgpu_max_kms_ioctl; 771 amdgpu_register_atpx_handler(); 772 /* let modprobe override vga console setting */ 773 return drm_pci_init(driver, pdriver); 774 775 error_sched: 776 amdgpu_fence_slab_fini(); 777 778 error_fence: 779 amdgpu_sync_fini(); 780 781 error_sync: 782 return r; 783 } 784 785 static void __exit amdgpu_exit(void) 786 { 787 amdgpu_amdkfd_fini(); 788 drm_pci_exit(driver, pdriver); 789 amdgpu_unregister_atpx_handler(); 790 amdgpu_sync_fini(); 791 amd_sched_fence_slab_fini(); 792 amdgpu_fence_slab_fini(); 793 } 794 795 module_init(amdgpu_init); 796 module_exit(amdgpu_exit); 797 798 MODULE_AUTHOR(DRIVER_AUTHOR); 799 MODULE_DESCRIPTION(DRIVER_DESC); 800 MODULE_LICENSE("GPL and additional rights"); 801