1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include "amdgpu_drv.h" 30 31 #include <drm/drm_pciids.h> 32 #include <linux/console.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "amdgpu.h" 40 #include "amdgpu_irq.h" 41 #include "amdgpu_dma_buf.h" 42 43 #include "amdgpu_amdkfd.h" 44 45 #include "amdgpu_ras.h" 46 47 /* 48 * KMS wrapper. 49 * - 3.0.0 - initial driver 50 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 51 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 52 * at the end of IBs. 53 * - 3.3.0 - Add VM support for UVD on supported hardware. 54 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 55 * - 3.5.0 - Add support for new UVD_NO_OP register. 56 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 57 * - 3.7.0 - Add support for VCE clock list packet 58 * - 3.8.0 - Add support raster config init in the kernel 59 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 60 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 61 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 62 * - 3.12.0 - Add query for double offchip LDS buffers 63 * - 3.13.0 - Add PRT support 64 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 65 * - 3.15.0 - Export more gpu info for gfx9 66 * - 3.16.0 - Add reserved vmid support 67 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 68 * - 3.18.0 - Export gpu always on cu bitmap 69 * - 3.19.0 - Add support for UVD MJPEG decode 70 * - 3.20.0 - Add support for local BOs 71 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 72 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 73 * - 3.23.0 - Add query for VRAM lost counter 74 * - 3.24.0 - Add high priority compute support for gfx9 75 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 76 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 77 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 78 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 79 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 80 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 81 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 82 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 83 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 84 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 85 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 86 */ 87 #define KMS_DRIVER_MAJOR 3 88 #define KMS_DRIVER_MINOR 35 89 #define KMS_DRIVER_PATCHLEVEL 0 90 91 int amdgpu_vram_limit = 0; 92 int amdgpu_vis_vram_limit = 0; 93 int amdgpu_gart_size = -1; /* auto */ 94 int amdgpu_gtt_size = -1; /* auto */ 95 int amdgpu_moverate = -1; /* auto */ 96 int amdgpu_benchmarking = 0; 97 int amdgpu_testing = 0; 98 int amdgpu_audio = -1; 99 int amdgpu_disp_priority = 0; 100 int amdgpu_hw_i2c = 0; 101 int amdgpu_pcie_gen2 = -1; 102 int amdgpu_msi = -1; 103 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 104 int amdgpu_dpm = -1; 105 int amdgpu_fw_load_type = -1; 106 int amdgpu_aspm = -1; 107 int amdgpu_runtime_pm = -1; 108 uint amdgpu_ip_block_mask = 0xffffffff; 109 int amdgpu_bapm = -1; 110 int amdgpu_deep_color = 0; 111 int amdgpu_vm_size = -1; 112 int amdgpu_vm_fragment_size = -1; 113 int amdgpu_vm_block_size = -1; 114 int amdgpu_vm_fault_stop = 0; 115 int amdgpu_vm_debug = 0; 116 int amdgpu_vm_update_mode = -1; 117 int amdgpu_exp_hw_support = 0; 118 int amdgpu_dc = -1; 119 int amdgpu_sched_jobs = 32; 120 int amdgpu_sched_hw_submission = 2; 121 uint amdgpu_pcie_gen_cap = 0; 122 uint amdgpu_pcie_lane_cap = 0; 123 uint amdgpu_cg_mask = 0xffffffff; 124 uint amdgpu_pg_mask = 0xffffffff; 125 uint amdgpu_sdma_phase_quantum = 32; 126 char *amdgpu_disable_cu = NULL; 127 char *amdgpu_virtual_display = NULL; 128 /* OverDrive(bit 14) disabled by default*/ 129 uint amdgpu_pp_feature_mask = 0xffffbfff; 130 uint amdgpu_force_long_training = 0; 131 int amdgpu_job_hang_limit = 0; 132 int amdgpu_lbpw = -1; 133 int amdgpu_compute_multipipe = -1; 134 int amdgpu_gpu_recovery = -1; /* auto */ 135 int amdgpu_emu_mode = 0; 136 uint amdgpu_smu_memory_pool_size = 0; 137 /* FBC (bit 0) disabled by default*/ 138 uint amdgpu_dc_feature_mask = 0; 139 int amdgpu_async_gfx_ring = 1; 140 int amdgpu_mcbp = 0; 141 int amdgpu_discovery = -1; 142 int amdgpu_mes = 0; 143 int amdgpu_noretry = 1; 144 int amdgpu_force_asic_type = -1; 145 146 struct amdgpu_mgpu_info mgpu_info = { 147 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 148 }; 149 int amdgpu_ras_enable = -1; 150 uint amdgpu_ras_mask = 0xffffffff; 151 152 /** 153 * DOC: vramlimit (int) 154 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 155 */ 156 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 157 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 158 159 /** 160 * DOC: vis_vramlimit (int) 161 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 162 */ 163 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 164 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 165 166 /** 167 * DOC: gartsize (uint) 168 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 169 */ 170 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 171 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 172 173 /** 174 * DOC: gttsize (int) 175 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 176 * otherwise 3/4 RAM size). 177 */ 178 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 179 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 180 181 /** 182 * DOC: moverate (int) 183 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 184 */ 185 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 186 module_param_named(moverate, amdgpu_moverate, int, 0600); 187 188 /** 189 * DOC: benchmark (int) 190 * Run benchmarks. The default is 0 (Skip benchmarks). 191 */ 192 MODULE_PARM_DESC(benchmark, "Run benchmark"); 193 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 194 195 /** 196 * DOC: test (int) 197 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 198 */ 199 MODULE_PARM_DESC(test, "Run tests"); 200 module_param_named(test, amdgpu_testing, int, 0444); 201 202 /** 203 * DOC: audio (int) 204 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 205 */ 206 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 207 module_param_named(audio, amdgpu_audio, int, 0444); 208 209 /** 210 * DOC: disp_priority (int) 211 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 212 */ 213 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 214 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 215 216 /** 217 * DOC: hw_i2c (int) 218 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 219 */ 220 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 221 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 222 223 /** 224 * DOC: pcie_gen2 (int) 225 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 226 */ 227 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 228 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 229 230 /** 231 * DOC: msi (int) 232 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 233 */ 234 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 235 module_param_named(msi, amdgpu_msi, int, 0444); 236 237 /** 238 * DOC: lockup_timeout (string) 239 * Set GPU scheduler timeout value in ms. 240 * 241 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 242 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 243 * to the default timeout. 244 * 245 * - With one value specified, the setting will apply to all non-compute jobs. 246 * - With multiple values specified, the first one will be for GFX. 247 * The second one is for Compute. The third and fourth ones are 248 * for SDMA and Video. 249 * 250 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 251 * jobs is 10000. And there is no timeout enforced on compute jobs. 252 */ 253 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 254 "for passthrough or sriov, 10000 for all jobs." 255 " 0: keep default value. negative: infinity timeout), " 256 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 257 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 258 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 259 260 /** 261 * DOC: dpm (int) 262 * Override for dynamic power management setting 263 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 264 * The default is -1 (auto). 265 */ 266 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 267 module_param_named(dpm, amdgpu_dpm, int, 0444); 268 269 /** 270 * DOC: fw_load_type (int) 271 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 272 */ 273 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 274 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 275 276 /** 277 * DOC: aspm (int) 278 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 279 */ 280 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 281 module_param_named(aspm, amdgpu_aspm, int, 0444); 282 283 /** 284 * DOC: runpm (int) 285 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 286 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 287 */ 288 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 289 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 290 291 /** 292 * DOC: ip_block_mask (uint) 293 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 294 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 295 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 296 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 297 */ 298 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 299 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 300 301 /** 302 * DOC: bapm (int) 303 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 304 * The default -1 (auto, enabled) 305 */ 306 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 307 module_param_named(bapm, amdgpu_bapm, int, 0444); 308 309 /** 310 * DOC: deep_color (int) 311 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 312 */ 313 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 314 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 315 316 /** 317 * DOC: vm_size (int) 318 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 319 */ 320 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 321 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 322 323 /** 324 * DOC: vm_fragment_size (int) 325 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 326 */ 327 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 328 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 329 330 /** 331 * DOC: vm_block_size (int) 332 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 333 */ 334 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 335 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 336 337 /** 338 * DOC: vm_fault_stop (int) 339 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 340 */ 341 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 342 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 343 344 /** 345 * DOC: vm_debug (int) 346 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 347 */ 348 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 349 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 350 351 /** 352 * DOC: vm_update_mode (int) 353 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 354 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 355 */ 356 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 357 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 358 359 /** 360 * DOC: exp_hw_support (int) 361 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 362 */ 363 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 364 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 365 366 /** 367 * DOC: dc (int) 368 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 369 */ 370 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 371 module_param_named(dc, amdgpu_dc, int, 0444); 372 373 /** 374 * DOC: sched_jobs (int) 375 * Override the max number of jobs supported in the sw queue. The default is 32. 376 */ 377 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 378 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 379 380 /** 381 * DOC: sched_hw_submission (int) 382 * Override the max number of HW submissions. The default is 2. 383 */ 384 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 385 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 386 387 /** 388 * DOC: ppfeaturemask (uint) 389 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 390 * The default is the current set of stable power features. 391 */ 392 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 393 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 394 395 /** 396 * DOC: forcelongtraining (uint) 397 * Force long memory training in resume. 398 * The default is zero, indicates short training in resume. 399 */ 400 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 401 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 402 403 /** 404 * DOC: pcie_gen_cap (uint) 405 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 406 * The default is 0 (automatic for each asic). 407 */ 408 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 409 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 410 411 /** 412 * DOC: pcie_lane_cap (uint) 413 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 414 * The default is 0 (automatic for each asic). 415 */ 416 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 417 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 418 419 /** 420 * DOC: cg_mask (uint) 421 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 422 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 423 */ 424 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 425 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 426 427 /** 428 * DOC: pg_mask (uint) 429 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 430 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 431 */ 432 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 433 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 434 435 /** 436 * DOC: sdma_phase_quantum (uint) 437 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 438 */ 439 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 440 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 441 442 /** 443 * DOC: disable_cu (charp) 444 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 445 */ 446 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 447 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 448 449 /** 450 * DOC: virtual_display (charp) 451 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 452 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 453 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 454 * device at 26:00.0. The default is NULL. 455 */ 456 MODULE_PARM_DESC(virtual_display, 457 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 458 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 459 460 /** 461 * DOC: job_hang_limit (int) 462 * Set how much time allow a job hang and not drop it. The default is 0. 463 */ 464 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 465 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 466 467 /** 468 * DOC: lbpw (int) 469 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 470 */ 471 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 472 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 473 474 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 475 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 476 477 /** 478 * DOC: gpu_recovery (int) 479 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 480 */ 481 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 482 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 483 484 /** 485 * DOC: emu_mode (int) 486 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 487 */ 488 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 489 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 490 491 /** 492 * DOC: ras_enable (int) 493 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 494 */ 495 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 496 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 497 498 /** 499 * DOC: ras_mask (uint) 500 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 501 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 502 */ 503 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 504 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 505 506 /** 507 * DOC: si_support (int) 508 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 509 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 510 * otherwise using amdgpu driver. 511 */ 512 #ifdef CONFIG_DRM_AMDGPU_SI 513 514 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 515 int amdgpu_si_support = 0; 516 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 517 #else 518 int amdgpu_si_support = 1; 519 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 520 #endif 521 522 module_param_named(si_support, amdgpu_si_support, int, 0444); 523 #endif 524 525 /** 526 * DOC: cik_support (int) 527 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 528 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 529 * otherwise using amdgpu driver. 530 */ 531 #ifdef CONFIG_DRM_AMDGPU_CIK 532 533 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 534 int amdgpu_cik_support = 0; 535 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 536 #else 537 int amdgpu_cik_support = 1; 538 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 539 #endif 540 541 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 542 #endif 543 544 /** 545 * DOC: smu_memory_pool_size (uint) 546 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 547 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 548 */ 549 MODULE_PARM_DESC(smu_memory_pool_size, 550 "reserve gtt for smu debug usage, 0 = disable," 551 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 552 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 553 554 /** 555 * DOC: async_gfx_ring (int) 556 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 557 */ 558 MODULE_PARM_DESC(async_gfx_ring, 559 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 560 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 561 562 /** 563 * DOC: mcbp (int) 564 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 565 */ 566 MODULE_PARM_DESC(mcbp, 567 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 568 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 569 570 /** 571 * DOC: discovery (int) 572 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 573 * (-1 = auto (default), 0 = disabled, 1 = enabled) 574 */ 575 MODULE_PARM_DESC(discovery, 576 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 577 module_param_named(discovery, amdgpu_discovery, int, 0444); 578 579 /** 580 * DOC: mes (int) 581 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 582 * (0 = disabled (default), 1 = enabled) 583 */ 584 MODULE_PARM_DESC(mes, 585 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 586 module_param_named(mes, amdgpu_mes, int, 0444); 587 588 MODULE_PARM_DESC(noretry, 589 "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))"); 590 module_param_named(noretry, amdgpu_noretry, int, 0644); 591 592 /** 593 * DOC: force_asic_type (int) 594 * A non negative value used to specify the asic type for all supported GPUs. 595 */ 596 MODULE_PARM_DESC(force_asic_type, 597 "A non negative value used to specify the asic type for all supported GPUs"); 598 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 599 600 601 602 #ifdef CONFIG_HSA_AMD 603 /** 604 * DOC: sched_policy (int) 605 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 606 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 607 * assigns queues to HQDs. 608 */ 609 int sched_policy = KFD_SCHED_POLICY_HWS; 610 module_param(sched_policy, int, 0444); 611 MODULE_PARM_DESC(sched_policy, 612 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 613 614 /** 615 * DOC: hws_max_conc_proc (int) 616 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 617 * number of VMIDs assigned to the HWS, which is also the default. 618 */ 619 int hws_max_conc_proc = 8; 620 module_param(hws_max_conc_proc, int, 0444); 621 MODULE_PARM_DESC(hws_max_conc_proc, 622 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 623 624 /** 625 * DOC: cwsr_enable (int) 626 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 627 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 628 * disables it. 629 */ 630 int cwsr_enable = 1; 631 module_param(cwsr_enable, int, 0444); 632 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 633 634 /** 635 * DOC: max_num_of_queues_per_device (int) 636 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 637 * is 4096. 638 */ 639 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 640 module_param(max_num_of_queues_per_device, int, 0444); 641 MODULE_PARM_DESC(max_num_of_queues_per_device, 642 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 643 644 /** 645 * DOC: send_sigterm (int) 646 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 647 * but just print errors on dmesg. Setting 1 enables sending sigterm. 648 */ 649 int send_sigterm; 650 module_param(send_sigterm, int, 0444); 651 MODULE_PARM_DESC(send_sigterm, 652 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 653 654 /** 655 * DOC: debug_largebar (int) 656 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 657 * system. This limits the VRAM size reported to ROCm applications to the visible 658 * size, usually 256MB. 659 * Default value is 0, diabled. 660 */ 661 int debug_largebar; 662 module_param(debug_largebar, int, 0444); 663 MODULE_PARM_DESC(debug_largebar, 664 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 665 666 /** 667 * DOC: ignore_crat (int) 668 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 669 * table to get information about AMD APUs. This option can serve as a workaround on 670 * systems with a broken CRAT table. 671 */ 672 int ignore_crat; 673 module_param(ignore_crat, int, 0444); 674 MODULE_PARM_DESC(ignore_crat, 675 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 676 677 /** 678 * DOC: halt_if_hws_hang (int) 679 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 680 * Setting 1 enables halt on hang. 681 */ 682 int halt_if_hws_hang; 683 module_param(halt_if_hws_hang, int, 0644); 684 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 685 686 /** 687 * DOC: hws_gws_support(bool) 688 * Whether HWS support gws barriers. Default value: false (not supported) 689 * This will be replaced with a MEC firmware version check once firmware 690 * is ready 691 */ 692 bool hws_gws_support; 693 module_param(hws_gws_support, bool, 0444); 694 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 695 696 /** 697 * DOC: queue_preemption_timeout_ms (int) 698 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 699 */ 700 int queue_preemption_timeout_ms = 9000; 701 module_param(queue_preemption_timeout_ms, int, 0644); 702 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 703 #endif 704 705 /** 706 * DOC: dcfeaturemask (uint) 707 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 708 * The default is the current set of stable display features. 709 */ 710 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 711 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 712 713 /** 714 * DOC: abmlevel (uint) 715 * Override the default ABM (Adaptive Backlight Management) level used for DC 716 * enabled hardware. Requires DMCU to be supported and loaded. 717 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 718 * default. Values 1-4 control the maximum allowable brightness reduction via 719 * the ABM algorithm, with 1 being the least reduction and 4 being the most 720 * reduction. 721 * 722 * Defaults to 0, or disabled. Userspace can still override this level later 723 * after boot. 724 */ 725 uint amdgpu_dm_abm_level = 0; 726 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 727 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 728 729 static const struct pci_device_id pciidlist[] = { 730 #ifdef CONFIG_DRM_AMDGPU_SI 731 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 732 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 733 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 734 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 735 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 736 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 737 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 738 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 739 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 740 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 741 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 742 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 743 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 744 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 745 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 746 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 747 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 748 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 749 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 750 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 751 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 752 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 753 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 754 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 755 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 756 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 757 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 758 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 759 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 760 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 761 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 762 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 763 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 764 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 765 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 766 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 767 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 768 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 769 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 770 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 771 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 772 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 773 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 774 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 775 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 776 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 777 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 778 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 779 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 780 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 781 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 782 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 783 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 784 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 785 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 786 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 787 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 788 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 789 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 790 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 791 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 792 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 793 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 794 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 795 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 796 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 797 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 798 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 799 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 800 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 801 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 802 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 803 #endif 804 #ifdef CONFIG_DRM_AMDGPU_CIK 805 /* Kaveri */ 806 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 807 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 808 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 809 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 810 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 811 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 812 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 813 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 814 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 815 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 816 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 817 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 818 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 819 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 820 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 821 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 822 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 823 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 824 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 825 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 826 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 827 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 828 /* Bonaire */ 829 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 830 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 831 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 832 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 833 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 834 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 835 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 836 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 837 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 838 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 839 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 840 /* Hawaii */ 841 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 842 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 843 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 844 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 845 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 846 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 847 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 848 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 849 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 850 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 851 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 852 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 853 /* Kabini */ 854 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 855 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 856 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 857 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 858 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 859 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 860 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 861 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 862 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 863 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 864 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 865 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 866 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 867 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 868 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 869 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 870 /* mullins */ 871 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 872 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 873 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 874 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 875 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 876 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 877 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 878 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 879 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 880 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 881 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 882 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 884 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 887 #endif 888 /* topaz */ 889 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 890 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 891 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 892 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 893 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 894 /* tonga */ 895 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 896 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 897 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 898 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 899 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 900 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 901 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 902 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 903 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 904 /* fiji */ 905 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 906 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 907 /* carrizo */ 908 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 909 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 910 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 911 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 912 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 913 /* stoney */ 914 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 915 /* Polaris11 */ 916 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 917 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 918 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 919 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 920 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 921 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 922 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 923 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 924 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 925 /* Polaris10 */ 926 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 927 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 928 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 929 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 930 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 931 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 932 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 933 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 934 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 935 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 936 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 937 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 938 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 939 /* Polaris12 */ 940 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 941 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 942 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 943 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 944 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 945 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 946 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 947 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 948 /* VEGAM */ 949 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 950 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 951 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 952 /* Vega 10 */ 953 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 954 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 955 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 956 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 957 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 958 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 959 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 960 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 961 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 962 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 963 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 964 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 965 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 966 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 967 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 968 /* Vega 12 */ 969 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 970 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 971 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 972 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 973 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 974 /* Vega 20 */ 975 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 976 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 977 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 978 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 979 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 980 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 981 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 982 /* Raven */ 983 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 984 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 985 /* Arcturus */ 986 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 987 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 988 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 989 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 990 /* Navi10 */ 991 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 992 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 993 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 994 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 995 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 996 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 997 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 998 /* Navi14 */ 999 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1000 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1001 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1002 1003 /* Renoir */ 1004 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, 1005 1006 /* Navi12 */ 1007 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1008 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1009 1010 {0, 0, 0} 1011 }; 1012 1013 MODULE_DEVICE_TABLE(pci, pciidlist); 1014 1015 static struct drm_driver kms_driver; 1016 1017 static int amdgpu_pci_probe(struct pci_dev *pdev, 1018 const struct pci_device_id *ent) 1019 { 1020 struct drm_device *dev; 1021 unsigned long flags = ent->driver_data; 1022 int ret, retry = 0; 1023 bool supports_atomic = false; 1024 1025 if (!amdgpu_virtual_display && 1026 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1027 supports_atomic = true; 1028 1029 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1030 DRM_INFO("This hardware requires experimental hardware support.\n" 1031 "See modparam exp_hw_support\n"); 1032 return -ENODEV; 1033 } 1034 1035 #ifdef CONFIG_DRM_AMDGPU_SI 1036 if (!amdgpu_si_support) { 1037 switch (flags & AMD_ASIC_MASK) { 1038 case CHIP_TAHITI: 1039 case CHIP_PITCAIRN: 1040 case CHIP_VERDE: 1041 case CHIP_OLAND: 1042 case CHIP_HAINAN: 1043 dev_info(&pdev->dev, 1044 "SI support provided by radeon.\n"); 1045 dev_info(&pdev->dev, 1046 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1047 ); 1048 return -ENODEV; 1049 } 1050 } 1051 #endif 1052 #ifdef CONFIG_DRM_AMDGPU_CIK 1053 if (!amdgpu_cik_support) { 1054 switch (flags & AMD_ASIC_MASK) { 1055 case CHIP_KAVERI: 1056 case CHIP_BONAIRE: 1057 case CHIP_HAWAII: 1058 case CHIP_KABINI: 1059 case CHIP_MULLINS: 1060 dev_info(&pdev->dev, 1061 "CIK support provided by radeon.\n"); 1062 dev_info(&pdev->dev, 1063 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1064 ); 1065 return -ENODEV; 1066 } 1067 } 1068 #endif 1069 1070 /* Get rid of things like offb */ 1071 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 1072 if (ret) 1073 return ret; 1074 1075 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1076 if (IS_ERR(dev)) 1077 return PTR_ERR(dev); 1078 1079 if (!supports_atomic) 1080 dev->driver_features &= ~DRIVER_ATOMIC; 1081 1082 ret = pci_enable_device(pdev); 1083 if (ret) 1084 goto err_free; 1085 1086 dev->pdev = pdev; 1087 1088 pci_set_drvdata(pdev, dev); 1089 1090 retry_init: 1091 ret = drm_dev_register(dev, ent->driver_data); 1092 if (ret == -EAGAIN && ++retry <= 3) { 1093 DRM_INFO("retry init %d\n", retry); 1094 /* Don't request EX mode too frequently which is attacking */ 1095 msleep(5000); 1096 goto retry_init; 1097 } else if (ret) 1098 goto err_pci; 1099 1100 return 0; 1101 1102 err_pci: 1103 pci_disable_device(pdev); 1104 err_free: 1105 drm_dev_put(dev); 1106 return ret; 1107 } 1108 1109 static void 1110 amdgpu_pci_remove(struct pci_dev *pdev) 1111 { 1112 struct drm_device *dev = pci_get_drvdata(pdev); 1113 1114 #ifdef MODULE 1115 if (THIS_MODULE->state != MODULE_STATE_GOING) 1116 #endif 1117 DRM_ERROR("Hotplug removal is not supported\n"); 1118 drm_dev_unplug(dev); 1119 drm_dev_put(dev); 1120 pci_disable_device(pdev); 1121 pci_set_drvdata(pdev, NULL); 1122 } 1123 1124 static void 1125 amdgpu_pci_shutdown(struct pci_dev *pdev) 1126 { 1127 struct drm_device *dev = pci_get_drvdata(pdev); 1128 struct amdgpu_device *adev = dev->dev_private; 1129 1130 if (amdgpu_ras_intr_triggered()) 1131 return; 1132 1133 /* if we are running in a VM, make sure the device 1134 * torn down properly on reboot/shutdown. 1135 * unfortunately we can't detect certain 1136 * hypervisors so just do this all the time. 1137 */ 1138 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1139 amdgpu_device_ip_suspend(adev); 1140 adev->mp1_state = PP_MP1_STATE_NONE; 1141 } 1142 1143 static int amdgpu_pmops_suspend(struct device *dev) 1144 { 1145 struct drm_device *drm_dev = dev_get_drvdata(dev); 1146 1147 return amdgpu_device_suspend(drm_dev, true, true); 1148 } 1149 1150 static int amdgpu_pmops_resume(struct device *dev) 1151 { 1152 struct drm_device *drm_dev = dev_get_drvdata(dev); 1153 1154 /* GPU comes up enabled by the bios on resume */ 1155 if (amdgpu_device_is_px(drm_dev)) { 1156 pm_runtime_disable(dev); 1157 pm_runtime_set_active(dev); 1158 pm_runtime_enable(dev); 1159 } 1160 1161 return amdgpu_device_resume(drm_dev, true, true); 1162 } 1163 1164 static int amdgpu_pmops_freeze(struct device *dev) 1165 { 1166 struct drm_device *drm_dev = dev_get_drvdata(dev); 1167 struct amdgpu_device *adev = drm_dev->dev_private; 1168 int r; 1169 1170 r = amdgpu_device_suspend(drm_dev, false, true); 1171 if (r) 1172 return r; 1173 return amdgpu_asic_reset(adev); 1174 } 1175 1176 static int amdgpu_pmops_thaw(struct device *dev) 1177 { 1178 struct drm_device *drm_dev = dev_get_drvdata(dev); 1179 1180 return amdgpu_device_resume(drm_dev, false, true); 1181 } 1182 1183 static int amdgpu_pmops_poweroff(struct device *dev) 1184 { 1185 struct drm_device *drm_dev = dev_get_drvdata(dev); 1186 1187 return amdgpu_device_suspend(drm_dev, true, true); 1188 } 1189 1190 static int amdgpu_pmops_restore(struct device *dev) 1191 { 1192 struct drm_device *drm_dev = dev_get_drvdata(dev); 1193 1194 return amdgpu_device_resume(drm_dev, false, true); 1195 } 1196 1197 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1198 { 1199 struct pci_dev *pdev = to_pci_dev(dev); 1200 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1201 int ret; 1202 1203 if (!amdgpu_device_is_px(drm_dev)) { 1204 pm_runtime_forbid(dev); 1205 return -EBUSY; 1206 } 1207 1208 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1209 drm_kms_helper_poll_disable(drm_dev); 1210 1211 ret = amdgpu_device_suspend(drm_dev, false, false); 1212 pci_save_state(pdev); 1213 pci_disable_device(pdev); 1214 pci_ignore_hotplug(pdev); 1215 if (amdgpu_is_atpx_hybrid()) 1216 pci_set_power_state(pdev, PCI_D3cold); 1217 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1218 pci_set_power_state(pdev, PCI_D3hot); 1219 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1220 1221 return 0; 1222 } 1223 1224 static int amdgpu_pmops_runtime_resume(struct device *dev) 1225 { 1226 struct pci_dev *pdev = to_pci_dev(dev); 1227 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1228 int ret; 1229 1230 if (!amdgpu_device_is_px(drm_dev)) 1231 return -EINVAL; 1232 1233 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1234 1235 if (amdgpu_is_atpx_hybrid() || 1236 !amdgpu_has_atpx_dgpu_power_cntl()) 1237 pci_set_power_state(pdev, PCI_D0); 1238 pci_restore_state(pdev); 1239 ret = pci_enable_device(pdev); 1240 if (ret) 1241 return ret; 1242 pci_set_master(pdev); 1243 1244 ret = amdgpu_device_resume(drm_dev, false, false); 1245 drm_kms_helper_poll_enable(drm_dev); 1246 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1247 return 0; 1248 } 1249 1250 static int amdgpu_pmops_runtime_idle(struct device *dev) 1251 { 1252 struct drm_device *drm_dev = dev_get_drvdata(dev); 1253 struct drm_crtc *crtc; 1254 1255 if (!amdgpu_device_is_px(drm_dev)) { 1256 pm_runtime_forbid(dev); 1257 return -EBUSY; 1258 } 1259 1260 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1261 if (crtc->enabled) { 1262 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1263 return -EBUSY; 1264 } 1265 } 1266 1267 pm_runtime_mark_last_busy(dev); 1268 pm_runtime_autosuspend(dev); 1269 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1270 return 1; 1271 } 1272 1273 long amdgpu_drm_ioctl(struct file *filp, 1274 unsigned int cmd, unsigned long arg) 1275 { 1276 struct drm_file *file_priv = filp->private_data; 1277 struct drm_device *dev; 1278 long ret; 1279 dev = file_priv->minor->dev; 1280 ret = pm_runtime_get_sync(dev->dev); 1281 if (ret < 0) 1282 return ret; 1283 1284 ret = drm_ioctl(filp, cmd, arg); 1285 1286 pm_runtime_mark_last_busy(dev->dev); 1287 pm_runtime_put_autosuspend(dev->dev); 1288 return ret; 1289 } 1290 1291 static const struct dev_pm_ops amdgpu_pm_ops = { 1292 .suspend = amdgpu_pmops_suspend, 1293 .resume = amdgpu_pmops_resume, 1294 .freeze = amdgpu_pmops_freeze, 1295 .thaw = amdgpu_pmops_thaw, 1296 .poweroff = amdgpu_pmops_poweroff, 1297 .restore = amdgpu_pmops_restore, 1298 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1299 .runtime_resume = amdgpu_pmops_runtime_resume, 1300 .runtime_idle = amdgpu_pmops_runtime_idle, 1301 }; 1302 1303 static int amdgpu_flush(struct file *f, fl_owner_t id) 1304 { 1305 struct drm_file *file_priv = f->private_data; 1306 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1307 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1308 1309 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1310 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1311 1312 return timeout >= 0 ? 0 : timeout; 1313 } 1314 1315 static const struct file_operations amdgpu_driver_kms_fops = { 1316 .owner = THIS_MODULE, 1317 .open = drm_open, 1318 .flush = amdgpu_flush, 1319 .release = drm_release, 1320 .unlocked_ioctl = amdgpu_drm_ioctl, 1321 .mmap = amdgpu_mmap, 1322 .poll = drm_poll, 1323 .read = drm_read, 1324 #ifdef CONFIG_COMPAT 1325 .compat_ioctl = amdgpu_kms_compat_ioctl, 1326 #endif 1327 }; 1328 1329 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1330 { 1331 struct drm_file *file; 1332 1333 if (!filp) 1334 return -EINVAL; 1335 1336 if (filp->f_op != &amdgpu_driver_kms_fops) { 1337 return -EINVAL; 1338 } 1339 1340 file = filp->private_data; 1341 *fpriv = file->driver_priv; 1342 return 0; 1343 } 1344 1345 static bool 1346 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1347 bool in_vblank_irq, int *vpos, int *hpos, 1348 ktime_t *stime, ktime_t *etime, 1349 const struct drm_display_mode *mode) 1350 { 1351 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1352 stime, etime, mode); 1353 } 1354 1355 static struct drm_driver kms_driver = { 1356 .driver_features = 1357 DRIVER_USE_AGP | DRIVER_ATOMIC | 1358 DRIVER_GEM | 1359 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1360 .load = amdgpu_driver_load_kms, 1361 .open = amdgpu_driver_open_kms, 1362 .postclose = amdgpu_driver_postclose_kms, 1363 .lastclose = amdgpu_driver_lastclose_kms, 1364 .unload = amdgpu_driver_unload_kms, 1365 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1366 .enable_vblank = amdgpu_enable_vblank_kms, 1367 .disable_vblank = amdgpu_disable_vblank_kms, 1368 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1369 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1370 .irq_handler = amdgpu_irq_handler, 1371 .ioctls = amdgpu_ioctls_kms, 1372 .gem_free_object_unlocked = amdgpu_gem_object_free, 1373 .gem_open_object = amdgpu_gem_object_open, 1374 .gem_close_object = amdgpu_gem_object_close, 1375 .dumb_create = amdgpu_mode_dumb_create, 1376 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1377 .fops = &amdgpu_driver_kms_fops, 1378 1379 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1380 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1381 .gem_prime_export = amdgpu_gem_prime_export, 1382 .gem_prime_import = amdgpu_gem_prime_import, 1383 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1384 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1385 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1386 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1387 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1388 1389 .name = DRIVER_NAME, 1390 .desc = DRIVER_DESC, 1391 .date = DRIVER_DATE, 1392 .major = KMS_DRIVER_MAJOR, 1393 .minor = KMS_DRIVER_MINOR, 1394 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1395 }; 1396 1397 static struct pci_driver amdgpu_kms_pci_driver = { 1398 .name = DRIVER_NAME, 1399 .id_table = pciidlist, 1400 .probe = amdgpu_pci_probe, 1401 .remove = amdgpu_pci_remove, 1402 .shutdown = amdgpu_pci_shutdown, 1403 .driver.pm = &amdgpu_pm_ops, 1404 }; 1405 1406 1407 1408 static int __init amdgpu_init(void) 1409 { 1410 int r; 1411 1412 if (vgacon_text_force()) { 1413 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1414 return -EINVAL; 1415 } 1416 1417 r = amdgpu_sync_init(); 1418 if (r) 1419 goto error_sync; 1420 1421 r = amdgpu_fence_slab_init(); 1422 if (r) 1423 goto error_fence; 1424 1425 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1426 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1427 amdgpu_register_atpx_handler(); 1428 1429 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1430 amdgpu_amdkfd_init(); 1431 1432 /* let modprobe override vga console setting */ 1433 return pci_register_driver(&amdgpu_kms_pci_driver); 1434 1435 error_fence: 1436 amdgpu_sync_fini(); 1437 1438 error_sync: 1439 return r; 1440 } 1441 1442 static void __exit amdgpu_exit(void) 1443 { 1444 amdgpu_amdkfd_fini(); 1445 pci_unregister_driver(&amdgpu_kms_pci_driver); 1446 amdgpu_unregister_atpx_handler(); 1447 amdgpu_sync_fini(); 1448 amdgpu_fence_slab_fini(); 1449 } 1450 1451 module_init(amdgpu_init); 1452 module_exit(amdgpu_exit); 1453 1454 MODULE_AUTHOR(DRIVER_AUTHOR); 1455 MODULE_DESCRIPTION(DRIVER_DESC); 1456 MODULE_LICENSE("GPL and additional rights"); 1457