1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/fb.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 */ 104 #define KMS_DRIVER_MAJOR 3 105 #define KMS_DRIVER_MINOR 45 106 #define KMS_DRIVER_PATCHLEVEL 0 107 108 int amdgpu_vram_limit; 109 int amdgpu_vis_vram_limit; 110 int amdgpu_gart_size = -1; /* auto */ 111 int amdgpu_gtt_size = -1; /* auto */ 112 int amdgpu_moverate = -1; /* auto */ 113 int amdgpu_audio = -1; 114 int amdgpu_disp_priority; 115 int amdgpu_hw_i2c; 116 int amdgpu_pcie_gen2 = -1; 117 int amdgpu_msi = -1; 118 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 119 int amdgpu_dpm = -1; 120 int amdgpu_fw_load_type = -1; 121 int amdgpu_aspm = -1; 122 int amdgpu_runtime_pm = -1; 123 uint amdgpu_ip_block_mask = 0xffffffff; 124 int amdgpu_bapm = -1; 125 int amdgpu_deep_color; 126 int amdgpu_vm_size = -1; 127 int amdgpu_vm_fragment_size = -1; 128 int amdgpu_vm_block_size = -1; 129 int amdgpu_vm_fault_stop; 130 int amdgpu_vm_debug; 131 int amdgpu_vm_update_mode = -1; 132 int amdgpu_exp_hw_support; 133 int amdgpu_dc = -1; 134 int amdgpu_sched_jobs = 32; 135 int amdgpu_sched_hw_submission = 2; 136 uint amdgpu_pcie_gen_cap; 137 uint amdgpu_pcie_lane_cap; 138 uint amdgpu_cg_mask = 0xffffffff; 139 uint amdgpu_pg_mask = 0xffffffff; 140 uint amdgpu_sdma_phase_quantum = 32; 141 char *amdgpu_disable_cu = NULL; 142 char *amdgpu_virtual_display = NULL; 143 144 /* 145 * OverDrive(bit 14) disabled by default 146 * GFX DCS(bit 19) disabled by default 147 */ 148 uint amdgpu_pp_feature_mask = 0xfff7bfff; 149 uint amdgpu_force_long_training; 150 int amdgpu_job_hang_limit; 151 int amdgpu_lbpw = -1; 152 int amdgpu_compute_multipipe = -1; 153 int amdgpu_gpu_recovery = -1; /* auto */ 154 int amdgpu_emu_mode; 155 uint amdgpu_smu_memory_pool_size; 156 int amdgpu_smu_pptable_id = -1; 157 /* 158 * FBC (bit 0) disabled by default 159 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 160 * - With this, for multiple monitors in sync(e.g. with the same model), 161 * mclk switching will be allowed. And the mclk will be not foced to the 162 * highest. That helps saving some idle power. 163 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 164 * PSR (bit 3) disabled by default 165 * EDP NO POWER SEQUENCING (bit 4) disabled by default 166 */ 167 uint amdgpu_dc_feature_mask = 2; 168 uint amdgpu_dc_debug_mask; 169 int amdgpu_async_gfx_ring = 1; 170 int amdgpu_mcbp; 171 int amdgpu_discovery = -1; 172 int amdgpu_mes; 173 int amdgpu_noretry = -1; 174 int amdgpu_force_asic_type = -1; 175 int amdgpu_tmz = -1; /* auto */ 176 int amdgpu_reset_method = -1; /* auto */ 177 int amdgpu_num_kcq = -1; 178 int amdgpu_smartshift_bias; 179 int amdgpu_use_xgmi_p2p = 1; 180 181 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 182 183 struct amdgpu_mgpu_info mgpu_info = { 184 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 185 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 186 mgpu_info.delayed_reset_work, 187 amdgpu_drv_delayed_reset_work_handler, 0), 188 }; 189 int amdgpu_ras_enable = -1; 190 uint amdgpu_ras_mask = 0xffffffff; 191 int amdgpu_bad_page_threshold = -1; 192 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 193 .timeout_fatal_disable = false, 194 .period = 0x0, /* default to 0x0 (timeout disable) */ 195 }; 196 197 /** 198 * DOC: vramlimit (int) 199 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 200 */ 201 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 202 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 203 204 /** 205 * DOC: vis_vramlimit (int) 206 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 207 */ 208 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 209 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 210 211 /** 212 * DOC: gartsize (uint) 213 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 214 */ 215 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 216 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 217 218 /** 219 * DOC: gttsize (int) 220 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 221 * otherwise 3/4 RAM size). 222 */ 223 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 224 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 225 226 /** 227 * DOC: moverate (int) 228 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 229 */ 230 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 231 module_param_named(moverate, amdgpu_moverate, int, 0600); 232 233 /** 234 * DOC: audio (int) 235 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 236 */ 237 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 238 module_param_named(audio, amdgpu_audio, int, 0444); 239 240 /** 241 * DOC: disp_priority (int) 242 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 243 */ 244 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 245 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 246 247 /** 248 * DOC: hw_i2c (int) 249 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 250 */ 251 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 252 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 253 254 /** 255 * DOC: pcie_gen2 (int) 256 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 257 */ 258 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 259 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 260 261 /** 262 * DOC: msi (int) 263 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 264 */ 265 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 266 module_param_named(msi, amdgpu_msi, int, 0444); 267 268 /** 269 * DOC: lockup_timeout (string) 270 * Set GPU scheduler timeout value in ms. 271 * 272 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 273 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 274 * to the default timeout. 275 * 276 * - With one value specified, the setting will apply to all non-compute jobs. 277 * - With multiple values specified, the first one will be for GFX. 278 * The second one is for Compute. The third and fourth ones are 279 * for SDMA and Video. 280 * 281 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 282 * jobs is 10000. The timeout for compute is 60000. 283 */ 284 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 285 "for passthrough or sriov, 10000 for all jobs." 286 " 0: keep default value. negative: infinity timeout), " 287 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 288 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 289 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 290 291 /** 292 * DOC: dpm (int) 293 * Override for dynamic power management setting 294 * (0 = disable, 1 = enable) 295 * The default is -1 (auto). 296 */ 297 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 298 module_param_named(dpm, amdgpu_dpm, int, 0444); 299 300 /** 301 * DOC: fw_load_type (int) 302 * Set different firmware loading type for debugging, if supported. 303 * Set to 0 to force direct loading if supported by the ASIC. Set 304 * to -1 to select the default loading mode for the ASIC, as defined 305 * by the driver. The default is -1 (auto). 306 */ 307 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)"); 308 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 309 310 /** 311 * DOC: aspm (int) 312 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 313 */ 314 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 315 module_param_named(aspm, amdgpu_aspm, int, 0444); 316 317 /** 318 * DOC: runpm (int) 319 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 320 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 321 * Setting the value to 0 disables this functionality. 322 */ 323 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 324 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 325 326 /** 327 * DOC: ip_block_mask (uint) 328 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 329 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 330 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 331 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 332 */ 333 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 334 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 335 336 /** 337 * DOC: bapm (int) 338 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 339 * The default -1 (auto, enabled) 340 */ 341 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 342 module_param_named(bapm, amdgpu_bapm, int, 0444); 343 344 /** 345 * DOC: deep_color (int) 346 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 347 */ 348 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 349 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 350 351 /** 352 * DOC: vm_size (int) 353 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 354 */ 355 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 356 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 357 358 /** 359 * DOC: vm_fragment_size (int) 360 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 361 */ 362 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 363 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 364 365 /** 366 * DOC: vm_block_size (int) 367 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 368 */ 369 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 370 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 371 372 /** 373 * DOC: vm_fault_stop (int) 374 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 375 */ 376 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 377 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 378 379 /** 380 * DOC: vm_debug (int) 381 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 382 */ 383 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 384 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 385 386 /** 387 * DOC: vm_update_mode (int) 388 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 389 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 390 */ 391 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 392 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 393 394 /** 395 * DOC: exp_hw_support (int) 396 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 397 */ 398 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 399 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 400 401 /** 402 * DOC: dc (int) 403 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 404 */ 405 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 406 module_param_named(dc, amdgpu_dc, int, 0444); 407 408 /** 409 * DOC: sched_jobs (int) 410 * Override the max number of jobs supported in the sw queue. The default is 32. 411 */ 412 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 413 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 414 415 /** 416 * DOC: sched_hw_submission (int) 417 * Override the max number of HW submissions. The default is 2. 418 */ 419 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 420 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 421 422 /** 423 * DOC: ppfeaturemask (hexint) 424 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 425 * The default is the current set of stable power features. 426 */ 427 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 428 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 429 430 /** 431 * DOC: forcelongtraining (uint) 432 * Force long memory training in resume. 433 * The default is zero, indicates short training in resume. 434 */ 435 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 436 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 437 438 /** 439 * DOC: pcie_gen_cap (uint) 440 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 441 * The default is 0 (automatic for each asic). 442 */ 443 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 444 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 445 446 /** 447 * DOC: pcie_lane_cap (uint) 448 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 449 * The default is 0 (automatic for each asic). 450 */ 451 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 452 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 453 454 /** 455 * DOC: cg_mask (uint) 456 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 457 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 458 */ 459 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 460 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 461 462 /** 463 * DOC: pg_mask (uint) 464 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 465 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 466 */ 467 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 468 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 469 470 /** 471 * DOC: sdma_phase_quantum (uint) 472 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 473 */ 474 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 475 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 476 477 /** 478 * DOC: disable_cu (charp) 479 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 480 */ 481 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 482 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 483 484 /** 485 * DOC: virtual_display (charp) 486 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 487 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 488 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 489 * device at 26:00.0. The default is NULL. 490 */ 491 MODULE_PARM_DESC(virtual_display, 492 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 493 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 494 495 /** 496 * DOC: job_hang_limit (int) 497 * Set how much time allow a job hang and not drop it. The default is 0. 498 */ 499 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 500 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 501 502 /** 503 * DOC: lbpw (int) 504 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 505 */ 506 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 507 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 508 509 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 510 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 511 512 /** 513 * DOC: gpu_recovery (int) 514 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 515 */ 516 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 517 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 518 519 /** 520 * DOC: emu_mode (int) 521 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 522 */ 523 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 524 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 525 526 /** 527 * DOC: ras_enable (int) 528 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 529 */ 530 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 531 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 532 533 /** 534 * DOC: ras_mask (uint) 535 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 536 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 537 */ 538 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 539 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 540 541 /** 542 * DOC: timeout_fatal_disable (bool) 543 * Disable Watchdog timeout fatal error event 544 */ 545 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 546 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 547 548 /** 549 * DOC: timeout_period (uint) 550 * Modify the watchdog timeout max_cycles as (1 << period) 551 */ 552 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 553 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 554 555 /** 556 * DOC: si_support (int) 557 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 558 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 559 * otherwise using amdgpu driver. 560 */ 561 #ifdef CONFIG_DRM_AMDGPU_SI 562 563 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 564 int amdgpu_si_support = 0; 565 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 566 #else 567 int amdgpu_si_support = 1; 568 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 569 #endif 570 571 module_param_named(si_support, amdgpu_si_support, int, 0444); 572 #endif 573 574 /** 575 * DOC: cik_support (int) 576 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 577 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 578 * otherwise using amdgpu driver. 579 */ 580 #ifdef CONFIG_DRM_AMDGPU_CIK 581 582 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 583 int amdgpu_cik_support = 0; 584 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 585 #else 586 int amdgpu_cik_support = 1; 587 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 588 #endif 589 590 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 591 #endif 592 593 /** 594 * DOC: smu_memory_pool_size (uint) 595 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 596 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 597 */ 598 MODULE_PARM_DESC(smu_memory_pool_size, 599 "reserve gtt for smu debug usage, 0 = disable," 600 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 601 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 602 603 /** 604 * DOC: async_gfx_ring (int) 605 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 606 */ 607 MODULE_PARM_DESC(async_gfx_ring, 608 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 609 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 610 611 /** 612 * DOC: mcbp (int) 613 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 614 */ 615 MODULE_PARM_DESC(mcbp, 616 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 617 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 618 619 /** 620 * DOC: discovery (int) 621 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 622 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 623 */ 624 MODULE_PARM_DESC(discovery, 625 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 626 module_param_named(discovery, amdgpu_discovery, int, 0444); 627 628 /** 629 * DOC: mes (int) 630 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 631 * (0 = disabled (default), 1 = enabled) 632 */ 633 MODULE_PARM_DESC(mes, 634 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 635 module_param_named(mes, amdgpu_mes, int, 0444); 636 637 /** 638 * DOC: noretry (int) 639 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 640 * do not support per-process XNACK this also disables retry page faults. 641 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 642 */ 643 MODULE_PARM_DESC(noretry, 644 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 645 module_param_named(noretry, amdgpu_noretry, int, 0644); 646 647 /** 648 * DOC: force_asic_type (int) 649 * A non negative value used to specify the asic type for all supported GPUs. 650 */ 651 MODULE_PARM_DESC(force_asic_type, 652 "A non negative value used to specify the asic type for all supported GPUs"); 653 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 654 655 /** 656 * DOC: use_xgmi_p2p (int) 657 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 658 */ 659 MODULE_PARM_DESC(use_xgmi_p2p, 660 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 661 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 662 663 664 #ifdef CONFIG_HSA_AMD 665 /** 666 * DOC: sched_policy (int) 667 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 668 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 669 * assigns queues to HQDs. 670 */ 671 int sched_policy = KFD_SCHED_POLICY_HWS; 672 module_param(sched_policy, int, 0444); 673 MODULE_PARM_DESC(sched_policy, 674 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 675 676 /** 677 * DOC: hws_max_conc_proc (int) 678 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 679 * number of VMIDs assigned to the HWS, which is also the default. 680 */ 681 int hws_max_conc_proc = 8; 682 module_param(hws_max_conc_proc, int, 0444); 683 MODULE_PARM_DESC(hws_max_conc_proc, 684 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 685 686 /** 687 * DOC: cwsr_enable (int) 688 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 689 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 690 * disables it. 691 */ 692 int cwsr_enable = 1; 693 module_param(cwsr_enable, int, 0444); 694 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 695 696 /** 697 * DOC: max_num_of_queues_per_device (int) 698 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 699 * is 4096. 700 */ 701 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 702 module_param(max_num_of_queues_per_device, int, 0444); 703 MODULE_PARM_DESC(max_num_of_queues_per_device, 704 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 705 706 /** 707 * DOC: send_sigterm (int) 708 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 709 * but just print errors on dmesg. Setting 1 enables sending sigterm. 710 */ 711 int send_sigterm; 712 module_param(send_sigterm, int, 0444); 713 MODULE_PARM_DESC(send_sigterm, 714 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 715 716 /** 717 * DOC: debug_largebar (int) 718 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 719 * system. This limits the VRAM size reported to ROCm applications to the visible 720 * size, usually 256MB. 721 * Default value is 0, diabled. 722 */ 723 int debug_largebar; 724 module_param(debug_largebar, int, 0444); 725 MODULE_PARM_DESC(debug_largebar, 726 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 727 728 /** 729 * DOC: ignore_crat (int) 730 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 731 * table to get information about AMD APUs. This option can serve as a workaround on 732 * systems with a broken CRAT table. 733 * 734 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 735 * whether use CRAT) 736 */ 737 int ignore_crat; 738 module_param(ignore_crat, int, 0444); 739 MODULE_PARM_DESC(ignore_crat, 740 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 741 742 /** 743 * DOC: halt_if_hws_hang (int) 744 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 745 * Setting 1 enables halt on hang. 746 */ 747 int halt_if_hws_hang; 748 module_param(halt_if_hws_hang, int, 0644); 749 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 750 751 /** 752 * DOC: hws_gws_support(bool) 753 * Assume that HWS supports GWS barriers regardless of what firmware version 754 * check says. Default value: false (rely on MEC2 firmware version check). 755 */ 756 bool hws_gws_support; 757 module_param(hws_gws_support, bool, 0444); 758 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 759 760 /** 761 * DOC: queue_preemption_timeout_ms (int) 762 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 763 */ 764 int queue_preemption_timeout_ms = 9000; 765 module_param(queue_preemption_timeout_ms, int, 0644); 766 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 767 768 /** 769 * DOC: debug_evictions(bool) 770 * Enable extra debug messages to help determine the cause of evictions 771 */ 772 bool debug_evictions; 773 module_param(debug_evictions, bool, 0644); 774 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 775 776 /** 777 * DOC: no_system_mem_limit(bool) 778 * Disable system memory limit, to support multiple process shared memory 779 */ 780 bool no_system_mem_limit; 781 module_param(no_system_mem_limit, bool, 0644); 782 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 783 784 /** 785 * DOC: no_queue_eviction_on_vm_fault (int) 786 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 787 */ 788 int amdgpu_no_queue_eviction_on_vm_fault = 0; 789 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 790 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 791 #endif 792 793 /** 794 * DOC: dcfeaturemask (uint) 795 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 796 * The default is the current set of stable display features. 797 */ 798 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 799 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 800 801 /** 802 * DOC: dcdebugmask (uint) 803 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 804 */ 805 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 806 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 807 808 /** 809 * DOC: abmlevel (uint) 810 * Override the default ABM (Adaptive Backlight Management) level used for DC 811 * enabled hardware. Requires DMCU to be supported and loaded. 812 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 813 * default. Values 1-4 control the maximum allowable brightness reduction via 814 * the ABM algorithm, with 1 being the least reduction and 4 being the most 815 * reduction. 816 * 817 * Defaults to 0, or disabled. Userspace can still override this level later 818 * after boot. 819 */ 820 uint amdgpu_dm_abm_level; 821 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 822 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 823 824 int amdgpu_backlight = -1; 825 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 826 module_param_named(backlight, amdgpu_backlight, bint, 0444); 827 828 /** 829 * DOC: tmz (int) 830 * Trusted Memory Zone (TMZ) is a method to protect data being written 831 * to or read from memory. 832 * 833 * The default value: 0 (off). TODO: change to auto till it is completed. 834 */ 835 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 836 module_param_named(tmz, amdgpu_tmz, int, 0444); 837 838 /** 839 * DOC: reset_method (int) 840 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 841 */ 842 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 843 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 844 845 /** 846 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 847 * threshold value of faulty pages detected by RAS ECC, which may 848 * result in the GPU entering bad status when the number of total 849 * faulty pages by ECC exceeds the threshold value. 850 */ 851 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 852 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 853 854 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 855 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 856 857 /** 858 * DOC: smu_pptable_id (int) 859 * Used to override pptable id. id = 0 use VBIOS pptable. 860 * id > 0 use the soft pptable with specicfied id. 861 */ 862 MODULE_PARM_DESC(smu_pptable_id, 863 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 864 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 865 866 /* These devices are not supported by amdgpu. 867 * They are supported by the mach64, r128, radeon drivers 868 */ 869 static const u16 amdgpu_unsupported_pciidlist[] = { 870 /* mach64 */ 871 0x4354, 872 0x4358, 873 0x4554, 874 0x4742, 875 0x4744, 876 0x4749, 877 0x474C, 878 0x474D, 879 0x474E, 880 0x474F, 881 0x4750, 882 0x4751, 883 0x4752, 884 0x4753, 885 0x4754, 886 0x4755, 887 0x4756, 888 0x4757, 889 0x4758, 890 0x4759, 891 0x475A, 892 0x4C42, 893 0x4C44, 894 0x4C47, 895 0x4C49, 896 0x4C4D, 897 0x4C4E, 898 0x4C50, 899 0x4C51, 900 0x4C52, 901 0x4C53, 902 0x5654, 903 0x5655, 904 0x5656, 905 /* r128 */ 906 0x4c45, 907 0x4c46, 908 0x4d46, 909 0x4d4c, 910 0x5041, 911 0x5042, 912 0x5043, 913 0x5044, 914 0x5045, 915 0x5046, 916 0x5047, 917 0x5048, 918 0x5049, 919 0x504A, 920 0x504B, 921 0x504C, 922 0x504D, 923 0x504E, 924 0x504F, 925 0x5050, 926 0x5051, 927 0x5052, 928 0x5053, 929 0x5054, 930 0x5055, 931 0x5056, 932 0x5057, 933 0x5058, 934 0x5245, 935 0x5246, 936 0x5247, 937 0x524b, 938 0x524c, 939 0x534d, 940 0x5446, 941 0x544C, 942 0x5452, 943 /* radeon */ 944 0x3150, 945 0x3151, 946 0x3152, 947 0x3154, 948 0x3155, 949 0x3E50, 950 0x3E54, 951 0x4136, 952 0x4137, 953 0x4144, 954 0x4145, 955 0x4146, 956 0x4147, 957 0x4148, 958 0x4149, 959 0x414A, 960 0x414B, 961 0x4150, 962 0x4151, 963 0x4152, 964 0x4153, 965 0x4154, 966 0x4155, 967 0x4156, 968 0x4237, 969 0x4242, 970 0x4336, 971 0x4337, 972 0x4437, 973 0x4966, 974 0x4967, 975 0x4A48, 976 0x4A49, 977 0x4A4A, 978 0x4A4B, 979 0x4A4C, 980 0x4A4D, 981 0x4A4E, 982 0x4A4F, 983 0x4A50, 984 0x4A54, 985 0x4B48, 986 0x4B49, 987 0x4B4A, 988 0x4B4B, 989 0x4B4C, 990 0x4C57, 991 0x4C58, 992 0x4C59, 993 0x4C5A, 994 0x4C64, 995 0x4C66, 996 0x4C67, 997 0x4E44, 998 0x4E45, 999 0x4E46, 1000 0x4E47, 1001 0x4E48, 1002 0x4E49, 1003 0x4E4A, 1004 0x4E4B, 1005 0x4E50, 1006 0x4E51, 1007 0x4E52, 1008 0x4E53, 1009 0x4E54, 1010 0x4E56, 1011 0x5144, 1012 0x5145, 1013 0x5146, 1014 0x5147, 1015 0x5148, 1016 0x514C, 1017 0x514D, 1018 0x5157, 1019 0x5158, 1020 0x5159, 1021 0x515A, 1022 0x515E, 1023 0x5460, 1024 0x5462, 1025 0x5464, 1026 0x5548, 1027 0x5549, 1028 0x554A, 1029 0x554B, 1030 0x554C, 1031 0x554D, 1032 0x554E, 1033 0x554F, 1034 0x5550, 1035 0x5551, 1036 0x5552, 1037 0x5554, 1038 0x564A, 1039 0x564B, 1040 0x564F, 1041 0x5652, 1042 0x5653, 1043 0x5657, 1044 0x5834, 1045 0x5835, 1046 0x5954, 1047 0x5955, 1048 0x5974, 1049 0x5975, 1050 0x5960, 1051 0x5961, 1052 0x5962, 1053 0x5964, 1054 0x5965, 1055 0x5969, 1056 0x5a41, 1057 0x5a42, 1058 0x5a61, 1059 0x5a62, 1060 0x5b60, 1061 0x5b62, 1062 0x5b63, 1063 0x5b64, 1064 0x5b65, 1065 0x5c61, 1066 0x5c63, 1067 0x5d48, 1068 0x5d49, 1069 0x5d4a, 1070 0x5d4c, 1071 0x5d4d, 1072 0x5d4e, 1073 0x5d4f, 1074 0x5d50, 1075 0x5d52, 1076 0x5d57, 1077 0x5e48, 1078 0x5e4a, 1079 0x5e4b, 1080 0x5e4c, 1081 0x5e4d, 1082 0x5e4f, 1083 0x6700, 1084 0x6701, 1085 0x6702, 1086 0x6703, 1087 0x6704, 1088 0x6705, 1089 0x6706, 1090 0x6707, 1091 0x6708, 1092 0x6709, 1093 0x6718, 1094 0x6719, 1095 0x671c, 1096 0x671d, 1097 0x671f, 1098 0x6720, 1099 0x6721, 1100 0x6722, 1101 0x6723, 1102 0x6724, 1103 0x6725, 1104 0x6726, 1105 0x6727, 1106 0x6728, 1107 0x6729, 1108 0x6738, 1109 0x6739, 1110 0x673e, 1111 0x6740, 1112 0x6741, 1113 0x6742, 1114 0x6743, 1115 0x6744, 1116 0x6745, 1117 0x6746, 1118 0x6747, 1119 0x6748, 1120 0x6749, 1121 0x674A, 1122 0x6750, 1123 0x6751, 1124 0x6758, 1125 0x6759, 1126 0x675B, 1127 0x675D, 1128 0x675F, 1129 0x6760, 1130 0x6761, 1131 0x6762, 1132 0x6763, 1133 0x6764, 1134 0x6765, 1135 0x6766, 1136 0x6767, 1137 0x6768, 1138 0x6770, 1139 0x6771, 1140 0x6772, 1141 0x6778, 1142 0x6779, 1143 0x677B, 1144 0x6840, 1145 0x6841, 1146 0x6842, 1147 0x6843, 1148 0x6849, 1149 0x684C, 1150 0x6850, 1151 0x6858, 1152 0x6859, 1153 0x6880, 1154 0x6888, 1155 0x6889, 1156 0x688A, 1157 0x688C, 1158 0x688D, 1159 0x6898, 1160 0x6899, 1161 0x689b, 1162 0x689c, 1163 0x689d, 1164 0x689e, 1165 0x68a0, 1166 0x68a1, 1167 0x68a8, 1168 0x68a9, 1169 0x68b0, 1170 0x68b8, 1171 0x68b9, 1172 0x68ba, 1173 0x68be, 1174 0x68bf, 1175 0x68c0, 1176 0x68c1, 1177 0x68c7, 1178 0x68c8, 1179 0x68c9, 1180 0x68d8, 1181 0x68d9, 1182 0x68da, 1183 0x68de, 1184 0x68e0, 1185 0x68e1, 1186 0x68e4, 1187 0x68e5, 1188 0x68e8, 1189 0x68e9, 1190 0x68f1, 1191 0x68f2, 1192 0x68f8, 1193 0x68f9, 1194 0x68fa, 1195 0x68fe, 1196 0x7100, 1197 0x7101, 1198 0x7102, 1199 0x7103, 1200 0x7104, 1201 0x7105, 1202 0x7106, 1203 0x7108, 1204 0x7109, 1205 0x710A, 1206 0x710B, 1207 0x710C, 1208 0x710E, 1209 0x710F, 1210 0x7140, 1211 0x7141, 1212 0x7142, 1213 0x7143, 1214 0x7144, 1215 0x7145, 1216 0x7146, 1217 0x7147, 1218 0x7149, 1219 0x714A, 1220 0x714B, 1221 0x714C, 1222 0x714D, 1223 0x714E, 1224 0x714F, 1225 0x7151, 1226 0x7152, 1227 0x7153, 1228 0x715E, 1229 0x715F, 1230 0x7180, 1231 0x7181, 1232 0x7183, 1233 0x7186, 1234 0x7187, 1235 0x7188, 1236 0x718A, 1237 0x718B, 1238 0x718C, 1239 0x718D, 1240 0x718F, 1241 0x7193, 1242 0x7196, 1243 0x719B, 1244 0x719F, 1245 0x71C0, 1246 0x71C1, 1247 0x71C2, 1248 0x71C3, 1249 0x71C4, 1250 0x71C5, 1251 0x71C6, 1252 0x71C7, 1253 0x71CD, 1254 0x71CE, 1255 0x71D2, 1256 0x71D4, 1257 0x71D5, 1258 0x71D6, 1259 0x71DA, 1260 0x71DE, 1261 0x7200, 1262 0x7210, 1263 0x7211, 1264 0x7240, 1265 0x7243, 1266 0x7244, 1267 0x7245, 1268 0x7246, 1269 0x7247, 1270 0x7248, 1271 0x7249, 1272 0x724A, 1273 0x724B, 1274 0x724C, 1275 0x724D, 1276 0x724E, 1277 0x724F, 1278 0x7280, 1279 0x7281, 1280 0x7283, 1281 0x7284, 1282 0x7287, 1283 0x7288, 1284 0x7289, 1285 0x728B, 1286 0x728C, 1287 0x7290, 1288 0x7291, 1289 0x7293, 1290 0x7297, 1291 0x7834, 1292 0x7835, 1293 0x791e, 1294 0x791f, 1295 0x793f, 1296 0x7941, 1297 0x7942, 1298 0x796c, 1299 0x796d, 1300 0x796e, 1301 0x796f, 1302 0x9400, 1303 0x9401, 1304 0x9402, 1305 0x9403, 1306 0x9405, 1307 0x940A, 1308 0x940B, 1309 0x940F, 1310 0x94A0, 1311 0x94A1, 1312 0x94A3, 1313 0x94B1, 1314 0x94B3, 1315 0x94B4, 1316 0x94B5, 1317 0x94B9, 1318 0x9440, 1319 0x9441, 1320 0x9442, 1321 0x9443, 1322 0x9444, 1323 0x9446, 1324 0x944A, 1325 0x944B, 1326 0x944C, 1327 0x944E, 1328 0x9450, 1329 0x9452, 1330 0x9456, 1331 0x945A, 1332 0x945B, 1333 0x945E, 1334 0x9460, 1335 0x9462, 1336 0x946A, 1337 0x946B, 1338 0x947A, 1339 0x947B, 1340 0x9480, 1341 0x9487, 1342 0x9488, 1343 0x9489, 1344 0x948A, 1345 0x948F, 1346 0x9490, 1347 0x9491, 1348 0x9495, 1349 0x9498, 1350 0x949C, 1351 0x949E, 1352 0x949F, 1353 0x94C0, 1354 0x94C1, 1355 0x94C3, 1356 0x94C4, 1357 0x94C5, 1358 0x94C6, 1359 0x94C7, 1360 0x94C8, 1361 0x94C9, 1362 0x94CB, 1363 0x94CC, 1364 0x94CD, 1365 0x9500, 1366 0x9501, 1367 0x9504, 1368 0x9505, 1369 0x9506, 1370 0x9507, 1371 0x9508, 1372 0x9509, 1373 0x950F, 1374 0x9511, 1375 0x9515, 1376 0x9517, 1377 0x9519, 1378 0x9540, 1379 0x9541, 1380 0x9542, 1381 0x954E, 1382 0x954F, 1383 0x9552, 1384 0x9553, 1385 0x9555, 1386 0x9557, 1387 0x955f, 1388 0x9580, 1389 0x9581, 1390 0x9583, 1391 0x9586, 1392 0x9587, 1393 0x9588, 1394 0x9589, 1395 0x958A, 1396 0x958B, 1397 0x958C, 1398 0x958D, 1399 0x958E, 1400 0x958F, 1401 0x9590, 1402 0x9591, 1403 0x9593, 1404 0x9595, 1405 0x9596, 1406 0x9597, 1407 0x9598, 1408 0x9599, 1409 0x959B, 1410 0x95C0, 1411 0x95C2, 1412 0x95C4, 1413 0x95C5, 1414 0x95C6, 1415 0x95C7, 1416 0x95C9, 1417 0x95CC, 1418 0x95CD, 1419 0x95CE, 1420 0x95CF, 1421 0x9610, 1422 0x9611, 1423 0x9612, 1424 0x9613, 1425 0x9614, 1426 0x9615, 1427 0x9616, 1428 0x9640, 1429 0x9641, 1430 0x9642, 1431 0x9643, 1432 0x9644, 1433 0x9645, 1434 0x9647, 1435 0x9648, 1436 0x9649, 1437 0x964a, 1438 0x964b, 1439 0x964c, 1440 0x964e, 1441 0x964f, 1442 0x9710, 1443 0x9711, 1444 0x9712, 1445 0x9713, 1446 0x9714, 1447 0x9715, 1448 0x9802, 1449 0x9803, 1450 0x9804, 1451 0x9805, 1452 0x9806, 1453 0x9807, 1454 0x9808, 1455 0x9809, 1456 0x980A, 1457 0x9900, 1458 0x9901, 1459 0x9903, 1460 0x9904, 1461 0x9905, 1462 0x9906, 1463 0x9907, 1464 0x9908, 1465 0x9909, 1466 0x990A, 1467 0x990B, 1468 0x990C, 1469 0x990D, 1470 0x990E, 1471 0x990F, 1472 0x9910, 1473 0x9913, 1474 0x9917, 1475 0x9918, 1476 0x9919, 1477 0x9990, 1478 0x9991, 1479 0x9992, 1480 0x9993, 1481 0x9994, 1482 0x9995, 1483 0x9996, 1484 0x9997, 1485 0x9998, 1486 0x9999, 1487 0x999A, 1488 0x999B, 1489 0x999C, 1490 0x999D, 1491 0x99A0, 1492 0x99A2, 1493 0x99A4, 1494 /* radeon secondary ids */ 1495 0x3171, 1496 0x3e70, 1497 0x4164, 1498 0x4165, 1499 0x4166, 1500 0x4168, 1501 0x4170, 1502 0x4171, 1503 0x4172, 1504 0x4173, 1505 0x496e, 1506 0x4a69, 1507 0x4a6a, 1508 0x4a6b, 1509 0x4a70, 1510 0x4a74, 1511 0x4b69, 1512 0x4b6b, 1513 0x4b6c, 1514 0x4c6e, 1515 0x4e64, 1516 0x4e65, 1517 0x4e66, 1518 0x4e67, 1519 0x4e68, 1520 0x4e69, 1521 0x4e6a, 1522 0x4e71, 1523 0x4f73, 1524 0x5569, 1525 0x556b, 1526 0x556d, 1527 0x556f, 1528 0x5571, 1529 0x5854, 1530 0x5874, 1531 0x5940, 1532 0x5941, 1533 0x5b72, 1534 0x5b73, 1535 0x5b74, 1536 0x5b75, 1537 0x5d44, 1538 0x5d45, 1539 0x5d6d, 1540 0x5d6f, 1541 0x5d72, 1542 0x5d77, 1543 0x5e6b, 1544 0x5e6d, 1545 0x7120, 1546 0x7124, 1547 0x7129, 1548 0x712e, 1549 0x712f, 1550 0x7162, 1551 0x7163, 1552 0x7166, 1553 0x7167, 1554 0x7172, 1555 0x7173, 1556 0x71a0, 1557 0x71a1, 1558 0x71a3, 1559 0x71a7, 1560 0x71bb, 1561 0x71e0, 1562 0x71e1, 1563 0x71e2, 1564 0x71e6, 1565 0x71e7, 1566 0x71f2, 1567 0x7269, 1568 0x726b, 1569 0x726e, 1570 0x72a0, 1571 0x72a8, 1572 0x72b1, 1573 0x72b3, 1574 0x793f, 1575 }; 1576 1577 static const struct pci_device_id pciidlist[] = { 1578 #ifdef CONFIG_DRM_AMDGPU_SI 1579 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1580 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1581 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1582 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1583 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1584 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1585 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1586 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1587 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1588 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1589 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1590 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1591 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1592 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1593 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1594 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1595 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1596 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1597 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1598 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1599 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1600 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1601 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1602 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1603 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1604 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1605 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1606 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1607 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1608 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1609 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1610 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1611 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1612 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1613 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1614 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1615 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1616 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1617 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1618 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1619 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1620 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1621 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1622 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1623 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1624 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1625 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1626 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1627 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1630 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1631 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1632 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1633 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1634 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1635 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1636 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1637 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1638 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1639 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1640 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1641 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1642 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1643 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1644 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1645 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1647 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1648 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1649 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1650 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1651 #endif 1652 #ifdef CONFIG_DRM_AMDGPU_CIK 1653 /* Kaveri */ 1654 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1655 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1656 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1657 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1658 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1659 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1660 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1661 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1662 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1663 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1664 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1665 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1666 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1667 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1668 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1669 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1670 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1671 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1672 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1673 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1674 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1675 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1676 /* Bonaire */ 1677 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1678 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1679 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1680 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1681 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1682 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1683 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1684 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1685 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1686 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1687 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1688 /* Hawaii */ 1689 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1690 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1691 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1692 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1693 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1694 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1695 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1696 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1697 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1698 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1699 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1700 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1701 /* Kabini */ 1702 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1703 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1704 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1705 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1706 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1707 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1708 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1709 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1710 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1711 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1713 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1714 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1715 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1716 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1717 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1718 /* mullins */ 1719 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1720 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1721 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1722 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1723 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1724 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1725 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1726 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1727 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1728 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1729 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1730 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1731 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1733 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1735 #endif 1736 /* topaz */ 1737 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1738 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1739 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1740 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1741 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1742 /* tonga */ 1743 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1744 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1745 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1746 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1747 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1748 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1749 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1750 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1751 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1752 /* fiji */ 1753 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1754 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1755 /* carrizo */ 1756 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1757 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1758 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1759 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1760 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1761 /* stoney */ 1762 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1763 /* Polaris11 */ 1764 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1765 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1766 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1767 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1768 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1769 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1770 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1771 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1772 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1773 /* Polaris10 */ 1774 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1775 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1776 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1777 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1778 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1779 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1780 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1781 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1782 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1783 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1784 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1785 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1786 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1787 /* Polaris12 */ 1788 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1789 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1790 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1791 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1792 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1793 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1794 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1795 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1796 /* VEGAM */ 1797 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1798 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1799 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1800 /* Vega 10 */ 1801 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1802 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1803 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1804 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1805 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1806 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1807 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1808 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1809 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1810 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1811 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1812 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1813 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1814 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1815 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1816 /* Vega 12 */ 1817 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1818 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1819 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1820 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1821 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1822 /* Vega 20 */ 1823 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1824 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1825 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1826 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1827 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1828 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1829 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1830 /* Raven */ 1831 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1832 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1833 /* Arcturus */ 1834 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1835 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1836 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1837 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1838 /* Navi10 */ 1839 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1840 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1841 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1842 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1843 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1844 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1845 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1846 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1847 /* Navi14 */ 1848 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1849 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1850 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1851 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1852 1853 /* Renoir */ 1854 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1855 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1856 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1857 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1858 1859 /* Navi12 */ 1860 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1861 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1862 1863 /* Sienna_Cichlid */ 1864 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1865 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1866 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1867 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1868 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1869 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1870 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1871 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1872 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1873 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1874 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1875 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1876 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1877 1878 /* Van Gogh */ 1879 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1880 1881 /* Yellow Carp */ 1882 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1883 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1884 1885 /* Navy_Flounder */ 1886 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1887 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1888 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1889 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1890 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1891 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1892 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1893 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1894 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1895 1896 /* DIMGREY_CAVEFISH */ 1897 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1898 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1899 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1900 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1901 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1902 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1903 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1904 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1905 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1906 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1907 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1908 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1909 1910 /* Aldebaran */ 1911 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1912 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1913 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1914 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1915 1916 /* CYAN_SKILLFISH */ 1917 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1918 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1919 1920 /* BEIGE_GOBY */ 1921 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1922 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1923 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1924 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1925 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1926 1927 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1928 .class = PCI_CLASS_DISPLAY_VGA << 8, 1929 .class_mask = 0xffffff, 1930 .driver_data = CHIP_IP_DISCOVERY }, 1931 1932 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1933 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1934 .class_mask = 0xffffff, 1935 .driver_data = CHIP_IP_DISCOVERY }, 1936 1937 {0, 0, 0} 1938 }; 1939 1940 MODULE_DEVICE_TABLE(pci, pciidlist); 1941 1942 static const struct drm_driver amdgpu_kms_driver; 1943 1944 static bool amdgpu_is_fw_framebuffer(resource_size_t base, 1945 resource_size_t size) 1946 { 1947 bool found = false; 1948 #if IS_REACHABLE(CONFIG_FB) 1949 struct apertures_struct *a; 1950 1951 a = alloc_apertures(1); 1952 if (!a) 1953 return false; 1954 1955 a->ranges[0].base = base; 1956 a->ranges[0].size = size; 1957 1958 found = is_firmware_framebuffer(a); 1959 kfree(a); 1960 #endif 1961 return found; 1962 } 1963 1964 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1965 { 1966 struct pci_dev *p = NULL; 1967 int i; 1968 1969 /* 0 - GPU 1970 * 1 - audio 1971 * 2 - USB 1972 * 3 - UCSI 1973 */ 1974 for (i = 1; i < 4; i++) { 1975 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1976 adev->pdev->bus->number, i); 1977 if (p) { 1978 pm_runtime_get_sync(&p->dev); 1979 pm_runtime_mark_last_busy(&p->dev); 1980 pm_runtime_put_autosuspend(&p->dev); 1981 pci_dev_put(p); 1982 } 1983 } 1984 } 1985 1986 static int amdgpu_pci_probe(struct pci_dev *pdev, 1987 const struct pci_device_id *ent) 1988 { 1989 struct drm_device *ddev; 1990 struct amdgpu_device *adev; 1991 unsigned long flags = ent->driver_data; 1992 int ret, retry = 0, i; 1993 bool supports_atomic = false; 1994 bool is_fw_fb; 1995 resource_size_t base, size; 1996 1997 /* skip devices which are owned by radeon */ 1998 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1999 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2000 return -ENODEV; 2001 } 2002 2003 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2004 amdgpu_aspm = 0; 2005 2006 if (amdgpu_virtual_display || 2007 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2008 supports_atomic = true; 2009 2010 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2011 DRM_INFO("This hardware requires experimental hardware support.\n" 2012 "See modparam exp_hw_support\n"); 2013 return -ENODEV; 2014 } 2015 2016 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2017 * however, SME requires an indirect IOMMU mapping because the encryption 2018 * bit is beyond the DMA mask of the chip. 2019 */ 2020 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2021 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2022 dev_info(&pdev->dev, 2023 "SME is not compatible with RAVEN\n"); 2024 return -ENOTSUPP; 2025 } 2026 2027 #ifdef CONFIG_DRM_AMDGPU_SI 2028 if (!amdgpu_si_support) { 2029 switch (flags & AMD_ASIC_MASK) { 2030 case CHIP_TAHITI: 2031 case CHIP_PITCAIRN: 2032 case CHIP_VERDE: 2033 case CHIP_OLAND: 2034 case CHIP_HAINAN: 2035 dev_info(&pdev->dev, 2036 "SI support provided by radeon.\n"); 2037 dev_info(&pdev->dev, 2038 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2039 ); 2040 return -ENODEV; 2041 } 2042 } 2043 #endif 2044 #ifdef CONFIG_DRM_AMDGPU_CIK 2045 if (!amdgpu_cik_support) { 2046 switch (flags & AMD_ASIC_MASK) { 2047 case CHIP_KAVERI: 2048 case CHIP_BONAIRE: 2049 case CHIP_HAWAII: 2050 case CHIP_KABINI: 2051 case CHIP_MULLINS: 2052 dev_info(&pdev->dev, 2053 "CIK support provided by radeon.\n"); 2054 dev_info(&pdev->dev, 2055 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2056 ); 2057 return -ENODEV; 2058 } 2059 } 2060 #endif 2061 2062 base = pci_resource_start(pdev, 0); 2063 size = pci_resource_len(pdev, 0); 2064 is_fw_fb = amdgpu_is_fw_framebuffer(base, size); 2065 2066 /* Get rid of things like offb */ 2067 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2068 if (ret) 2069 return ret; 2070 2071 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2072 if (IS_ERR(adev)) 2073 return PTR_ERR(adev); 2074 2075 adev->dev = &pdev->dev; 2076 adev->pdev = pdev; 2077 ddev = adev_to_drm(adev); 2078 adev->is_fw_fb = is_fw_fb; 2079 2080 if (!supports_atomic) 2081 ddev->driver_features &= ~DRIVER_ATOMIC; 2082 2083 ret = pci_enable_device(pdev); 2084 if (ret) 2085 return ret; 2086 2087 pci_set_drvdata(pdev, ddev); 2088 2089 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2090 if (ret) 2091 goto err_pci; 2092 2093 retry_init: 2094 ret = drm_dev_register(ddev, ent->driver_data); 2095 if (ret == -EAGAIN && ++retry <= 3) { 2096 DRM_INFO("retry init %d\n", retry); 2097 /* Don't request EX mode too frequently which is attacking */ 2098 msleep(5000); 2099 goto retry_init; 2100 } else if (ret) { 2101 goto err_pci; 2102 } 2103 2104 /* 2105 * 1. don't init fbdev on hw without DCE 2106 * 2. don't init fbdev if there are no connectors 2107 */ 2108 if (adev->mode_info.mode_config_initialized && 2109 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2110 /* select 8 bpp console on low vram cards */ 2111 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2112 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2113 else 2114 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2115 } 2116 2117 ret = amdgpu_debugfs_init(adev); 2118 if (ret) 2119 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2120 2121 if (adev->runpm) { 2122 /* only need to skip on ATPX */ 2123 if (amdgpu_device_supports_px(ddev)) 2124 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2125 /* we want direct complete for BOCO */ 2126 if (amdgpu_device_supports_boco(ddev)) 2127 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2128 DPM_FLAG_SMART_SUSPEND | 2129 DPM_FLAG_MAY_SKIP_RESUME); 2130 pm_runtime_use_autosuspend(ddev->dev); 2131 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2132 2133 pm_runtime_allow(ddev->dev); 2134 2135 pm_runtime_mark_last_busy(ddev->dev); 2136 pm_runtime_put_autosuspend(ddev->dev); 2137 2138 /* 2139 * For runpm implemented via BACO, PMFW will handle the 2140 * timing for BACO in and out: 2141 * - put ASIC into BACO state only when both video and 2142 * audio functions are in D3 state. 2143 * - pull ASIC out of BACO state when either video or 2144 * audio function is in D0 state. 2145 * Also, at startup, PMFW assumes both functions are in 2146 * D0 state. 2147 * 2148 * So if snd driver was loaded prior to amdgpu driver 2149 * and audio function was put into D3 state, there will 2150 * be no PMFW-aware D-state transition(D0->D3) on runpm 2151 * suspend. Thus the BACO will be not correctly kicked in. 2152 * 2153 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2154 * into D0 state. Then there will be a PMFW-aware D-state 2155 * transition(D0->D3) on runpm suspend. 2156 */ 2157 if (amdgpu_device_supports_baco(ddev) && 2158 !(adev->flags & AMD_IS_APU) && 2159 (adev->asic_type >= CHIP_NAVI10)) 2160 amdgpu_get_secondary_funcs(adev); 2161 } 2162 2163 return 0; 2164 2165 err_pci: 2166 pci_disable_device(pdev); 2167 return ret; 2168 } 2169 2170 static void 2171 amdgpu_pci_remove(struct pci_dev *pdev) 2172 { 2173 struct drm_device *dev = pci_get_drvdata(pdev); 2174 struct amdgpu_device *adev = drm_to_adev(dev); 2175 2176 drm_dev_unplug(dev); 2177 2178 if (adev->runpm) { 2179 pm_runtime_get_sync(dev->dev); 2180 pm_runtime_forbid(dev->dev); 2181 } 2182 2183 amdgpu_driver_unload_kms(dev); 2184 2185 /* 2186 * Flush any in flight DMA operations from device. 2187 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2188 * StatusTransactions Pending bit. 2189 */ 2190 pci_disable_device(pdev); 2191 pci_wait_for_pending_transaction(pdev); 2192 } 2193 2194 static void 2195 amdgpu_pci_shutdown(struct pci_dev *pdev) 2196 { 2197 struct drm_device *dev = pci_get_drvdata(pdev); 2198 struct amdgpu_device *adev = drm_to_adev(dev); 2199 2200 if (amdgpu_ras_intr_triggered()) 2201 return; 2202 2203 /* if we are running in a VM, make sure the device 2204 * torn down properly on reboot/shutdown. 2205 * unfortunately we can't detect certain 2206 * hypervisors so just do this all the time. 2207 */ 2208 if (!amdgpu_passthrough(adev)) 2209 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2210 amdgpu_device_ip_suspend(adev); 2211 adev->mp1_state = PP_MP1_STATE_NONE; 2212 } 2213 2214 /** 2215 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2216 * 2217 * @work: work_struct. 2218 */ 2219 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2220 { 2221 struct list_head device_list; 2222 struct amdgpu_device *adev; 2223 int i, r; 2224 struct amdgpu_reset_context reset_context; 2225 2226 memset(&reset_context, 0, sizeof(reset_context)); 2227 2228 mutex_lock(&mgpu_info.mutex); 2229 if (mgpu_info.pending_reset == true) { 2230 mutex_unlock(&mgpu_info.mutex); 2231 return; 2232 } 2233 mgpu_info.pending_reset = true; 2234 mutex_unlock(&mgpu_info.mutex); 2235 2236 /* Use a common context, just need to make sure full reset is done */ 2237 reset_context.method = AMD_RESET_METHOD_NONE; 2238 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2239 2240 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2241 adev = mgpu_info.gpu_ins[i].adev; 2242 reset_context.reset_req_dev = adev; 2243 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2244 if (r) { 2245 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2246 r, adev_to_drm(adev)->unique); 2247 } 2248 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2249 r = -EALREADY; 2250 } 2251 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2252 adev = mgpu_info.gpu_ins[i].adev; 2253 flush_work(&adev->xgmi_reset_work); 2254 adev->gmc.xgmi.pending_reset = false; 2255 } 2256 2257 /* reset function will rebuild the xgmi hive info , clear it now */ 2258 for (i = 0; i < mgpu_info.num_dgpu; i++) 2259 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2260 2261 INIT_LIST_HEAD(&device_list); 2262 2263 for (i = 0; i < mgpu_info.num_dgpu; i++) 2264 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2265 2266 /* unregister the GPU first, reset function will add them back */ 2267 list_for_each_entry(adev, &device_list, reset_list) 2268 amdgpu_unregister_gpu_instance(adev); 2269 2270 /* Use a common context, just need to make sure full reset is done */ 2271 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2272 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2273 2274 if (r) { 2275 DRM_ERROR("reinit gpus failure"); 2276 return; 2277 } 2278 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2279 adev = mgpu_info.gpu_ins[i].adev; 2280 if (!adev->kfd.init_complete) 2281 amdgpu_amdkfd_device_init(adev); 2282 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2283 } 2284 return; 2285 } 2286 2287 static int amdgpu_pmops_prepare(struct device *dev) 2288 { 2289 struct drm_device *drm_dev = dev_get_drvdata(dev); 2290 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2291 2292 /* Return a positive number here so 2293 * DPM_FLAG_SMART_SUSPEND works properly 2294 */ 2295 if (amdgpu_device_supports_boco(drm_dev)) 2296 return pm_runtime_suspended(dev); 2297 2298 /* if we will not support s3 or s2i for the device 2299 * then skip suspend 2300 */ 2301 if (!amdgpu_acpi_is_s0ix_active(adev) && 2302 !amdgpu_acpi_is_s3_active(adev)) 2303 return 1; 2304 2305 return 0; 2306 } 2307 2308 static void amdgpu_pmops_complete(struct device *dev) 2309 { 2310 /* nothing to do */ 2311 } 2312 2313 static int amdgpu_pmops_suspend(struct device *dev) 2314 { 2315 struct drm_device *drm_dev = dev_get_drvdata(dev); 2316 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2317 int r; 2318 2319 if (amdgpu_acpi_is_s0ix_active(adev)) 2320 adev->in_s0ix = true; 2321 else 2322 adev->in_s3 = true; 2323 r = amdgpu_device_suspend(drm_dev, true); 2324 if (r) 2325 return r; 2326 if (!adev->in_s0ix) 2327 r = amdgpu_asic_reset(adev); 2328 return r; 2329 } 2330 2331 static int amdgpu_pmops_resume(struct device *dev) 2332 { 2333 struct drm_device *drm_dev = dev_get_drvdata(dev); 2334 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2335 int r; 2336 2337 /* Avoids registers access if device is physically gone */ 2338 if (!pci_device_is_present(adev->pdev)) 2339 adev->no_hw_access = true; 2340 2341 r = amdgpu_device_resume(drm_dev, true); 2342 if (amdgpu_acpi_is_s0ix_active(adev)) 2343 adev->in_s0ix = false; 2344 else 2345 adev->in_s3 = false; 2346 return r; 2347 } 2348 2349 static int amdgpu_pmops_freeze(struct device *dev) 2350 { 2351 struct drm_device *drm_dev = dev_get_drvdata(dev); 2352 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2353 int r; 2354 2355 adev->in_s4 = true; 2356 r = amdgpu_device_suspend(drm_dev, true); 2357 adev->in_s4 = false; 2358 if (r) 2359 return r; 2360 return amdgpu_asic_reset(adev); 2361 } 2362 2363 static int amdgpu_pmops_thaw(struct device *dev) 2364 { 2365 struct drm_device *drm_dev = dev_get_drvdata(dev); 2366 2367 return amdgpu_device_resume(drm_dev, true); 2368 } 2369 2370 static int amdgpu_pmops_poweroff(struct device *dev) 2371 { 2372 struct drm_device *drm_dev = dev_get_drvdata(dev); 2373 2374 return amdgpu_device_suspend(drm_dev, true); 2375 } 2376 2377 static int amdgpu_pmops_restore(struct device *dev) 2378 { 2379 struct drm_device *drm_dev = dev_get_drvdata(dev); 2380 2381 return amdgpu_device_resume(drm_dev, true); 2382 } 2383 2384 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2385 { 2386 struct pci_dev *pdev = to_pci_dev(dev); 2387 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2388 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2389 int ret, i; 2390 2391 if (!adev->runpm) { 2392 pm_runtime_forbid(dev); 2393 return -EBUSY; 2394 } 2395 2396 /* wait for all rings to drain before suspending */ 2397 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2398 struct amdgpu_ring *ring = adev->rings[i]; 2399 if (ring && ring->sched.ready) { 2400 ret = amdgpu_fence_wait_empty(ring); 2401 if (ret) 2402 return -EBUSY; 2403 } 2404 } 2405 2406 adev->in_runpm = true; 2407 if (amdgpu_device_supports_px(drm_dev)) 2408 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2409 2410 /* 2411 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2412 * proper cleanups and put itself into a state ready for PNP. That 2413 * can address some random resuming failure observed on BOCO capable 2414 * platforms. 2415 * TODO: this may be also needed for PX capable platform. 2416 */ 2417 if (amdgpu_device_supports_boco(drm_dev)) 2418 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2419 2420 ret = amdgpu_device_suspend(drm_dev, false); 2421 if (ret) { 2422 adev->in_runpm = false; 2423 if (amdgpu_device_supports_boco(drm_dev)) 2424 adev->mp1_state = PP_MP1_STATE_NONE; 2425 return ret; 2426 } 2427 2428 if (amdgpu_device_supports_boco(drm_dev)) 2429 adev->mp1_state = PP_MP1_STATE_NONE; 2430 2431 if (amdgpu_device_supports_px(drm_dev)) { 2432 /* Only need to handle PCI state in the driver for ATPX 2433 * PCI core handles it for _PR3. 2434 */ 2435 amdgpu_device_cache_pci_state(pdev); 2436 pci_disable_device(pdev); 2437 pci_ignore_hotplug(pdev); 2438 pci_set_power_state(pdev, PCI_D3cold); 2439 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2440 } else if (amdgpu_device_supports_boco(drm_dev)) { 2441 /* nothing to do */ 2442 } else if (amdgpu_device_supports_baco(drm_dev)) { 2443 amdgpu_device_baco_enter(drm_dev); 2444 } 2445 2446 return 0; 2447 } 2448 2449 static int amdgpu_pmops_runtime_resume(struct device *dev) 2450 { 2451 struct pci_dev *pdev = to_pci_dev(dev); 2452 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2453 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2454 int ret; 2455 2456 if (!adev->runpm) 2457 return -EINVAL; 2458 2459 /* Avoids registers access if device is physically gone */ 2460 if (!pci_device_is_present(adev->pdev)) 2461 adev->no_hw_access = true; 2462 2463 if (amdgpu_device_supports_px(drm_dev)) { 2464 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2465 2466 /* Only need to handle PCI state in the driver for ATPX 2467 * PCI core handles it for _PR3. 2468 */ 2469 pci_set_power_state(pdev, PCI_D0); 2470 amdgpu_device_load_pci_state(pdev); 2471 ret = pci_enable_device(pdev); 2472 if (ret) 2473 return ret; 2474 pci_set_master(pdev); 2475 } else if (amdgpu_device_supports_boco(drm_dev)) { 2476 /* Only need to handle PCI state in the driver for ATPX 2477 * PCI core handles it for _PR3. 2478 */ 2479 pci_set_master(pdev); 2480 } else if (amdgpu_device_supports_baco(drm_dev)) { 2481 amdgpu_device_baco_exit(drm_dev); 2482 } 2483 ret = amdgpu_device_resume(drm_dev, false); 2484 if (ret) 2485 return ret; 2486 2487 if (amdgpu_device_supports_px(drm_dev)) 2488 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2489 adev->in_runpm = false; 2490 return 0; 2491 } 2492 2493 static int amdgpu_pmops_runtime_idle(struct device *dev) 2494 { 2495 struct drm_device *drm_dev = dev_get_drvdata(dev); 2496 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2497 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2498 int ret = 1; 2499 2500 if (!adev->runpm) { 2501 pm_runtime_forbid(dev); 2502 return -EBUSY; 2503 } 2504 2505 if (amdgpu_device_has_dc_support(adev)) { 2506 struct drm_crtc *crtc; 2507 2508 drm_for_each_crtc(crtc, drm_dev) { 2509 drm_modeset_lock(&crtc->mutex, NULL); 2510 if (crtc->state->active) 2511 ret = -EBUSY; 2512 drm_modeset_unlock(&crtc->mutex); 2513 if (ret < 0) 2514 break; 2515 } 2516 2517 } else { 2518 struct drm_connector *list_connector; 2519 struct drm_connector_list_iter iter; 2520 2521 mutex_lock(&drm_dev->mode_config.mutex); 2522 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2523 2524 drm_connector_list_iter_begin(drm_dev, &iter); 2525 drm_for_each_connector_iter(list_connector, &iter) { 2526 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2527 ret = -EBUSY; 2528 break; 2529 } 2530 } 2531 2532 drm_connector_list_iter_end(&iter); 2533 2534 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2535 mutex_unlock(&drm_dev->mode_config.mutex); 2536 } 2537 2538 if (ret == -EBUSY) 2539 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2540 2541 pm_runtime_mark_last_busy(dev); 2542 pm_runtime_autosuspend(dev); 2543 return ret; 2544 } 2545 2546 long amdgpu_drm_ioctl(struct file *filp, 2547 unsigned int cmd, unsigned long arg) 2548 { 2549 struct drm_file *file_priv = filp->private_data; 2550 struct drm_device *dev; 2551 long ret; 2552 dev = file_priv->minor->dev; 2553 ret = pm_runtime_get_sync(dev->dev); 2554 if (ret < 0) 2555 goto out; 2556 2557 ret = drm_ioctl(filp, cmd, arg); 2558 2559 pm_runtime_mark_last_busy(dev->dev); 2560 out: 2561 pm_runtime_put_autosuspend(dev->dev); 2562 return ret; 2563 } 2564 2565 static const struct dev_pm_ops amdgpu_pm_ops = { 2566 .prepare = amdgpu_pmops_prepare, 2567 .complete = amdgpu_pmops_complete, 2568 .suspend = amdgpu_pmops_suspend, 2569 .resume = amdgpu_pmops_resume, 2570 .freeze = amdgpu_pmops_freeze, 2571 .thaw = amdgpu_pmops_thaw, 2572 .poweroff = amdgpu_pmops_poweroff, 2573 .restore = amdgpu_pmops_restore, 2574 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2575 .runtime_resume = amdgpu_pmops_runtime_resume, 2576 .runtime_idle = amdgpu_pmops_runtime_idle, 2577 }; 2578 2579 static int amdgpu_flush(struct file *f, fl_owner_t id) 2580 { 2581 struct drm_file *file_priv = f->private_data; 2582 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2583 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2584 2585 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2586 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2587 2588 return timeout >= 0 ? 0 : timeout; 2589 } 2590 2591 static const struct file_operations amdgpu_driver_kms_fops = { 2592 .owner = THIS_MODULE, 2593 .open = drm_open, 2594 .flush = amdgpu_flush, 2595 .release = drm_release, 2596 .unlocked_ioctl = amdgpu_drm_ioctl, 2597 .mmap = drm_gem_mmap, 2598 .poll = drm_poll, 2599 .read = drm_read, 2600 #ifdef CONFIG_COMPAT 2601 .compat_ioctl = amdgpu_kms_compat_ioctl, 2602 #endif 2603 #ifdef CONFIG_PROC_FS 2604 .show_fdinfo = amdgpu_show_fdinfo 2605 #endif 2606 }; 2607 2608 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2609 { 2610 struct drm_file *file; 2611 2612 if (!filp) 2613 return -EINVAL; 2614 2615 if (filp->f_op != &amdgpu_driver_kms_fops) { 2616 return -EINVAL; 2617 } 2618 2619 file = filp->private_data; 2620 *fpriv = file->driver_priv; 2621 return 0; 2622 } 2623 2624 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2625 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2626 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2627 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2628 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2629 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2630 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2631 /* KMS */ 2632 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2633 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2634 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2635 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2636 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2637 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2638 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2639 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2640 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2641 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2642 }; 2643 2644 static const struct drm_driver amdgpu_kms_driver = { 2645 .driver_features = 2646 DRIVER_ATOMIC | 2647 DRIVER_GEM | 2648 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2649 DRIVER_SYNCOBJ_TIMELINE, 2650 .open = amdgpu_driver_open_kms, 2651 .postclose = amdgpu_driver_postclose_kms, 2652 .lastclose = amdgpu_driver_lastclose_kms, 2653 .ioctls = amdgpu_ioctls_kms, 2654 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2655 .dumb_create = amdgpu_mode_dumb_create, 2656 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2657 .fops = &amdgpu_driver_kms_fops, 2658 .release = &amdgpu_driver_release_kms, 2659 2660 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2661 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2662 .gem_prime_import = amdgpu_gem_prime_import, 2663 .gem_prime_mmap = drm_gem_prime_mmap, 2664 2665 .name = DRIVER_NAME, 2666 .desc = DRIVER_DESC, 2667 .date = DRIVER_DATE, 2668 .major = KMS_DRIVER_MAJOR, 2669 .minor = KMS_DRIVER_MINOR, 2670 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2671 }; 2672 2673 static struct pci_error_handlers amdgpu_pci_err_handler = { 2674 .error_detected = amdgpu_pci_error_detected, 2675 .mmio_enabled = amdgpu_pci_mmio_enabled, 2676 .slot_reset = amdgpu_pci_slot_reset, 2677 .resume = amdgpu_pci_resume, 2678 }; 2679 2680 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2681 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2682 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2683 2684 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2685 &amdgpu_vram_mgr_attr_group, 2686 &amdgpu_gtt_mgr_attr_group, 2687 &amdgpu_vbios_version_attr_group, 2688 NULL, 2689 }; 2690 2691 2692 static struct pci_driver amdgpu_kms_pci_driver = { 2693 .name = DRIVER_NAME, 2694 .id_table = pciidlist, 2695 .probe = amdgpu_pci_probe, 2696 .remove = amdgpu_pci_remove, 2697 .shutdown = amdgpu_pci_shutdown, 2698 .driver.pm = &amdgpu_pm_ops, 2699 .err_handler = &amdgpu_pci_err_handler, 2700 .dev_groups = amdgpu_sysfs_groups, 2701 }; 2702 2703 static int __init amdgpu_init(void) 2704 { 2705 int r; 2706 2707 if (drm_firmware_drivers_only()) 2708 return -EINVAL; 2709 2710 r = amdgpu_sync_init(); 2711 if (r) 2712 goto error_sync; 2713 2714 r = amdgpu_fence_slab_init(); 2715 if (r) 2716 goto error_fence; 2717 2718 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2719 amdgpu_register_atpx_handler(); 2720 amdgpu_acpi_detect(); 2721 2722 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2723 amdgpu_amdkfd_init(); 2724 2725 /* let modprobe override vga console setting */ 2726 return pci_register_driver(&amdgpu_kms_pci_driver); 2727 2728 error_fence: 2729 amdgpu_sync_fini(); 2730 2731 error_sync: 2732 return r; 2733 } 2734 2735 static void __exit amdgpu_exit(void) 2736 { 2737 amdgpu_amdkfd_fini(); 2738 pci_unregister_driver(&amdgpu_kms_pci_driver); 2739 amdgpu_unregister_atpx_handler(); 2740 amdgpu_sync_fini(); 2741 amdgpu_fence_slab_fini(); 2742 mmu_notifier_synchronize(); 2743 } 2744 2745 module_init(amdgpu_init); 2746 module_exit(amdgpu_exit); 2747 2748 MODULE_AUTHOR(DRIVER_AUTHOR); 2749 MODULE_DESCRIPTION(DRIVER_DESC); 2750 MODULE_LICENSE("GPL and additional rights"); 2751