1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/fb.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 */ 104 #define KMS_DRIVER_MAJOR 3 105 #define KMS_DRIVER_MINOR 45 106 #define KMS_DRIVER_PATCHLEVEL 0 107 108 int amdgpu_vram_limit; 109 int amdgpu_vis_vram_limit; 110 int amdgpu_gart_size = -1; /* auto */ 111 int amdgpu_gtt_size = -1; /* auto */ 112 int amdgpu_moverate = -1; /* auto */ 113 int amdgpu_audio = -1; 114 int amdgpu_disp_priority; 115 int amdgpu_hw_i2c; 116 int amdgpu_pcie_gen2 = -1; 117 int amdgpu_msi = -1; 118 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 119 int amdgpu_dpm = -1; 120 int amdgpu_fw_load_type = -1; 121 int amdgpu_aspm = -1; 122 int amdgpu_runtime_pm = -1; 123 uint amdgpu_ip_block_mask = 0xffffffff; 124 int amdgpu_bapm = -1; 125 int amdgpu_deep_color; 126 int amdgpu_vm_size = -1; 127 int amdgpu_vm_fragment_size = -1; 128 int amdgpu_vm_block_size = -1; 129 int amdgpu_vm_fault_stop; 130 int amdgpu_vm_debug; 131 int amdgpu_vm_update_mode = -1; 132 int amdgpu_exp_hw_support; 133 int amdgpu_dc = -1; 134 int amdgpu_sched_jobs = 32; 135 int amdgpu_sched_hw_submission = 2; 136 uint amdgpu_pcie_gen_cap; 137 uint amdgpu_pcie_lane_cap; 138 uint amdgpu_cg_mask = 0xffffffff; 139 uint amdgpu_pg_mask = 0xffffffff; 140 uint amdgpu_sdma_phase_quantum = 32; 141 char *amdgpu_disable_cu = NULL; 142 char *amdgpu_virtual_display = NULL; 143 144 /* 145 * OverDrive(bit 14) disabled by default 146 * GFX DCS(bit 19) disabled by default 147 */ 148 uint amdgpu_pp_feature_mask = 0xfff7bfff; 149 uint amdgpu_force_long_training; 150 int amdgpu_job_hang_limit; 151 int amdgpu_lbpw = -1; 152 int amdgpu_compute_multipipe = -1; 153 int amdgpu_gpu_recovery = -1; /* auto */ 154 int amdgpu_emu_mode; 155 uint amdgpu_smu_memory_pool_size; 156 int amdgpu_smu_pptable_id = -1; 157 /* 158 * FBC (bit 0) disabled by default 159 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 160 * - With this, for multiple monitors in sync(e.g. with the same model), 161 * mclk switching will be allowed. And the mclk will be not foced to the 162 * highest. That helps saving some idle power. 163 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 164 * PSR (bit 3) disabled by default 165 * EDP NO POWER SEQUENCING (bit 4) disabled by default 166 */ 167 uint amdgpu_dc_feature_mask = 2; 168 uint amdgpu_dc_debug_mask; 169 int amdgpu_async_gfx_ring = 1; 170 int amdgpu_mcbp; 171 int amdgpu_discovery = -1; 172 int amdgpu_mes; 173 int amdgpu_noretry = -1; 174 int amdgpu_force_asic_type = -1; 175 int amdgpu_tmz = -1; /* auto */ 176 int amdgpu_reset_method = -1; /* auto */ 177 int amdgpu_num_kcq = -1; 178 int amdgpu_smartshift_bias; 179 180 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 181 182 struct amdgpu_mgpu_info mgpu_info = { 183 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 184 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 185 mgpu_info.delayed_reset_work, 186 amdgpu_drv_delayed_reset_work_handler, 0), 187 }; 188 int amdgpu_ras_enable = -1; 189 uint amdgpu_ras_mask = 0xffffffff; 190 int amdgpu_bad_page_threshold = -1; 191 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 192 .timeout_fatal_disable = false, 193 .period = 0x0, /* default to 0x0 (timeout disable) */ 194 }; 195 196 /** 197 * DOC: vramlimit (int) 198 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 199 */ 200 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 201 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 202 203 /** 204 * DOC: vis_vramlimit (int) 205 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 206 */ 207 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 208 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 209 210 /** 211 * DOC: gartsize (uint) 212 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 213 */ 214 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 215 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 216 217 /** 218 * DOC: gttsize (int) 219 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 220 * otherwise 3/4 RAM size). 221 */ 222 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 223 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 224 225 /** 226 * DOC: moverate (int) 227 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 228 */ 229 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 230 module_param_named(moverate, amdgpu_moverate, int, 0600); 231 232 /** 233 * DOC: audio (int) 234 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 235 */ 236 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 237 module_param_named(audio, amdgpu_audio, int, 0444); 238 239 /** 240 * DOC: disp_priority (int) 241 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 242 */ 243 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 244 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 245 246 /** 247 * DOC: hw_i2c (int) 248 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 249 */ 250 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 251 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 252 253 /** 254 * DOC: pcie_gen2 (int) 255 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 256 */ 257 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 258 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 259 260 /** 261 * DOC: msi (int) 262 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 263 */ 264 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 265 module_param_named(msi, amdgpu_msi, int, 0444); 266 267 /** 268 * DOC: lockup_timeout (string) 269 * Set GPU scheduler timeout value in ms. 270 * 271 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 272 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 273 * to the default timeout. 274 * 275 * - With one value specified, the setting will apply to all non-compute jobs. 276 * - With multiple values specified, the first one will be for GFX. 277 * The second one is for Compute. The third and fourth ones are 278 * for SDMA and Video. 279 * 280 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 281 * jobs is 10000. The timeout for compute is 60000. 282 */ 283 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 284 "for passthrough or sriov, 10000 for all jobs." 285 " 0: keep default value. negative: infinity timeout), " 286 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 287 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 288 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 289 290 /** 291 * DOC: dpm (int) 292 * Override for dynamic power management setting 293 * (0 = disable, 1 = enable) 294 * The default is -1 (auto). 295 */ 296 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 297 module_param_named(dpm, amdgpu_dpm, int, 0444); 298 299 /** 300 * DOC: fw_load_type (int) 301 * Set different firmware loading type for debugging, if supported. 302 * Set to 0 to force direct loading if supported by the ASIC. Set 303 * to -1 to select the default loading mode for the ASIC, as defined 304 * by the driver. The default is -1 (auto). 305 */ 306 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)"); 307 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 308 309 /** 310 * DOC: aspm (int) 311 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 312 */ 313 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 314 module_param_named(aspm, amdgpu_aspm, int, 0444); 315 316 /** 317 * DOC: runpm (int) 318 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 319 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 320 * Setting the value to 0 disables this functionality. 321 */ 322 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 323 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 324 325 /** 326 * DOC: ip_block_mask (uint) 327 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 328 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 329 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 330 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 331 */ 332 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 333 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 334 335 /** 336 * DOC: bapm (int) 337 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 338 * The default -1 (auto, enabled) 339 */ 340 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 341 module_param_named(bapm, amdgpu_bapm, int, 0444); 342 343 /** 344 * DOC: deep_color (int) 345 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 346 */ 347 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 348 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 349 350 /** 351 * DOC: vm_size (int) 352 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 353 */ 354 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 355 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 356 357 /** 358 * DOC: vm_fragment_size (int) 359 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 360 */ 361 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 362 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 363 364 /** 365 * DOC: vm_block_size (int) 366 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 367 */ 368 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 369 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 370 371 /** 372 * DOC: vm_fault_stop (int) 373 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 374 */ 375 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 376 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 377 378 /** 379 * DOC: vm_debug (int) 380 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 381 */ 382 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 383 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 384 385 /** 386 * DOC: vm_update_mode (int) 387 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 388 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 389 */ 390 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 391 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 392 393 /** 394 * DOC: exp_hw_support (int) 395 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 396 */ 397 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 398 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 399 400 /** 401 * DOC: dc (int) 402 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 403 */ 404 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 405 module_param_named(dc, amdgpu_dc, int, 0444); 406 407 /** 408 * DOC: sched_jobs (int) 409 * Override the max number of jobs supported in the sw queue. The default is 32. 410 */ 411 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 412 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 413 414 /** 415 * DOC: sched_hw_submission (int) 416 * Override the max number of HW submissions. The default is 2. 417 */ 418 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 419 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 420 421 /** 422 * DOC: ppfeaturemask (hexint) 423 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 424 * The default is the current set of stable power features. 425 */ 426 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 427 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 428 429 /** 430 * DOC: forcelongtraining (uint) 431 * Force long memory training in resume. 432 * The default is zero, indicates short training in resume. 433 */ 434 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 435 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 436 437 /** 438 * DOC: pcie_gen_cap (uint) 439 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 440 * The default is 0 (automatic for each asic). 441 */ 442 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 443 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 444 445 /** 446 * DOC: pcie_lane_cap (uint) 447 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 448 * The default is 0 (automatic for each asic). 449 */ 450 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 451 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 452 453 /** 454 * DOC: cg_mask (uint) 455 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 456 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 457 */ 458 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 459 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 460 461 /** 462 * DOC: pg_mask (uint) 463 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 464 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 465 */ 466 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 467 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 468 469 /** 470 * DOC: sdma_phase_quantum (uint) 471 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 472 */ 473 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 474 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 475 476 /** 477 * DOC: disable_cu (charp) 478 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 479 */ 480 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 481 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 482 483 /** 484 * DOC: virtual_display (charp) 485 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 486 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 487 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 488 * device at 26:00.0. The default is NULL. 489 */ 490 MODULE_PARM_DESC(virtual_display, 491 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 492 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 493 494 /** 495 * DOC: job_hang_limit (int) 496 * Set how much time allow a job hang and not drop it. The default is 0. 497 */ 498 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 499 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 500 501 /** 502 * DOC: lbpw (int) 503 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 504 */ 505 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 506 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 507 508 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 509 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 510 511 /** 512 * DOC: gpu_recovery (int) 513 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 514 */ 515 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 516 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 517 518 /** 519 * DOC: emu_mode (int) 520 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 521 */ 522 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 523 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 524 525 /** 526 * DOC: ras_enable (int) 527 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 528 */ 529 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 530 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 531 532 /** 533 * DOC: ras_mask (uint) 534 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 535 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 536 */ 537 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 538 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 539 540 /** 541 * DOC: timeout_fatal_disable (bool) 542 * Disable Watchdog timeout fatal error event 543 */ 544 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 545 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 546 547 /** 548 * DOC: timeout_period (uint) 549 * Modify the watchdog timeout max_cycles as (1 << period) 550 */ 551 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 552 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 553 554 /** 555 * DOC: si_support (int) 556 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 557 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 558 * otherwise using amdgpu driver. 559 */ 560 #ifdef CONFIG_DRM_AMDGPU_SI 561 562 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 563 int amdgpu_si_support = 0; 564 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 565 #else 566 int amdgpu_si_support = 1; 567 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 568 #endif 569 570 module_param_named(si_support, amdgpu_si_support, int, 0444); 571 #endif 572 573 /** 574 * DOC: cik_support (int) 575 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 576 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 577 * otherwise using amdgpu driver. 578 */ 579 #ifdef CONFIG_DRM_AMDGPU_CIK 580 581 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 582 int amdgpu_cik_support = 0; 583 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 584 #else 585 int amdgpu_cik_support = 1; 586 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 587 #endif 588 589 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 590 #endif 591 592 /** 593 * DOC: smu_memory_pool_size (uint) 594 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 595 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 596 */ 597 MODULE_PARM_DESC(smu_memory_pool_size, 598 "reserve gtt for smu debug usage, 0 = disable," 599 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 600 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 601 602 /** 603 * DOC: async_gfx_ring (int) 604 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 605 */ 606 MODULE_PARM_DESC(async_gfx_ring, 607 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 608 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 609 610 /** 611 * DOC: mcbp (int) 612 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 613 */ 614 MODULE_PARM_DESC(mcbp, 615 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 616 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 617 618 /** 619 * DOC: discovery (int) 620 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 621 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 622 */ 623 MODULE_PARM_DESC(discovery, 624 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 625 module_param_named(discovery, amdgpu_discovery, int, 0444); 626 627 /** 628 * DOC: mes (int) 629 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 630 * (0 = disabled (default), 1 = enabled) 631 */ 632 MODULE_PARM_DESC(mes, 633 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 634 module_param_named(mes, amdgpu_mes, int, 0444); 635 636 /** 637 * DOC: noretry (int) 638 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 639 * do not support per-process XNACK this also disables retry page faults. 640 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 641 */ 642 MODULE_PARM_DESC(noretry, 643 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 644 module_param_named(noretry, amdgpu_noretry, int, 0644); 645 646 /** 647 * DOC: force_asic_type (int) 648 * A non negative value used to specify the asic type for all supported GPUs. 649 */ 650 MODULE_PARM_DESC(force_asic_type, 651 "A non negative value used to specify the asic type for all supported GPUs"); 652 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 653 654 655 656 #ifdef CONFIG_HSA_AMD 657 /** 658 * DOC: sched_policy (int) 659 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 660 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 661 * assigns queues to HQDs. 662 */ 663 int sched_policy = KFD_SCHED_POLICY_HWS; 664 module_param(sched_policy, int, 0444); 665 MODULE_PARM_DESC(sched_policy, 666 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 667 668 /** 669 * DOC: hws_max_conc_proc (int) 670 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 671 * number of VMIDs assigned to the HWS, which is also the default. 672 */ 673 int hws_max_conc_proc = 8; 674 module_param(hws_max_conc_proc, int, 0444); 675 MODULE_PARM_DESC(hws_max_conc_proc, 676 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 677 678 /** 679 * DOC: cwsr_enable (int) 680 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 681 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 682 * disables it. 683 */ 684 int cwsr_enable = 1; 685 module_param(cwsr_enable, int, 0444); 686 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 687 688 /** 689 * DOC: max_num_of_queues_per_device (int) 690 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 691 * is 4096. 692 */ 693 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 694 module_param(max_num_of_queues_per_device, int, 0444); 695 MODULE_PARM_DESC(max_num_of_queues_per_device, 696 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 697 698 /** 699 * DOC: send_sigterm (int) 700 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 701 * but just print errors on dmesg. Setting 1 enables sending sigterm. 702 */ 703 int send_sigterm; 704 module_param(send_sigterm, int, 0444); 705 MODULE_PARM_DESC(send_sigterm, 706 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 707 708 /** 709 * DOC: debug_largebar (int) 710 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 711 * system. This limits the VRAM size reported to ROCm applications to the visible 712 * size, usually 256MB. 713 * Default value is 0, diabled. 714 */ 715 int debug_largebar; 716 module_param(debug_largebar, int, 0444); 717 MODULE_PARM_DESC(debug_largebar, 718 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 719 720 /** 721 * DOC: ignore_crat (int) 722 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 723 * table to get information about AMD APUs. This option can serve as a workaround on 724 * systems with a broken CRAT table. 725 * 726 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 727 * whether use CRAT) 728 */ 729 int ignore_crat; 730 module_param(ignore_crat, int, 0444); 731 MODULE_PARM_DESC(ignore_crat, 732 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 733 734 /** 735 * DOC: halt_if_hws_hang (int) 736 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 737 * Setting 1 enables halt on hang. 738 */ 739 int halt_if_hws_hang; 740 module_param(halt_if_hws_hang, int, 0644); 741 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 742 743 /** 744 * DOC: hws_gws_support(bool) 745 * Assume that HWS supports GWS barriers regardless of what firmware version 746 * check says. Default value: false (rely on MEC2 firmware version check). 747 */ 748 bool hws_gws_support; 749 module_param(hws_gws_support, bool, 0444); 750 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 751 752 /** 753 * DOC: queue_preemption_timeout_ms (int) 754 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 755 */ 756 int queue_preemption_timeout_ms = 9000; 757 module_param(queue_preemption_timeout_ms, int, 0644); 758 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 759 760 /** 761 * DOC: debug_evictions(bool) 762 * Enable extra debug messages to help determine the cause of evictions 763 */ 764 bool debug_evictions; 765 module_param(debug_evictions, bool, 0644); 766 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 767 768 /** 769 * DOC: no_system_mem_limit(bool) 770 * Disable system memory limit, to support multiple process shared memory 771 */ 772 bool no_system_mem_limit; 773 module_param(no_system_mem_limit, bool, 0644); 774 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 775 776 /** 777 * DOC: no_queue_eviction_on_vm_fault (int) 778 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 779 */ 780 int amdgpu_no_queue_eviction_on_vm_fault = 0; 781 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 782 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 783 #endif 784 785 /** 786 * DOC: dcfeaturemask (uint) 787 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 788 * The default is the current set of stable display features. 789 */ 790 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 791 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 792 793 /** 794 * DOC: dcdebugmask (uint) 795 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 796 */ 797 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 798 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 799 800 /** 801 * DOC: abmlevel (uint) 802 * Override the default ABM (Adaptive Backlight Management) level used for DC 803 * enabled hardware. Requires DMCU to be supported and loaded. 804 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 805 * default. Values 1-4 control the maximum allowable brightness reduction via 806 * the ABM algorithm, with 1 being the least reduction and 4 being the most 807 * reduction. 808 * 809 * Defaults to 0, or disabled. Userspace can still override this level later 810 * after boot. 811 */ 812 uint amdgpu_dm_abm_level; 813 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 814 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 815 816 int amdgpu_backlight = -1; 817 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 818 module_param_named(backlight, amdgpu_backlight, bint, 0444); 819 820 /** 821 * DOC: tmz (int) 822 * Trusted Memory Zone (TMZ) is a method to protect data being written 823 * to or read from memory. 824 * 825 * The default value: 0 (off). TODO: change to auto till it is completed. 826 */ 827 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 828 module_param_named(tmz, amdgpu_tmz, int, 0444); 829 830 /** 831 * DOC: reset_method (int) 832 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 833 */ 834 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 835 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 836 837 /** 838 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 839 * threshold value of faulty pages detected by RAS ECC, which may 840 * result in the GPU entering bad status when the number of total 841 * faulty pages by ECC exceeds the threshold value. 842 */ 843 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 844 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 845 846 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 847 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 848 849 /** 850 * DOC: smu_pptable_id (int) 851 * Used to override pptable id. id = 0 use VBIOS pptable. 852 * id > 0 use the soft pptable with specicfied id. 853 */ 854 MODULE_PARM_DESC(smu_pptable_id, 855 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 856 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 857 858 /* These devices are not supported by amdgpu. 859 * They are supported by the mach64, r128, radeon drivers 860 */ 861 static const u16 amdgpu_unsupported_pciidlist[] = { 862 /* mach64 */ 863 0x4354, 864 0x4358, 865 0x4554, 866 0x4742, 867 0x4744, 868 0x4749, 869 0x474C, 870 0x474D, 871 0x474E, 872 0x474F, 873 0x4750, 874 0x4751, 875 0x4752, 876 0x4753, 877 0x4754, 878 0x4755, 879 0x4756, 880 0x4757, 881 0x4758, 882 0x4759, 883 0x475A, 884 0x4C42, 885 0x4C44, 886 0x4C47, 887 0x4C49, 888 0x4C4D, 889 0x4C4E, 890 0x4C50, 891 0x4C51, 892 0x4C52, 893 0x4C53, 894 0x5654, 895 0x5655, 896 0x5656, 897 /* r128 */ 898 0x4c45, 899 0x4c46, 900 0x4d46, 901 0x4d4c, 902 0x5041, 903 0x5042, 904 0x5043, 905 0x5044, 906 0x5045, 907 0x5046, 908 0x5047, 909 0x5048, 910 0x5049, 911 0x504A, 912 0x504B, 913 0x504C, 914 0x504D, 915 0x504E, 916 0x504F, 917 0x5050, 918 0x5051, 919 0x5052, 920 0x5053, 921 0x5054, 922 0x5055, 923 0x5056, 924 0x5057, 925 0x5058, 926 0x5245, 927 0x5246, 928 0x5247, 929 0x524b, 930 0x524c, 931 0x534d, 932 0x5446, 933 0x544C, 934 0x5452, 935 /* radeon */ 936 0x3150, 937 0x3151, 938 0x3152, 939 0x3154, 940 0x3155, 941 0x3E50, 942 0x3E54, 943 0x4136, 944 0x4137, 945 0x4144, 946 0x4145, 947 0x4146, 948 0x4147, 949 0x4148, 950 0x4149, 951 0x414A, 952 0x414B, 953 0x4150, 954 0x4151, 955 0x4152, 956 0x4153, 957 0x4154, 958 0x4155, 959 0x4156, 960 0x4237, 961 0x4242, 962 0x4336, 963 0x4337, 964 0x4437, 965 0x4966, 966 0x4967, 967 0x4A48, 968 0x4A49, 969 0x4A4A, 970 0x4A4B, 971 0x4A4C, 972 0x4A4D, 973 0x4A4E, 974 0x4A4F, 975 0x4A50, 976 0x4A54, 977 0x4B48, 978 0x4B49, 979 0x4B4A, 980 0x4B4B, 981 0x4B4C, 982 0x4C57, 983 0x4C58, 984 0x4C59, 985 0x4C5A, 986 0x4C64, 987 0x4C66, 988 0x4C67, 989 0x4E44, 990 0x4E45, 991 0x4E46, 992 0x4E47, 993 0x4E48, 994 0x4E49, 995 0x4E4A, 996 0x4E4B, 997 0x4E50, 998 0x4E51, 999 0x4E52, 1000 0x4E53, 1001 0x4E54, 1002 0x4E56, 1003 0x5144, 1004 0x5145, 1005 0x5146, 1006 0x5147, 1007 0x5148, 1008 0x514C, 1009 0x514D, 1010 0x5157, 1011 0x5158, 1012 0x5159, 1013 0x515A, 1014 0x515E, 1015 0x5460, 1016 0x5462, 1017 0x5464, 1018 0x5548, 1019 0x5549, 1020 0x554A, 1021 0x554B, 1022 0x554C, 1023 0x554D, 1024 0x554E, 1025 0x554F, 1026 0x5550, 1027 0x5551, 1028 0x5552, 1029 0x5554, 1030 0x564A, 1031 0x564B, 1032 0x564F, 1033 0x5652, 1034 0x5653, 1035 0x5657, 1036 0x5834, 1037 0x5835, 1038 0x5954, 1039 0x5955, 1040 0x5974, 1041 0x5975, 1042 0x5960, 1043 0x5961, 1044 0x5962, 1045 0x5964, 1046 0x5965, 1047 0x5969, 1048 0x5a41, 1049 0x5a42, 1050 0x5a61, 1051 0x5a62, 1052 0x5b60, 1053 0x5b62, 1054 0x5b63, 1055 0x5b64, 1056 0x5b65, 1057 0x5c61, 1058 0x5c63, 1059 0x5d48, 1060 0x5d49, 1061 0x5d4a, 1062 0x5d4c, 1063 0x5d4d, 1064 0x5d4e, 1065 0x5d4f, 1066 0x5d50, 1067 0x5d52, 1068 0x5d57, 1069 0x5e48, 1070 0x5e4a, 1071 0x5e4b, 1072 0x5e4c, 1073 0x5e4d, 1074 0x5e4f, 1075 0x6700, 1076 0x6701, 1077 0x6702, 1078 0x6703, 1079 0x6704, 1080 0x6705, 1081 0x6706, 1082 0x6707, 1083 0x6708, 1084 0x6709, 1085 0x6718, 1086 0x6719, 1087 0x671c, 1088 0x671d, 1089 0x671f, 1090 0x6720, 1091 0x6721, 1092 0x6722, 1093 0x6723, 1094 0x6724, 1095 0x6725, 1096 0x6726, 1097 0x6727, 1098 0x6728, 1099 0x6729, 1100 0x6738, 1101 0x6739, 1102 0x673e, 1103 0x6740, 1104 0x6741, 1105 0x6742, 1106 0x6743, 1107 0x6744, 1108 0x6745, 1109 0x6746, 1110 0x6747, 1111 0x6748, 1112 0x6749, 1113 0x674A, 1114 0x6750, 1115 0x6751, 1116 0x6758, 1117 0x6759, 1118 0x675B, 1119 0x675D, 1120 0x675F, 1121 0x6760, 1122 0x6761, 1123 0x6762, 1124 0x6763, 1125 0x6764, 1126 0x6765, 1127 0x6766, 1128 0x6767, 1129 0x6768, 1130 0x6770, 1131 0x6771, 1132 0x6772, 1133 0x6778, 1134 0x6779, 1135 0x677B, 1136 0x6840, 1137 0x6841, 1138 0x6842, 1139 0x6843, 1140 0x6849, 1141 0x684C, 1142 0x6850, 1143 0x6858, 1144 0x6859, 1145 0x6880, 1146 0x6888, 1147 0x6889, 1148 0x688A, 1149 0x688C, 1150 0x688D, 1151 0x6898, 1152 0x6899, 1153 0x689b, 1154 0x689c, 1155 0x689d, 1156 0x689e, 1157 0x68a0, 1158 0x68a1, 1159 0x68a8, 1160 0x68a9, 1161 0x68b0, 1162 0x68b8, 1163 0x68b9, 1164 0x68ba, 1165 0x68be, 1166 0x68bf, 1167 0x68c0, 1168 0x68c1, 1169 0x68c7, 1170 0x68c8, 1171 0x68c9, 1172 0x68d8, 1173 0x68d9, 1174 0x68da, 1175 0x68de, 1176 0x68e0, 1177 0x68e1, 1178 0x68e4, 1179 0x68e5, 1180 0x68e8, 1181 0x68e9, 1182 0x68f1, 1183 0x68f2, 1184 0x68f8, 1185 0x68f9, 1186 0x68fa, 1187 0x68fe, 1188 0x7100, 1189 0x7101, 1190 0x7102, 1191 0x7103, 1192 0x7104, 1193 0x7105, 1194 0x7106, 1195 0x7108, 1196 0x7109, 1197 0x710A, 1198 0x710B, 1199 0x710C, 1200 0x710E, 1201 0x710F, 1202 0x7140, 1203 0x7141, 1204 0x7142, 1205 0x7143, 1206 0x7144, 1207 0x7145, 1208 0x7146, 1209 0x7147, 1210 0x7149, 1211 0x714A, 1212 0x714B, 1213 0x714C, 1214 0x714D, 1215 0x714E, 1216 0x714F, 1217 0x7151, 1218 0x7152, 1219 0x7153, 1220 0x715E, 1221 0x715F, 1222 0x7180, 1223 0x7181, 1224 0x7183, 1225 0x7186, 1226 0x7187, 1227 0x7188, 1228 0x718A, 1229 0x718B, 1230 0x718C, 1231 0x718D, 1232 0x718F, 1233 0x7193, 1234 0x7196, 1235 0x719B, 1236 0x719F, 1237 0x71C0, 1238 0x71C1, 1239 0x71C2, 1240 0x71C3, 1241 0x71C4, 1242 0x71C5, 1243 0x71C6, 1244 0x71C7, 1245 0x71CD, 1246 0x71CE, 1247 0x71D2, 1248 0x71D4, 1249 0x71D5, 1250 0x71D6, 1251 0x71DA, 1252 0x71DE, 1253 0x7200, 1254 0x7210, 1255 0x7211, 1256 0x7240, 1257 0x7243, 1258 0x7244, 1259 0x7245, 1260 0x7246, 1261 0x7247, 1262 0x7248, 1263 0x7249, 1264 0x724A, 1265 0x724B, 1266 0x724C, 1267 0x724D, 1268 0x724E, 1269 0x724F, 1270 0x7280, 1271 0x7281, 1272 0x7283, 1273 0x7284, 1274 0x7287, 1275 0x7288, 1276 0x7289, 1277 0x728B, 1278 0x728C, 1279 0x7290, 1280 0x7291, 1281 0x7293, 1282 0x7297, 1283 0x7834, 1284 0x7835, 1285 0x791e, 1286 0x791f, 1287 0x793f, 1288 0x7941, 1289 0x7942, 1290 0x796c, 1291 0x796d, 1292 0x796e, 1293 0x796f, 1294 0x9400, 1295 0x9401, 1296 0x9402, 1297 0x9403, 1298 0x9405, 1299 0x940A, 1300 0x940B, 1301 0x940F, 1302 0x94A0, 1303 0x94A1, 1304 0x94A3, 1305 0x94B1, 1306 0x94B3, 1307 0x94B4, 1308 0x94B5, 1309 0x94B9, 1310 0x9440, 1311 0x9441, 1312 0x9442, 1313 0x9443, 1314 0x9444, 1315 0x9446, 1316 0x944A, 1317 0x944B, 1318 0x944C, 1319 0x944E, 1320 0x9450, 1321 0x9452, 1322 0x9456, 1323 0x945A, 1324 0x945B, 1325 0x945E, 1326 0x9460, 1327 0x9462, 1328 0x946A, 1329 0x946B, 1330 0x947A, 1331 0x947B, 1332 0x9480, 1333 0x9487, 1334 0x9488, 1335 0x9489, 1336 0x948A, 1337 0x948F, 1338 0x9490, 1339 0x9491, 1340 0x9495, 1341 0x9498, 1342 0x949C, 1343 0x949E, 1344 0x949F, 1345 0x94C0, 1346 0x94C1, 1347 0x94C3, 1348 0x94C4, 1349 0x94C5, 1350 0x94C6, 1351 0x94C7, 1352 0x94C8, 1353 0x94C9, 1354 0x94CB, 1355 0x94CC, 1356 0x94CD, 1357 0x9500, 1358 0x9501, 1359 0x9504, 1360 0x9505, 1361 0x9506, 1362 0x9507, 1363 0x9508, 1364 0x9509, 1365 0x950F, 1366 0x9511, 1367 0x9515, 1368 0x9517, 1369 0x9519, 1370 0x9540, 1371 0x9541, 1372 0x9542, 1373 0x954E, 1374 0x954F, 1375 0x9552, 1376 0x9553, 1377 0x9555, 1378 0x9557, 1379 0x955f, 1380 0x9580, 1381 0x9581, 1382 0x9583, 1383 0x9586, 1384 0x9587, 1385 0x9588, 1386 0x9589, 1387 0x958A, 1388 0x958B, 1389 0x958C, 1390 0x958D, 1391 0x958E, 1392 0x958F, 1393 0x9590, 1394 0x9591, 1395 0x9593, 1396 0x9595, 1397 0x9596, 1398 0x9597, 1399 0x9598, 1400 0x9599, 1401 0x959B, 1402 0x95C0, 1403 0x95C2, 1404 0x95C4, 1405 0x95C5, 1406 0x95C6, 1407 0x95C7, 1408 0x95C9, 1409 0x95CC, 1410 0x95CD, 1411 0x95CE, 1412 0x95CF, 1413 0x9610, 1414 0x9611, 1415 0x9612, 1416 0x9613, 1417 0x9614, 1418 0x9615, 1419 0x9616, 1420 0x9640, 1421 0x9641, 1422 0x9642, 1423 0x9643, 1424 0x9644, 1425 0x9645, 1426 0x9647, 1427 0x9648, 1428 0x9649, 1429 0x964a, 1430 0x964b, 1431 0x964c, 1432 0x964e, 1433 0x964f, 1434 0x9710, 1435 0x9711, 1436 0x9712, 1437 0x9713, 1438 0x9714, 1439 0x9715, 1440 0x9802, 1441 0x9803, 1442 0x9804, 1443 0x9805, 1444 0x9806, 1445 0x9807, 1446 0x9808, 1447 0x9809, 1448 0x980A, 1449 0x9900, 1450 0x9901, 1451 0x9903, 1452 0x9904, 1453 0x9905, 1454 0x9906, 1455 0x9907, 1456 0x9908, 1457 0x9909, 1458 0x990A, 1459 0x990B, 1460 0x990C, 1461 0x990D, 1462 0x990E, 1463 0x990F, 1464 0x9910, 1465 0x9913, 1466 0x9917, 1467 0x9918, 1468 0x9919, 1469 0x9990, 1470 0x9991, 1471 0x9992, 1472 0x9993, 1473 0x9994, 1474 0x9995, 1475 0x9996, 1476 0x9997, 1477 0x9998, 1478 0x9999, 1479 0x999A, 1480 0x999B, 1481 0x999C, 1482 0x999D, 1483 0x99A0, 1484 0x99A2, 1485 0x99A4, 1486 /* radeon secondary ids */ 1487 0x3171, 1488 0x3e70, 1489 0x4164, 1490 0x4165, 1491 0x4166, 1492 0x4168, 1493 0x4170, 1494 0x4171, 1495 0x4172, 1496 0x4173, 1497 0x496e, 1498 0x4a69, 1499 0x4a6a, 1500 0x4a6b, 1501 0x4a70, 1502 0x4a74, 1503 0x4b69, 1504 0x4b6b, 1505 0x4b6c, 1506 0x4c6e, 1507 0x4e64, 1508 0x4e65, 1509 0x4e66, 1510 0x4e67, 1511 0x4e68, 1512 0x4e69, 1513 0x4e6a, 1514 0x4e71, 1515 0x4f73, 1516 0x5569, 1517 0x556b, 1518 0x556d, 1519 0x556f, 1520 0x5571, 1521 0x5854, 1522 0x5874, 1523 0x5940, 1524 0x5941, 1525 0x5b72, 1526 0x5b73, 1527 0x5b74, 1528 0x5b75, 1529 0x5d44, 1530 0x5d45, 1531 0x5d6d, 1532 0x5d6f, 1533 0x5d72, 1534 0x5d77, 1535 0x5e6b, 1536 0x5e6d, 1537 0x7120, 1538 0x7124, 1539 0x7129, 1540 0x712e, 1541 0x712f, 1542 0x7162, 1543 0x7163, 1544 0x7166, 1545 0x7167, 1546 0x7172, 1547 0x7173, 1548 0x71a0, 1549 0x71a1, 1550 0x71a3, 1551 0x71a7, 1552 0x71bb, 1553 0x71e0, 1554 0x71e1, 1555 0x71e2, 1556 0x71e6, 1557 0x71e7, 1558 0x71f2, 1559 0x7269, 1560 0x726b, 1561 0x726e, 1562 0x72a0, 1563 0x72a8, 1564 0x72b1, 1565 0x72b3, 1566 0x793f, 1567 }; 1568 1569 static const struct pci_device_id pciidlist[] = { 1570 #ifdef CONFIG_DRM_AMDGPU_SI 1571 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1572 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1573 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1574 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1575 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1576 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1577 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1578 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1579 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1580 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1581 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1582 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1583 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1584 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1585 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1586 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1587 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1588 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1589 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1590 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1591 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1592 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1593 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1594 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1595 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1596 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1597 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1598 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1599 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1600 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1601 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1602 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1603 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1604 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1605 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1606 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1607 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1608 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1609 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1610 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1611 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1612 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1613 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1614 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1615 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1616 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1617 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1618 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1619 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1620 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1621 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1622 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1623 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1624 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1625 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1626 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1627 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1630 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1631 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1632 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1633 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1634 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1635 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1636 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1637 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1638 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1639 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1640 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1641 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1642 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1643 #endif 1644 #ifdef CONFIG_DRM_AMDGPU_CIK 1645 /* Kaveri */ 1646 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1647 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1648 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1649 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1650 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1651 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1652 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1653 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1654 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1655 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1656 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1657 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1658 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1659 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1660 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1661 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1662 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1663 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1664 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1665 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1666 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1667 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1668 /* Bonaire */ 1669 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1670 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1671 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1674 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1675 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1676 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1677 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1678 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1679 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1680 /* Hawaii */ 1681 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1682 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1683 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1684 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1685 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1686 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1687 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1688 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1689 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1690 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1691 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1692 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1693 /* Kabini */ 1694 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1695 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1696 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1697 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1698 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1699 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1700 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1701 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1702 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1703 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1704 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1705 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1706 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1707 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1708 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1709 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1710 /* mullins */ 1711 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1713 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1714 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1715 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1716 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1717 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1718 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1719 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1720 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1721 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1722 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1723 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1724 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1725 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1726 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1727 #endif 1728 /* topaz */ 1729 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1730 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1731 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1732 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1733 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1734 /* tonga */ 1735 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1736 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1737 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1738 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1739 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1740 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1741 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1742 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1743 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1744 /* fiji */ 1745 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1746 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1747 /* carrizo */ 1748 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1749 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1750 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1751 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1752 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1753 /* stoney */ 1754 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1755 /* Polaris11 */ 1756 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1757 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1758 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1759 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1760 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1761 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1762 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1763 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1764 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1765 /* Polaris10 */ 1766 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1767 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1768 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1769 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1770 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1771 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1772 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1773 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1774 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1775 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1776 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1777 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1778 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1779 /* Polaris12 */ 1780 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1781 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1782 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1783 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1784 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1785 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1786 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1787 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1788 /* VEGAM */ 1789 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1790 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1791 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1792 /* Vega 10 */ 1793 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1794 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1795 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1796 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1797 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1798 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1799 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1800 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1801 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1802 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1803 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1804 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1805 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1806 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1807 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1808 /* Vega 12 */ 1809 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1810 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1811 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1812 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1813 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1814 /* Vega 20 */ 1815 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1816 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1817 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1818 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1819 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1820 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1821 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1822 /* Raven */ 1823 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1824 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1825 /* Arcturus */ 1826 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1827 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1828 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1829 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1830 /* Navi10 */ 1831 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1832 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1833 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1834 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1835 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1836 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1837 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1838 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1839 /* Navi14 */ 1840 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1841 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1842 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1843 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1844 1845 /* Renoir */ 1846 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1847 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1848 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1849 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1850 1851 /* Navi12 */ 1852 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1853 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1854 1855 /* Sienna_Cichlid */ 1856 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1857 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1858 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1859 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1860 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1861 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1862 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1863 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1864 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1865 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1866 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1867 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1868 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1869 1870 /* Van Gogh */ 1871 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1872 1873 /* Yellow Carp */ 1874 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1875 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1876 1877 /* Navy_Flounder */ 1878 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1879 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1880 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1881 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1882 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1883 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1884 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1885 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1886 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1887 1888 /* DIMGREY_CAVEFISH */ 1889 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1890 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1891 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1892 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1893 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1894 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1895 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1896 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1897 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1898 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1899 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1900 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1901 1902 /* Aldebaran */ 1903 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1904 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1905 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1906 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1907 1908 /* CYAN_SKILLFISH */ 1909 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1910 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1911 1912 /* BEIGE_GOBY */ 1913 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1914 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1915 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1916 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1917 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1918 1919 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1920 .class = PCI_CLASS_DISPLAY_VGA << 8, 1921 .class_mask = 0xffffff, 1922 .driver_data = CHIP_IP_DISCOVERY }, 1923 1924 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1925 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1926 .class_mask = 0xffffff, 1927 .driver_data = CHIP_IP_DISCOVERY }, 1928 1929 {0, 0, 0} 1930 }; 1931 1932 MODULE_DEVICE_TABLE(pci, pciidlist); 1933 1934 static const struct drm_driver amdgpu_kms_driver; 1935 1936 static bool amdgpu_is_fw_framebuffer(resource_size_t base, 1937 resource_size_t size) 1938 { 1939 bool found = false; 1940 #if IS_REACHABLE(CONFIG_FB) 1941 struct apertures_struct *a; 1942 1943 a = alloc_apertures(1); 1944 if (!a) 1945 return false; 1946 1947 a->ranges[0].base = base; 1948 a->ranges[0].size = size; 1949 1950 found = is_firmware_framebuffer(a); 1951 kfree(a); 1952 #endif 1953 return found; 1954 } 1955 1956 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1957 { 1958 struct pci_dev *p = NULL; 1959 int i; 1960 1961 /* 0 - GPU 1962 * 1 - audio 1963 * 2 - USB 1964 * 3 - UCSI 1965 */ 1966 for (i = 1; i < 4; i++) { 1967 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1968 adev->pdev->bus->number, i); 1969 if (p) { 1970 pm_runtime_get_sync(&p->dev); 1971 pm_runtime_mark_last_busy(&p->dev); 1972 pm_runtime_put_autosuspend(&p->dev); 1973 pci_dev_put(p); 1974 } 1975 } 1976 } 1977 1978 static int amdgpu_pci_probe(struct pci_dev *pdev, 1979 const struct pci_device_id *ent) 1980 { 1981 struct drm_device *ddev; 1982 struct amdgpu_device *adev; 1983 unsigned long flags = ent->driver_data; 1984 int ret, retry = 0, i; 1985 bool supports_atomic = false; 1986 bool is_fw_fb; 1987 resource_size_t base, size; 1988 1989 /* skip devices which are owned by radeon */ 1990 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1991 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 1992 return -ENODEV; 1993 } 1994 1995 if (amdgpu_virtual_display || 1996 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1997 supports_atomic = true; 1998 1999 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2000 DRM_INFO("This hardware requires experimental hardware support.\n" 2001 "See modparam exp_hw_support\n"); 2002 return -ENODEV; 2003 } 2004 2005 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2006 * however, SME requires an indirect IOMMU mapping because the encryption 2007 * bit is beyond the DMA mask of the chip. 2008 */ 2009 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2010 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2011 dev_info(&pdev->dev, 2012 "SME is not compatible with RAVEN\n"); 2013 return -ENOTSUPP; 2014 } 2015 2016 #ifdef CONFIG_DRM_AMDGPU_SI 2017 if (!amdgpu_si_support) { 2018 switch (flags & AMD_ASIC_MASK) { 2019 case CHIP_TAHITI: 2020 case CHIP_PITCAIRN: 2021 case CHIP_VERDE: 2022 case CHIP_OLAND: 2023 case CHIP_HAINAN: 2024 dev_info(&pdev->dev, 2025 "SI support provided by radeon.\n"); 2026 dev_info(&pdev->dev, 2027 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2028 ); 2029 return -ENODEV; 2030 } 2031 } 2032 #endif 2033 #ifdef CONFIG_DRM_AMDGPU_CIK 2034 if (!amdgpu_cik_support) { 2035 switch (flags & AMD_ASIC_MASK) { 2036 case CHIP_KAVERI: 2037 case CHIP_BONAIRE: 2038 case CHIP_HAWAII: 2039 case CHIP_KABINI: 2040 case CHIP_MULLINS: 2041 dev_info(&pdev->dev, 2042 "CIK support provided by radeon.\n"); 2043 dev_info(&pdev->dev, 2044 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2045 ); 2046 return -ENODEV; 2047 } 2048 } 2049 #endif 2050 2051 base = pci_resource_start(pdev, 0); 2052 size = pci_resource_len(pdev, 0); 2053 is_fw_fb = amdgpu_is_fw_framebuffer(base, size); 2054 2055 /* Get rid of things like offb */ 2056 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2057 if (ret) 2058 return ret; 2059 2060 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2061 if (IS_ERR(adev)) 2062 return PTR_ERR(adev); 2063 2064 adev->dev = &pdev->dev; 2065 adev->pdev = pdev; 2066 ddev = adev_to_drm(adev); 2067 adev->is_fw_fb = is_fw_fb; 2068 2069 if (!supports_atomic) 2070 ddev->driver_features &= ~DRIVER_ATOMIC; 2071 2072 ret = pci_enable_device(pdev); 2073 if (ret) 2074 return ret; 2075 2076 pci_set_drvdata(pdev, ddev); 2077 2078 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2079 if (ret) 2080 goto err_pci; 2081 2082 retry_init: 2083 ret = drm_dev_register(ddev, ent->driver_data); 2084 if (ret == -EAGAIN && ++retry <= 3) { 2085 DRM_INFO("retry init %d\n", retry); 2086 /* Don't request EX mode too frequently which is attacking */ 2087 msleep(5000); 2088 goto retry_init; 2089 } else if (ret) { 2090 goto err_pci; 2091 } 2092 2093 /* 2094 * 1. don't init fbdev on hw without DCE 2095 * 2. don't init fbdev if there are no connectors 2096 */ 2097 if (adev->mode_info.mode_config_initialized && 2098 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2099 /* select 8 bpp console on low vram cards */ 2100 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2101 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2102 else 2103 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2104 } 2105 2106 ret = amdgpu_debugfs_init(adev); 2107 if (ret) 2108 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2109 2110 if (adev->runpm) { 2111 /* only need to skip on ATPX */ 2112 if (amdgpu_device_supports_px(ddev)) 2113 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2114 /* we want direct complete for BOCO */ 2115 if (amdgpu_device_supports_boco(ddev)) 2116 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2117 DPM_FLAG_SMART_SUSPEND | 2118 DPM_FLAG_MAY_SKIP_RESUME); 2119 pm_runtime_use_autosuspend(ddev->dev); 2120 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2121 2122 pm_runtime_allow(ddev->dev); 2123 2124 pm_runtime_mark_last_busy(ddev->dev); 2125 pm_runtime_put_autosuspend(ddev->dev); 2126 2127 /* 2128 * For runpm implemented via BACO, PMFW will handle the 2129 * timing for BACO in and out: 2130 * - put ASIC into BACO state only when both video and 2131 * audio functions are in D3 state. 2132 * - pull ASIC out of BACO state when either video or 2133 * audio function is in D0 state. 2134 * Also, at startup, PMFW assumes both functions are in 2135 * D0 state. 2136 * 2137 * So if snd driver was loaded prior to amdgpu driver 2138 * and audio function was put into D3 state, there will 2139 * be no PMFW-aware D-state transition(D0->D3) on runpm 2140 * suspend. Thus the BACO will be not correctly kicked in. 2141 * 2142 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2143 * into D0 state. Then there will be a PMFW-aware D-state 2144 * transition(D0->D3) on runpm suspend. 2145 */ 2146 if (amdgpu_device_supports_baco(ddev) && 2147 !(adev->flags & AMD_IS_APU) && 2148 (adev->asic_type >= CHIP_NAVI10)) 2149 amdgpu_get_secondary_funcs(adev); 2150 } 2151 2152 return 0; 2153 2154 err_pci: 2155 pci_disable_device(pdev); 2156 return ret; 2157 } 2158 2159 static void 2160 amdgpu_pci_remove(struct pci_dev *pdev) 2161 { 2162 struct drm_device *dev = pci_get_drvdata(pdev); 2163 struct amdgpu_device *adev = drm_to_adev(dev); 2164 2165 drm_dev_unplug(dev); 2166 2167 if (adev->runpm) { 2168 pm_runtime_get_sync(dev->dev); 2169 pm_runtime_forbid(dev->dev); 2170 } 2171 2172 amdgpu_driver_unload_kms(dev); 2173 2174 /* 2175 * Flush any in flight DMA operations from device. 2176 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2177 * StatusTransactions Pending bit. 2178 */ 2179 pci_disable_device(pdev); 2180 pci_wait_for_pending_transaction(pdev); 2181 } 2182 2183 static void 2184 amdgpu_pci_shutdown(struct pci_dev *pdev) 2185 { 2186 struct drm_device *dev = pci_get_drvdata(pdev); 2187 struct amdgpu_device *adev = drm_to_adev(dev); 2188 2189 if (amdgpu_ras_intr_triggered()) 2190 return; 2191 2192 /* if we are running in a VM, make sure the device 2193 * torn down properly on reboot/shutdown. 2194 * unfortunately we can't detect certain 2195 * hypervisors so just do this all the time. 2196 */ 2197 if (!amdgpu_passthrough(adev)) 2198 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2199 amdgpu_device_ip_suspend(adev); 2200 adev->mp1_state = PP_MP1_STATE_NONE; 2201 } 2202 2203 /** 2204 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2205 * 2206 * @work: work_struct. 2207 */ 2208 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2209 { 2210 struct list_head device_list; 2211 struct amdgpu_device *adev; 2212 int i, r; 2213 struct amdgpu_reset_context reset_context; 2214 2215 memset(&reset_context, 0, sizeof(reset_context)); 2216 2217 mutex_lock(&mgpu_info.mutex); 2218 if (mgpu_info.pending_reset == true) { 2219 mutex_unlock(&mgpu_info.mutex); 2220 return; 2221 } 2222 mgpu_info.pending_reset = true; 2223 mutex_unlock(&mgpu_info.mutex); 2224 2225 /* Use a common context, just need to make sure full reset is done */ 2226 reset_context.method = AMD_RESET_METHOD_NONE; 2227 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2228 2229 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2230 adev = mgpu_info.gpu_ins[i].adev; 2231 reset_context.reset_req_dev = adev; 2232 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2233 if (r) { 2234 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2235 r, adev_to_drm(adev)->unique); 2236 } 2237 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2238 r = -EALREADY; 2239 } 2240 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2241 adev = mgpu_info.gpu_ins[i].adev; 2242 flush_work(&adev->xgmi_reset_work); 2243 adev->gmc.xgmi.pending_reset = false; 2244 } 2245 2246 /* reset function will rebuild the xgmi hive info , clear it now */ 2247 for (i = 0; i < mgpu_info.num_dgpu; i++) 2248 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2249 2250 INIT_LIST_HEAD(&device_list); 2251 2252 for (i = 0; i < mgpu_info.num_dgpu; i++) 2253 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2254 2255 /* unregister the GPU first, reset function will add them back */ 2256 list_for_each_entry(adev, &device_list, reset_list) 2257 amdgpu_unregister_gpu_instance(adev); 2258 2259 /* Use a common context, just need to make sure full reset is done */ 2260 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2261 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2262 2263 if (r) { 2264 DRM_ERROR("reinit gpus failure"); 2265 return; 2266 } 2267 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2268 adev = mgpu_info.gpu_ins[i].adev; 2269 if (!adev->kfd.init_complete) 2270 amdgpu_amdkfd_device_init(adev); 2271 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2272 } 2273 return; 2274 } 2275 2276 static int amdgpu_pmops_prepare(struct device *dev) 2277 { 2278 struct drm_device *drm_dev = dev_get_drvdata(dev); 2279 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2280 2281 /* Return a positive number here so 2282 * DPM_FLAG_SMART_SUSPEND works properly 2283 */ 2284 if (amdgpu_device_supports_boco(drm_dev)) 2285 return pm_runtime_suspended(dev); 2286 2287 /* if we will not support s3 or s2i for the device 2288 * then skip suspend 2289 */ 2290 if (!amdgpu_acpi_is_s0ix_active(adev) && 2291 !amdgpu_acpi_is_s3_active(adev)) 2292 return 1; 2293 2294 return 0; 2295 } 2296 2297 static void amdgpu_pmops_complete(struct device *dev) 2298 { 2299 /* nothing to do */ 2300 } 2301 2302 static int amdgpu_pmops_suspend(struct device *dev) 2303 { 2304 struct drm_device *drm_dev = dev_get_drvdata(dev); 2305 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2306 int r; 2307 2308 if (amdgpu_acpi_is_s0ix_active(adev)) 2309 adev->in_s0ix = true; 2310 else 2311 adev->in_s3 = true; 2312 r = amdgpu_device_suspend(drm_dev, true); 2313 if (r) 2314 return r; 2315 if (!adev->in_s0ix) 2316 r = amdgpu_asic_reset(adev); 2317 return r; 2318 } 2319 2320 static int amdgpu_pmops_resume(struct device *dev) 2321 { 2322 struct drm_device *drm_dev = dev_get_drvdata(dev); 2323 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2324 int r; 2325 2326 /* Avoids registers access if device is physically gone */ 2327 if (!pci_device_is_present(adev->pdev)) 2328 adev->no_hw_access = true; 2329 2330 r = amdgpu_device_resume(drm_dev, true); 2331 if (amdgpu_acpi_is_s0ix_active(adev)) 2332 adev->in_s0ix = false; 2333 else 2334 adev->in_s3 = false; 2335 return r; 2336 } 2337 2338 static int amdgpu_pmops_freeze(struct device *dev) 2339 { 2340 struct drm_device *drm_dev = dev_get_drvdata(dev); 2341 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2342 int r; 2343 2344 adev->in_s4 = true; 2345 r = amdgpu_device_suspend(drm_dev, true); 2346 adev->in_s4 = false; 2347 if (r) 2348 return r; 2349 return amdgpu_asic_reset(adev); 2350 } 2351 2352 static int amdgpu_pmops_thaw(struct device *dev) 2353 { 2354 struct drm_device *drm_dev = dev_get_drvdata(dev); 2355 2356 return amdgpu_device_resume(drm_dev, true); 2357 } 2358 2359 static int amdgpu_pmops_poweroff(struct device *dev) 2360 { 2361 struct drm_device *drm_dev = dev_get_drvdata(dev); 2362 2363 return amdgpu_device_suspend(drm_dev, true); 2364 } 2365 2366 static int amdgpu_pmops_restore(struct device *dev) 2367 { 2368 struct drm_device *drm_dev = dev_get_drvdata(dev); 2369 2370 return amdgpu_device_resume(drm_dev, true); 2371 } 2372 2373 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2374 { 2375 struct pci_dev *pdev = to_pci_dev(dev); 2376 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2377 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2378 int ret, i; 2379 2380 if (!adev->runpm) { 2381 pm_runtime_forbid(dev); 2382 return -EBUSY; 2383 } 2384 2385 /* wait for all rings to drain before suspending */ 2386 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2387 struct amdgpu_ring *ring = adev->rings[i]; 2388 if (ring && ring->sched.ready) { 2389 ret = amdgpu_fence_wait_empty(ring); 2390 if (ret) 2391 return -EBUSY; 2392 } 2393 } 2394 2395 adev->in_runpm = true; 2396 if (amdgpu_device_supports_px(drm_dev)) 2397 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2398 2399 /* 2400 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2401 * proper cleanups and put itself into a state ready for PNP. That 2402 * can address some random resuming failure observed on BOCO capable 2403 * platforms. 2404 * TODO: this may be also needed for PX capable platform. 2405 */ 2406 if (amdgpu_device_supports_boco(drm_dev)) 2407 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2408 2409 ret = amdgpu_device_suspend(drm_dev, false); 2410 if (ret) { 2411 adev->in_runpm = false; 2412 if (amdgpu_device_supports_boco(drm_dev)) 2413 adev->mp1_state = PP_MP1_STATE_NONE; 2414 return ret; 2415 } 2416 2417 if (amdgpu_device_supports_boco(drm_dev)) 2418 adev->mp1_state = PP_MP1_STATE_NONE; 2419 2420 if (amdgpu_device_supports_px(drm_dev)) { 2421 /* Only need to handle PCI state in the driver for ATPX 2422 * PCI core handles it for _PR3. 2423 */ 2424 amdgpu_device_cache_pci_state(pdev); 2425 pci_disable_device(pdev); 2426 pci_ignore_hotplug(pdev); 2427 pci_set_power_state(pdev, PCI_D3cold); 2428 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2429 } else if (amdgpu_device_supports_boco(drm_dev)) { 2430 /* nothing to do */ 2431 } else if (amdgpu_device_supports_baco(drm_dev)) { 2432 amdgpu_device_baco_enter(drm_dev); 2433 } 2434 2435 return 0; 2436 } 2437 2438 static int amdgpu_pmops_runtime_resume(struct device *dev) 2439 { 2440 struct pci_dev *pdev = to_pci_dev(dev); 2441 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2442 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2443 int ret; 2444 2445 if (!adev->runpm) 2446 return -EINVAL; 2447 2448 /* Avoids registers access if device is physically gone */ 2449 if (!pci_device_is_present(adev->pdev)) 2450 adev->no_hw_access = true; 2451 2452 if (amdgpu_device_supports_px(drm_dev)) { 2453 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2454 2455 /* Only need to handle PCI state in the driver for ATPX 2456 * PCI core handles it for _PR3. 2457 */ 2458 pci_set_power_state(pdev, PCI_D0); 2459 amdgpu_device_load_pci_state(pdev); 2460 ret = pci_enable_device(pdev); 2461 if (ret) 2462 return ret; 2463 pci_set_master(pdev); 2464 } else if (amdgpu_device_supports_boco(drm_dev)) { 2465 /* Only need to handle PCI state in the driver for ATPX 2466 * PCI core handles it for _PR3. 2467 */ 2468 pci_set_master(pdev); 2469 } else if (amdgpu_device_supports_baco(drm_dev)) { 2470 amdgpu_device_baco_exit(drm_dev); 2471 } 2472 ret = amdgpu_device_resume(drm_dev, false); 2473 if (ret) 2474 return ret; 2475 2476 if (amdgpu_device_supports_px(drm_dev)) 2477 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2478 adev->in_runpm = false; 2479 return 0; 2480 } 2481 2482 static int amdgpu_pmops_runtime_idle(struct device *dev) 2483 { 2484 struct drm_device *drm_dev = dev_get_drvdata(dev); 2485 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2486 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2487 int ret = 1; 2488 2489 if (!adev->runpm) { 2490 pm_runtime_forbid(dev); 2491 return -EBUSY; 2492 } 2493 2494 if (amdgpu_device_has_dc_support(adev)) { 2495 struct drm_crtc *crtc; 2496 2497 drm_for_each_crtc(crtc, drm_dev) { 2498 drm_modeset_lock(&crtc->mutex, NULL); 2499 if (crtc->state->active) 2500 ret = -EBUSY; 2501 drm_modeset_unlock(&crtc->mutex); 2502 if (ret < 0) 2503 break; 2504 } 2505 2506 } else { 2507 struct drm_connector *list_connector; 2508 struct drm_connector_list_iter iter; 2509 2510 mutex_lock(&drm_dev->mode_config.mutex); 2511 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2512 2513 drm_connector_list_iter_begin(drm_dev, &iter); 2514 drm_for_each_connector_iter(list_connector, &iter) { 2515 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2516 ret = -EBUSY; 2517 break; 2518 } 2519 } 2520 2521 drm_connector_list_iter_end(&iter); 2522 2523 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2524 mutex_unlock(&drm_dev->mode_config.mutex); 2525 } 2526 2527 if (ret == -EBUSY) 2528 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2529 2530 pm_runtime_mark_last_busy(dev); 2531 pm_runtime_autosuspend(dev); 2532 return ret; 2533 } 2534 2535 long amdgpu_drm_ioctl(struct file *filp, 2536 unsigned int cmd, unsigned long arg) 2537 { 2538 struct drm_file *file_priv = filp->private_data; 2539 struct drm_device *dev; 2540 long ret; 2541 dev = file_priv->minor->dev; 2542 ret = pm_runtime_get_sync(dev->dev); 2543 if (ret < 0) 2544 goto out; 2545 2546 ret = drm_ioctl(filp, cmd, arg); 2547 2548 pm_runtime_mark_last_busy(dev->dev); 2549 out: 2550 pm_runtime_put_autosuspend(dev->dev); 2551 return ret; 2552 } 2553 2554 static const struct dev_pm_ops amdgpu_pm_ops = { 2555 .prepare = amdgpu_pmops_prepare, 2556 .complete = amdgpu_pmops_complete, 2557 .suspend = amdgpu_pmops_suspend, 2558 .resume = amdgpu_pmops_resume, 2559 .freeze = amdgpu_pmops_freeze, 2560 .thaw = amdgpu_pmops_thaw, 2561 .poweroff = amdgpu_pmops_poweroff, 2562 .restore = amdgpu_pmops_restore, 2563 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2564 .runtime_resume = amdgpu_pmops_runtime_resume, 2565 .runtime_idle = amdgpu_pmops_runtime_idle, 2566 }; 2567 2568 static int amdgpu_flush(struct file *f, fl_owner_t id) 2569 { 2570 struct drm_file *file_priv = f->private_data; 2571 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2572 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2573 2574 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2575 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2576 2577 return timeout >= 0 ? 0 : timeout; 2578 } 2579 2580 static const struct file_operations amdgpu_driver_kms_fops = { 2581 .owner = THIS_MODULE, 2582 .open = drm_open, 2583 .flush = amdgpu_flush, 2584 .release = drm_release, 2585 .unlocked_ioctl = amdgpu_drm_ioctl, 2586 .mmap = drm_gem_mmap, 2587 .poll = drm_poll, 2588 .read = drm_read, 2589 #ifdef CONFIG_COMPAT 2590 .compat_ioctl = amdgpu_kms_compat_ioctl, 2591 #endif 2592 #ifdef CONFIG_PROC_FS 2593 .show_fdinfo = amdgpu_show_fdinfo 2594 #endif 2595 }; 2596 2597 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2598 { 2599 struct drm_file *file; 2600 2601 if (!filp) 2602 return -EINVAL; 2603 2604 if (filp->f_op != &amdgpu_driver_kms_fops) { 2605 return -EINVAL; 2606 } 2607 2608 file = filp->private_data; 2609 *fpriv = file->driver_priv; 2610 return 0; 2611 } 2612 2613 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2614 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2615 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2616 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2617 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2618 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2619 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2620 /* KMS */ 2621 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2622 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2623 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2624 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2625 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2626 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2627 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2628 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2629 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2630 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2631 }; 2632 2633 static const struct drm_driver amdgpu_kms_driver = { 2634 .driver_features = 2635 DRIVER_ATOMIC | 2636 DRIVER_GEM | 2637 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2638 DRIVER_SYNCOBJ_TIMELINE, 2639 .open = amdgpu_driver_open_kms, 2640 .postclose = amdgpu_driver_postclose_kms, 2641 .lastclose = amdgpu_driver_lastclose_kms, 2642 .ioctls = amdgpu_ioctls_kms, 2643 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2644 .dumb_create = amdgpu_mode_dumb_create, 2645 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2646 .fops = &amdgpu_driver_kms_fops, 2647 .release = &amdgpu_driver_release_kms, 2648 2649 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2650 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2651 .gem_prime_import = amdgpu_gem_prime_import, 2652 .gem_prime_mmap = drm_gem_prime_mmap, 2653 2654 .name = DRIVER_NAME, 2655 .desc = DRIVER_DESC, 2656 .date = DRIVER_DATE, 2657 .major = KMS_DRIVER_MAJOR, 2658 .minor = KMS_DRIVER_MINOR, 2659 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2660 }; 2661 2662 static struct pci_error_handlers amdgpu_pci_err_handler = { 2663 .error_detected = amdgpu_pci_error_detected, 2664 .mmio_enabled = amdgpu_pci_mmio_enabled, 2665 .slot_reset = amdgpu_pci_slot_reset, 2666 .resume = amdgpu_pci_resume, 2667 }; 2668 2669 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2670 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2671 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2672 2673 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2674 &amdgpu_vram_mgr_attr_group, 2675 &amdgpu_gtt_mgr_attr_group, 2676 &amdgpu_vbios_version_attr_group, 2677 NULL, 2678 }; 2679 2680 2681 static struct pci_driver amdgpu_kms_pci_driver = { 2682 .name = DRIVER_NAME, 2683 .id_table = pciidlist, 2684 .probe = amdgpu_pci_probe, 2685 .remove = amdgpu_pci_remove, 2686 .shutdown = amdgpu_pci_shutdown, 2687 .driver.pm = &amdgpu_pm_ops, 2688 .err_handler = &amdgpu_pci_err_handler, 2689 .dev_groups = amdgpu_sysfs_groups, 2690 }; 2691 2692 static int __init amdgpu_init(void) 2693 { 2694 int r; 2695 2696 if (drm_firmware_drivers_only()) 2697 return -EINVAL; 2698 2699 r = amdgpu_sync_init(); 2700 if (r) 2701 goto error_sync; 2702 2703 r = amdgpu_fence_slab_init(); 2704 if (r) 2705 goto error_fence; 2706 2707 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2708 amdgpu_register_atpx_handler(); 2709 amdgpu_acpi_detect(); 2710 2711 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2712 amdgpu_amdkfd_init(); 2713 2714 /* let modprobe override vga console setting */ 2715 return pci_register_driver(&amdgpu_kms_pci_driver); 2716 2717 error_fence: 2718 amdgpu_sync_fini(); 2719 2720 error_sync: 2721 return r; 2722 } 2723 2724 static void __exit amdgpu_exit(void) 2725 { 2726 amdgpu_amdkfd_fini(); 2727 pci_unregister_driver(&amdgpu_kms_pci_driver); 2728 amdgpu_unregister_atpx_handler(); 2729 amdgpu_sync_fini(); 2730 amdgpu_fence_slab_fini(); 2731 mmu_notifier_synchronize(); 2732 } 2733 2734 module_init(amdgpu_init); 2735 module_exit(amdgpu_exit); 2736 2737 MODULE_AUTHOR(DRIVER_AUTHOR); 2738 MODULE_DESCRIPTION(DRIVER_DESC); 2739 MODULE_LICENSE("GPL and additional rights"); 2740