1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/console.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 40 #include "amdgpu.h" 41 #include "amdgpu_irq.h" 42 #include "amdgpu_dma_buf.h" 43 #include "amdgpu_sched.h" 44 45 #include "amdgpu_amdkfd.h" 46 47 #include "amdgpu_ras.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 * - 3.16.0 - Add reserved vmid support 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 70 * - 3.18.0 - Export gpu always on cu bitmap 71 * - 3.19.0 - Add support for UVD MJPEG decode 72 * - 3.20.0 - Add support for local BOs 73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 75 * - 3.23.0 - Add query for VRAM lost counter 76 * - 3.24.0 - Add high priority compute support for gfx9 77 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 78 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 79 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 80 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 81 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 82 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 83 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 84 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 85 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 86 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 87 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 88 * - 3.36.0 - Allow reading more status registers on si/cik 89 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 90 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 91 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 92 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 93 */ 94 #define KMS_DRIVER_MAJOR 3 95 #define KMS_DRIVER_MINOR 40 96 #define KMS_DRIVER_PATCHLEVEL 0 97 98 int amdgpu_vram_limit; 99 int amdgpu_vis_vram_limit; 100 int amdgpu_gart_size = -1; /* auto */ 101 int amdgpu_gtt_size = -1; /* auto */ 102 int amdgpu_moverate = -1; /* auto */ 103 int amdgpu_benchmarking; 104 int amdgpu_testing; 105 int amdgpu_audio = -1; 106 int amdgpu_disp_priority; 107 int amdgpu_hw_i2c; 108 int amdgpu_pcie_gen2 = -1; 109 int amdgpu_msi = -1; 110 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 111 int amdgpu_dpm = -1; 112 int amdgpu_fw_load_type = -1; 113 int amdgpu_aspm = -1; 114 int amdgpu_runtime_pm = -1; 115 uint amdgpu_ip_block_mask = 0xffffffff; 116 int amdgpu_bapm = -1; 117 int amdgpu_deep_color; 118 int amdgpu_vm_size = -1; 119 int amdgpu_vm_fragment_size = -1; 120 int amdgpu_vm_block_size = -1; 121 int amdgpu_vm_fault_stop; 122 int amdgpu_vm_debug; 123 int amdgpu_vm_update_mode = -1; 124 int amdgpu_exp_hw_support; 125 int amdgpu_dc = -1; 126 int amdgpu_sched_jobs = 32; 127 int amdgpu_sched_hw_submission = 2; 128 uint amdgpu_pcie_gen_cap; 129 uint amdgpu_pcie_lane_cap; 130 uint amdgpu_cg_mask = 0xffffffff; 131 uint amdgpu_pg_mask = 0xffffffff; 132 uint amdgpu_sdma_phase_quantum = 32; 133 char *amdgpu_disable_cu = NULL; 134 char *amdgpu_virtual_display = NULL; 135 /* OverDrive(bit 14) disabled by default*/ 136 uint amdgpu_pp_feature_mask = 0xffffbfff; 137 uint amdgpu_force_long_training; 138 int amdgpu_job_hang_limit; 139 int amdgpu_lbpw = -1; 140 int amdgpu_compute_multipipe = -1; 141 int amdgpu_gpu_recovery = -1; /* auto */ 142 int amdgpu_emu_mode; 143 uint amdgpu_smu_memory_pool_size; 144 /* 145 * FBC (bit 0) disabled by default 146 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 147 * - With this, for multiple monitors in sync(e.g. with the same model), 148 * mclk switching will be allowed. And the mclk will be not foced to the 149 * highest. That helps saving some idle power. 150 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 151 * PSR (bit 3) disabled by default 152 */ 153 uint amdgpu_dc_feature_mask = 2; 154 uint amdgpu_dc_debug_mask; 155 int amdgpu_async_gfx_ring = 1; 156 int amdgpu_mcbp; 157 int amdgpu_discovery = -1; 158 int amdgpu_mes; 159 int amdgpu_noretry = -1; 160 int amdgpu_force_asic_type = -1; 161 int amdgpu_tmz; 162 int amdgpu_reset_method = -1; /* auto */ 163 int amdgpu_num_kcq = -1; 164 165 struct amdgpu_mgpu_info mgpu_info = { 166 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 167 }; 168 int amdgpu_ras_enable = -1; 169 uint amdgpu_ras_mask = 0xffffffff; 170 int amdgpu_bad_page_threshold = -1; 171 172 /** 173 * DOC: vramlimit (int) 174 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 175 */ 176 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 177 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 178 179 /** 180 * DOC: vis_vramlimit (int) 181 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 182 */ 183 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 184 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 185 186 /** 187 * DOC: gartsize (uint) 188 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 189 */ 190 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 191 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 192 193 /** 194 * DOC: gttsize (int) 195 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 196 * otherwise 3/4 RAM size). 197 */ 198 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 199 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 200 201 /** 202 * DOC: moverate (int) 203 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 204 */ 205 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 206 module_param_named(moverate, amdgpu_moverate, int, 0600); 207 208 /** 209 * DOC: benchmark (int) 210 * Run benchmarks. The default is 0 (Skip benchmarks). 211 */ 212 MODULE_PARM_DESC(benchmark, "Run benchmark"); 213 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 214 215 /** 216 * DOC: test (int) 217 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 218 */ 219 MODULE_PARM_DESC(test, "Run tests"); 220 module_param_named(test, amdgpu_testing, int, 0444); 221 222 /** 223 * DOC: audio (int) 224 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 225 */ 226 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 227 module_param_named(audio, amdgpu_audio, int, 0444); 228 229 /** 230 * DOC: disp_priority (int) 231 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 232 */ 233 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 234 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 235 236 /** 237 * DOC: hw_i2c (int) 238 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 239 */ 240 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 241 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 242 243 /** 244 * DOC: pcie_gen2 (int) 245 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 246 */ 247 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 248 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 249 250 /** 251 * DOC: msi (int) 252 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 253 */ 254 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 255 module_param_named(msi, amdgpu_msi, int, 0444); 256 257 /** 258 * DOC: lockup_timeout (string) 259 * Set GPU scheduler timeout value in ms. 260 * 261 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 262 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 263 * to the default timeout. 264 * 265 * - With one value specified, the setting will apply to all non-compute jobs. 266 * - With multiple values specified, the first one will be for GFX. 267 * The second one is for Compute. The third and fourth ones are 268 * for SDMA and Video. 269 * 270 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 271 * jobs is 10000. And there is no timeout enforced on compute jobs. 272 */ 273 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 274 "for passthrough or sriov, 10000 for all jobs." 275 " 0: keep default value. negative: infinity timeout), " 276 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 277 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 278 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 279 280 /** 281 * DOC: dpm (int) 282 * Override for dynamic power management setting 283 * (0 = disable, 1 = enable) 284 * The default is -1 (auto). 285 */ 286 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 287 module_param_named(dpm, amdgpu_dpm, int, 0444); 288 289 /** 290 * DOC: fw_load_type (int) 291 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 292 */ 293 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 294 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 295 296 /** 297 * DOC: aspm (int) 298 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 299 */ 300 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 301 module_param_named(aspm, amdgpu_aspm, int, 0444); 302 303 /** 304 * DOC: runpm (int) 305 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 306 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 307 */ 308 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 309 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 310 311 /** 312 * DOC: ip_block_mask (uint) 313 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 314 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 315 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 316 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 317 */ 318 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 319 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 320 321 /** 322 * DOC: bapm (int) 323 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 324 * The default -1 (auto, enabled) 325 */ 326 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 327 module_param_named(bapm, amdgpu_bapm, int, 0444); 328 329 /** 330 * DOC: deep_color (int) 331 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 332 */ 333 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 334 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 335 336 /** 337 * DOC: vm_size (int) 338 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 339 */ 340 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 341 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 342 343 /** 344 * DOC: vm_fragment_size (int) 345 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 346 */ 347 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 348 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 349 350 /** 351 * DOC: vm_block_size (int) 352 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 353 */ 354 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 355 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 356 357 /** 358 * DOC: vm_fault_stop (int) 359 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 360 */ 361 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 362 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 363 364 /** 365 * DOC: vm_debug (int) 366 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 367 */ 368 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 369 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 370 371 /** 372 * DOC: vm_update_mode (int) 373 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 374 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 375 */ 376 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 377 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 378 379 /** 380 * DOC: exp_hw_support (int) 381 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 382 */ 383 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 384 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 385 386 /** 387 * DOC: dc (int) 388 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 389 */ 390 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 391 module_param_named(dc, amdgpu_dc, int, 0444); 392 393 /** 394 * DOC: sched_jobs (int) 395 * Override the max number of jobs supported in the sw queue. The default is 32. 396 */ 397 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 398 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 399 400 /** 401 * DOC: sched_hw_submission (int) 402 * Override the max number of HW submissions. The default is 2. 403 */ 404 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 405 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 406 407 /** 408 * DOC: ppfeaturemask (hexint) 409 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 410 * The default is the current set of stable power features. 411 */ 412 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 413 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 414 415 /** 416 * DOC: forcelongtraining (uint) 417 * Force long memory training in resume. 418 * The default is zero, indicates short training in resume. 419 */ 420 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 421 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 422 423 /** 424 * DOC: pcie_gen_cap (uint) 425 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 426 * The default is 0 (automatic for each asic). 427 */ 428 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 429 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 430 431 /** 432 * DOC: pcie_lane_cap (uint) 433 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 434 * The default is 0 (automatic for each asic). 435 */ 436 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 437 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 438 439 /** 440 * DOC: cg_mask (uint) 441 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 442 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 443 */ 444 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 445 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 446 447 /** 448 * DOC: pg_mask (uint) 449 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 450 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 451 */ 452 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 453 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 454 455 /** 456 * DOC: sdma_phase_quantum (uint) 457 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 458 */ 459 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 460 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 461 462 /** 463 * DOC: disable_cu (charp) 464 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 465 */ 466 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 467 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 468 469 /** 470 * DOC: virtual_display (charp) 471 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 472 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 473 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 474 * device at 26:00.0. The default is NULL. 475 */ 476 MODULE_PARM_DESC(virtual_display, 477 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 478 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 479 480 /** 481 * DOC: job_hang_limit (int) 482 * Set how much time allow a job hang and not drop it. The default is 0. 483 */ 484 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 485 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 486 487 /** 488 * DOC: lbpw (int) 489 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 490 */ 491 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 492 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 493 494 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 495 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 496 497 /** 498 * DOC: gpu_recovery (int) 499 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 500 */ 501 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 502 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 503 504 /** 505 * DOC: emu_mode (int) 506 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 507 */ 508 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 509 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 510 511 /** 512 * DOC: ras_enable (int) 513 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 514 */ 515 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 516 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 517 518 /** 519 * DOC: ras_mask (uint) 520 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 521 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 522 */ 523 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 524 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 525 526 /** 527 * DOC: si_support (int) 528 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 529 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 530 * otherwise using amdgpu driver. 531 */ 532 #ifdef CONFIG_DRM_AMDGPU_SI 533 534 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 535 int amdgpu_si_support = 0; 536 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 537 #else 538 int amdgpu_si_support = 1; 539 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 540 #endif 541 542 module_param_named(si_support, amdgpu_si_support, int, 0444); 543 #endif 544 545 /** 546 * DOC: cik_support (int) 547 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 548 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 549 * otherwise using amdgpu driver. 550 */ 551 #ifdef CONFIG_DRM_AMDGPU_CIK 552 553 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 554 int amdgpu_cik_support = 0; 555 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 556 #else 557 int amdgpu_cik_support = 1; 558 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 559 #endif 560 561 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 562 #endif 563 564 /** 565 * DOC: smu_memory_pool_size (uint) 566 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 567 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 568 */ 569 MODULE_PARM_DESC(smu_memory_pool_size, 570 "reserve gtt for smu debug usage, 0 = disable," 571 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 572 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 573 574 /** 575 * DOC: async_gfx_ring (int) 576 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 577 */ 578 MODULE_PARM_DESC(async_gfx_ring, 579 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 580 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 581 582 /** 583 * DOC: mcbp (int) 584 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 585 */ 586 MODULE_PARM_DESC(mcbp, 587 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 588 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 589 590 /** 591 * DOC: discovery (int) 592 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 593 * (-1 = auto (default), 0 = disabled, 1 = enabled) 594 */ 595 MODULE_PARM_DESC(discovery, 596 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 597 module_param_named(discovery, amdgpu_discovery, int, 0444); 598 599 /** 600 * DOC: mes (int) 601 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 602 * (0 = disabled (default), 1 = enabled) 603 */ 604 MODULE_PARM_DESC(mes, 605 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 606 module_param_named(mes, amdgpu_mes, int, 0444); 607 608 /** 609 * DOC: noretry (int) 610 * Disable retry faults in the GPU memory controller. 611 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 612 */ 613 MODULE_PARM_DESC(noretry, 614 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 615 module_param_named(noretry, amdgpu_noretry, int, 0644); 616 617 /** 618 * DOC: force_asic_type (int) 619 * A non negative value used to specify the asic type for all supported GPUs. 620 */ 621 MODULE_PARM_DESC(force_asic_type, 622 "A non negative value used to specify the asic type for all supported GPUs"); 623 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 624 625 626 627 #ifdef CONFIG_HSA_AMD 628 /** 629 * DOC: sched_policy (int) 630 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 631 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 632 * assigns queues to HQDs. 633 */ 634 int sched_policy = KFD_SCHED_POLICY_HWS; 635 module_param(sched_policy, int, 0444); 636 MODULE_PARM_DESC(sched_policy, 637 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 638 639 /** 640 * DOC: hws_max_conc_proc (int) 641 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 642 * number of VMIDs assigned to the HWS, which is also the default. 643 */ 644 int hws_max_conc_proc = 8; 645 module_param(hws_max_conc_proc, int, 0444); 646 MODULE_PARM_DESC(hws_max_conc_proc, 647 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 648 649 /** 650 * DOC: cwsr_enable (int) 651 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 652 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 653 * disables it. 654 */ 655 int cwsr_enable = 1; 656 module_param(cwsr_enable, int, 0444); 657 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 658 659 /** 660 * DOC: max_num_of_queues_per_device (int) 661 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 662 * is 4096. 663 */ 664 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 665 module_param(max_num_of_queues_per_device, int, 0444); 666 MODULE_PARM_DESC(max_num_of_queues_per_device, 667 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 668 669 /** 670 * DOC: send_sigterm (int) 671 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 672 * but just print errors on dmesg. Setting 1 enables sending sigterm. 673 */ 674 int send_sigterm; 675 module_param(send_sigterm, int, 0444); 676 MODULE_PARM_DESC(send_sigterm, 677 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 678 679 /** 680 * DOC: debug_largebar (int) 681 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 682 * system. This limits the VRAM size reported to ROCm applications to the visible 683 * size, usually 256MB. 684 * Default value is 0, diabled. 685 */ 686 int debug_largebar; 687 module_param(debug_largebar, int, 0444); 688 MODULE_PARM_DESC(debug_largebar, 689 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 690 691 /** 692 * DOC: ignore_crat (int) 693 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 694 * table to get information about AMD APUs. This option can serve as a workaround on 695 * systems with a broken CRAT table. 696 * 697 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 698 * whehter use CRAT) 699 */ 700 int ignore_crat; 701 module_param(ignore_crat, int, 0444); 702 MODULE_PARM_DESC(ignore_crat, 703 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 704 705 /** 706 * DOC: halt_if_hws_hang (int) 707 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 708 * Setting 1 enables halt on hang. 709 */ 710 int halt_if_hws_hang; 711 module_param(halt_if_hws_hang, int, 0644); 712 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 713 714 /** 715 * DOC: hws_gws_support(bool) 716 * Assume that HWS supports GWS barriers regardless of what firmware version 717 * check says. Default value: false (rely on MEC2 firmware version check). 718 */ 719 bool hws_gws_support; 720 module_param(hws_gws_support, bool, 0444); 721 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 722 723 /** 724 * DOC: queue_preemption_timeout_ms (int) 725 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 726 */ 727 int queue_preemption_timeout_ms = 9000; 728 module_param(queue_preemption_timeout_ms, int, 0644); 729 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 730 731 /** 732 * DOC: debug_evictions(bool) 733 * Enable extra debug messages to help determine the cause of evictions 734 */ 735 bool debug_evictions; 736 module_param(debug_evictions, bool, 0644); 737 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 738 739 /** 740 * DOC: no_system_mem_limit(bool) 741 * Disable system memory limit, to support multiple process shared memory 742 */ 743 bool no_system_mem_limit; 744 module_param(no_system_mem_limit, bool, 0644); 745 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 746 747 #endif 748 749 /** 750 * DOC: dcfeaturemask (uint) 751 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 752 * The default is the current set of stable display features. 753 */ 754 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 755 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 756 757 /** 758 * DOC: dcdebugmask (uint) 759 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 760 */ 761 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 762 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 763 764 /** 765 * DOC: abmlevel (uint) 766 * Override the default ABM (Adaptive Backlight Management) level used for DC 767 * enabled hardware. Requires DMCU to be supported and loaded. 768 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 769 * default. Values 1-4 control the maximum allowable brightness reduction via 770 * the ABM algorithm, with 1 being the least reduction and 4 being the most 771 * reduction. 772 * 773 * Defaults to 0, or disabled. Userspace can still override this level later 774 * after boot. 775 */ 776 uint amdgpu_dm_abm_level; 777 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 778 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 779 780 /** 781 * DOC: tmz (int) 782 * Trusted Memory Zone (TMZ) is a method to protect data being written 783 * to or read from memory. 784 * 785 * The default value: 0 (off). TODO: change to auto till it is completed. 786 */ 787 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); 788 module_param_named(tmz, amdgpu_tmz, int, 0444); 789 790 /** 791 * DOC: reset_method (int) 792 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 793 */ 794 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 795 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 796 797 /** 798 * DOC: bad_page_threshold (int) 799 * Bad page threshold is to specify the threshold value of faulty pages 800 * detected by RAS ECC, that may result in GPU entering bad status if total 801 * faulty pages by ECC exceed threshold value and leave it for user's further 802 * check. 803 */ 804 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 805 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 806 807 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 808 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 809 810 static const struct pci_device_id pciidlist[] = { 811 #ifdef CONFIG_DRM_AMDGPU_SI 812 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 813 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 814 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 815 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 816 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 817 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 818 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 819 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 820 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 821 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 822 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 823 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 824 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 825 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 826 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 827 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 828 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 829 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 830 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 831 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 832 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 833 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 834 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 835 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 836 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 837 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 838 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 839 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 840 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 841 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 842 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 843 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 844 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 845 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 846 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 847 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 848 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 849 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 850 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 851 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 852 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 853 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 854 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 855 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 856 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 857 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 858 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 859 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 860 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 861 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 862 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 863 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 864 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 865 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 866 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 867 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 868 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 869 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 870 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 871 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 872 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 873 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 874 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 875 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 876 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 877 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 878 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 879 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 880 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 881 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 882 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 883 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 884 #endif 885 #ifdef CONFIG_DRM_AMDGPU_CIK 886 /* Kaveri */ 887 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 888 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 889 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 890 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 891 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 892 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 893 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 894 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 895 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 896 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 897 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 898 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 899 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 900 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 901 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 902 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 903 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 904 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 905 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 906 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 907 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 908 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 909 /* Bonaire */ 910 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 911 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 912 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 913 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 914 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 915 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 916 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 917 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 918 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 919 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 920 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 921 /* Hawaii */ 922 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 923 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 924 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 925 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 926 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 927 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 928 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 929 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 930 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 931 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 932 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 933 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 934 /* Kabini */ 935 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 936 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 937 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 938 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 939 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 940 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 941 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 942 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 943 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 944 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 945 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 946 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 947 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 948 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 949 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 950 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 951 /* mullins */ 952 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 953 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 954 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 955 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 956 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 957 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 958 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 959 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 960 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 961 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 962 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 963 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 964 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 965 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 966 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 967 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 968 #endif 969 /* topaz */ 970 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 971 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 972 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 973 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 974 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 975 /* tonga */ 976 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 977 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 978 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 979 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 980 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 981 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 982 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 983 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 984 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 985 /* fiji */ 986 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 987 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 988 /* carrizo */ 989 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 990 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 991 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 992 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 993 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 994 /* stoney */ 995 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 996 /* Polaris11 */ 997 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 998 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 999 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1000 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1001 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1002 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1003 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1004 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1005 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1006 /* Polaris10 */ 1007 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1008 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1009 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1010 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1011 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1012 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1013 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1014 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1015 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1016 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1017 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1018 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1019 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1020 /* Polaris12 */ 1021 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1022 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1023 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1024 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1025 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1026 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1027 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1028 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1029 /* VEGAM */ 1030 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1031 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1032 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1033 /* Vega 10 */ 1034 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1035 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1036 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1037 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1038 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1039 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1040 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1041 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1042 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1043 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1044 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1045 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1046 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1047 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1048 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1049 /* Vega 12 */ 1050 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1051 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1052 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1053 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1054 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1055 /* Vega 20 */ 1056 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1057 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1058 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1059 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1060 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1061 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1062 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1063 /* Raven */ 1064 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1065 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1066 /* Arcturus */ 1067 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1068 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1069 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1070 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1071 /* Navi10 */ 1072 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1073 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1074 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1075 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1076 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1077 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1078 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1079 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1080 /* Navi14 */ 1081 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1082 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1083 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1084 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1085 1086 /* Renoir */ 1087 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1088 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1089 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1090 1091 /* Navi12 */ 1092 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1093 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1094 1095 /* Sienna_Cichlid */ 1096 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1097 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1098 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1099 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1100 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1101 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1102 1103 /* Van Gogh */ 1104 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1105 1106 /* Navy_Flounder */ 1107 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1108 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1109 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1110 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1111 1112 /* DIMGREY_CAVEFISH */ 1113 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1114 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1115 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1116 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1117 1118 {0, 0, 0} 1119 }; 1120 1121 MODULE_DEVICE_TABLE(pci, pciidlist); 1122 1123 static const struct drm_driver amdgpu_kms_driver; 1124 1125 static int amdgpu_pci_probe(struct pci_dev *pdev, 1126 const struct pci_device_id *ent) 1127 { 1128 struct drm_device *ddev; 1129 struct amdgpu_device *adev; 1130 unsigned long flags = ent->driver_data; 1131 int ret, retry = 0; 1132 bool supports_atomic = false; 1133 1134 if (!amdgpu_virtual_display && 1135 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1136 supports_atomic = true; 1137 1138 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1139 DRM_INFO("This hardware requires experimental hardware support.\n" 1140 "See modparam exp_hw_support\n"); 1141 return -ENODEV; 1142 } 1143 1144 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1145 * however, SME requires an indirect IOMMU mapping because the encryption 1146 * bit is beyond the DMA mask of the chip. 1147 */ 1148 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1149 dev_info(&pdev->dev, 1150 "SME is not compatible with RAVEN\n"); 1151 return -ENOTSUPP; 1152 } 1153 1154 #ifdef CONFIG_DRM_AMDGPU_SI 1155 if (!amdgpu_si_support) { 1156 switch (flags & AMD_ASIC_MASK) { 1157 case CHIP_TAHITI: 1158 case CHIP_PITCAIRN: 1159 case CHIP_VERDE: 1160 case CHIP_OLAND: 1161 case CHIP_HAINAN: 1162 dev_info(&pdev->dev, 1163 "SI support provided by radeon.\n"); 1164 dev_info(&pdev->dev, 1165 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1166 ); 1167 return -ENODEV; 1168 } 1169 } 1170 #endif 1171 #ifdef CONFIG_DRM_AMDGPU_CIK 1172 if (!amdgpu_cik_support) { 1173 switch (flags & AMD_ASIC_MASK) { 1174 case CHIP_KAVERI: 1175 case CHIP_BONAIRE: 1176 case CHIP_HAWAII: 1177 case CHIP_KABINI: 1178 case CHIP_MULLINS: 1179 dev_info(&pdev->dev, 1180 "CIK support provided by radeon.\n"); 1181 dev_info(&pdev->dev, 1182 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1183 ); 1184 return -ENODEV; 1185 } 1186 } 1187 #endif 1188 1189 /* Get rid of things like offb */ 1190 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1191 if (ret) 1192 return ret; 1193 1194 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1195 if (IS_ERR(adev)) 1196 return PTR_ERR(adev); 1197 1198 adev->dev = &pdev->dev; 1199 adev->pdev = pdev; 1200 ddev = adev_to_drm(adev); 1201 1202 if (!supports_atomic) 1203 ddev->driver_features &= ~DRIVER_ATOMIC; 1204 1205 ret = pci_enable_device(pdev); 1206 if (ret) 1207 return ret; 1208 1209 ddev->pdev = pdev; 1210 pci_set_drvdata(pdev, ddev); 1211 1212 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1213 if (ret) 1214 goto err_pci; 1215 1216 retry_init: 1217 ret = drm_dev_register(ddev, ent->driver_data); 1218 if (ret == -EAGAIN && ++retry <= 3) { 1219 DRM_INFO("retry init %d\n", retry); 1220 /* Don't request EX mode too frequently which is attacking */ 1221 msleep(5000); 1222 goto retry_init; 1223 } else if (ret) { 1224 goto err_pci; 1225 } 1226 1227 ret = amdgpu_debugfs_init(adev); 1228 if (ret) 1229 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1230 1231 return 0; 1232 1233 err_pci: 1234 pci_disable_device(pdev); 1235 return ret; 1236 } 1237 1238 static void 1239 amdgpu_pci_remove(struct pci_dev *pdev) 1240 { 1241 struct drm_device *dev = pci_get_drvdata(pdev); 1242 1243 #ifdef MODULE 1244 if (THIS_MODULE->state != MODULE_STATE_GOING) 1245 #endif 1246 DRM_ERROR("Hotplug removal is not supported\n"); 1247 drm_dev_unplug(dev); 1248 amdgpu_driver_unload_kms(dev); 1249 pci_disable_device(pdev); 1250 pci_set_drvdata(pdev, NULL); 1251 } 1252 1253 static void 1254 amdgpu_pci_shutdown(struct pci_dev *pdev) 1255 { 1256 struct drm_device *dev = pci_get_drvdata(pdev); 1257 struct amdgpu_device *adev = drm_to_adev(dev); 1258 1259 if (amdgpu_ras_intr_triggered()) 1260 return; 1261 1262 /* if we are running in a VM, make sure the device 1263 * torn down properly on reboot/shutdown. 1264 * unfortunately we can't detect certain 1265 * hypervisors so just do this all the time. 1266 */ 1267 if (!amdgpu_passthrough(adev)) 1268 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1269 amdgpu_device_ip_suspend(adev); 1270 adev->mp1_state = PP_MP1_STATE_NONE; 1271 } 1272 1273 static int amdgpu_pmops_suspend(struct device *dev) 1274 { 1275 struct drm_device *drm_dev = dev_get_drvdata(dev); 1276 1277 return amdgpu_device_suspend(drm_dev, true); 1278 } 1279 1280 static int amdgpu_pmops_resume(struct device *dev) 1281 { 1282 struct drm_device *drm_dev = dev_get_drvdata(dev); 1283 1284 return amdgpu_device_resume(drm_dev, true); 1285 } 1286 1287 static int amdgpu_pmops_freeze(struct device *dev) 1288 { 1289 struct drm_device *drm_dev = dev_get_drvdata(dev); 1290 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1291 int r; 1292 1293 adev->in_hibernate = true; 1294 r = amdgpu_device_suspend(drm_dev, true); 1295 adev->in_hibernate = false; 1296 if (r) 1297 return r; 1298 return amdgpu_asic_reset(adev); 1299 } 1300 1301 static int amdgpu_pmops_thaw(struct device *dev) 1302 { 1303 struct drm_device *drm_dev = dev_get_drvdata(dev); 1304 1305 return amdgpu_device_resume(drm_dev, true); 1306 } 1307 1308 static int amdgpu_pmops_poweroff(struct device *dev) 1309 { 1310 struct drm_device *drm_dev = dev_get_drvdata(dev); 1311 1312 return amdgpu_device_suspend(drm_dev, true); 1313 } 1314 1315 static int amdgpu_pmops_restore(struct device *dev) 1316 { 1317 struct drm_device *drm_dev = dev_get_drvdata(dev); 1318 1319 return amdgpu_device_resume(drm_dev, true); 1320 } 1321 1322 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1323 { 1324 struct pci_dev *pdev = to_pci_dev(dev); 1325 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1326 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1327 int ret, i; 1328 1329 if (!adev->runpm) { 1330 pm_runtime_forbid(dev); 1331 return -EBUSY; 1332 } 1333 1334 /* wait for all rings to drain before suspending */ 1335 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1336 struct amdgpu_ring *ring = adev->rings[i]; 1337 if (ring && ring->sched.ready) { 1338 ret = amdgpu_fence_wait_empty(ring); 1339 if (ret) 1340 return -EBUSY; 1341 } 1342 } 1343 1344 adev->in_runpm = true; 1345 if (amdgpu_device_supports_atpx(drm_dev)) 1346 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1347 drm_kms_helper_poll_disable(drm_dev); 1348 1349 ret = amdgpu_device_suspend(drm_dev, false); 1350 if (ret) 1351 return ret; 1352 1353 if (amdgpu_device_supports_atpx(drm_dev)) { 1354 /* Only need to handle PCI state in the driver for ATPX 1355 * PCI core handles it for _PR3. 1356 */ 1357 if (!amdgpu_is_atpx_hybrid()) { 1358 amdgpu_device_cache_pci_state(pdev); 1359 pci_disable_device(pdev); 1360 pci_ignore_hotplug(pdev); 1361 pci_set_power_state(pdev, PCI_D3cold); 1362 } 1363 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1364 } else if (amdgpu_device_supports_baco(drm_dev)) { 1365 amdgpu_device_baco_enter(drm_dev); 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int amdgpu_pmops_runtime_resume(struct device *dev) 1372 { 1373 struct pci_dev *pdev = to_pci_dev(dev); 1374 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1375 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1376 int ret; 1377 1378 if (!adev->runpm) 1379 return -EINVAL; 1380 1381 if (amdgpu_device_supports_atpx(drm_dev)) { 1382 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1383 1384 /* Only need to handle PCI state in the driver for ATPX 1385 * PCI core handles it for _PR3. 1386 */ 1387 if (!amdgpu_is_atpx_hybrid()) { 1388 pci_set_power_state(pdev, PCI_D0); 1389 amdgpu_device_load_pci_state(pdev); 1390 ret = pci_enable_device(pdev); 1391 if (ret) 1392 return ret; 1393 } 1394 pci_set_master(pdev); 1395 } else if (amdgpu_device_supports_boco(drm_dev)) { 1396 /* Only need to handle PCI state in the driver for ATPX 1397 * PCI core handles it for _PR3. 1398 */ 1399 pci_set_master(pdev); 1400 } else if (amdgpu_device_supports_baco(drm_dev)) { 1401 amdgpu_device_baco_exit(drm_dev); 1402 } 1403 ret = amdgpu_device_resume(drm_dev, false); 1404 drm_kms_helper_poll_enable(drm_dev); 1405 if (amdgpu_device_supports_atpx(drm_dev)) 1406 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1407 adev->in_runpm = false; 1408 return 0; 1409 } 1410 1411 static int amdgpu_pmops_runtime_idle(struct device *dev) 1412 { 1413 struct drm_device *drm_dev = dev_get_drvdata(dev); 1414 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1415 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1416 int ret = 1; 1417 1418 if (!adev->runpm) { 1419 pm_runtime_forbid(dev); 1420 return -EBUSY; 1421 } 1422 1423 if (amdgpu_device_has_dc_support(adev)) { 1424 struct drm_crtc *crtc; 1425 1426 drm_modeset_lock_all(drm_dev); 1427 1428 drm_for_each_crtc(crtc, drm_dev) { 1429 if (crtc->state->active) { 1430 ret = -EBUSY; 1431 break; 1432 } 1433 } 1434 1435 drm_modeset_unlock_all(drm_dev); 1436 1437 } else { 1438 struct drm_connector *list_connector; 1439 struct drm_connector_list_iter iter; 1440 1441 mutex_lock(&drm_dev->mode_config.mutex); 1442 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1443 1444 drm_connector_list_iter_begin(drm_dev, &iter); 1445 drm_for_each_connector_iter(list_connector, &iter) { 1446 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1447 ret = -EBUSY; 1448 break; 1449 } 1450 } 1451 1452 drm_connector_list_iter_end(&iter); 1453 1454 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1455 mutex_unlock(&drm_dev->mode_config.mutex); 1456 } 1457 1458 if (ret == -EBUSY) 1459 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1460 1461 pm_runtime_mark_last_busy(dev); 1462 pm_runtime_autosuspend(dev); 1463 return ret; 1464 } 1465 1466 long amdgpu_drm_ioctl(struct file *filp, 1467 unsigned int cmd, unsigned long arg) 1468 { 1469 struct drm_file *file_priv = filp->private_data; 1470 struct drm_device *dev; 1471 long ret; 1472 dev = file_priv->minor->dev; 1473 ret = pm_runtime_get_sync(dev->dev); 1474 if (ret < 0) 1475 goto out; 1476 1477 ret = drm_ioctl(filp, cmd, arg); 1478 1479 pm_runtime_mark_last_busy(dev->dev); 1480 out: 1481 pm_runtime_put_autosuspend(dev->dev); 1482 return ret; 1483 } 1484 1485 static const struct dev_pm_ops amdgpu_pm_ops = { 1486 .suspend = amdgpu_pmops_suspend, 1487 .resume = amdgpu_pmops_resume, 1488 .freeze = amdgpu_pmops_freeze, 1489 .thaw = amdgpu_pmops_thaw, 1490 .poweroff = amdgpu_pmops_poweroff, 1491 .restore = amdgpu_pmops_restore, 1492 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1493 .runtime_resume = amdgpu_pmops_runtime_resume, 1494 .runtime_idle = amdgpu_pmops_runtime_idle, 1495 }; 1496 1497 static int amdgpu_flush(struct file *f, fl_owner_t id) 1498 { 1499 struct drm_file *file_priv = f->private_data; 1500 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1501 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1502 1503 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1504 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1505 1506 return timeout >= 0 ? 0 : timeout; 1507 } 1508 1509 static const struct file_operations amdgpu_driver_kms_fops = { 1510 .owner = THIS_MODULE, 1511 .open = drm_open, 1512 .flush = amdgpu_flush, 1513 .release = drm_release, 1514 .unlocked_ioctl = amdgpu_drm_ioctl, 1515 .mmap = amdgpu_mmap, 1516 .poll = drm_poll, 1517 .read = drm_read, 1518 #ifdef CONFIG_COMPAT 1519 .compat_ioctl = amdgpu_kms_compat_ioctl, 1520 #endif 1521 }; 1522 1523 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1524 { 1525 struct drm_file *file; 1526 1527 if (!filp) 1528 return -EINVAL; 1529 1530 if (filp->f_op != &amdgpu_driver_kms_fops) { 1531 return -EINVAL; 1532 } 1533 1534 file = filp->private_data; 1535 *fpriv = file->driver_priv; 1536 return 0; 1537 } 1538 1539 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1540 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1541 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1542 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1543 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1544 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1545 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1546 /* KMS */ 1547 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1548 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1549 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1550 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1551 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1552 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1553 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1554 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1555 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1556 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1557 }; 1558 1559 static const struct drm_driver amdgpu_kms_driver = { 1560 .driver_features = 1561 DRIVER_ATOMIC | 1562 DRIVER_GEM | 1563 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1564 DRIVER_SYNCOBJ_TIMELINE, 1565 .open = amdgpu_driver_open_kms, 1566 .postclose = amdgpu_driver_postclose_kms, 1567 .lastclose = amdgpu_driver_lastclose_kms, 1568 .irq_handler = amdgpu_irq_handler, 1569 .ioctls = amdgpu_ioctls_kms, 1570 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1571 .dumb_create = amdgpu_mode_dumb_create, 1572 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1573 .fops = &amdgpu_driver_kms_fops, 1574 1575 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1576 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1577 .gem_prime_import = amdgpu_gem_prime_import, 1578 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1579 1580 .name = DRIVER_NAME, 1581 .desc = DRIVER_DESC, 1582 .date = DRIVER_DATE, 1583 .major = KMS_DRIVER_MAJOR, 1584 .minor = KMS_DRIVER_MINOR, 1585 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1586 }; 1587 1588 static struct pci_error_handlers amdgpu_pci_err_handler = { 1589 .error_detected = amdgpu_pci_error_detected, 1590 .mmio_enabled = amdgpu_pci_mmio_enabled, 1591 .slot_reset = amdgpu_pci_slot_reset, 1592 .resume = amdgpu_pci_resume, 1593 }; 1594 1595 static struct pci_driver amdgpu_kms_pci_driver = { 1596 .name = DRIVER_NAME, 1597 .id_table = pciidlist, 1598 .probe = amdgpu_pci_probe, 1599 .remove = amdgpu_pci_remove, 1600 .shutdown = amdgpu_pci_shutdown, 1601 .driver.pm = &amdgpu_pm_ops, 1602 .err_handler = &amdgpu_pci_err_handler, 1603 }; 1604 1605 static int __init amdgpu_init(void) 1606 { 1607 int r; 1608 1609 if (vgacon_text_force()) { 1610 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1611 return -EINVAL; 1612 } 1613 1614 r = amdgpu_sync_init(); 1615 if (r) 1616 goto error_sync; 1617 1618 r = amdgpu_fence_slab_init(); 1619 if (r) 1620 goto error_fence; 1621 1622 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1623 amdgpu_register_atpx_handler(); 1624 1625 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1626 amdgpu_amdkfd_init(); 1627 1628 /* let modprobe override vga console setting */ 1629 return pci_register_driver(&amdgpu_kms_pci_driver); 1630 1631 error_fence: 1632 amdgpu_sync_fini(); 1633 1634 error_sync: 1635 return r; 1636 } 1637 1638 static void __exit amdgpu_exit(void) 1639 { 1640 amdgpu_amdkfd_fini(); 1641 pci_unregister_driver(&amdgpu_kms_pci_driver); 1642 amdgpu_unregister_atpx_handler(); 1643 amdgpu_sync_fini(); 1644 amdgpu_fence_slab_fini(); 1645 mmu_notifier_synchronize(); 1646 } 1647 1648 module_init(amdgpu_init); 1649 module_exit(amdgpu_exit); 1650 1651 MODULE_AUTHOR(DRIVER_AUTHOR); 1652 MODULE_DESCRIPTION(DRIVER_DESC); 1653 MODULE_LICENSE("GPL and additional rights"); 1654