1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/console.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 40 #include "amdgpu.h" 41 #include "amdgpu_irq.h" 42 #include "amdgpu_dma_buf.h" 43 #include "amdgpu_sched.h" 44 45 #include "amdgpu_amdkfd.h" 46 47 #include "amdgpu_ras.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 * - 3.16.0 - Add reserved vmid support 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 70 * - 3.18.0 - Export gpu always on cu bitmap 71 * - 3.19.0 - Add support for UVD MJPEG decode 72 * - 3.20.0 - Add support for local BOs 73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 75 * - 3.23.0 - Add query for VRAM lost counter 76 * - 3.24.0 - Add high priority compute support for gfx9 77 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 78 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 79 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 80 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 81 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 82 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 83 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 84 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 85 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 86 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 87 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 88 * - 3.36.0 - Allow reading more status registers on si/cik 89 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 90 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 91 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 92 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 93 */ 94 #define KMS_DRIVER_MAJOR 3 95 #define KMS_DRIVER_MINOR 40 96 #define KMS_DRIVER_PATCHLEVEL 0 97 98 int amdgpu_vram_limit = 0; 99 int amdgpu_vis_vram_limit = 0; 100 int amdgpu_gart_size = -1; /* auto */ 101 int amdgpu_gtt_size = -1; /* auto */ 102 int amdgpu_moverate = -1; /* auto */ 103 int amdgpu_benchmarking = 0; 104 int amdgpu_testing = 0; 105 int amdgpu_audio = -1; 106 int amdgpu_disp_priority = 0; 107 int amdgpu_hw_i2c = 0; 108 int amdgpu_pcie_gen2 = -1; 109 int amdgpu_msi = -1; 110 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 111 int amdgpu_dpm = -1; 112 int amdgpu_fw_load_type = -1; 113 int amdgpu_aspm = -1; 114 int amdgpu_runtime_pm = -1; 115 uint amdgpu_ip_block_mask = 0xffffffff; 116 int amdgpu_bapm = -1; 117 int amdgpu_deep_color = 0; 118 int amdgpu_vm_size = -1; 119 int amdgpu_vm_fragment_size = -1; 120 int amdgpu_vm_block_size = -1; 121 int amdgpu_vm_fault_stop = 0; 122 int amdgpu_vm_debug = 0; 123 int amdgpu_vm_update_mode = -1; 124 int amdgpu_exp_hw_support = 0; 125 int amdgpu_dc = -1; 126 int amdgpu_sched_jobs = 32; 127 int amdgpu_sched_hw_submission = 2; 128 uint amdgpu_pcie_gen_cap = 0; 129 uint amdgpu_pcie_lane_cap = 0; 130 uint amdgpu_cg_mask = 0xffffffff; 131 uint amdgpu_pg_mask = 0xffffffff; 132 uint amdgpu_sdma_phase_quantum = 32; 133 char *amdgpu_disable_cu = NULL; 134 char *amdgpu_virtual_display = NULL; 135 /* OverDrive(bit 14) disabled by default*/ 136 uint amdgpu_pp_feature_mask = 0xffffbfff; 137 uint amdgpu_force_long_training = 0; 138 int amdgpu_job_hang_limit = 0; 139 int amdgpu_lbpw = -1; 140 int amdgpu_compute_multipipe = -1; 141 int amdgpu_gpu_recovery = -1; /* auto */ 142 int amdgpu_emu_mode = 0; 143 uint amdgpu_smu_memory_pool_size = 0; 144 /* FBC (bit 0) disabled by default*/ 145 uint amdgpu_dc_feature_mask = 0; 146 uint amdgpu_dc_debug_mask = 0; 147 int amdgpu_async_gfx_ring = 1; 148 int amdgpu_mcbp = 0; 149 int amdgpu_discovery = -1; 150 int amdgpu_mes = 0; 151 int amdgpu_noretry = -1; 152 int amdgpu_force_asic_type = -1; 153 int amdgpu_tmz = 0; 154 int amdgpu_reset_method = -1; /* auto */ 155 int amdgpu_num_kcq = -1; 156 157 struct amdgpu_mgpu_info mgpu_info = { 158 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 159 }; 160 int amdgpu_ras_enable = -1; 161 uint amdgpu_ras_mask = 0xffffffff; 162 int amdgpu_bad_page_threshold = -1; 163 164 /** 165 * DOC: vramlimit (int) 166 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 167 */ 168 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 169 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 170 171 /** 172 * DOC: vis_vramlimit (int) 173 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 174 */ 175 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 176 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 177 178 /** 179 * DOC: gartsize (uint) 180 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 181 */ 182 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 183 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 184 185 /** 186 * DOC: gttsize (int) 187 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 188 * otherwise 3/4 RAM size). 189 */ 190 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 191 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 192 193 /** 194 * DOC: moverate (int) 195 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 196 */ 197 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 198 module_param_named(moverate, amdgpu_moverate, int, 0600); 199 200 /** 201 * DOC: benchmark (int) 202 * Run benchmarks. The default is 0 (Skip benchmarks). 203 */ 204 MODULE_PARM_DESC(benchmark, "Run benchmark"); 205 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 206 207 /** 208 * DOC: test (int) 209 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 210 */ 211 MODULE_PARM_DESC(test, "Run tests"); 212 module_param_named(test, amdgpu_testing, int, 0444); 213 214 /** 215 * DOC: audio (int) 216 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 217 */ 218 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 219 module_param_named(audio, amdgpu_audio, int, 0444); 220 221 /** 222 * DOC: disp_priority (int) 223 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 224 */ 225 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 226 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 227 228 /** 229 * DOC: hw_i2c (int) 230 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 231 */ 232 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 233 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 234 235 /** 236 * DOC: pcie_gen2 (int) 237 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 238 */ 239 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 240 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 241 242 /** 243 * DOC: msi (int) 244 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 245 */ 246 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 247 module_param_named(msi, amdgpu_msi, int, 0444); 248 249 /** 250 * DOC: lockup_timeout (string) 251 * Set GPU scheduler timeout value in ms. 252 * 253 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 254 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 255 * to the default timeout. 256 * 257 * - With one value specified, the setting will apply to all non-compute jobs. 258 * - With multiple values specified, the first one will be for GFX. 259 * The second one is for Compute. The third and fourth ones are 260 * for SDMA and Video. 261 * 262 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 263 * jobs is 10000. And there is no timeout enforced on compute jobs. 264 */ 265 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 266 "for passthrough or sriov, 10000 for all jobs." 267 " 0: keep default value. negative: infinity timeout), " 268 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 269 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 270 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 271 272 /** 273 * DOC: dpm (int) 274 * Override for dynamic power management setting 275 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 276 * The default is -1 (auto). 277 */ 278 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 279 module_param_named(dpm, amdgpu_dpm, int, 0444); 280 281 /** 282 * DOC: fw_load_type (int) 283 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 284 */ 285 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 286 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 287 288 /** 289 * DOC: aspm (int) 290 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 291 */ 292 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 293 module_param_named(aspm, amdgpu_aspm, int, 0444); 294 295 /** 296 * DOC: runpm (int) 297 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 298 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 299 */ 300 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 301 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 302 303 /** 304 * DOC: ip_block_mask (uint) 305 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 306 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 307 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 308 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 309 */ 310 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 311 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 312 313 /** 314 * DOC: bapm (int) 315 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 316 * The default -1 (auto, enabled) 317 */ 318 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 319 module_param_named(bapm, amdgpu_bapm, int, 0444); 320 321 /** 322 * DOC: deep_color (int) 323 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 324 */ 325 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 326 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 327 328 /** 329 * DOC: vm_size (int) 330 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 331 */ 332 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 333 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 334 335 /** 336 * DOC: vm_fragment_size (int) 337 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 338 */ 339 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 340 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 341 342 /** 343 * DOC: vm_block_size (int) 344 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 345 */ 346 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 347 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 348 349 /** 350 * DOC: vm_fault_stop (int) 351 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 352 */ 353 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 354 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 355 356 /** 357 * DOC: vm_debug (int) 358 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 359 */ 360 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 361 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 362 363 /** 364 * DOC: vm_update_mode (int) 365 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 366 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 367 */ 368 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 369 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 370 371 /** 372 * DOC: exp_hw_support (int) 373 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 374 */ 375 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 376 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 377 378 /** 379 * DOC: dc (int) 380 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 381 */ 382 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 383 module_param_named(dc, amdgpu_dc, int, 0444); 384 385 /** 386 * DOC: sched_jobs (int) 387 * Override the max number of jobs supported in the sw queue. The default is 32. 388 */ 389 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 390 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 391 392 /** 393 * DOC: sched_hw_submission (int) 394 * Override the max number of HW submissions. The default is 2. 395 */ 396 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 397 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 398 399 /** 400 * DOC: ppfeaturemask (hexint) 401 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 402 * The default is the current set of stable power features. 403 */ 404 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 405 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 406 407 /** 408 * DOC: forcelongtraining (uint) 409 * Force long memory training in resume. 410 * The default is zero, indicates short training in resume. 411 */ 412 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 413 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 414 415 /** 416 * DOC: pcie_gen_cap (uint) 417 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 418 * The default is 0 (automatic for each asic). 419 */ 420 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 421 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 422 423 /** 424 * DOC: pcie_lane_cap (uint) 425 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 426 * The default is 0 (automatic for each asic). 427 */ 428 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 429 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 430 431 /** 432 * DOC: cg_mask (uint) 433 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 434 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 435 */ 436 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 437 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 438 439 /** 440 * DOC: pg_mask (uint) 441 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 442 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 443 */ 444 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 445 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 446 447 /** 448 * DOC: sdma_phase_quantum (uint) 449 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 450 */ 451 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 452 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 453 454 /** 455 * DOC: disable_cu (charp) 456 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 457 */ 458 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 459 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 460 461 /** 462 * DOC: virtual_display (charp) 463 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 464 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 465 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 466 * device at 26:00.0. The default is NULL. 467 */ 468 MODULE_PARM_DESC(virtual_display, 469 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 470 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 471 472 /** 473 * DOC: job_hang_limit (int) 474 * Set how much time allow a job hang and not drop it. The default is 0. 475 */ 476 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 477 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 478 479 /** 480 * DOC: lbpw (int) 481 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 482 */ 483 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 484 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 485 486 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 487 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 488 489 /** 490 * DOC: gpu_recovery (int) 491 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 492 */ 493 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 494 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 495 496 /** 497 * DOC: emu_mode (int) 498 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 499 */ 500 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 501 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 502 503 /** 504 * DOC: ras_enable (int) 505 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 506 */ 507 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 508 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 509 510 /** 511 * DOC: ras_mask (uint) 512 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 513 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 514 */ 515 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 516 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 517 518 /** 519 * DOC: si_support (int) 520 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 521 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 522 * otherwise using amdgpu driver. 523 */ 524 #ifdef CONFIG_DRM_AMDGPU_SI 525 526 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 527 int amdgpu_si_support = 0; 528 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 529 #else 530 int amdgpu_si_support = 1; 531 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 532 #endif 533 534 module_param_named(si_support, amdgpu_si_support, int, 0444); 535 #endif 536 537 /** 538 * DOC: cik_support (int) 539 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 540 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 541 * otherwise using amdgpu driver. 542 */ 543 #ifdef CONFIG_DRM_AMDGPU_CIK 544 545 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 546 int amdgpu_cik_support = 0; 547 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 548 #else 549 int amdgpu_cik_support = 1; 550 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 551 #endif 552 553 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 554 #endif 555 556 /** 557 * DOC: smu_memory_pool_size (uint) 558 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 559 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 560 */ 561 MODULE_PARM_DESC(smu_memory_pool_size, 562 "reserve gtt for smu debug usage, 0 = disable," 563 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 564 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 565 566 /** 567 * DOC: async_gfx_ring (int) 568 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 569 */ 570 MODULE_PARM_DESC(async_gfx_ring, 571 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 572 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 573 574 /** 575 * DOC: mcbp (int) 576 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 577 */ 578 MODULE_PARM_DESC(mcbp, 579 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 580 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 581 582 /** 583 * DOC: discovery (int) 584 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 585 * (-1 = auto (default), 0 = disabled, 1 = enabled) 586 */ 587 MODULE_PARM_DESC(discovery, 588 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 589 module_param_named(discovery, amdgpu_discovery, int, 0444); 590 591 /** 592 * DOC: mes (int) 593 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 594 * (0 = disabled (default), 1 = enabled) 595 */ 596 MODULE_PARM_DESC(mes, 597 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 598 module_param_named(mes, amdgpu_mes, int, 0444); 599 600 /** 601 * DOC: noretry (int) 602 * Disable retry faults in the GPU memory controller. 603 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 604 */ 605 MODULE_PARM_DESC(noretry, 606 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 607 module_param_named(noretry, amdgpu_noretry, int, 0644); 608 609 /** 610 * DOC: force_asic_type (int) 611 * A non negative value used to specify the asic type for all supported GPUs. 612 */ 613 MODULE_PARM_DESC(force_asic_type, 614 "A non negative value used to specify the asic type for all supported GPUs"); 615 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 616 617 618 619 #ifdef CONFIG_HSA_AMD 620 /** 621 * DOC: sched_policy (int) 622 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 623 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 624 * assigns queues to HQDs. 625 */ 626 int sched_policy = KFD_SCHED_POLICY_HWS; 627 module_param(sched_policy, int, 0444); 628 MODULE_PARM_DESC(sched_policy, 629 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 630 631 /** 632 * DOC: hws_max_conc_proc (int) 633 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 634 * number of VMIDs assigned to the HWS, which is also the default. 635 */ 636 int hws_max_conc_proc = 8; 637 module_param(hws_max_conc_proc, int, 0444); 638 MODULE_PARM_DESC(hws_max_conc_proc, 639 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 640 641 /** 642 * DOC: cwsr_enable (int) 643 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 644 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 645 * disables it. 646 */ 647 int cwsr_enable = 1; 648 module_param(cwsr_enable, int, 0444); 649 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 650 651 /** 652 * DOC: max_num_of_queues_per_device (int) 653 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 654 * is 4096. 655 */ 656 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 657 module_param(max_num_of_queues_per_device, int, 0444); 658 MODULE_PARM_DESC(max_num_of_queues_per_device, 659 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 660 661 /** 662 * DOC: send_sigterm (int) 663 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 664 * but just print errors on dmesg. Setting 1 enables sending sigterm. 665 */ 666 int send_sigterm; 667 module_param(send_sigterm, int, 0444); 668 MODULE_PARM_DESC(send_sigterm, 669 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 670 671 /** 672 * DOC: debug_largebar (int) 673 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 674 * system. This limits the VRAM size reported to ROCm applications to the visible 675 * size, usually 256MB. 676 * Default value is 0, diabled. 677 */ 678 int debug_largebar; 679 module_param(debug_largebar, int, 0444); 680 MODULE_PARM_DESC(debug_largebar, 681 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 682 683 /** 684 * DOC: ignore_crat (int) 685 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 686 * table to get information about AMD APUs. This option can serve as a workaround on 687 * systems with a broken CRAT table. 688 * 689 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 690 * whehter use CRAT) 691 */ 692 int ignore_crat; 693 module_param(ignore_crat, int, 0444); 694 MODULE_PARM_DESC(ignore_crat, 695 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 696 697 /** 698 * DOC: halt_if_hws_hang (int) 699 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 700 * Setting 1 enables halt on hang. 701 */ 702 int halt_if_hws_hang; 703 module_param(halt_if_hws_hang, int, 0644); 704 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 705 706 /** 707 * DOC: hws_gws_support(bool) 708 * Assume that HWS supports GWS barriers regardless of what firmware version 709 * check says. Default value: false (rely on MEC2 firmware version check). 710 */ 711 bool hws_gws_support; 712 module_param(hws_gws_support, bool, 0444); 713 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 714 715 /** 716 * DOC: queue_preemption_timeout_ms (int) 717 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 718 */ 719 int queue_preemption_timeout_ms = 9000; 720 module_param(queue_preemption_timeout_ms, int, 0644); 721 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 722 723 /** 724 * DOC: debug_evictions(bool) 725 * Enable extra debug messages to help determine the cause of evictions 726 */ 727 bool debug_evictions; 728 module_param(debug_evictions, bool, 0644); 729 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 730 731 /** 732 * DOC: no_system_mem_limit(bool) 733 * Disable system memory limit, to support multiple process shared memory 734 */ 735 bool no_system_mem_limit; 736 module_param(no_system_mem_limit, bool, 0644); 737 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 738 739 #endif 740 741 /** 742 * DOC: dcfeaturemask (uint) 743 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 744 * The default is the current set of stable display features. 745 */ 746 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 747 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 748 749 /** 750 * DOC: dcdebugmask (uint) 751 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 752 */ 753 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 754 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 755 756 /** 757 * DOC: abmlevel (uint) 758 * Override the default ABM (Adaptive Backlight Management) level used for DC 759 * enabled hardware. Requires DMCU to be supported and loaded. 760 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 761 * default. Values 1-4 control the maximum allowable brightness reduction via 762 * the ABM algorithm, with 1 being the least reduction and 4 being the most 763 * reduction. 764 * 765 * Defaults to 0, or disabled. Userspace can still override this level later 766 * after boot. 767 */ 768 uint amdgpu_dm_abm_level = 0; 769 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 770 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 771 772 /** 773 * DOC: tmz (int) 774 * Trusted Memory Zone (TMZ) is a method to protect data being written 775 * to or read from memory. 776 * 777 * The default value: 0 (off). TODO: change to auto till it is completed. 778 */ 779 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); 780 module_param_named(tmz, amdgpu_tmz, int, 0444); 781 782 /** 783 * DOC: reset_method (int) 784 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 785 */ 786 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)"); 787 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 788 789 /** 790 * DOC: bad_page_threshold (int) 791 * Bad page threshold is to specify the threshold value of faulty pages 792 * detected by RAS ECC, that may result in GPU entering bad status if total 793 * faulty pages by ECC exceed threshold value and leave it for user's further 794 * check. 795 */ 796 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 797 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 798 799 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 800 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 801 802 static const struct pci_device_id pciidlist[] = { 803 #ifdef CONFIG_DRM_AMDGPU_SI 804 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 805 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 806 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 807 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 808 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 809 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 810 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 811 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 812 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 813 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 814 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 815 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 816 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 817 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 818 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 819 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 820 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 821 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 822 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 823 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 824 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 825 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 826 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 827 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 828 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 829 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 830 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 831 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 832 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 833 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 834 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 835 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 836 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 837 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 838 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 839 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 840 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 841 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 842 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 843 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 844 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 845 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 846 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 847 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 848 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 849 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 850 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 851 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 852 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 853 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 854 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 855 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 856 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 857 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 858 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 859 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 860 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 861 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 862 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 863 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 864 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 865 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 866 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 867 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 868 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 869 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 870 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 871 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 872 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 873 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 874 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 875 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 876 #endif 877 #ifdef CONFIG_DRM_AMDGPU_CIK 878 /* Kaveri */ 879 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 880 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 881 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 882 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 883 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 884 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 888 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 889 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 890 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 891 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 892 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 893 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 894 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 895 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 896 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 897 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 898 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 899 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 900 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 901 /* Bonaire */ 902 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 903 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 904 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 905 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 906 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 907 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 908 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 909 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 910 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 911 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 912 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 913 /* Hawaii */ 914 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 915 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 916 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 917 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 918 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 919 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 920 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 921 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 922 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 923 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 924 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 925 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 926 /* Kabini */ 927 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 928 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 929 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 930 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 931 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 932 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 933 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 934 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 935 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 936 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 937 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 938 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 939 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 940 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 941 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 942 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 943 /* mullins */ 944 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 945 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 946 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 947 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 948 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 949 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 950 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 951 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 952 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 953 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 954 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 955 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 956 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 957 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 958 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 959 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 960 #endif 961 /* topaz */ 962 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 963 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 964 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 965 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 966 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 967 /* tonga */ 968 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 969 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 970 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 971 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 972 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 973 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 974 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 975 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 976 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 977 /* fiji */ 978 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 979 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 980 /* carrizo */ 981 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 982 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 983 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 984 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 985 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 986 /* stoney */ 987 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 988 /* Polaris11 */ 989 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 990 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 991 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 992 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 993 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 994 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 995 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 996 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 997 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 998 /* Polaris10 */ 999 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1000 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1001 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1002 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1003 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1004 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1005 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1006 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1007 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1008 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1009 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1010 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1011 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1012 /* Polaris12 */ 1013 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1014 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1015 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1016 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1017 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1018 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1019 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1020 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1021 /* VEGAM */ 1022 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1023 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1024 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1025 /* Vega 10 */ 1026 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1027 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1028 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1029 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1030 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1031 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1032 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1033 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1034 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1035 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1036 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1037 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1038 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1039 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1040 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1041 /* Vega 12 */ 1042 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1043 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1044 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1045 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1046 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1047 /* Vega 20 */ 1048 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1049 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1050 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1051 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1052 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1053 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1054 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1055 /* Raven */ 1056 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1057 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1058 /* Arcturus */ 1059 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1060 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1061 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1062 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1063 /* Navi10 */ 1064 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1065 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1066 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1067 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1068 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1069 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1070 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1071 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1072 /* Navi14 */ 1073 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1074 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1075 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1076 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1077 1078 /* Renoir */ 1079 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1080 1081 /* Navi12 */ 1082 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1083 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1084 1085 /* Sienna_Cichlid */ 1086 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1087 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1088 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1089 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1090 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1091 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1092 1093 {0, 0, 0} 1094 }; 1095 1096 MODULE_DEVICE_TABLE(pci, pciidlist); 1097 1098 static const struct drm_driver amdgpu_kms_driver; 1099 1100 static int amdgpu_pci_probe(struct pci_dev *pdev, 1101 const struct pci_device_id *ent) 1102 { 1103 struct drm_device *ddev; 1104 struct amdgpu_device *adev; 1105 unsigned long flags = ent->driver_data; 1106 int ret, retry = 0; 1107 bool supports_atomic = false; 1108 1109 if (!amdgpu_virtual_display && 1110 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1111 supports_atomic = true; 1112 1113 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1114 DRM_INFO("This hardware requires experimental hardware support.\n" 1115 "See modparam exp_hw_support\n"); 1116 return -ENODEV; 1117 } 1118 1119 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1120 * however, SME requires an indirect IOMMU mapping because the encryption 1121 * bit is beyond the DMA mask of the chip. 1122 */ 1123 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1124 dev_info(&pdev->dev, 1125 "SME is not compatible with RAVEN\n"); 1126 return -ENOTSUPP; 1127 } 1128 1129 #ifdef CONFIG_DRM_AMDGPU_SI 1130 if (!amdgpu_si_support) { 1131 switch (flags & AMD_ASIC_MASK) { 1132 case CHIP_TAHITI: 1133 case CHIP_PITCAIRN: 1134 case CHIP_VERDE: 1135 case CHIP_OLAND: 1136 case CHIP_HAINAN: 1137 dev_info(&pdev->dev, 1138 "SI support provided by radeon.\n"); 1139 dev_info(&pdev->dev, 1140 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1141 ); 1142 return -ENODEV; 1143 } 1144 } 1145 #endif 1146 #ifdef CONFIG_DRM_AMDGPU_CIK 1147 if (!amdgpu_cik_support) { 1148 switch (flags & AMD_ASIC_MASK) { 1149 case CHIP_KAVERI: 1150 case CHIP_BONAIRE: 1151 case CHIP_HAWAII: 1152 case CHIP_KABINI: 1153 case CHIP_MULLINS: 1154 dev_info(&pdev->dev, 1155 "CIK support provided by radeon.\n"); 1156 dev_info(&pdev->dev, 1157 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1158 ); 1159 return -ENODEV; 1160 } 1161 } 1162 #endif 1163 1164 /* Get rid of things like offb */ 1165 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1166 if (ret) 1167 return ret; 1168 1169 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1170 if (IS_ERR(adev)) 1171 return PTR_ERR(adev); 1172 1173 adev->dev = &pdev->dev; 1174 adev->pdev = pdev; 1175 ddev = adev_to_drm(adev); 1176 1177 if (!supports_atomic) 1178 ddev->driver_features &= ~DRIVER_ATOMIC; 1179 1180 ret = pci_enable_device(pdev); 1181 if (ret) 1182 return ret; 1183 1184 ddev->pdev = pdev; 1185 pci_set_drvdata(pdev, ddev); 1186 1187 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1188 if (ret) 1189 goto err_pci; 1190 1191 retry_init: 1192 ret = drm_dev_register(ddev, ent->driver_data); 1193 if (ret == -EAGAIN && ++retry <= 3) { 1194 DRM_INFO("retry init %d\n", retry); 1195 /* Don't request EX mode too frequently which is attacking */ 1196 msleep(5000); 1197 goto retry_init; 1198 } else if (ret) { 1199 goto err_pci; 1200 } 1201 1202 ret = amdgpu_debugfs_init(adev); 1203 if (ret) 1204 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1205 1206 return 0; 1207 1208 err_pci: 1209 pci_disable_device(pdev); 1210 return ret; 1211 } 1212 1213 static void 1214 amdgpu_pci_remove(struct pci_dev *pdev) 1215 { 1216 struct drm_device *dev = pci_get_drvdata(pdev); 1217 1218 #ifdef MODULE 1219 if (THIS_MODULE->state != MODULE_STATE_GOING) 1220 #endif 1221 DRM_ERROR("Hotplug removal is not supported\n"); 1222 drm_dev_unplug(dev); 1223 amdgpu_driver_unload_kms(dev); 1224 pci_disable_device(pdev); 1225 pci_set_drvdata(pdev, NULL); 1226 } 1227 1228 static void 1229 amdgpu_pci_shutdown(struct pci_dev *pdev) 1230 { 1231 struct drm_device *dev = pci_get_drvdata(pdev); 1232 struct amdgpu_device *adev = drm_to_adev(dev); 1233 1234 if (amdgpu_ras_intr_triggered()) 1235 return; 1236 1237 /* if we are running in a VM, make sure the device 1238 * torn down properly on reboot/shutdown. 1239 * unfortunately we can't detect certain 1240 * hypervisors so just do this all the time. 1241 */ 1242 if (!amdgpu_passthrough(adev)) 1243 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1244 amdgpu_device_ip_suspend(adev); 1245 adev->mp1_state = PP_MP1_STATE_NONE; 1246 } 1247 1248 static int amdgpu_pmops_suspend(struct device *dev) 1249 { 1250 struct drm_device *drm_dev = dev_get_drvdata(dev); 1251 1252 return amdgpu_device_suspend(drm_dev, true); 1253 } 1254 1255 static int amdgpu_pmops_resume(struct device *dev) 1256 { 1257 struct drm_device *drm_dev = dev_get_drvdata(dev); 1258 1259 return amdgpu_device_resume(drm_dev, true); 1260 } 1261 1262 static int amdgpu_pmops_freeze(struct device *dev) 1263 { 1264 struct drm_device *drm_dev = dev_get_drvdata(dev); 1265 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1266 int r; 1267 1268 adev->in_hibernate = true; 1269 r = amdgpu_device_suspend(drm_dev, true); 1270 adev->in_hibernate = false; 1271 if (r) 1272 return r; 1273 return amdgpu_asic_reset(adev); 1274 } 1275 1276 static int amdgpu_pmops_thaw(struct device *dev) 1277 { 1278 struct drm_device *drm_dev = dev_get_drvdata(dev); 1279 1280 return amdgpu_device_resume(drm_dev, true); 1281 } 1282 1283 static int amdgpu_pmops_poweroff(struct device *dev) 1284 { 1285 struct drm_device *drm_dev = dev_get_drvdata(dev); 1286 1287 return amdgpu_device_suspend(drm_dev, true); 1288 } 1289 1290 static int amdgpu_pmops_restore(struct device *dev) 1291 { 1292 struct drm_device *drm_dev = dev_get_drvdata(dev); 1293 1294 return amdgpu_device_resume(drm_dev, true); 1295 } 1296 1297 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1298 { 1299 struct pci_dev *pdev = to_pci_dev(dev); 1300 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1301 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1302 int ret, i; 1303 1304 if (!adev->runpm) { 1305 pm_runtime_forbid(dev); 1306 return -EBUSY; 1307 } 1308 1309 /* wait for all rings to drain before suspending */ 1310 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1311 struct amdgpu_ring *ring = adev->rings[i]; 1312 if (ring && ring->sched.ready) { 1313 ret = amdgpu_fence_wait_empty(ring); 1314 if (ret) 1315 return -EBUSY; 1316 } 1317 } 1318 1319 adev->in_runpm = true; 1320 if (amdgpu_device_supports_boco(drm_dev)) 1321 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1322 drm_kms_helper_poll_disable(drm_dev); 1323 1324 ret = amdgpu_device_suspend(drm_dev, false); 1325 if (ret) 1326 return ret; 1327 1328 if (amdgpu_device_supports_boco(drm_dev)) { 1329 /* Only need to handle PCI state in the driver for ATPX 1330 * PCI core handles it for _PR3. 1331 */ 1332 if (amdgpu_is_atpx_hybrid()) { 1333 pci_ignore_hotplug(pdev); 1334 } else { 1335 amdgpu_device_cache_pci_state(pdev); 1336 pci_disable_device(pdev); 1337 pci_ignore_hotplug(pdev); 1338 pci_set_power_state(pdev, PCI_D3cold); 1339 } 1340 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1341 } else if (amdgpu_device_supports_baco(drm_dev)) { 1342 amdgpu_device_baco_enter(drm_dev); 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int amdgpu_pmops_runtime_resume(struct device *dev) 1349 { 1350 struct pci_dev *pdev = to_pci_dev(dev); 1351 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1352 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1353 int ret; 1354 1355 if (!adev->runpm) 1356 return -EINVAL; 1357 1358 if (amdgpu_device_supports_boco(drm_dev)) { 1359 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1360 1361 /* Only need to handle PCI state in the driver for ATPX 1362 * PCI core handles it for _PR3. 1363 */ 1364 if (amdgpu_is_atpx_hybrid()) { 1365 pci_set_master(pdev); 1366 } else { 1367 pci_set_power_state(pdev, PCI_D0); 1368 amdgpu_device_load_pci_state(pdev); 1369 ret = pci_enable_device(pdev); 1370 if (ret) 1371 return ret; 1372 pci_set_master(pdev); 1373 } 1374 } else if (amdgpu_device_supports_baco(drm_dev)) { 1375 amdgpu_device_baco_exit(drm_dev); 1376 } 1377 ret = amdgpu_device_resume(drm_dev, false); 1378 drm_kms_helper_poll_enable(drm_dev); 1379 if (amdgpu_device_supports_boco(drm_dev)) 1380 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1381 adev->in_runpm = false; 1382 return 0; 1383 } 1384 1385 static int amdgpu_pmops_runtime_idle(struct device *dev) 1386 { 1387 struct drm_device *drm_dev = dev_get_drvdata(dev); 1388 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1389 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1390 int ret = 1; 1391 1392 if (!adev->runpm) { 1393 pm_runtime_forbid(dev); 1394 return -EBUSY; 1395 } 1396 1397 if (amdgpu_device_has_dc_support(adev)) { 1398 struct drm_crtc *crtc; 1399 1400 drm_modeset_lock_all(drm_dev); 1401 1402 drm_for_each_crtc(crtc, drm_dev) { 1403 if (crtc->state->active) { 1404 ret = -EBUSY; 1405 break; 1406 } 1407 } 1408 1409 drm_modeset_unlock_all(drm_dev); 1410 1411 } else { 1412 struct drm_connector *list_connector; 1413 struct drm_connector_list_iter iter; 1414 1415 mutex_lock(&drm_dev->mode_config.mutex); 1416 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1417 1418 drm_connector_list_iter_begin(drm_dev, &iter); 1419 drm_for_each_connector_iter(list_connector, &iter) { 1420 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1421 ret = -EBUSY; 1422 break; 1423 } 1424 } 1425 1426 drm_connector_list_iter_end(&iter); 1427 1428 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1429 mutex_unlock(&drm_dev->mode_config.mutex); 1430 } 1431 1432 if (ret == -EBUSY) 1433 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1434 1435 pm_runtime_mark_last_busy(dev); 1436 pm_runtime_autosuspend(dev); 1437 return ret; 1438 } 1439 1440 long amdgpu_drm_ioctl(struct file *filp, 1441 unsigned int cmd, unsigned long arg) 1442 { 1443 struct drm_file *file_priv = filp->private_data; 1444 struct drm_device *dev; 1445 long ret; 1446 dev = file_priv->minor->dev; 1447 ret = pm_runtime_get_sync(dev->dev); 1448 if (ret < 0) 1449 goto out; 1450 1451 ret = drm_ioctl(filp, cmd, arg); 1452 1453 pm_runtime_mark_last_busy(dev->dev); 1454 out: 1455 pm_runtime_put_autosuspend(dev->dev); 1456 return ret; 1457 } 1458 1459 static const struct dev_pm_ops amdgpu_pm_ops = { 1460 .suspend = amdgpu_pmops_suspend, 1461 .resume = amdgpu_pmops_resume, 1462 .freeze = amdgpu_pmops_freeze, 1463 .thaw = amdgpu_pmops_thaw, 1464 .poweroff = amdgpu_pmops_poweroff, 1465 .restore = amdgpu_pmops_restore, 1466 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1467 .runtime_resume = amdgpu_pmops_runtime_resume, 1468 .runtime_idle = amdgpu_pmops_runtime_idle, 1469 }; 1470 1471 static int amdgpu_flush(struct file *f, fl_owner_t id) 1472 { 1473 struct drm_file *file_priv = f->private_data; 1474 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1475 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1476 1477 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1478 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1479 1480 return timeout >= 0 ? 0 : timeout; 1481 } 1482 1483 static const struct file_operations amdgpu_driver_kms_fops = { 1484 .owner = THIS_MODULE, 1485 .open = drm_open, 1486 .flush = amdgpu_flush, 1487 .release = drm_release, 1488 .unlocked_ioctl = amdgpu_drm_ioctl, 1489 .mmap = amdgpu_mmap, 1490 .poll = drm_poll, 1491 .read = drm_read, 1492 #ifdef CONFIG_COMPAT 1493 .compat_ioctl = amdgpu_kms_compat_ioctl, 1494 #endif 1495 }; 1496 1497 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1498 { 1499 struct drm_file *file; 1500 1501 if (!filp) 1502 return -EINVAL; 1503 1504 if (filp->f_op != &amdgpu_driver_kms_fops) { 1505 return -EINVAL; 1506 } 1507 1508 file = filp->private_data; 1509 *fpriv = file->driver_priv; 1510 return 0; 1511 } 1512 1513 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1514 1515 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1516 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1517 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1518 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1519 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1520 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1521 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1522 /* KMS */ 1523 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1524 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1525 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1526 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1527 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1528 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1529 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1530 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1531 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1532 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1533 }; 1534 1535 static const struct drm_driver amdgpu_kms_driver = { 1536 .driver_features = 1537 DRIVER_ATOMIC | 1538 DRIVER_GEM | 1539 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1540 DRIVER_SYNCOBJ_TIMELINE, 1541 .open = amdgpu_driver_open_kms, 1542 .postclose = amdgpu_driver_postclose_kms, 1543 .lastclose = amdgpu_driver_lastclose_kms, 1544 .irq_handler = amdgpu_irq_handler, 1545 .ioctls = amdgpu_ioctls_kms, 1546 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1547 .dumb_create = amdgpu_mode_dumb_create, 1548 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1549 .fops = &amdgpu_driver_kms_fops, 1550 1551 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1552 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1553 .gem_prime_import = amdgpu_gem_prime_import, 1554 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1555 1556 .name = DRIVER_NAME, 1557 .desc = DRIVER_DESC, 1558 .date = DRIVER_DATE, 1559 .major = KMS_DRIVER_MAJOR, 1560 .minor = KMS_DRIVER_MINOR, 1561 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1562 }; 1563 1564 static struct pci_error_handlers amdgpu_pci_err_handler = { 1565 .error_detected = amdgpu_pci_error_detected, 1566 .mmio_enabled = amdgpu_pci_mmio_enabled, 1567 .slot_reset = amdgpu_pci_slot_reset, 1568 .resume = amdgpu_pci_resume, 1569 }; 1570 1571 static struct pci_driver amdgpu_kms_pci_driver = { 1572 .name = DRIVER_NAME, 1573 .id_table = pciidlist, 1574 .probe = amdgpu_pci_probe, 1575 .remove = amdgpu_pci_remove, 1576 .shutdown = amdgpu_pci_shutdown, 1577 .driver.pm = &amdgpu_pm_ops, 1578 .err_handler = &amdgpu_pci_err_handler, 1579 }; 1580 1581 static int __init amdgpu_init(void) 1582 { 1583 int r; 1584 1585 if (vgacon_text_force()) { 1586 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1587 return -EINVAL; 1588 } 1589 1590 r = amdgpu_sync_init(); 1591 if (r) 1592 goto error_sync; 1593 1594 r = amdgpu_fence_slab_init(); 1595 if (r) 1596 goto error_fence; 1597 1598 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1599 amdgpu_register_atpx_handler(); 1600 1601 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1602 amdgpu_amdkfd_init(); 1603 1604 /* let modprobe override vga console setting */ 1605 return pci_register_driver(&amdgpu_kms_pci_driver); 1606 1607 error_fence: 1608 amdgpu_sync_fini(); 1609 1610 error_sync: 1611 return r; 1612 } 1613 1614 static void __exit amdgpu_exit(void) 1615 { 1616 amdgpu_amdkfd_fini(); 1617 pci_unregister_driver(&amdgpu_kms_pci_driver); 1618 amdgpu_unregister_atpx_handler(); 1619 amdgpu_sync_fini(); 1620 amdgpu_fence_slab_fini(); 1621 mmu_notifier_synchronize(); 1622 } 1623 1624 module_init(amdgpu_init); 1625 module_exit(amdgpu_exit); 1626 1627 MODULE_AUTHOR(DRIVER_AUTHOR); 1628 MODULE_DESCRIPTION(DRIVER_DESC); 1629 MODULE_LICENSE("GPL and additional rights"); 1630