1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 105 * - 3.48.0 - Add IP discovery version info to HW INFO 106 * - 3.49.0 - Add gang submit into CS IOCTL 107 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 108 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 109 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 110 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 111 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 112 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 113 * 3.53.0 - Support for GFX11 CP GFX shadowing 114 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 115 */ 116 #define KMS_DRIVER_MAJOR 3 117 #define KMS_DRIVER_MINOR 54 118 #define KMS_DRIVER_PATCHLEVEL 0 119 120 unsigned int amdgpu_vram_limit = UINT_MAX; 121 int amdgpu_vis_vram_limit; 122 int amdgpu_gart_size = -1; /* auto */ 123 int amdgpu_gtt_size = -1; /* auto */ 124 int amdgpu_moverate = -1; /* auto */ 125 int amdgpu_audio = -1; 126 int amdgpu_disp_priority; 127 int amdgpu_hw_i2c; 128 int amdgpu_pcie_gen2 = -1; 129 int amdgpu_msi = -1; 130 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 131 int amdgpu_dpm = -1; 132 int amdgpu_fw_load_type = -1; 133 int amdgpu_aspm = -1; 134 int amdgpu_runtime_pm = -1; 135 uint amdgpu_ip_block_mask = 0xffffffff; 136 int amdgpu_bapm = -1; 137 int amdgpu_deep_color; 138 int amdgpu_vm_size = -1; 139 int amdgpu_vm_fragment_size = -1; 140 int amdgpu_vm_block_size = -1; 141 int amdgpu_vm_fault_stop; 142 int amdgpu_vm_debug; 143 int amdgpu_vm_update_mode = -1; 144 int amdgpu_exp_hw_support; 145 int amdgpu_dc = -1; 146 int amdgpu_sched_jobs = 32; 147 int amdgpu_sched_hw_submission = 2; 148 uint amdgpu_pcie_gen_cap; 149 uint amdgpu_pcie_lane_cap; 150 u64 amdgpu_cg_mask = 0xffffffffffffffff; 151 uint amdgpu_pg_mask = 0xffffffff; 152 uint amdgpu_sdma_phase_quantum = 32; 153 char *amdgpu_disable_cu; 154 char *amdgpu_virtual_display; 155 156 /* 157 * OverDrive(bit 14) disabled by default 158 * GFX DCS(bit 19) disabled by default 159 */ 160 uint amdgpu_pp_feature_mask = 0xfff7bfff; 161 uint amdgpu_force_long_training; 162 int amdgpu_lbpw = -1; 163 int amdgpu_compute_multipipe = -1; 164 int amdgpu_gpu_recovery = -1; /* auto */ 165 int amdgpu_emu_mode; 166 uint amdgpu_smu_memory_pool_size; 167 int amdgpu_smu_pptable_id = -1; 168 /* 169 * FBC (bit 0) disabled by default 170 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 171 * - With this, for multiple monitors in sync(e.g. with the same model), 172 * mclk switching will be allowed. And the mclk will be not foced to the 173 * highest. That helps saving some idle power. 174 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 175 * PSR (bit 3) disabled by default 176 * EDP NO POWER SEQUENCING (bit 4) disabled by default 177 */ 178 uint amdgpu_dc_feature_mask = 2; 179 uint amdgpu_dc_debug_mask; 180 uint amdgpu_dc_visual_confirm; 181 int amdgpu_async_gfx_ring = 1; 182 int amdgpu_mcbp; 183 int amdgpu_discovery = -1; 184 int amdgpu_mes; 185 int amdgpu_mes_kiq; 186 int amdgpu_noretry = -1; 187 int amdgpu_force_asic_type = -1; 188 int amdgpu_tmz = -1; /* auto */ 189 uint amdgpu_freesync_vid_mode; 190 int amdgpu_reset_method = -1; /* auto */ 191 int amdgpu_num_kcq = -1; 192 int amdgpu_smartshift_bias; 193 int amdgpu_use_xgmi_p2p = 1; 194 int amdgpu_vcnfw_log; 195 int amdgpu_sg_display = -1; /* auto */ 196 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 197 198 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 199 200 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 201 "DRM_UT_CORE", 202 "DRM_UT_DRIVER", 203 "DRM_UT_KMS", 204 "DRM_UT_PRIME", 205 "DRM_UT_ATOMIC", 206 "DRM_UT_VBL", 207 "DRM_UT_STATE", 208 "DRM_UT_LEASE", 209 "DRM_UT_DP", 210 "DRM_UT_DRMRES"); 211 212 struct amdgpu_mgpu_info mgpu_info = { 213 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 214 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 215 mgpu_info.delayed_reset_work, 216 amdgpu_drv_delayed_reset_work_handler, 0), 217 }; 218 int amdgpu_ras_enable = -1; 219 uint amdgpu_ras_mask = 0xffffffff; 220 int amdgpu_bad_page_threshold = -1; 221 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 222 .timeout_fatal_disable = false, 223 .period = 0x0, /* default to 0x0 (timeout disable) */ 224 }; 225 226 /** 227 * DOC: vramlimit (int) 228 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 229 */ 230 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 231 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 232 233 /** 234 * DOC: vis_vramlimit (int) 235 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 236 */ 237 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 238 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 239 240 /** 241 * DOC: gartsize (uint) 242 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 243 * The default is -1 (The size depends on asic). 244 */ 245 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 246 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 247 248 /** 249 * DOC: gttsize (int) 250 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 251 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 252 */ 253 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 254 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 255 256 /** 257 * DOC: moverate (int) 258 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 259 */ 260 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 261 module_param_named(moverate, amdgpu_moverate, int, 0600); 262 263 /** 264 * DOC: audio (int) 265 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 266 */ 267 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 268 module_param_named(audio, amdgpu_audio, int, 0444); 269 270 /** 271 * DOC: disp_priority (int) 272 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 273 */ 274 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 275 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 276 277 /** 278 * DOC: hw_i2c (int) 279 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 280 */ 281 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 282 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 283 284 /** 285 * DOC: pcie_gen2 (int) 286 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 287 */ 288 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 289 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 290 291 /** 292 * DOC: msi (int) 293 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 294 */ 295 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 296 module_param_named(msi, amdgpu_msi, int, 0444); 297 298 /** 299 * DOC: lockup_timeout (string) 300 * Set GPU scheduler timeout value in ms. 301 * 302 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 303 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 304 * to the default timeout. 305 * 306 * - With one value specified, the setting will apply to all non-compute jobs. 307 * - With multiple values specified, the first one will be for GFX. 308 * The second one is for Compute. The third and fourth ones are 309 * for SDMA and Video. 310 * 311 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 312 * jobs is 10000. The timeout for compute is 60000. 313 */ 314 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 315 "for passthrough or sriov, 10000 for all jobs." 316 " 0: keep default value. negative: infinity timeout), " 317 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 318 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 319 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 320 321 /** 322 * DOC: dpm (int) 323 * Override for dynamic power management setting 324 * (0 = disable, 1 = enable) 325 * The default is -1 (auto). 326 */ 327 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 328 module_param_named(dpm, amdgpu_dpm, int, 0444); 329 330 /** 331 * DOC: fw_load_type (int) 332 * Set different firmware loading type for debugging, if supported. 333 * Set to 0 to force direct loading if supported by the ASIC. Set 334 * to -1 to select the default loading mode for the ASIC, as defined 335 * by the driver. The default is -1 (auto). 336 */ 337 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 338 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 339 340 /** 341 * DOC: aspm (int) 342 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 343 */ 344 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 345 module_param_named(aspm, amdgpu_aspm, int, 0444); 346 347 /** 348 * DOC: runpm (int) 349 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 350 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 351 * Setting the value to 0 disables this functionality. 352 */ 353 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 354 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 355 356 /** 357 * DOC: ip_block_mask (uint) 358 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 359 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 360 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 361 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 362 */ 363 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 364 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 365 366 /** 367 * DOC: bapm (int) 368 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 369 * The default -1 (auto, enabled) 370 */ 371 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 372 module_param_named(bapm, amdgpu_bapm, int, 0444); 373 374 /** 375 * DOC: deep_color (int) 376 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 377 */ 378 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 379 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 380 381 /** 382 * DOC: vm_size (int) 383 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 384 */ 385 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 386 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 387 388 /** 389 * DOC: vm_fragment_size (int) 390 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 391 */ 392 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 393 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 394 395 /** 396 * DOC: vm_block_size (int) 397 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 398 */ 399 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 400 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 401 402 /** 403 * DOC: vm_fault_stop (int) 404 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 405 */ 406 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 407 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 408 409 /** 410 * DOC: vm_debug (int) 411 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 412 */ 413 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 414 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 415 416 /** 417 * DOC: vm_update_mode (int) 418 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 419 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 420 */ 421 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 422 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 423 424 /** 425 * DOC: exp_hw_support (int) 426 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 427 */ 428 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 429 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 430 431 /** 432 * DOC: dc (int) 433 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 434 */ 435 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 436 module_param_named(dc, amdgpu_dc, int, 0444); 437 438 /** 439 * DOC: sched_jobs (int) 440 * Override the max number of jobs supported in the sw queue. The default is 32. 441 */ 442 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 443 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 444 445 /** 446 * DOC: sched_hw_submission (int) 447 * Override the max number of HW submissions. The default is 2. 448 */ 449 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 450 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 451 452 /** 453 * DOC: ppfeaturemask (hexint) 454 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 455 * The default is the current set of stable power features. 456 */ 457 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 458 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 459 460 /** 461 * DOC: forcelongtraining (uint) 462 * Force long memory training in resume. 463 * The default is zero, indicates short training in resume. 464 */ 465 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 466 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 467 468 /** 469 * DOC: pcie_gen_cap (uint) 470 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 471 * The default is 0 (automatic for each asic). 472 */ 473 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 474 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 475 476 /** 477 * DOC: pcie_lane_cap (uint) 478 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 479 * The default is 0 (automatic for each asic). 480 */ 481 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 482 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 483 484 /** 485 * DOC: cg_mask (ullong) 486 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 487 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 488 */ 489 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 490 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 491 492 /** 493 * DOC: pg_mask (uint) 494 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 495 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 496 */ 497 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 498 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 499 500 /** 501 * DOC: sdma_phase_quantum (uint) 502 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 503 */ 504 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 505 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 506 507 /** 508 * DOC: disable_cu (charp) 509 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 510 */ 511 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 512 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 513 514 /** 515 * DOC: virtual_display (charp) 516 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 517 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 518 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 519 * device at 26:00.0. The default is NULL. 520 */ 521 MODULE_PARM_DESC(virtual_display, 522 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 523 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 524 525 /** 526 * DOC: lbpw (int) 527 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 528 */ 529 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 530 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 531 532 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 533 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 534 535 /** 536 * DOC: gpu_recovery (int) 537 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 538 */ 539 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 540 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 541 542 /** 543 * DOC: emu_mode (int) 544 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 545 */ 546 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 547 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 548 549 /** 550 * DOC: ras_enable (int) 551 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 552 */ 553 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 554 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 555 556 /** 557 * DOC: ras_mask (uint) 558 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 559 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 560 */ 561 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 562 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 563 564 /** 565 * DOC: timeout_fatal_disable (bool) 566 * Disable Watchdog timeout fatal error event 567 */ 568 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 569 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 570 571 /** 572 * DOC: timeout_period (uint) 573 * Modify the watchdog timeout max_cycles as (1 << period) 574 */ 575 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 576 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 577 578 /** 579 * DOC: si_support (int) 580 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 581 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 582 * otherwise using amdgpu driver. 583 */ 584 #ifdef CONFIG_DRM_AMDGPU_SI 585 586 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 587 int amdgpu_si_support = 0; 588 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 589 #else 590 int amdgpu_si_support = 1; 591 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 592 #endif 593 594 module_param_named(si_support, amdgpu_si_support, int, 0444); 595 #endif 596 597 /** 598 * DOC: cik_support (int) 599 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 600 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 601 * otherwise using amdgpu driver. 602 */ 603 #ifdef CONFIG_DRM_AMDGPU_CIK 604 605 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 606 int amdgpu_cik_support = 0; 607 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 608 #else 609 int amdgpu_cik_support = 1; 610 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 611 #endif 612 613 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 614 #endif 615 616 /** 617 * DOC: smu_memory_pool_size (uint) 618 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 619 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 620 */ 621 MODULE_PARM_DESC(smu_memory_pool_size, 622 "reserve gtt for smu debug usage, 0 = disable," 623 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 624 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 625 626 /** 627 * DOC: async_gfx_ring (int) 628 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 629 */ 630 MODULE_PARM_DESC(async_gfx_ring, 631 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 632 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 633 634 /** 635 * DOC: mcbp (int) 636 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 637 */ 638 MODULE_PARM_DESC(mcbp, 639 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 640 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 641 642 /** 643 * DOC: discovery (int) 644 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 645 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 646 */ 647 MODULE_PARM_DESC(discovery, 648 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 649 module_param_named(discovery, amdgpu_discovery, int, 0444); 650 651 /** 652 * DOC: mes (int) 653 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 654 * (0 = disabled (default), 1 = enabled) 655 */ 656 MODULE_PARM_DESC(mes, 657 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 658 module_param_named(mes, amdgpu_mes, int, 0444); 659 660 /** 661 * DOC: mes_kiq (int) 662 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 663 * (0 = disabled (default), 1 = enabled) 664 */ 665 MODULE_PARM_DESC(mes_kiq, 666 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 667 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 668 669 /** 670 * DOC: noretry (int) 671 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 672 * do not support per-process XNACK this also disables retry page faults. 673 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 674 */ 675 MODULE_PARM_DESC(noretry, 676 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 677 module_param_named(noretry, amdgpu_noretry, int, 0644); 678 679 /** 680 * DOC: force_asic_type (int) 681 * A non negative value used to specify the asic type for all supported GPUs. 682 */ 683 MODULE_PARM_DESC(force_asic_type, 684 "A non negative value used to specify the asic type for all supported GPUs"); 685 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 686 687 /** 688 * DOC: use_xgmi_p2p (int) 689 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 690 */ 691 MODULE_PARM_DESC(use_xgmi_p2p, 692 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 693 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 694 695 696 #ifdef CONFIG_HSA_AMD 697 /** 698 * DOC: sched_policy (int) 699 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 700 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 701 * assigns queues to HQDs. 702 */ 703 int sched_policy = KFD_SCHED_POLICY_HWS; 704 module_param(sched_policy, int, 0444); 705 MODULE_PARM_DESC(sched_policy, 706 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 707 708 /** 709 * DOC: hws_max_conc_proc (int) 710 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 711 * number of VMIDs assigned to the HWS, which is also the default. 712 */ 713 int hws_max_conc_proc = -1; 714 module_param(hws_max_conc_proc, int, 0444); 715 MODULE_PARM_DESC(hws_max_conc_proc, 716 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 717 718 /** 719 * DOC: cwsr_enable (int) 720 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 721 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 722 * disables it. 723 */ 724 int cwsr_enable = 1; 725 module_param(cwsr_enable, int, 0444); 726 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 727 728 /** 729 * DOC: max_num_of_queues_per_device (int) 730 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 731 * is 4096. 732 */ 733 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 734 module_param(max_num_of_queues_per_device, int, 0444); 735 MODULE_PARM_DESC(max_num_of_queues_per_device, 736 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 737 738 /** 739 * DOC: send_sigterm (int) 740 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 741 * but just print errors on dmesg. Setting 1 enables sending sigterm. 742 */ 743 int send_sigterm; 744 module_param(send_sigterm, int, 0444); 745 MODULE_PARM_DESC(send_sigterm, 746 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 747 748 /** 749 * DOC: debug_largebar (int) 750 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 751 * system. This limits the VRAM size reported to ROCm applications to the visible 752 * size, usually 256MB. 753 * Default value is 0, diabled. 754 */ 755 int debug_largebar; 756 module_param(debug_largebar, int, 0444); 757 MODULE_PARM_DESC(debug_largebar, 758 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 759 760 /** 761 * DOC: ignore_crat (int) 762 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 763 * table to get information about AMD APUs. This option can serve as a workaround on 764 * systems with a broken CRAT table. 765 * 766 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 767 * whether use CRAT) 768 */ 769 int ignore_crat; 770 module_param(ignore_crat, int, 0444); 771 MODULE_PARM_DESC(ignore_crat, 772 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 773 774 /** 775 * DOC: halt_if_hws_hang (int) 776 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 777 * Setting 1 enables halt on hang. 778 */ 779 int halt_if_hws_hang; 780 module_param(halt_if_hws_hang, int, 0644); 781 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 782 783 /** 784 * DOC: hws_gws_support(bool) 785 * Assume that HWS supports GWS barriers regardless of what firmware version 786 * check says. Default value: false (rely on MEC2 firmware version check). 787 */ 788 bool hws_gws_support; 789 module_param(hws_gws_support, bool, 0444); 790 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 791 792 /** 793 * DOC: queue_preemption_timeout_ms (int) 794 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 795 */ 796 int queue_preemption_timeout_ms = 9000; 797 module_param(queue_preemption_timeout_ms, int, 0644); 798 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 799 800 /** 801 * DOC: debug_evictions(bool) 802 * Enable extra debug messages to help determine the cause of evictions 803 */ 804 bool debug_evictions; 805 module_param(debug_evictions, bool, 0644); 806 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 807 808 /** 809 * DOC: no_system_mem_limit(bool) 810 * Disable system memory limit, to support multiple process shared memory 811 */ 812 bool no_system_mem_limit; 813 module_param(no_system_mem_limit, bool, 0644); 814 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 815 816 /** 817 * DOC: no_queue_eviction_on_vm_fault (int) 818 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 819 */ 820 int amdgpu_no_queue_eviction_on_vm_fault; 821 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 822 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 823 #endif 824 825 /** 826 * DOC: mtype_local (int) 827 */ 828 int amdgpu_mtype_local; 829 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 830 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 831 832 /** 833 * DOC: pcie_p2p (bool) 834 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 835 */ 836 #ifdef CONFIG_HSA_AMD_P2P 837 bool pcie_p2p = true; 838 module_param(pcie_p2p, bool, 0444); 839 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 840 #endif 841 842 /** 843 * DOC: dcfeaturemask (uint) 844 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 845 * The default is the current set of stable display features. 846 */ 847 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 848 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 849 850 /** 851 * DOC: dcdebugmask (uint) 852 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 853 */ 854 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 855 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 856 857 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 858 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 859 860 /** 861 * DOC: abmlevel (uint) 862 * Override the default ABM (Adaptive Backlight Management) level used for DC 863 * enabled hardware. Requires DMCU to be supported and loaded. 864 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 865 * default. Values 1-4 control the maximum allowable brightness reduction via 866 * the ABM algorithm, with 1 being the least reduction and 4 being the most 867 * reduction. 868 * 869 * Defaults to 0, or disabled. Userspace can still override this level later 870 * after boot. 871 */ 872 uint amdgpu_dm_abm_level; 873 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 874 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 875 876 int amdgpu_backlight = -1; 877 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 878 module_param_named(backlight, amdgpu_backlight, bint, 0444); 879 880 /** 881 * DOC: tmz (int) 882 * Trusted Memory Zone (TMZ) is a method to protect data being written 883 * to or read from memory. 884 * 885 * The default value: 0 (off). TODO: change to auto till it is completed. 886 */ 887 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 888 module_param_named(tmz, amdgpu_tmz, int, 0444); 889 890 /** 891 * DOC: freesync_video (uint) 892 * Enable the optimization to adjust front porch timing to achieve seamless 893 * mode change experience when setting a freesync supported mode for which full 894 * modeset is not needed. 895 * 896 * The Display Core will add a set of modes derived from the base FreeSync 897 * video mode into the corresponding connector's mode list based on commonly 898 * used refresh rates and VRR range of the connected display, when users enable 899 * this feature. From the userspace perspective, they can see a seamless mode 900 * change experience when the change between different refresh rates under the 901 * same resolution. Additionally, userspace applications such as Video playback 902 * can read this modeset list and change the refresh rate based on the video 903 * frame rate. Finally, the userspace can also derive an appropriate mode for a 904 * particular refresh rate based on the FreeSync Mode and add it to the 905 * connector's mode list. 906 * 907 * Note: This is an experimental feature. 908 * 909 * The default value: 0 (off). 910 */ 911 MODULE_PARM_DESC( 912 freesync_video, 913 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 914 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 915 916 /** 917 * DOC: reset_method (int) 918 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 919 */ 920 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 921 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 922 923 /** 924 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 925 * threshold value of faulty pages detected by RAS ECC, which may 926 * result in the GPU entering bad status when the number of total 927 * faulty pages by ECC exceeds the threshold value. 928 */ 929 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 930 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 931 932 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 933 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 934 935 /** 936 * DOC: vcnfw_log (int) 937 * Enable vcnfw log output for debugging, the default is disabled. 938 */ 939 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 940 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 941 942 /** 943 * DOC: sg_display (int) 944 * Disable S/G (scatter/gather) display (i.e., display from system memory). 945 * This option is only relevant on APUs. Set this option to 0 to disable 946 * S/G display if you experience flickering or other issues under memory 947 * pressure and report the issue. 948 */ 949 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 950 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 951 952 /** 953 * DOC: smu_pptable_id (int) 954 * Used to override pptable id. id = 0 use VBIOS pptable. 955 * id > 0 use the soft pptable with specicfied id. 956 */ 957 MODULE_PARM_DESC(smu_pptable_id, 958 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 959 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 960 961 /** 962 * DOC: partition_mode (int) 963 * Used to override the default SPX mode. 964 */ 965 MODULE_PARM_DESC( 966 user_partt_mode, 967 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 968 0 = AMDGPU_SPX_PARTITION_MODE, \ 969 1 = AMDGPU_DPX_PARTITION_MODE, \ 970 2 = AMDGPU_TPX_PARTITION_MODE, \ 971 3 = AMDGPU_QPX_PARTITION_MODE, \ 972 4 = AMDGPU_CPX_PARTITION_MODE)"); 973 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 974 975 /* These devices are not supported by amdgpu. 976 * They are supported by the mach64, r128, radeon drivers 977 */ 978 static const u16 amdgpu_unsupported_pciidlist[] = { 979 /* mach64 */ 980 0x4354, 981 0x4358, 982 0x4554, 983 0x4742, 984 0x4744, 985 0x4749, 986 0x474C, 987 0x474D, 988 0x474E, 989 0x474F, 990 0x4750, 991 0x4751, 992 0x4752, 993 0x4753, 994 0x4754, 995 0x4755, 996 0x4756, 997 0x4757, 998 0x4758, 999 0x4759, 1000 0x475A, 1001 0x4C42, 1002 0x4C44, 1003 0x4C47, 1004 0x4C49, 1005 0x4C4D, 1006 0x4C4E, 1007 0x4C50, 1008 0x4C51, 1009 0x4C52, 1010 0x4C53, 1011 0x5654, 1012 0x5655, 1013 0x5656, 1014 /* r128 */ 1015 0x4c45, 1016 0x4c46, 1017 0x4d46, 1018 0x4d4c, 1019 0x5041, 1020 0x5042, 1021 0x5043, 1022 0x5044, 1023 0x5045, 1024 0x5046, 1025 0x5047, 1026 0x5048, 1027 0x5049, 1028 0x504A, 1029 0x504B, 1030 0x504C, 1031 0x504D, 1032 0x504E, 1033 0x504F, 1034 0x5050, 1035 0x5051, 1036 0x5052, 1037 0x5053, 1038 0x5054, 1039 0x5055, 1040 0x5056, 1041 0x5057, 1042 0x5058, 1043 0x5245, 1044 0x5246, 1045 0x5247, 1046 0x524b, 1047 0x524c, 1048 0x534d, 1049 0x5446, 1050 0x544C, 1051 0x5452, 1052 /* radeon */ 1053 0x3150, 1054 0x3151, 1055 0x3152, 1056 0x3154, 1057 0x3155, 1058 0x3E50, 1059 0x3E54, 1060 0x4136, 1061 0x4137, 1062 0x4144, 1063 0x4145, 1064 0x4146, 1065 0x4147, 1066 0x4148, 1067 0x4149, 1068 0x414A, 1069 0x414B, 1070 0x4150, 1071 0x4151, 1072 0x4152, 1073 0x4153, 1074 0x4154, 1075 0x4155, 1076 0x4156, 1077 0x4237, 1078 0x4242, 1079 0x4336, 1080 0x4337, 1081 0x4437, 1082 0x4966, 1083 0x4967, 1084 0x4A48, 1085 0x4A49, 1086 0x4A4A, 1087 0x4A4B, 1088 0x4A4C, 1089 0x4A4D, 1090 0x4A4E, 1091 0x4A4F, 1092 0x4A50, 1093 0x4A54, 1094 0x4B48, 1095 0x4B49, 1096 0x4B4A, 1097 0x4B4B, 1098 0x4B4C, 1099 0x4C57, 1100 0x4C58, 1101 0x4C59, 1102 0x4C5A, 1103 0x4C64, 1104 0x4C66, 1105 0x4C67, 1106 0x4E44, 1107 0x4E45, 1108 0x4E46, 1109 0x4E47, 1110 0x4E48, 1111 0x4E49, 1112 0x4E4A, 1113 0x4E4B, 1114 0x4E50, 1115 0x4E51, 1116 0x4E52, 1117 0x4E53, 1118 0x4E54, 1119 0x4E56, 1120 0x5144, 1121 0x5145, 1122 0x5146, 1123 0x5147, 1124 0x5148, 1125 0x514C, 1126 0x514D, 1127 0x5157, 1128 0x5158, 1129 0x5159, 1130 0x515A, 1131 0x515E, 1132 0x5460, 1133 0x5462, 1134 0x5464, 1135 0x5548, 1136 0x5549, 1137 0x554A, 1138 0x554B, 1139 0x554C, 1140 0x554D, 1141 0x554E, 1142 0x554F, 1143 0x5550, 1144 0x5551, 1145 0x5552, 1146 0x5554, 1147 0x564A, 1148 0x564B, 1149 0x564F, 1150 0x5652, 1151 0x5653, 1152 0x5657, 1153 0x5834, 1154 0x5835, 1155 0x5954, 1156 0x5955, 1157 0x5974, 1158 0x5975, 1159 0x5960, 1160 0x5961, 1161 0x5962, 1162 0x5964, 1163 0x5965, 1164 0x5969, 1165 0x5a41, 1166 0x5a42, 1167 0x5a61, 1168 0x5a62, 1169 0x5b60, 1170 0x5b62, 1171 0x5b63, 1172 0x5b64, 1173 0x5b65, 1174 0x5c61, 1175 0x5c63, 1176 0x5d48, 1177 0x5d49, 1178 0x5d4a, 1179 0x5d4c, 1180 0x5d4d, 1181 0x5d4e, 1182 0x5d4f, 1183 0x5d50, 1184 0x5d52, 1185 0x5d57, 1186 0x5e48, 1187 0x5e4a, 1188 0x5e4b, 1189 0x5e4c, 1190 0x5e4d, 1191 0x5e4f, 1192 0x6700, 1193 0x6701, 1194 0x6702, 1195 0x6703, 1196 0x6704, 1197 0x6705, 1198 0x6706, 1199 0x6707, 1200 0x6708, 1201 0x6709, 1202 0x6718, 1203 0x6719, 1204 0x671c, 1205 0x671d, 1206 0x671f, 1207 0x6720, 1208 0x6721, 1209 0x6722, 1210 0x6723, 1211 0x6724, 1212 0x6725, 1213 0x6726, 1214 0x6727, 1215 0x6728, 1216 0x6729, 1217 0x6738, 1218 0x6739, 1219 0x673e, 1220 0x6740, 1221 0x6741, 1222 0x6742, 1223 0x6743, 1224 0x6744, 1225 0x6745, 1226 0x6746, 1227 0x6747, 1228 0x6748, 1229 0x6749, 1230 0x674A, 1231 0x6750, 1232 0x6751, 1233 0x6758, 1234 0x6759, 1235 0x675B, 1236 0x675D, 1237 0x675F, 1238 0x6760, 1239 0x6761, 1240 0x6762, 1241 0x6763, 1242 0x6764, 1243 0x6765, 1244 0x6766, 1245 0x6767, 1246 0x6768, 1247 0x6770, 1248 0x6771, 1249 0x6772, 1250 0x6778, 1251 0x6779, 1252 0x677B, 1253 0x6840, 1254 0x6841, 1255 0x6842, 1256 0x6843, 1257 0x6849, 1258 0x684C, 1259 0x6850, 1260 0x6858, 1261 0x6859, 1262 0x6880, 1263 0x6888, 1264 0x6889, 1265 0x688A, 1266 0x688C, 1267 0x688D, 1268 0x6898, 1269 0x6899, 1270 0x689b, 1271 0x689c, 1272 0x689d, 1273 0x689e, 1274 0x68a0, 1275 0x68a1, 1276 0x68a8, 1277 0x68a9, 1278 0x68b0, 1279 0x68b8, 1280 0x68b9, 1281 0x68ba, 1282 0x68be, 1283 0x68bf, 1284 0x68c0, 1285 0x68c1, 1286 0x68c7, 1287 0x68c8, 1288 0x68c9, 1289 0x68d8, 1290 0x68d9, 1291 0x68da, 1292 0x68de, 1293 0x68e0, 1294 0x68e1, 1295 0x68e4, 1296 0x68e5, 1297 0x68e8, 1298 0x68e9, 1299 0x68f1, 1300 0x68f2, 1301 0x68f8, 1302 0x68f9, 1303 0x68fa, 1304 0x68fe, 1305 0x7100, 1306 0x7101, 1307 0x7102, 1308 0x7103, 1309 0x7104, 1310 0x7105, 1311 0x7106, 1312 0x7108, 1313 0x7109, 1314 0x710A, 1315 0x710B, 1316 0x710C, 1317 0x710E, 1318 0x710F, 1319 0x7140, 1320 0x7141, 1321 0x7142, 1322 0x7143, 1323 0x7144, 1324 0x7145, 1325 0x7146, 1326 0x7147, 1327 0x7149, 1328 0x714A, 1329 0x714B, 1330 0x714C, 1331 0x714D, 1332 0x714E, 1333 0x714F, 1334 0x7151, 1335 0x7152, 1336 0x7153, 1337 0x715E, 1338 0x715F, 1339 0x7180, 1340 0x7181, 1341 0x7183, 1342 0x7186, 1343 0x7187, 1344 0x7188, 1345 0x718A, 1346 0x718B, 1347 0x718C, 1348 0x718D, 1349 0x718F, 1350 0x7193, 1351 0x7196, 1352 0x719B, 1353 0x719F, 1354 0x71C0, 1355 0x71C1, 1356 0x71C2, 1357 0x71C3, 1358 0x71C4, 1359 0x71C5, 1360 0x71C6, 1361 0x71C7, 1362 0x71CD, 1363 0x71CE, 1364 0x71D2, 1365 0x71D4, 1366 0x71D5, 1367 0x71D6, 1368 0x71DA, 1369 0x71DE, 1370 0x7200, 1371 0x7210, 1372 0x7211, 1373 0x7240, 1374 0x7243, 1375 0x7244, 1376 0x7245, 1377 0x7246, 1378 0x7247, 1379 0x7248, 1380 0x7249, 1381 0x724A, 1382 0x724B, 1383 0x724C, 1384 0x724D, 1385 0x724E, 1386 0x724F, 1387 0x7280, 1388 0x7281, 1389 0x7283, 1390 0x7284, 1391 0x7287, 1392 0x7288, 1393 0x7289, 1394 0x728B, 1395 0x728C, 1396 0x7290, 1397 0x7291, 1398 0x7293, 1399 0x7297, 1400 0x7834, 1401 0x7835, 1402 0x791e, 1403 0x791f, 1404 0x793f, 1405 0x7941, 1406 0x7942, 1407 0x796c, 1408 0x796d, 1409 0x796e, 1410 0x796f, 1411 0x9400, 1412 0x9401, 1413 0x9402, 1414 0x9403, 1415 0x9405, 1416 0x940A, 1417 0x940B, 1418 0x940F, 1419 0x94A0, 1420 0x94A1, 1421 0x94A3, 1422 0x94B1, 1423 0x94B3, 1424 0x94B4, 1425 0x94B5, 1426 0x94B9, 1427 0x9440, 1428 0x9441, 1429 0x9442, 1430 0x9443, 1431 0x9444, 1432 0x9446, 1433 0x944A, 1434 0x944B, 1435 0x944C, 1436 0x944E, 1437 0x9450, 1438 0x9452, 1439 0x9456, 1440 0x945A, 1441 0x945B, 1442 0x945E, 1443 0x9460, 1444 0x9462, 1445 0x946A, 1446 0x946B, 1447 0x947A, 1448 0x947B, 1449 0x9480, 1450 0x9487, 1451 0x9488, 1452 0x9489, 1453 0x948A, 1454 0x948F, 1455 0x9490, 1456 0x9491, 1457 0x9495, 1458 0x9498, 1459 0x949C, 1460 0x949E, 1461 0x949F, 1462 0x94C0, 1463 0x94C1, 1464 0x94C3, 1465 0x94C4, 1466 0x94C5, 1467 0x94C6, 1468 0x94C7, 1469 0x94C8, 1470 0x94C9, 1471 0x94CB, 1472 0x94CC, 1473 0x94CD, 1474 0x9500, 1475 0x9501, 1476 0x9504, 1477 0x9505, 1478 0x9506, 1479 0x9507, 1480 0x9508, 1481 0x9509, 1482 0x950F, 1483 0x9511, 1484 0x9515, 1485 0x9517, 1486 0x9519, 1487 0x9540, 1488 0x9541, 1489 0x9542, 1490 0x954E, 1491 0x954F, 1492 0x9552, 1493 0x9553, 1494 0x9555, 1495 0x9557, 1496 0x955f, 1497 0x9580, 1498 0x9581, 1499 0x9583, 1500 0x9586, 1501 0x9587, 1502 0x9588, 1503 0x9589, 1504 0x958A, 1505 0x958B, 1506 0x958C, 1507 0x958D, 1508 0x958E, 1509 0x958F, 1510 0x9590, 1511 0x9591, 1512 0x9593, 1513 0x9595, 1514 0x9596, 1515 0x9597, 1516 0x9598, 1517 0x9599, 1518 0x959B, 1519 0x95C0, 1520 0x95C2, 1521 0x95C4, 1522 0x95C5, 1523 0x95C6, 1524 0x95C7, 1525 0x95C9, 1526 0x95CC, 1527 0x95CD, 1528 0x95CE, 1529 0x95CF, 1530 0x9610, 1531 0x9611, 1532 0x9612, 1533 0x9613, 1534 0x9614, 1535 0x9615, 1536 0x9616, 1537 0x9640, 1538 0x9641, 1539 0x9642, 1540 0x9643, 1541 0x9644, 1542 0x9645, 1543 0x9647, 1544 0x9648, 1545 0x9649, 1546 0x964a, 1547 0x964b, 1548 0x964c, 1549 0x964e, 1550 0x964f, 1551 0x9710, 1552 0x9711, 1553 0x9712, 1554 0x9713, 1555 0x9714, 1556 0x9715, 1557 0x9802, 1558 0x9803, 1559 0x9804, 1560 0x9805, 1561 0x9806, 1562 0x9807, 1563 0x9808, 1564 0x9809, 1565 0x980A, 1566 0x9900, 1567 0x9901, 1568 0x9903, 1569 0x9904, 1570 0x9905, 1571 0x9906, 1572 0x9907, 1573 0x9908, 1574 0x9909, 1575 0x990A, 1576 0x990B, 1577 0x990C, 1578 0x990D, 1579 0x990E, 1580 0x990F, 1581 0x9910, 1582 0x9913, 1583 0x9917, 1584 0x9918, 1585 0x9919, 1586 0x9990, 1587 0x9991, 1588 0x9992, 1589 0x9993, 1590 0x9994, 1591 0x9995, 1592 0x9996, 1593 0x9997, 1594 0x9998, 1595 0x9999, 1596 0x999A, 1597 0x999B, 1598 0x999C, 1599 0x999D, 1600 0x99A0, 1601 0x99A2, 1602 0x99A4, 1603 /* radeon secondary ids */ 1604 0x3171, 1605 0x3e70, 1606 0x4164, 1607 0x4165, 1608 0x4166, 1609 0x4168, 1610 0x4170, 1611 0x4171, 1612 0x4172, 1613 0x4173, 1614 0x496e, 1615 0x4a69, 1616 0x4a6a, 1617 0x4a6b, 1618 0x4a70, 1619 0x4a74, 1620 0x4b69, 1621 0x4b6b, 1622 0x4b6c, 1623 0x4c6e, 1624 0x4e64, 1625 0x4e65, 1626 0x4e66, 1627 0x4e67, 1628 0x4e68, 1629 0x4e69, 1630 0x4e6a, 1631 0x4e71, 1632 0x4f73, 1633 0x5569, 1634 0x556b, 1635 0x556d, 1636 0x556f, 1637 0x5571, 1638 0x5854, 1639 0x5874, 1640 0x5940, 1641 0x5941, 1642 0x5b72, 1643 0x5b73, 1644 0x5b74, 1645 0x5b75, 1646 0x5d44, 1647 0x5d45, 1648 0x5d6d, 1649 0x5d6f, 1650 0x5d72, 1651 0x5d77, 1652 0x5e6b, 1653 0x5e6d, 1654 0x7120, 1655 0x7124, 1656 0x7129, 1657 0x712e, 1658 0x712f, 1659 0x7162, 1660 0x7163, 1661 0x7166, 1662 0x7167, 1663 0x7172, 1664 0x7173, 1665 0x71a0, 1666 0x71a1, 1667 0x71a3, 1668 0x71a7, 1669 0x71bb, 1670 0x71e0, 1671 0x71e1, 1672 0x71e2, 1673 0x71e6, 1674 0x71e7, 1675 0x71f2, 1676 0x7269, 1677 0x726b, 1678 0x726e, 1679 0x72a0, 1680 0x72a8, 1681 0x72b1, 1682 0x72b3, 1683 0x793f, 1684 }; 1685 1686 static const struct pci_device_id pciidlist[] = { 1687 #ifdef CONFIG_DRM_AMDGPU_SI 1688 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1689 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1690 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1691 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1692 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1693 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1694 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1695 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1696 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1697 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1698 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1699 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1700 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1701 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1705 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1706 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1707 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1708 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1709 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1710 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1711 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1712 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1713 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1717 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1718 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1719 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1720 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1722 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1723 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1724 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1725 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1729 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1730 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1731 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1732 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1737 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1738 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1739 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1740 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1741 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1742 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1743 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1744 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1745 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1746 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1747 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1748 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1749 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1750 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1751 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1752 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1753 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1754 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1755 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1757 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1758 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1759 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1760 #endif 1761 #ifdef CONFIG_DRM_AMDGPU_CIK 1762 /* Kaveri */ 1763 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1764 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1765 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1766 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1767 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1768 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1769 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1770 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1772 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1774 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1775 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1776 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1777 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1778 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1779 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1780 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1783 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1784 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1785 /* Bonaire */ 1786 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1787 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1788 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1789 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1790 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1791 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1792 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1793 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1794 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1795 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1796 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1797 /* Hawaii */ 1798 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1799 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1800 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1801 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1802 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1803 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1804 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1805 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1806 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1807 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1808 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1809 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1810 /* Kabini */ 1811 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1813 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1814 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1815 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1816 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1817 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1818 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1819 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1822 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1823 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1824 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1825 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1826 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1827 /* mullins */ 1828 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1829 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1831 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1832 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1833 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1834 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1835 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1836 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1837 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1838 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1839 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1840 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1841 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1842 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1843 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1844 #endif 1845 /* topaz */ 1846 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1847 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1848 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1849 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1850 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1851 /* tonga */ 1852 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1853 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1854 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1855 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1856 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1857 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1858 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1859 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1860 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1861 /* fiji */ 1862 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1863 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1864 /* carrizo */ 1865 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1866 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1867 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1868 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1869 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1870 /* stoney */ 1871 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1872 /* Polaris11 */ 1873 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1874 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1875 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1876 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1877 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1878 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1879 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1880 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1881 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1882 /* Polaris10 */ 1883 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1884 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1885 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1886 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1887 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1888 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1889 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1890 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1891 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1892 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1893 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1894 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1895 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1896 /* Polaris12 */ 1897 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1898 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1899 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1900 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1901 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1902 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1903 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1904 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1905 /* VEGAM */ 1906 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1907 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1908 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1909 /* Vega 10 */ 1910 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1911 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1912 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1913 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1914 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1915 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1916 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1917 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1918 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1919 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1920 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1921 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1922 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1923 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1924 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1925 /* Vega 12 */ 1926 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1927 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1928 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1929 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1930 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1931 /* Vega 20 */ 1932 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1933 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1934 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1935 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1936 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1937 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1938 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1939 /* Raven */ 1940 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1941 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1942 /* Arcturus */ 1943 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1944 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1945 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1946 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1947 /* Navi10 */ 1948 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1949 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1950 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1951 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1952 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1953 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1954 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1955 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1956 /* Navi14 */ 1957 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1958 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1959 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1960 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1961 1962 /* Renoir */ 1963 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1964 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1965 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1966 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1967 1968 /* Navi12 */ 1969 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1970 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1971 1972 /* Sienna_Cichlid */ 1973 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1974 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1975 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1976 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1977 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1978 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1979 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1980 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1981 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1982 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1983 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1984 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1985 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1986 1987 /* Yellow Carp */ 1988 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1989 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1990 1991 /* Navy_Flounder */ 1992 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1993 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1994 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1995 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1996 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1997 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1998 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1999 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2000 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2001 2002 /* DIMGREY_CAVEFISH */ 2003 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2004 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2005 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2006 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2007 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2008 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2009 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2010 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2011 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2012 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2013 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2014 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2015 2016 /* Aldebaran */ 2017 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2018 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2019 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2020 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2021 2022 /* CYAN_SKILLFISH */ 2023 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2024 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2025 2026 /* BEIGE_GOBY */ 2027 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2028 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2029 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2030 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2031 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2032 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2033 2034 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2035 .class = PCI_CLASS_DISPLAY_VGA << 8, 2036 .class_mask = 0xffffff, 2037 .driver_data = CHIP_IP_DISCOVERY }, 2038 2039 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2040 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2041 .class_mask = 0xffffff, 2042 .driver_data = CHIP_IP_DISCOVERY }, 2043 2044 {0, 0, 0} 2045 }; 2046 2047 MODULE_DEVICE_TABLE(pci, pciidlist); 2048 2049 static const struct drm_driver amdgpu_kms_driver; 2050 2051 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2052 { 2053 struct pci_dev *p = NULL; 2054 int i; 2055 2056 /* 0 - GPU 2057 * 1 - audio 2058 * 2 - USB 2059 * 3 - UCSI 2060 */ 2061 for (i = 1; i < 4; i++) { 2062 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2063 adev->pdev->bus->number, i); 2064 if (p) { 2065 pm_runtime_get_sync(&p->dev); 2066 pm_runtime_mark_last_busy(&p->dev); 2067 pm_runtime_put_autosuspend(&p->dev); 2068 pci_dev_put(p); 2069 } 2070 } 2071 } 2072 2073 static int amdgpu_pci_probe(struct pci_dev *pdev, 2074 const struct pci_device_id *ent) 2075 { 2076 struct drm_device *ddev; 2077 struct amdgpu_device *adev; 2078 unsigned long flags = ent->driver_data; 2079 int ret, retry = 0, i; 2080 bool supports_atomic = false; 2081 2082 /* skip devices which are owned by radeon */ 2083 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2084 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2085 return -ENODEV; 2086 } 2087 2088 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2089 amdgpu_aspm = 0; 2090 2091 if (amdgpu_virtual_display || 2092 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2093 supports_atomic = true; 2094 2095 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2096 DRM_INFO("This hardware requires experimental hardware support.\n" 2097 "See modparam exp_hw_support\n"); 2098 return -ENODEV; 2099 } 2100 /* differentiate between P10 and P11 asics with the same DID */ 2101 if (pdev->device == 0x67FF && 2102 (pdev->revision == 0xE3 || 2103 pdev->revision == 0xE7 || 2104 pdev->revision == 0xF3 || 2105 pdev->revision == 0xF7)) { 2106 flags &= ~AMD_ASIC_MASK; 2107 flags |= CHIP_POLARIS10; 2108 } 2109 2110 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2111 * however, SME requires an indirect IOMMU mapping because the encryption 2112 * bit is beyond the DMA mask of the chip. 2113 */ 2114 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2115 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2116 dev_info(&pdev->dev, 2117 "SME is not compatible with RAVEN\n"); 2118 return -ENOTSUPP; 2119 } 2120 2121 #ifdef CONFIG_DRM_AMDGPU_SI 2122 if (!amdgpu_si_support) { 2123 switch (flags & AMD_ASIC_MASK) { 2124 case CHIP_TAHITI: 2125 case CHIP_PITCAIRN: 2126 case CHIP_VERDE: 2127 case CHIP_OLAND: 2128 case CHIP_HAINAN: 2129 dev_info(&pdev->dev, 2130 "SI support provided by radeon.\n"); 2131 dev_info(&pdev->dev, 2132 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2133 ); 2134 return -ENODEV; 2135 } 2136 } 2137 #endif 2138 #ifdef CONFIG_DRM_AMDGPU_CIK 2139 if (!amdgpu_cik_support) { 2140 switch (flags & AMD_ASIC_MASK) { 2141 case CHIP_KAVERI: 2142 case CHIP_BONAIRE: 2143 case CHIP_HAWAII: 2144 case CHIP_KABINI: 2145 case CHIP_MULLINS: 2146 dev_info(&pdev->dev, 2147 "CIK support provided by radeon.\n"); 2148 dev_info(&pdev->dev, 2149 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2150 ); 2151 return -ENODEV; 2152 } 2153 } 2154 #endif 2155 2156 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2157 if (IS_ERR(adev)) 2158 return PTR_ERR(adev); 2159 2160 adev->dev = &pdev->dev; 2161 adev->pdev = pdev; 2162 ddev = adev_to_drm(adev); 2163 2164 if (!supports_atomic) 2165 ddev->driver_features &= ~DRIVER_ATOMIC; 2166 2167 ret = pci_enable_device(pdev); 2168 if (ret) 2169 return ret; 2170 2171 pci_set_drvdata(pdev, ddev); 2172 2173 ret = amdgpu_driver_load_kms(adev, flags); 2174 if (ret) 2175 goto err_pci; 2176 2177 retry_init: 2178 ret = drm_dev_register(ddev, flags); 2179 if (ret == -EAGAIN && ++retry <= 3) { 2180 DRM_INFO("retry init %d\n", retry); 2181 /* Don't request EX mode too frequently which is attacking */ 2182 msleep(5000); 2183 goto retry_init; 2184 } else if (ret) { 2185 goto err_pci; 2186 } 2187 2188 ret = amdgpu_xcp_dev_register(adev, ent); 2189 if (ret) 2190 goto err_pci; 2191 2192 /* 2193 * 1. don't init fbdev on hw without DCE 2194 * 2. don't init fbdev if there are no connectors 2195 */ 2196 if (adev->mode_info.mode_config_initialized && 2197 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2198 /* select 8 bpp console on low vram cards */ 2199 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2200 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2201 else 2202 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2203 } 2204 2205 ret = amdgpu_debugfs_init(adev); 2206 if (ret) 2207 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2208 2209 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2210 /* only need to skip on ATPX */ 2211 if (amdgpu_device_supports_px(ddev)) 2212 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2213 /* we want direct complete for BOCO */ 2214 if (amdgpu_device_supports_boco(ddev)) 2215 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2216 DPM_FLAG_SMART_SUSPEND | 2217 DPM_FLAG_MAY_SKIP_RESUME); 2218 pm_runtime_use_autosuspend(ddev->dev); 2219 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2220 2221 pm_runtime_allow(ddev->dev); 2222 2223 pm_runtime_mark_last_busy(ddev->dev); 2224 pm_runtime_put_autosuspend(ddev->dev); 2225 2226 /* 2227 * For runpm implemented via BACO, PMFW will handle the 2228 * timing for BACO in and out: 2229 * - put ASIC into BACO state only when both video and 2230 * audio functions are in D3 state. 2231 * - pull ASIC out of BACO state when either video or 2232 * audio function is in D0 state. 2233 * Also, at startup, PMFW assumes both functions are in 2234 * D0 state. 2235 * 2236 * So if snd driver was loaded prior to amdgpu driver 2237 * and audio function was put into D3 state, there will 2238 * be no PMFW-aware D-state transition(D0->D3) on runpm 2239 * suspend. Thus the BACO will be not correctly kicked in. 2240 * 2241 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2242 * into D0 state. Then there will be a PMFW-aware D-state 2243 * transition(D0->D3) on runpm suspend. 2244 */ 2245 if (amdgpu_device_supports_baco(ddev) && 2246 !(adev->flags & AMD_IS_APU) && 2247 (adev->asic_type >= CHIP_NAVI10)) 2248 amdgpu_get_secondary_funcs(adev); 2249 } 2250 2251 return 0; 2252 2253 err_pci: 2254 pci_disable_device(pdev); 2255 return ret; 2256 } 2257 2258 static void 2259 amdgpu_pci_remove(struct pci_dev *pdev) 2260 { 2261 struct drm_device *dev = pci_get_drvdata(pdev); 2262 struct amdgpu_device *adev = drm_to_adev(dev); 2263 2264 amdgpu_xcp_dev_unplug(adev); 2265 drm_dev_unplug(dev); 2266 2267 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2268 pm_runtime_get_sync(dev->dev); 2269 pm_runtime_forbid(dev->dev); 2270 } 2271 2272 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2273 !amdgpu_sriov_vf(adev)) { 2274 bool need_to_reset_gpu = false; 2275 2276 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2277 struct amdgpu_hive_info *hive; 2278 2279 hive = amdgpu_get_xgmi_hive(adev); 2280 if (hive->device_remove_count == 0) 2281 need_to_reset_gpu = true; 2282 hive->device_remove_count++; 2283 amdgpu_put_xgmi_hive(hive); 2284 } else { 2285 need_to_reset_gpu = true; 2286 } 2287 2288 /* Workaround for ASICs need to reset SMU. 2289 * Called only when the first device is removed. 2290 */ 2291 if (need_to_reset_gpu) { 2292 struct amdgpu_reset_context reset_context; 2293 2294 adev->shutdown = true; 2295 memset(&reset_context, 0, sizeof(reset_context)); 2296 reset_context.method = AMD_RESET_METHOD_NONE; 2297 reset_context.reset_req_dev = adev; 2298 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2299 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2300 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2301 } 2302 } 2303 2304 amdgpu_driver_unload_kms(dev); 2305 2306 /* 2307 * Flush any in flight DMA operations from device. 2308 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2309 * StatusTransactions Pending bit. 2310 */ 2311 pci_disable_device(pdev); 2312 pci_wait_for_pending_transaction(pdev); 2313 } 2314 2315 static void 2316 amdgpu_pci_shutdown(struct pci_dev *pdev) 2317 { 2318 struct drm_device *dev = pci_get_drvdata(pdev); 2319 struct amdgpu_device *adev = drm_to_adev(dev); 2320 2321 if (amdgpu_ras_intr_triggered()) 2322 return; 2323 2324 /* if we are running in a VM, make sure the device 2325 * torn down properly on reboot/shutdown. 2326 * unfortunately we can't detect certain 2327 * hypervisors so just do this all the time. 2328 */ 2329 if (!amdgpu_passthrough(adev)) 2330 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2331 amdgpu_device_ip_suspend(adev); 2332 adev->mp1_state = PP_MP1_STATE_NONE; 2333 } 2334 2335 /** 2336 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2337 * 2338 * @work: work_struct. 2339 */ 2340 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2341 { 2342 struct list_head device_list; 2343 struct amdgpu_device *adev; 2344 int i, r; 2345 struct amdgpu_reset_context reset_context; 2346 2347 memset(&reset_context, 0, sizeof(reset_context)); 2348 2349 mutex_lock(&mgpu_info.mutex); 2350 if (mgpu_info.pending_reset == true) { 2351 mutex_unlock(&mgpu_info.mutex); 2352 return; 2353 } 2354 mgpu_info.pending_reset = true; 2355 mutex_unlock(&mgpu_info.mutex); 2356 2357 /* Use a common context, just need to make sure full reset is done */ 2358 reset_context.method = AMD_RESET_METHOD_NONE; 2359 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2360 2361 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2362 adev = mgpu_info.gpu_ins[i].adev; 2363 reset_context.reset_req_dev = adev; 2364 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2365 if (r) { 2366 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2367 r, adev_to_drm(adev)->unique); 2368 } 2369 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2370 r = -EALREADY; 2371 } 2372 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2373 adev = mgpu_info.gpu_ins[i].adev; 2374 flush_work(&adev->xgmi_reset_work); 2375 adev->gmc.xgmi.pending_reset = false; 2376 } 2377 2378 /* reset function will rebuild the xgmi hive info , clear it now */ 2379 for (i = 0; i < mgpu_info.num_dgpu; i++) 2380 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2381 2382 INIT_LIST_HEAD(&device_list); 2383 2384 for (i = 0; i < mgpu_info.num_dgpu; i++) 2385 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2386 2387 /* unregister the GPU first, reset function will add them back */ 2388 list_for_each_entry(adev, &device_list, reset_list) 2389 amdgpu_unregister_gpu_instance(adev); 2390 2391 /* Use a common context, just need to make sure full reset is done */ 2392 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2393 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2394 2395 if (r) { 2396 DRM_ERROR("reinit gpus failure"); 2397 return; 2398 } 2399 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2400 adev = mgpu_info.gpu_ins[i].adev; 2401 if (!adev->kfd.init_complete) 2402 amdgpu_amdkfd_device_init(adev); 2403 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2404 } 2405 return; 2406 } 2407 2408 static int amdgpu_pmops_prepare(struct device *dev) 2409 { 2410 struct drm_device *drm_dev = dev_get_drvdata(dev); 2411 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2412 2413 /* Return a positive number here so 2414 * DPM_FLAG_SMART_SUSPEND works properly 2415 */ 2416 if (amdgpu_device_supports_boco(drm_dev)) 2417 return pm_runtime_suspended(dev); 2418 2419 /* if we will not support s3 or s2i for the device 2420 * then skip suspend 2421 */ 2422 if (!amdgpu_acpi_is_s0ix_active(adev) && 2423 !amdgpu_acpi_is_s3_active(adev)) 2424 return 1; 2425 2426 return 0; 2427 } 2428 2429 static void amdgpu_pmops_complete(struct device *dev) 2430 { 2431 /* nothing to do */ 2432 } 2433 2434 static int amdgpu_pmops_suspend(struct device *dev) 2435 { 2436 struct drm_device *drm_dev = dev_get_drvdata(dev); 2437 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2438 2439 if (amdgpu_acpi_is_s0ix_active(adev)) 2440 adev->in_s0ix = true; 2441 else if (amdgpu_acpi_is_s3_active(adev)) 2442 adev->in_s3 = true; 2443 if (!adev->in_s0ix && !adev->in_s3) 2444 return 0; 2445 return amdgpu_device_suspend(drm_dev, true); 2446 } 2447 2448 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2449 { 2450 struct drm_device *drm_dev = dev_get_drvdata(dev); 2451 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2452 2453 if (amdgpu_acpi_should_gpu_reset(adev)) 2454 return amdgpu_asic_reset(adev); 2455 2456 return 0; 2457 } 2458 2459 static int amdgpu_pmops_resume(struct device *dev) 2460 { 2461 struct drm_device *drm_dev = dev_get_drvdata(dev); 2462 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2463 int r; 2464 2465 if (!adev->in_s0ix && !adev->in_s3) 2466 return 0; 2467 2468 /* Avoids registers access if device is physically gone */ 2469 if (!pci_device_is_present(adev->pdev)) 2470 adev->no_hw_access = true; 2471 2472 r = amdgpu_device_resume(drm_dev, true); 2473 if (amdgpu_acpi_is_s0ix_active(adev)) 2474 adev->in_s0ix = false; 2475 else 2476 adev->in_s3 = false; 2477 return r; 2478 } 2479 2480 static int amdgpu_pmops_freeze(struct device *dev) 2481 { 2482 struct drm_device *drm_dev = dev_get_drvdata(dev); 2483 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2484 int r; 2485 2486 adev->in_s4 = true; 2487 r = amdgpu_device_suspend(drm_dev, true); 2488 adev->in_s4 = false; 2489 if (r) 2490 return r; 2491 2492 if (amdgpu_acpi_should_gpu_reset(adev)) 2493 return amdgpu_asic_reset(adev); 2494 return 0; 2495 } 2496 2497 static int amdgpu_pmops_thaw(struct device *dev) 2498 { 2499 struct drm_device *drm_dev = dev_get_drvdata(dev); 2500 2501 return amdgpu_device_resume(drm_dev, true); 2502 } 2503 2504 static int amdgpu_pmops_poweroff(struct device *dev) 2505 { 2506 struct drm_device *drm_dev = dev_get_drvdata(dev); 2507 2508 return amdgpu_device_suspend(drm_dev, true); 2509 } 2510 2511 static int amdgpu_pmops_restore(struct device *dev) 2512 { 2513 struct drm_device *drm_dev = dev_get_drvdata(dev); 2514 2515 return amdgpu_device_resume(drm_dev, true); 2516 } 2517 2518 static int amdgpu_runtime_idle_check_display(struct device *dev) 2519 { 2520 struct pci_dev *pdev = to_pci_dev(dev); 2521 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2522 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2523 2524 if (adev->mode_info.num_crtc) { 2525 struct drm_connector *list_connector; 2526 struct drm_connector_list_iter iter; 2527 int ret = 0; 2528 2529 /* XXX: Return busy if any displays are connected to avoid 2530 * possible display wakeups after runtime resume due to 2531 * hotplug events in case any displays were connected while 2532 * the GPU was in suspend. Remove this once that is fixed. 2533 */ 2534 mutex_lock(&drm_dev->mode_config.mutex); 2535 drm_connector_list_iter_begin(drm_dev, &iter); 2536 drm_for_each_connector_iter(list_connector, &iter) { 2537 if (list_connector->status == connector_status_connected) { 2538 ret = -EBUSY; 2539 break; 2540 } 2541 } 2542 drm_connector_list_iter_end(&iter); 2543 mutex_unlock(&drm_dev->mode_config.mutex); 2544 2545 if (ret) 2546 return ret; 2547 2548 if (adev->dc_enabled) { 2549 struct drm_crtc *crtc; 2550 2551 drm_for_each_crtc(crtc, drm_dev) { 2552 drm_modeset_lock(&crtc->mutex, NULL); 2553 if (crtc->state->active) 2554 ret = -EBUSY; 2555 drm_modeset_unlock(&crtc->mutex); 2556 if (ret < 0) 2557 break; 2558 } 2559 } else { 2560 mutex_lock(&drm_dev->mode_config.mutex); 2561 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2562 2563 drm_connector_list_iter_begin(drm_dev, &iter); 2564 drm_for_each_connector_iter(list_connector, &iter) { 2565 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2566 ret = -EBUSY; 2567 break; 2568 } 2569 } 2570 2571 drm_connector_list_iter_end(&iter); 2572 2573 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2574 mutex_unlock(&drm_dev->mode_config.mutex); 2575 } 2576 if (ret) 2577 return ret; 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2584 { 2585 struct pci_dev *pdev = to_pci_dev(dev); 2586 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2587 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2588 int ret, i; 2589 2590 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2591 pm_runtime_forbid(dev); 2592 return -EBUSY; 2593 } 2594 2595 ret = amdgpu_runtime_idle_check_display(dev); 2596 if (ret) 2597 return ret; 2598 2599 /* wait for all rings to drain before suspending */ 2600 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2601 struct amdgpu_ring *ring = adev->rings[i]; 2602 if (ring && ring->sched.ready) { 2603 ret = amdgpu_fence_wait_empty(ring); 2604 if (ret) 2605 return -EBUSY; 2606 } 2607 } 2608 2609 adev->in_runpm = true; 2610 if (amdgpu_device_supports_px(drm_dev)) 2611 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2612 2613 /* 2614 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2615 * proper cleanups and put itself into a state ready for PNP. That 2616 * can address some random resuming failure observed on BOCO capable 2617 * platforms. 2618 * TODO: this may be also needed for PX capable platform. 2619 */ 2620 if (amdgpu_device_supports_boco(drm_dev)) 2621 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2622 2623 ret = amdgpu_device_suspend(drm_dev, false); 2624 if (ret) { 2625 adev->in_runpm = false; 2626 if (amdgpu_device_supports_boco(drm_dev)) 2627 adev->mp1_state = PP_MP1_STATE_NONE; 2628 return ret; 2629 } 2630 2631 if (amdgpu_device_supports_boco(drm_dev)) 2632 adev->mp1_state = PP_MP1_STATE_NONE; 2633 2634 if (amdgpu_device_supports_px(drm_dev)) { 2635 /* Only need to handle PCI state in the driver for ATPX 2636 * PCI core handles it for _PR3. 2637 */ 2638 amdgpu_device_cache_pci_state(pdev); 2639 pci_disable_device(pdev); 2640 pci_ignore_hotplug(pdev); 2641 pci_set_power_state(pdev, PCI_D3cold); 2642 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2643 } else if (amdgpu_device_supports_boco(drm_dev)) { 2644 /* nothing to do */ 2645 } else if (amdgpu_device_supports_baco(drm_dev)) { 2646 amdgpu_device_baco_enter(drm_dev); 2647 } 2648 2649 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2650 2651 return 0; 2652 } 2653 2654 static int amdgpu_pmops_runtime_resume(struct device *dev) 2655 { 2656 struct pci_dev *pdev = to_pci_dev(dev); 2657 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2658 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2659 int ret; 2660 2661 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2662 return -EINVAL; 2663 2664 /* Avoids registers access if device is physically gone */ 2665 if (!pci_device_is_present(adev->pdev)) 2666 adev->no_hw_access = true; 2667 2668 if (amdgpu_device_supports_px(drm_dev)) { 2669 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2670 2671 /* Only need to handle PCI state in the driver for ATPX 2672 * PCI core handles it for _PR3. 2673 */ 2674 pci_set_power_state(pdev, PCI_D0); 2675 amdgpu_device_load_pci_state(pdev); 2676 ret = pci_enable_device(pdev); 2677 if (ret) 2678 return ret; 2679 pci_set_master(pdev); 2680 } else if (amdgpu_device_supports_boco(drm_dev)) { 2681 /* Only need to handle PCI state in the driver for ATPX 2682 * PCI core handles it for _PR3. 2683 */ 2684 pci_set_master(pdev); 2685 } else if (amdgpu_device_supports_baco(drm_dev)) { 2686 amdgpu_device_baco_exit(drm_dev); 2687 } 2688 ret = amdgpu_device_resume(drm_dev, false); 2689 if (ret) { 2690 if (amdgpu_device_supports_px(drm_dev)) 2691 pci_disable_device(pdev); 2692 return ret; 2693 } 2694 2695 if (amdgpu_device_supports_px(drm_dev)) 2696 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2697 adev->in_runpm = false; 2698 return 0; 2699 } 2700 2701 static int amdgpu_pmops_runtime_idle(struct device *dev) 2702 { 2703 struct drm_device *drm_dev = dev_get_drvdata(dev); 2704 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2705 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2706 int ret = 1; 2707 2708 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2709 pm_runtime_forbid(dev); 2710 return -EBUSY; 2711 } 2712 2713 ret = amdgpu_runtime_idle_check_display(dev); 2714 2715 pm_runtime_mark_last_busy(dev); 2716 pm_runtime_autosuspend(dev); 2717 return ret; 2718 } 2719 2720 long amdgpu_drm_ioctl(struct file *filp, 2721 unsigned int cmd, unsigned long arg) 2722 { 2723 struct drm_file *file_priv = filp->private_data; 2724 struct drm_device *dev; 2725 long ret; 2726 dev = file_priv->minor->dev; 2727 ret = pm_runtime_get_sync(dev->dev); 2728 if (ret < 0) 2729 goto out; 2730 2731 ret = drm_ioctl(filp, cmd, arg); 2732 2733 pm_runtime_mark_last_busy(dev->dev); 2734 out: 2735 pm_runtime_put_autosuspend(dev->dev); 2736 return ret; 2737 } 2738 2739 static const struct dev_pm_ops amdgpu_pm_ops = { 2740 .prepare = amdgpu_pmops_prepare, 2741 .complete = amdgpu_pmops_complete, 2742 .suspend = amdgpu_pmops_suspend, 2743 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2744 .resume = amdgpu_pmops_resume, 2745 .freeze = amdgpu_pmops_freeze, 2746 .thaw = amdgpu_pmops_thaw, 2747 .poweroff = amdgpu_pmops_poweroff, 2748 .restore = amdgpu_pmops_restore, 2749 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2750 .runtime_resume = amdgpu_pmops_runtime_resume, 2751 .runtime_idle = amdgpu_pmops_runtime_idle, 2752 }; 2753 2754 static int amdgpu_flush(struct file *f, fl_owner_t id) 2755 { 2756 struct drm_file *file_priv = f->private_data; 2757 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2758 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2759 2760 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2761 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2762 2763 return timeout >= 0 ? 0 : timeout; 2764 } 2765 2766 static const struct file_operations amdgpu_driver_kms_fops = { 2767 .owner = THIS_MODULE, 2768 .open = drm_open, 2769 .flush = amdgpu_flush, 2770 .release = drm_release, 2771 .unlocked_ioctl = amdgpu_drm_ioctl, 2772 .mmap = drm_gem_mmap, 2773 .poll = drm_poll, 2774 .read = drm_read, 2775 #ifdef CONFIG_COMPAT 2776 .compat_ioctl = amdgpu_kms_compat_ioctl, 2777 #endif 2778 #ifdef CONFIG_PROC_FS 2779 .show_fdinfo = amdgpu_show_fdinfo 2780 #endif 2781 }; 2782 2783 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2784 { 2785 struct drm_file *file; 2786 2787 if (!filp) 2788 return -EINVAL; 2789 2790 if (filp->f_op != &amdgpu_driver_kms_fops) { 2791 return -EINVAL; 2792 } 2793 2794 file = filp->private_data; 2795 *fpriv = file->driver_priv; 2796 return 0; 2797 } 2798 2799 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2800 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2801 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2802 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2803 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2804 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2805 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2806 /* KMS */ 2807 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2808 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2809 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2810 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2811 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2812 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2813 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2814 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2815 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2816 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2817 }; 2818 2819 static const struct drm_driver amdgpu_kms_driver = { 2820 .driver_features = 2821 DRIVER_ATOMIC | 2822 DRIVER_GEM | 2823 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2824 DRIVER_SYNCOBJ_TIMELINE, 2825 .open = amdgpu_driver_open_kms, 2826 .postclose = amdgpu_driver_postclose_kms, 2827 .lastclose = amdgpu_driver_lastclose_kms, 2828 .ioctls = amdgpu_ioctls_kms, 2829 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2830 .dumb_create = amdgpu_mode_dumb_create, 2831 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2832 .fops = &amdgpu_driver_kms_fops, 2833 .release = &amdgpu_driver_release_kms, 2834 2835 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2836 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2837 .gem_prime_import = amdgpu_gem_prime_import, 2838 .gem_prime_mmap = drm_gem_prime_mmap, 2839 2840 .name = DRIVER_NAME, 2841 .desc = DRIVER_DESC, 2842 .date = DRIVER_DATE, 2843 .major = KMS_DRIVER_MAJOR, 2844 .minor = KMS_DRIVER_MINOR, 2845 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2846 }; 2847 2848 const struct drm_driver amdgpu_partition_driver = { 2849 .driver_features = 2850 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2851 DRIVER_SYNCOBJ_TIMELINE, 2852 .open = amdgpu_driver_open_kms, 2853 .postclose = amdgpu_driver_postclose_kms, 2854 .lastclose = amdgpu_driver_lastclose_kms, 2855 .ioctls = amdgpu_ioctls_kms, 2856 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2857 .dumb_create = amdgpu_mode_dumb_create, 2858 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2859 .fops = &amdgpu_driver_kms_fops, 2860 .release = &amdgpu_driver_release_kms, 2861 2862 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2863 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2864 .gem_prime_import = amdgpu_gem_prime_import, 2865 .gem_prime_mmap = drm_gem_prime_mmap, 2866 2867 .name = DRIVER_NAME, 2868 .desc = DRIVER_DESC, 2869 .date = DRIVER_DATE, 2870 .major = KMS_DRIVER_MAJOR, 2871 .minor = KMS_DRIVER_MINOR, 2872 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2873 }; 2874 2875 static struct pci_error_handlers amdgpu_pci_err_handler = { 2876 .error_detected = amdgpu_pci_error_detected, 2877 .mmio_enabled = amdgpu_pci_mmio_enabled, 2878 .slot_reset = amdgpu_pci_slot_reset, 2879 .resume = amdgpu_pci_resume, 2880 }; 2881 2882 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2883 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2884 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2885 2886 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2887 &amdgpu_vram_mgr_attr_group, 2888 &amdgpu_gtt_mgr_attr_group, 2889 &amdgpu_vbios_version_attr_group, 2890 NULL, 2891 }; 2892 2893 2894 static struct pci_driver amdgpu_kms_pci_driver = { 2895 .name = DRIVER_NAME, 2896 .id_table = pciidlist, 2897 .probe = amdgpu_pci_probe, 2898 .remove = amdgpu_pci_remove, 2899 .shutdown = amdgpu_pci_shutdown, 2900 .driver.pm = &amdgpu_pm_ops, 2901 .err_handler = &amdgpu_pci_err_handler, 2902 .dev_groups = amdgpu_sysfs_groups, 2903 }; 2904 2905 static int __init amdgpu_init(void) 2906 { 2907 int r; 2908 2909 if (drm_firmware_drivers_only()) 2910 return -EINVAL; 2911 2912 r = amdgpu_sync_init(); 2913 if (r) 2914 goto error_sync; 2915 2916 r = amdgpu_fence_slab_init(); 2917 if (r) 2918 goto error_fence; 2919 2920 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2921 amdgpu_register_atpx_handler(); 2922 amdgpu_acpi_detect(); 2923 2924 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2925 amdgpu_amdkfd_init(); 2926 2927 /* let modprobe override vga console setting */ 2928 return pci_register_driver(&amdgpu_kms_pci_driver); 2929 2930 error_fence: 2931 amdgpu_sync_fini(); 2932 2933 error_sync: 2934 return r; 2935 } 2936 2937 static void __exit amdgpu_exit(void) 2938 { 2939 amdgpu_amdkfd_fini(); 2940 pci_unregister_driver(&amdgpu_kms_pci_driver); 2941 amdgpu_unregister_atpx_handler(); 2942 amdgpu_acpi_release(); 2943 amdgpu_sync_fini(); 2944 amdgpu_fence_slab_fini(); 2945 mmu_notifier_synchronize(); 2946 } 2947 2948 module_init(amdgpu_init); 2949 module_exit(amdgpu_exit); 2950 2951 MODULE_AUTHOR(DRIVER_AUTHOR); 2952 MODULE_DESCRIPTION(DRIVER_DESC); 2953 MODULE_LICENSE("GPL and additional rights"); 2954