1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/cc_platform.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 */ 101 #define KMS_DRIVER_MAJOR 3 102 #define KMS_DRIVER_MINOR 42 103 #define KMS_DRIVER_PATCHLEVEL 0 104 105 int amdgpu_vram_limit; 106 int amdgpu_vis_vram_limit; 107 int amdgpu_gart_size = -1; /* auto */ 108 int amdgpu_gtt_size = -1; /* auto */ 109 int amdgpu_moverate = -1; /* auto */ 110 int amdgpu_benchmarking; 111 int amdgpu_testing; 112 int amdgpu_audio = -1; 113 int amdgpu_disp_priority; 114 int amdgpu_hw_i2c; 115 int amdgpu_pcie_gen2 = -1; 116 int amdgpu_msi = -1; 117 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 118 int amdgpu_dpm = -1; 119 int amdgpu_fw_load_type = -1; 120 int amdgpu_aspm = -1; 121 int amdgpu_runtime_pm = -1; 122 uint amdgpu_ip_block_mask = 0xffffffff; 123 int amdgpu_bapm = -1; 124 int amdgpu_deep_color; 125 int amdgpu_vm_size = -1; 126 int amdgpu_vm_fragment_size = -1; 127 int amdgpu_vm_block_size = -1; 128 int amdgpu_vm_fault_stop; 129 int amdgpu_vm_debug; 130 int amdgpu_vm_update_mode = -1; 131 int amdgpu_exp_hw_support; 132 int amdgpu_dc = -1; 133 int amdgpu_sched_jobs = 32; 134 int amdgpu_sched_hw_submission = 2; 135 uint amdgpu_pcie_gen_cap; 136 uint amdgpu_pcie_lane_cap; 137 uint amdgpu_cg_mask = 0xffffffff; 138 uint amdgpu_pg_mask = 0xffffffff; 139 uint amdgpu_sdma_phase_quantum = 32; 140 char *amdgpu_disable_cu = NULL; 141 char *amdgpu_virtual_display = NULL; 142 143 /* 144 * OverDrive(bit 14) disabled by default 145 * GFX DCS(bit 19) disabled by default 146 */ 147 uint amdgpu_pp_feature_mask = 0xfff7bfff; 148 uint amdgpu_force_long_training; 149 int amdgpu_job_hang_limit; 150 int amdgpu_lbpw = -1; 151 int amdgpu_compute_multipipe = -1; 152 int amdgpu_gpu_recovery = -1; /* auto */ 153 int amdgpu_emu_mode; 154 uint amdgpu_smu_memory_pool_size; 155 int amdgpu_smu_pptable_id = -1; 156 /* 157 * FBC (bit 0) disabled by default 158 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 159 * - With this, for multiple monitors in sync(e.g. with the same model), 160 * mclk switching will be allowed. And the mclk will be not foced to the 161 * highest. That helps saving some idle power. 162 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 163 * PSR (bit 3) disabled by default 164 * EDP NO POWER SEQUENCING (bit 4) disabled by default 165 */ 166 uint amdgpu_dc_feature_mask = 2; 167 uint amdgpu_dc_debug_mask; 168 int amdgpu_async_gfx_ring = 1; 169 int amdgpu_mcbp; 170 int amdgpu_discovery = -1; 171 int amdgpu_mes; 172 int amdgpu_noretry = -1; 173 int amdgpu_force_asic_type = -1; 174 int amdgpu_tmz = -1; /* auto */ 175 uint amdgpu_freesync_vid_mode; 176 int amdgpu_reset_method = -1; /* auto */ 177 int amdgpu_num_kcq = -1; 178 int amdgpu_smartshift_bias; 179 180 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 181 182 struct amdgpu_mgpu_info mgpu_info = { 183 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 184 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 185 mgpu_info.delayed_reset_work, 186 amdgpu_drv_delayed_reset_work_handler, 0), 187 }; 188 int amdgpu_ras_enable = -1; 189 uint amdgpu_ras_mask = 0xffffffff; 190 int amdgpu_bad_page_threshold = -1; 191 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 192 .timeout_fatal_disable = false, 193 .period = 0x0, /* default to 0x0 (timeout disable) */ 194 }; 195 196 /** 197 * DOC: vramlimit (int) 198 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 199 */ 200 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 201 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 202 203 /** 204 * DOC: vis_vramlimit (int) 205 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 206 */ 207 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 208 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 209 210 /** 211 * DOC: gartsize (uint) 212 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 213 */ 214 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 215 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 216 217 /** 218 * DOC: gttsize (int) 219 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 220 * otherwise 3/4 RAM size). 221 */ 222 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 223 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 224 225 /** 226 * DOC: moverate (int) 227 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 228 */ 229 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 230 module_param_named(moverate, amdgpu_moverate, int, 0600); 231 232 /** 233 * DOC: benchmark (int) 234 * Run benchmarks. The default is 0 (Skip benchmarks). 235 */ 236 MODULE_PARM_DESC(benchmark, "Run benchmark"); 237 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 238 239 /** 240 * DOC: test (int) 241 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 242 */ 243 MODULE_PARM_DESC(test, "Run tests"); 244 module_param_named(test, amdgpu_testing, int, 0444); 245 246 /** 247 * DOC: audio (int) 248 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 249 */ 250 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 251 module_param_named(audio, amdgpu_audio, int, 0444); 252 253 /** 254 * DOC: disp_priority (int) 255 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 256 */ 257 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 258 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 259 260 /** 261 * DOC: hw_i2c (int) 262 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 263 */ 264 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 265 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 266 267 /** 268 * DOC: pcie_gen2 (int) 269 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 270 */ 271 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 272 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 273 274 /** 275 * DOC: msi (int) 276 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 277 */ 278 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 279 module_param_named(msi, amdgpu_msi, int, 0444); 280 281 /** 282 * DOC: lockup_timeout (string) 283 * Set GPU scheduler timeout value in ms. 284 * 285 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 286 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 287 * to the default timeout. 288 * 289 * - With one value specified, the setting will apply to all non-compute jobs. 290 * - With multiple values specified, the first one will be for GFX. 291 * The second one is for Compute. The third and fourth ones are 292 * for SDMA and Video. 293 * 294 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 295 * jobs is 10000. The timeout for compute is 60000. 296 */ 297 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 298 "for passthrough or sriov, 10000 for all jobs." 299 " 0: keep default value. negative: infinity timeout), " 300 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 301 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 302 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 303 304 /** 305 * DOC: dpm (int) 306 * Override for dynamic power management setting 307 * (0 = disable, 1 = enable) 308 * The default is -1 (auto). 309 */ 310 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 311 module_param_named(dpm, amdgpu_dpm, int, 0444); 312 313 /** 314 * DOC: fw_load_type (int) 315 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 316 */ 317 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 318 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 319 320 /** 321 * DOC: aspm (int) 322 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 323 */ 324 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 325 module_param_named(aspm, amdgpu_aspm, int, 0444); 326 327 /** 328 * DOC: runpm (int) 329 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 330 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 331 */ 332 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 333 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 334 335 /** 336 * DOC: ip_block_mask (uint) 337 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 338 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 339 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 340 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 341 */ 342 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 343 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 344 345 /** 346 * DOC: bapm (int) 347 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 348 * The default -1 (auto, enabled) 349 */ 350 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 351 module_param_named(bapm, amdgpu_bapm, int, 0444); 352 353 /** 354 * DOC: deep_color (int) 355 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 356 */ 357 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 358 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 359 360 /** 361 * DOC: vm_size (int) 362 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 363 */ 364 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 365 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 366 367 /** 368 * DOC: vm_fragment_size (int) 369 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 370 */ 371 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 372 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 373 374 /** 375 * DOC: vm_block_size (int) 376 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 377 */ 378 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 379 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 380 381 /** 382 * DOC: vm_fault_stop (int) 383 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 384 */ 385 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 386 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 387 388 /** 389 * DOC: vm_debug (int) 390 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 391 */ 392 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 393 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 394 395 /** 396 * DOC: vm_update_mode (int) 397 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 398 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 399 */ 400 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 401 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 402 403 /** 404 * DOC: exp_hw_support (int) 405 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 406 */ 407 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 408 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 409 410 /** 411 * DOC: dc (int) 412 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 413 */ 414 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 415 module_param_named(dc, amdgpu_dc, int, 0444); 416 417 /** 418 * DOC: sched_jobs (int) 419 * Override the max number of jobs supported in the sw queue. The default is 32. 420 */ 421 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 422 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 423 424 /** 425 * DOC: sched_hw_submission (int) 426 * Override the max number of HW submissions. The default is 2. 427 */ 428 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 429 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 430 431 /** 432 * DOC: ppfeaturemask (hexint) 433 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 434 * The default is the current set of stable power features. 435 */ 436 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 437 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 438 439 /** 440 * DOC: forcelongtraining (uint) 441 * Force long memory training in resume. 442 * The default is zero, indicates short training in resume. 443 */ 444 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 445 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 446 447 /** 448 * DOC: pcie_gen_cap (uint) 449 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 450 * The default is 0 (automatic for each asic). 451 */ 452 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 453 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 454 455 /** 456 * DOC: pcie_lane_cap (uint) 457 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 458 * The default is 0 (automatic for each asic). 459 */ 460 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 461 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 462 463 /** 464 * DOC: cg_mask (uint) 465 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 466 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 467 */ 468 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 469 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 470 471 /** 472 * DOC: pg_mask (uint) 473 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 474 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 475 */ 476 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 477 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 478 479 /** 480 * DOC: sdma_phase_quantum (uint) 481 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 482 */ 483 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 484 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 485 486 /** 487 * DOC: disable_cu (charp) 488 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 489 */ 490 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 491 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 492 493 /** 494 * DOC: virtual_display (charp) 495 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 496 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 497 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 498 * device at 26:00.0. The default is NULL. 499 */ 500 MODULE_PARM_DESC(virtual_display, 501 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 502 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 503 504 /** 505 * DOC: job_hang_limit (int) 506 * Set how much time allow a job hang and not drop it. The default is 0. 507 */ 508 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 509 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 510 511 /** 512 * DOC: lbpw (int) 513 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 514 */ 515 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 516 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 517 518 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 519 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 520 521 /** 522 * DOC: gpu_recovery (int) 523 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 524 */ 525 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 526 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 527 528 /** 529 * DOC: emu_mode (int) 530 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 531 */ 532 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 533 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 534 535 /** 536 * DOC: ras_enable (int) 537 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 538 */ 539 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 540 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 541 542 /** 543 * DOC: ras_mask (uint) 544 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 545 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 546 */ 547 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 548 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 549 550 /** 551 * DOC: timeout_fatal_disable (bool) 552 * Disable Watchdog timeout fatal error event 553 */ 554 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 555 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 556 557 /** 558 * DOC: timeout_period (uint) 559 * Modify the watchdog timeout max_cycles as (1 << period) 560 */ 561 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 562 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 563 564 /** 565 * DOC: si_support (int) 566 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 567 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 568 * otherwise using amdgpu driver. 569 */ 570 #ifdef CONFIG_DRM_AMDGPU_SI 571 572 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 573 int amdgpu_si_support = 0; 574 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 575 #else 576 int amdgpu_si_support = 1; 577 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 578 #endif 579 580 module_param_named(si_support, amdgpu_si_support, int, 0444); 581 #endif 582 583 /** 584 * DOC: cik_support (int) 585 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 586 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 587 * otherwise using amdgpu driver. 588 */ 589 #ifdef CONFIG_DRM_AMDGPU_CIK 590 591 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 592 int amdgpu_cik_support = 0; 593 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 594 #else 595 int amdgpu_cik_support = 1; 596 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 597 #endif 598 599 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 600 #endif 601 602 /** 603 * DOC: smu_memory_pool_size (uint) 604 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 605 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 606 */ 607 MODULE_PARM_DESC(smu_memory_pool_size, 608 "reserve gtt for smu debug usage, 0 = disable," 609 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 610 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 611 612 /** 613 * DOC: async_gfx_ring (int) 614 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 615 */ 616 MODULE_PARM_DESC(async_gfx_ring, 617 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 618 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 619 620 /** 621 * DOC: mcbp (int) 622 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 623 */ 624 MODULE_PARM_DESC(mcbp, 625 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 626 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 627 628 /** 629 * DOC: discovery (int) 630 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 631 * (-1 = auto (default), 0 = disabled, 1 = enabled) 632 */ 633 MODULE_PARM_DESC(discovery, 634 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 635 module_param_named(discovery, amdgpu_discovery, int, 0444); 636 637 /** 638 * DOC: mes (int) 639 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 640 * (0 = disabled (default), 1 = enabled) 641 */ 642 MODULE_PARM_DESC(mes, 643 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 644 module_param_named(mes, amdgpu_mes, int, 0444); 645 646 /** 647 * DOC: noretry (int) 648 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 649 * do not support per-process XNACK this also disables retry page faults. 650 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 651 */ 652 MODULE_PARM_DESC(noretry, 653 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 654 module_param_named(noretry, amdgpu_noretry, int, 0644); 655 656 /** 657 * DOC: force_asic_type (int) 658 * A non negative value used to specify the asic type for all supported GPUs. 659 */ 660 MODULE_PARM_DESC(force_asic_type, 661 "A non negative value used to specify the asic type for all supported GPUs"); 662 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 663 664 665 666 #ifdef CONFIG_HSA_AMD 667 /** 668 * DOC: sched_policy (int) 669 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 670 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 671 * assigns queues to HQDs. 672 */ 673 int sched_policy = KFD_SCHED_POLICY_HWS; 674 module_param(sched_policy, int, 0444); 675 MODULE_PARM_DESC(sched_policy, 676 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 677 678 /** 679 * DOC: hws_max_conc_proc (int) 680 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 681 * number of VMIDs assigned to the HWS, which is also the default. 682 */ 683 int hws_max_conc_proc = 8; 684 module_param(hws_max_conc_proc, int, 0444); 685 MODULE_PARM_DESC(hws_max_conc_proc, 686 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 687 688 /** 689 * DOC: cwsr_enable (int) 690 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 691 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 692 * disables it. 693 */ 694 int cwsr_enable = 1; 695 module_param(cwsr_enable, int, 0444); 696 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 697 698 /** 699 * DOC: max_num_of_queues_per_device (int) 700 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 701 * is 4096. 702 */ 703 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 704 module_param(max_num_of_queues_per_device, int, 0444); 705 MODULE_PARM_DESC(max_num_of_queues_per_device, 706 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 707 708 /** 709 * DOC: send_sigterm (int) 710 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 711 * but just print errors on dmesg. Setting 1 enables sending sigterm. 712 */ 713 int send_sigterm; 714 module_param(send_sigterm, int, 0444); 715 MODULE_PARM_DESC(send_sigterm, 716 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 717 718 /** 719 * DOC: debug_largebar (int) 720 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 721 * system. This limits the VRAM size reported to ROCm applications to the visible 722 * size, usually 256MB. 723 * Default value is 0, diabled. 724 */ 725 int debug_largebar; 726 module_param(debug_largebar, int, 0444); 727 MODULE_PARM_DESC(debug_largebar, 728 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 729 730 /** 731 * DOC: ignore_crat (int) 732 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 733 * table to get information about AMD APUs. This option can serve as a workaround on 734 * systems with a broken CRAT table. 735 * 736 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 737 * whehter use CRAT) 738 */ 739 int ignore_crat; 740 module_param(ignore_crat, int, 0444); 741 MODULE_PARM_DESC(ignore_crat, 742 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 743 744 /** 745 * DOC: halt_if_hws_hang (int) 746 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 747 * Setting 1 enables halt on hang. 748 */ 749 int halt_if_hws_hang; 750 module_param(halt_if_hws_hang, int, 0644); 751 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 752 753 /** 754 * DOC: hws_gws_support(bool) 755 * Assume that HWS supports GWS barriers regardless of what firmware version 756 * check says. Default value: false (rely on MEC2 firmware version check). 757 */ 758 bool hws_gws_support; 759 module_param(hws_gws_support, bool, 0444); 760 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 761 762 /** 763 * DOC: queue_preemption_timeout_ms (int) 764 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 765 */ 766 int queue_preemption_timeout_ms = 9000; 767 module_param(queue_preemption_timeout_ms, int, 0644); 768 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 769 770 /** 771 * DOC: debug_evictions(bool) 772 * Enable extra debug messages to help determine the cause of evictions 773 */ 774 bool debug_evictions; 775 module_param(debug_evictions, bool, 0644); 776 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 777 778 /** 779 * DOC: no_system_mem_limit(bool) 780 * Disable system memory limit, to support multiple process shared memory 781 */ 782 bool no_system_mem_limit; 783 module_param(no_system_mem_limit, bool, 0644); 784 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 785 786 /** 787 * DOC: no_queue_eviction_on_vm_fault (int) 788 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 789 */ 790 int amdgpu_no_queue_eviction_on_vm_fault = 0; 791 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 792 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 793 #endif 794 795 /** 796 * DOC: dcfeaturemask (uint) 797 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 798 * The default is the current set of stable display features. 799 */ 800 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 801 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 802 803 /** 804 * DOC: dcdebugmask (uint) 805 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 806 */ 807 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 808 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 809 810 /** 811 * DOC: abmlevel (uint) 812 * Override the default ABM (Adaptive Backlight Management) level used for DC 813 * enabled hardware. Requires DMCU to be supported and loaded. 814 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 815 * default. Values 1-4 control the maximum allowable brightness reduction via 816 * the ABM algorithm, with 1 being the least reduction and 4 being the most 817 * reduction. 818 * 819 * Defaults to 0, or disabled. Userspace can still override this level later 820 * after boot. 821 */ 822 uint amdgpu_dm_abm_level; 823 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 824 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 825 826 int amdgpu_backlight = -1; 827 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 828 module_param_named(backlight, amdgpu_backlight, bint, 0444); 829 830 /** 831 * DOC: tmz (int) 832 * Trusted Memory Zone (TMZ) is a method to protect data being written 833 * to or read from memory. 834 * 835 * The default value: 0 (off). TODO: change to auto till it is completed. 836 */ 837 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 838 module_param_named(tmz, amdgpu_tmz, int, 0444); 839 840 /** 841 * DOC: freesync_video (uint) 842 * Enable the optimization to adjust front porch timing to achieve seamless 843 * mode change experience when setting a freesync supported mode for which full 844 * modeset is not needed. 845 * 846 * The Display Core will add a set of modes derived from the base FreeSync 847 * video mode into the corresponding connector's mode list based on commonly 848 * used refresh rates and VRR range of the connected display, when users enable 849 * this feature. From the userspace perspective, they can see a seamless mode 850 * change experience when the change between different refresh rates under the 851 * same resolution. Additionally, userspace applications such as Video playback 852 * can read this modeset list and change the refresh rate based on the video 853 * frame rate. Finally, the userspace can also derive an appropriate mode for a 854 * particular refresh rate based on the FreeSync Mode and add it to the 855 * connector's mode list. 856 * 857 * Note: This is an experimental feature. 858 * 859 * The default value: 0 (off). 860 */ 861 MODULE_PARM_DESC( 862 freesync_video, 863 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 864 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 865 866 /** 867 * DOC: reset_method (int) 868 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 869 */ 870 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 871 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 872 873 /** 874 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 875 * threshold value of faulty pages detected by RAS ECC, which may 876 * result in the GPU entering bad status when the number of total 877 * faulty pages by ECC exceeds the threshold value. 878 */ 879 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 880 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 881 882 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 883 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 884 885 /** 886 * DOC: smu_pptable_id (int) 887 * Used to override pptable id. id = 0 use VBIOS pptable. 888 * id > 0 use the soft pptable with specicfied id. 889 */ 890 MODULE_PARM_DESC(smu_pptable_id, 891 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 892 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 893 894 static const struct pci_device_id pciidlist[] = { 895 #ifdef CONFIG_DRM_AMDGPU_SI 896 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 897 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 898 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 899 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 900 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 901 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 902 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 903 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 904 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 905 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 906 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 907 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 908 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 909 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 910 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 911 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 912 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 913 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 914 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 915 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 916 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 917 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 918 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 919 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 920 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 921 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 922 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 923 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 924 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 925 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 926 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 927 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 928 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 929 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 930 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 931 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 932 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 933 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 934 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 935 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 936 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 937 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 938 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 939 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 940 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 941 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 942 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 943 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 944 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 945 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 946 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 947 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 948 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 949 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 950 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 951 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 952 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 953 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 954 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 955 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 956 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 957 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 958 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 959 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 960 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 961 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 962 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 963 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 964 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 965 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 966 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 967 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 968 #endif 969 #ifdef CONFIG_DRM_AMDGPU_CIK 970 /* Kaveri */ 971 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 972 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 973 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 974 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 975 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 976 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 977 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 978 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 979 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 980 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 981 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 982 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 983 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 984 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 985 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 986 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 987 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 988 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 989 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 990 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 991 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 992 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 993 /* Bonaire */ 994 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 995 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 996 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 997 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 998 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 999 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1000 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1001 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1002 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1003 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1004 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1005 /* Hawaii */ 1006 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1007 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1008 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1009 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1010 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1011 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1012 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1013 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1014 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1015 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1016 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1017 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1018 /* Kabini */ 1019 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1020 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1021 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1022 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1023 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1024 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1025 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1026 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1027 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1028 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1029 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1030 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1031 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1032 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1033 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1034 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1035 /* mullins */ 1036 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1037 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1038 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1039 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1040 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1041 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1042 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1043 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1044 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1045 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1046 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1047 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1048 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1049 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1050 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1051 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1052 #endif 1053 /* topaz */ 1054 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1055 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1056 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1057 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1058 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1059 /* tonga */ 1060 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1061 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1062 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1063 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1064 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1065 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1066 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1067 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1068 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1069 /* fiji */ 1070 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1071 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1072 /* carrizo */ 1073 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1074 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1075 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1076 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1077 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1078 /* stoney */ 1079 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1080 /* Polaris11 */ 1081 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1082 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1083 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1084 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1085 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1086 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1087 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1088 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1089 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1090 /* Polaris10 */ 1091 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1092 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1093 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1094 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1095 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1096 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1097 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1098 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1099 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1100 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1101 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1102 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1103 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1104 /* Polaris12 */ 1105 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1106 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1107 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1108 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1109 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1110 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1111 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1112 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1113 /* VEGAM */ 1114 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1115 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1116 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1117 /* Vega 10 */ 1118 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1119 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1120 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1121 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1122 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1123 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1124 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1125 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1126 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1127 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1128 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1129 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1130 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1131 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1132 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1133 /* Vega 12 */ 1134 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1135 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1136 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1137 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1138 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1139 /* Vega 20 */ 1140 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1141 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1142 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1143 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1144 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1145 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1146 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1147 /* Raven */ 1148 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1149 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1150 /* Arcturus */ 1151 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1152 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1153 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1154 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1155 /* Navi10 */ 1156 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1157 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1158 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1159 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1160 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1161 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1162 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1163 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1164 /* Navi14 */ 1165 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1166 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1167 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1168 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1169 1170 /* Renoir */ 1171 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1172 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1173 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1174 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1175 1176 /* Navi12 */ 1177 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1178 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1179 1180 /* Sienna_Cichlid */ 1181 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1182 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1183 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1184 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1185 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1186 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1187 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1188 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1189 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1190 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1191 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1192 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1193 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1194 1195 /* Van Gogh */ 1196 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1197 1198 /* Yellow Carp */ 1199 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1200 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1201 1202 /* Navy_Flounder */ 1203 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1204 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1205 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1206 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1207 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1208 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1209 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1210 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1211 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1212 1213 /* DIMGREY_CAVEFISH */ 1214 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1215 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1216 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1217 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1218 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1219 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1220 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1221 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1222 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1223 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1224 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1225 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1226 1227 /* Aldebaran */ 1228 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1229 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1230 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1231 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1232 1233 /* CYAN_SKILLFISH */ 1234 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1235 1236 /* BEIGE_GOBY */ 1237 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1238 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1239 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1240 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1241 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1242 1243 {0, 0, 0} 1244 }; 1245 1246 MODULE_DEVICE_TABLE(pci, pciidlist); 1247 1248 static const struct drm_driver amdgpu_kms_driver; 1249 1250 static int amdgpu_pci_probe(struct pci_dev *pdev, 1251 const struct pci_device_id *ent) 1252 { 1253 struct drm_device *ddev; 1254 struct amdgpu_device *adev; 1255 unsigned long flags = ent->driver_data; 1256 int ret, retry = 0; 1257 bool supports_atomic = false; 1258 1259 if (amdgpu_virtual_display || 1260 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1261 supports_atomic = true; 1262 1263 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1264 DRM_INFO("This hardware requires experimental hardware support.\n" 1265 "See modparam exp_hw_support\n"); 1266 return -ENODEV; 1267 } 1268 1269 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1270 * however, SME requires an indirect IOMMU mapping because the encryption 1271 * bit is beyond the DMA mask of the chip. 1272 */ 1273 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 1274 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1275 dev_info(&pdev->dev, 1276 "SME is not compatible with RAVEN\n"); 1277 return -ENOTSUPP; 1278 } 1279 1280 #ifdef CONFIG_DRM_AMDGPU_SI 1281 if (!amdgpu_si_support) { 1282 switch (flags & AMD_ASIC_MASK) { 1283 case CHIP_TAHITI: 1284 case CHIP_PITCAIRN: 1285 case CHIP_VERDE: 1286 case CHIP_OLAND: 1287 case CHIP_HAINAN: 1288 dev_info(&pdev->dev, 1289 "SI support provided by radeon.\n"); 1290 dev_info(&pdev->dev, 1291 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1292 ); 1293 return -ENODEV; 1294 } 1295 } 1296 #endif 1297 #ifdef CONFIG_DRM_AMDGPU_CIK 1298 if (!amdgpu_cik_support) { 1299 switch (flags & AMD_ASIC_MASK) { 1300 case CHIP_KAVERI: 1301 case CHIP_BONAIRE: 1302 case CHIP_HAWAII: 1303 case CHIP_KABINI: 1304 case CHIP_MULLINS: 1305 dev_info(&pdev->dev, 1306 "CIK support provided by radeon.\n"); 1307 dev_info(&pdev->dev, 1308 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1309 ); 1310 return -ENODEV; 1311 } 1312 } 1313 #endif 1314 1315 /* Get rid of things like offb */ 1316 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 1317 if (ret) 1318 return ret; 1319 1320 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1321 if (IS_ERR(adev)) 1322 return PTR_ERR(adev); 1323 1324 adev->dev = &pdev->dev; 1325 adev->pdev = pdev; 1326 ddev = adev_to_drm(adev); 1327 1328 if (!supports_atomic) 1329 ddev->driver_features &= ~DRIVER_ATOMIC; 1330 1331 ret = pci_enable_device(pdev); 1332 if (ret) 1333 return ret; 1334 1335 pci_set_drvdata(pdev, ddev); 1336 1337 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1338 if (ret) 1339 goto err_pci; 1340 1341 retry_init: 1342 ret = drm_dev_register(ddev, ent->driver_data); 1343 if (ret == -EAGAIN && ++retry <= 3) { 1344 DRM_INFO("retry init %d\n", retry); 1345 /* Don't request EX mode too frequently which is attacking */ 1346 msleep(5000); 1347 goto retry_init; 1348 } else if (ret) { 1349 goto err_pci; 1350 } 1351 1352 ret = amdgpu_debugfs_init(adev); 1353 if (ret) 1354 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1355 1356 return 0; 1357 1358 err_pci: 1359 pci_disable_device(pdev); 1360 return ret; 1361 } 1362 1363 static void 1364 amdgpu_pci_remove(struct pci_dev *pdev) 1365 { 1366 struct drm_device *dev = pci_get_drvdata(pdev); 1367 1368 drm_dev_unplug(dev); 1369 amdgpu_driver_unload_kms(dev); 1370 1371 /* 1372 * Flush any in flight DMA operations from device. 1373 * Clear the Bus Master Enable bit and then wait on the PCIe Device 1374 * StatusTransactions Pending bit. 1375 */ 1376 pci_disable_device(pdev); 1377 pci_wait_for_pending_transaction(pdev); 1378 } 1379 1380 static void 1381 amdgpu_pci_shutdown(struct pci_dev *pdev) 1382 { 1383 struct drm_device *dev = pci_get_drvdata(pdev); 1384 struct amdgpu_device *adev = drm_to_adev(dev); 1385 1386 if (amdgpu_ras_intr_triggered()) 1387 return; 1388 1389 /* if we are running in a VM, make sure the device 1390 * torn down properly on reboot/shutdown. 1391 * unfortunately we can't detect certain 1392 * hypervisors so just do this all the time. 1393 */ 1394 if (!amdgpu_passthrough(adev)) 1395 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1396 amdgpu_device_ip_suspend(adev); 1397 adev->mp1_state = PP_MP1_STATE_NONE; 1398 } 1399 1400 /** 1401 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 1402 * 1403 * @work: work_struct. 1404 */ 1405 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 1406 { 1407 struct list_head device_list; 1408 struct amdgpu_device *adev; 1409 int i, r; 1410 struct amdgpu_reset_context reset_context; 1411 1412 memset(&reset_context, 0, sizeof(reset_context)); 1413 1414 mutex_lock(&mgpu_info.mutex); 1415 if (mgpu_info.pending_reset == true) { 1416 mutex_unlock(&mgpu_info.mutex); 1417 return; 1418 } 1419 mgpu_info.pending_reset = true; 1420 mutex_unlock(&mgpu_info.mutex); 1421 1422 /* Use a common context, just need to make sure full reset is done */ 1423 reset_context.method = AMD_RESET_METHOD_NONE; 1424 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 1425 1426 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1427 adev = mgpu_info.gpu_ins[i].adev; 1428 reset_context.reset_req_dev = adev; 1429 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 1430 if (r) { 1431 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 1432 r, adev_to_drm(adev)->unique); 1433 } 1434 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 1435 r = -EALREADY; 1436 } 1437 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1438 adev = mgpu_info.gpu_ins[i].adev; 1439 flush_work(&adev->xgmi_reset_work); 1440 adev->gmc.xgmi.pending_reset = false; 1441 } 1442 1443 /* reset function will rebuild the xgmi hive info , clear it now */ 1444 for (i = 0; i < mgpu_info.num_dgpu; i++) 1445 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 1446 1447 INIT_LIST_HEAD(&device_list); 1448 1449 for (i = 0; i < mgpu_info.num_dgpu; i++) 1450 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 1451 1452 /* unregister the GPU first, reset function will add them back */ 1453 list_for_each_entry(adev, &device_list, reset_list) 1454 amdgpu_unregister_gpu_instance(adev); 1455 1456 /* Use a common context, just need to make sure full reset is done */ 1457 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 1458 r = amdgpu_do_asic_reset(&device_list, &reset_context); 1459 1460 if (r) { 1461 DRM_ERROR("reinit gpus failure"); 1462 return; 1463 } 1464 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1465 adev = mgpu_info.gpu_ins[i].adev; 1466 if (!adev->kfd.init_complete) 1467 amdgpu_amdkfd_device_init(adev); 1468 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1469 } 1470 return; 1471 } 1472 1473 static int amdgpu_pmops_prepare(struct device *dev) 1474 { 1475 struct drm_device *drm_dev = dev_get_drvdata(dev); 1476 1477 /* Return a positive number here so 1478 * DPM_FLAG_SMART_SUSPEND works properly 1479 */ 1480 if (amdgpu_device_supports_boco(drm_dev)) 1481 return pm_runtime_suspended(dev) && 1482 pm_suspend_via_firmware(); 1483 1484 return 0; 1485 } 1486 1487 static void amdgpu_pmops_complete(struct device *dev) 1488 { 1489 /* nothing to do */ 1490 } 1491 1492 static int amdgpu_pmops_suspend(struct device *dev) 1493 { 1494 struct drm_device *drm_dev = dev_get_drvdata(dev); 1495 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1496 int r; 1497 1498 if (amdgpu_acpi_is_s0ix_active(adev)) 1499 adev->in_s0ix = true; 1500 adev->in_s3 = true; 1501 r = amdgpu_device_suspend(drm_dev, true); 1502 adev->in_s3 = false; 1503 1504 return r; 1505 } 1506 1507 static int amdgpu_pmops_resume(struct device *dev) 1508 { 1509 struct drm_device *drm_dev = dev_get_drvdata(dev); 1510 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1511 int r; 1512 1513 r = amdgpu_device_resume(drm_dev, true); 1514 if (amdgpu_acpi_is_s0ix_active(adev)) 1515 adev->in_s0ix = false; 1516 return r; 1517 } 1518 1519 static int amdgpu_pmops_freeze(struct device *dev) 1520 { 1521 struct drm_device *drm_dev = dev_get_drvdata(dev); 1522 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1523 int r; 1524 1525 adev->in_s4 = true; 1526 r = amdgpu_device_suspend(drm_dev, true); 1527 adev->in_s4 = false; 1528 if (r) 1529 return r; 1530 return amdgpu_asic_reset(adev); 1531 } 1532 1533 static int amdgpu_pmops_thaw(struct device *dev) 1534 { 1535 struct drm_device *drm_dev = dev_get_drvdata(dev); 1536 1537 return amdgpu_device_resume(drm_dev, true); 1538 } 1539 1540 static int amdgpu_pmops_poweroff(struct device *dev) 1541 { 1542 struct drm_device *drm_dev = dev_get_drvdata(dev); 1543 1544 return amdgpu_device_suspend(drm_dev, true); 1545 } 1546 1547 static int amdgpu_pmops_restore(struct device *dev) 1548 { 1549 struct drm_device *drm_dev = dev_get_drvdata(dev); 1550 1551 return amdgpu_device_resume(drm_dev, true); 1552 } 1553 1554 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1555 { 1556 struct pci_dev *pdev = to_pci_dev(dev); 1557 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1558 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1559 int ret, i; 1560 1561 if (!adev->runpm) { 1562 pm_runtime_forbid(dev); 1563 return -EBUSY; 1564 } 1565 1566 /* wait for all rings to drain before suspending */ 1567 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1568 struct amdgpu_ring *ring = adev->rings[i]; 1569 if (ring && ring->sched.ready) { 1570 ret = amdgpu_fence_wait_empty(ring); 1571 if (ret) 1572 return -EBUSY; 1573 } 1574 } 1575 1576 adev->in_runpm = true; 1577 if (amdgpu_device_supports_px(drm_dev)) 1578 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1579 1580 ret = amdgpu_device_suspend(drm_dev, false); 1581 if (ret) { 1582 adev->in_runpm = false; 1583 return ret; 1584 } 1585 1586 if (amdgpu_device_supports_px(drm_dev)) { 1587 /* Only need to handle PCI state in the driver for ATPX 1588 * PCI core handles it for _PR3. 1589 */ 1590 amdgpu_device_cache_pci_state(pdev); 1591 pci_disable_device(pdev); 1592 pci_ignore_hotplug(pdev); 1593 pci_set_power_state(pdev, PCI_D3cold); 1594 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1595 } else if (amdgpu_device_supports_boco(drm_dev)) { 1596 /* nothing to do */ 1597 } else if (amdgpu_device_supports_baco(drm_dev)) { 1598 amdgpu_device_baco_enter(drm_dev); 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int amdgpu_pmops_runtime_resume(struct device *dev) 1605 { 1606 struct pci_dev *pdev = to_pci_dev(dev); 1607 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1608 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1609 int ret; 1610 1611 if (!adev->runpm) 1612 return -EINVAL; 1613 1614 /* Avoids registers access if device is physically gone */ 1615 if (!pci_device_is_present(adev->pdev)) 1616 adev->no_hw_access = true; 1617 1618 if (amdgpu_device_supports_px(drm_dev)) { 1619 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1620 1621 /* Only need to handle PCI state in the driver for ATPX 1622 * PCI core handles it for _PR3. 1623 */ 1624 pci_set_power_state(pdev, PCI_D0); 1625 amdgpu_device_load_pci_state(pdev); 1626 ret = pci_enable_device(pdev); 1627 if (ret) 1628 return ret; 1629 pci_set_master(pdev); 1630 } else if (amdgpu_device_supports_boco(drm_dev)) { 1631 /* Only need to handle PCI state in the driver for ATPX 1632 * PCI core handles it for _PR3. 1633 */ 1634 pci_set_master(pdev); 1635 } else if (amdgpu_device_supports_baco(drm_dev)) { 1636 amdgpu_device_baco_exit(drm_dev); 1637 } 1638 ret = amdgpu_device_resume(drm_dev, false); 1639 if (ret) 1640 return ret; 1641 1642 if (amdgpu_device_supports_px(drm_dev)) 1643 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1644 adev->in_runpm = false; 1645 return 0; 1646 } 1647 1648 static int amdgpu_pmops_runtime_idle(struct device *dev) 1649 { 1650 struct drm_device *drm_dev = dev_get_drvdata(dev); 1651 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1652 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1653 int ret = 1; 1654 1655 if (!adev->runpm) { 1656 pm_runtime_forbid(dev); 1657 return -EBUSY; 1658 } 1659 1660 if (amdgpu_device_has_dc_support(adev)) { 1661 struct drm_crtc *crtc; 1662 1663 drm_for_each_crtc(crtc, drm_dev) { 1664 drm_modeset_lock(&crtc->mutex, NULL); 1665 if (crtc->state->active) 1666 ret = -EBUSY; 1667 drm_modeset_unlock(&crtc->mutex); 1668 if (ret < 0) 1669 break; 1670 } 1671 1672 } else { 1673 struct drm_connector *list_connector; 1674 struct drm_connector_list_iter iter; 1675 1676 mutex_lock(&drm_dev->mode_config.mutex); 1677 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1678 1679 drm_connector_list_iter_begin(drm_dev, &iter); 1680 drm_for_each_connector_iter(list_connector, &iter) { 1681 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1682 ret = -EBUSY; 1683 break; 1684 } 1685 } 1686 1687 drm_connector_list_iter_end(&iter); 1688 1689 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1690 mutex_unlock(&drm_dev->mode_config.mutex); 1691 } 1692 1693 if (ret == -EBUSY) 1694 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1695 1696 pm_runtime_mark_last_busy(dev); 1697 pm_runtime_autosuspend(dev); 1698 return ret; 1699 } 1700 1701 long amdgpu_drm_ioctl(struct file *filp, 1702 unsigned int cmd, unsigned long arg) 1703 { 1704 struct drm_file *file_priv = filp->private_data; 1705 struct drm_device *dev; 1706 long ret; 1707 dev = file_priv->minor->dev; 1708 ret = pm_runtime_get_sync(dev->dev); 1709 if (ret < 0) 1710 goto out; 1711 1712 ret = drm_ioctl(filp, cmd, arg); 1713 1714 pm_runtime_mark_last_busy(dev->dev); 1715 out: 1716 pm_runtime_put_autosuspend(dev->dev); 1717 return ret; 1718 } 1719 1720 static const struct dev_pm_ops amdgpu_pm_ops = { 1721 .prepare = amdgpu_pmops_prepare, 1722 .complete = amdgpu_pmops_complete, 1723 .suspend = amdgpu_pmops_suspend, 1724 .resume = amdgpu_pmops_resume, 1725 .freeze = amdgpu_pmops_freeze, 1726 .thaw = amdgpu_pmops_thaw, 1727 .poweroff = amdgpu_pmops_poweroff, 1728 .restore = amdgpu_pmops_restore, 1729 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1730 .runtime_resume = amdgpu_pmops_runtime_resume, 1731 .runtime_idle = amdgpu_pmops_runtime_idle, 1732 }; 1733 1734 static int amdgpu_flush(struct file *f, fl_owner_t id) 1735 { 1736 struct drm_file *file_priv = f->private_data; 1737 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1738 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1739 1740 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1741 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1742 1743 return timeout >= 0 ? 0 : timeout; 1744 } 1745 1746 static const struct file_operations amdgpu_driver_kms_fops = { 1747 .owner = THIS_MODULE, 1748 .open = drm_open, 1749 .flush = amdgpu_flush, 1750 .release = drm_release, 1751 .unlocked_ioctl = amdgpu_drm_ioctl, 1752 .mmap = drm_gem_mmap, 1753 .poll = drm_poll, 1754 .read = drm_read, 1755 #ifdef CONFIG_COMPAT 1756 .compat_ioctl = amdgpu_kms_compat_ioctl, 1757 #endif 1758 #ifdef CONFIG_PROC_FS 1759 .show_fdinfo = amdgpu_show_fdinfo 1760 #endif 1761 }; 1762 1763 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1764 { 1765 struct drm_file *file; 1766 1767 if (!filp) 1768 return -EINVAL; 1769 1770 if (filp->f_op != &amdgpu_driver_kms_fops) { 1771 return -EINVAL; 1772 } 1773 1774 file = filp->private_data; 1775 *fpriv = file->driver_priv; 1776 return 0; 1777 } 1778 1779 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1780 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1781 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1782 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1783 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1784 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1785 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1786 /* KMS */ 1787 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1788 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1789 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1790 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1791 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1792 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1793 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1794 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1795 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1796 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1797 }; 1798 1799 static const struct drm_driver amdgpu_kms_driver = { 1800 .driver_features = 1801 DRIVER_ATOMIC | 1802 DRIVER_GEM | 1803 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1804 DRIVER_SYNCOBJ_TIMELINE, 1805 .open = amdgpu_driver_open_kms, 1806 .postclose = amdgpu_driver_postclose_kms, 1807 .lastclose = amdgpu_driver_lastclose_kms, 1808 .ioctls = amdgpu_ioctls_kms, 1809 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1810 .dumb_create = amdgpu_mode_dumb_create, 1811 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1812 .fops = &amdgpu_driver_kms_fops, 1813 .release = &amdgpu_driver_release_kms, 1814 1815 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1816 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1817 .gem_prime_import = amdgpu_gem_prime_import, 1818 .gem_prime_mmap = drm_gem_prime_mmap, 1819 1820 .name = DRIVER_NAME, 1821 .desc = DRIVER_DESC, 1822 .date = DRIVER_DATE, 1823 .major = KMS_DRIVER_MAJOR, 1824 .minor = KMS_DRIVER_MINOR, 1825 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1826 }; 1827 1828 static struct pci_error_handlers amdgpu_pci_err_handler = { 1829 .error_detected = amdgpu_pci_error_detected, 1830 .mmio_enabled = amdgpu_pci_mmio_enabled, 1831 .slot_reset = amdgpu_pci_slot_reset, 1832 .resume = amdgpu_pci_resume, 1833 }; 1834 1835 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1836 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1837 extern const struct attribute_group amdgpu_vbios_version_attr_group; 1838 1839 static const struct attribute_group *amdgpu_sysfs_groups[] = { 1840 &amdgpu_vram_mgr_attr_group, 1841 &amdgpu_gtt_mgr_attr_group, 1842 &amdgpu_vbios_version_attr_group, 1843 NULL, 1844 }; 1845 1846 1847 static struct pci_driver amdgpu_kms_pci_driver = { 1848 .name = DRIVER_NAME, 1849 .id_table = pciidlist, 1850 .probe = amdgpu_pci_probe, 1851 .remove = amdgpu_pci_remove, 1852 .shutdown = amdgpu_pci_shutdown, 1853 .driver.pm = &amdgpu_pm_ops, 1854 .err_handler = &amdgpu_pci_err_handler, 1855 .dev_groups = amdgpu_sysfs_groups, 1856 }; 1857 1858 static int __init amdgpu_init(void) 1859 { 1860 int r; 1861 1862 if (vgacon_text_force()) { 1863 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1864 return -EINVAL; 1865 } 1866 1867 r = amdgpu_sync_init(); 1868 if (r) 1869 goto error_sync; 1870 1871 r = amdgpu_fence_slab_init(); 1872 if (r) 1873 goto error_fence; 1874 1875 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1876 amdgpu_register_atpx_handler(); 1877 amdgpu_acpi_detect(); 1878 1879 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1880 amdgpu_amdkfd_init(); 1881 1882 /* let modprobe override vga console setting */ 1883 return pci_register_driver(&amdgpu_kms_pci_driver); 1884 1885 error_fence: 1886 amdgpu_sync_fini(); 1887 1888 error_sync: 1889 return r; 1890 } 1891 1892 static void __exit amdgpu_exit(void) 1893 { 1894 amdgpu_amdkfd_fini(); 1895 pci_unregister_driver(&amdgpu_kms_pci_driver); 1896 amdgpu_unregister_atpx_handler(); 1897 amdgpu_sync_fini(); 1898 amdgpu_fence_slab_fini(); 1899 mmu_notifier_synchronize(); 1900 } 1901 1902 module_init(amdgpu_init); 1903 module_exit(amdgpu_exit); 1904 1905 MODULE_AUTHOR(DRIVER_AUTHOR); 1906 MODULE_DESCRIPTION(DRIVER_DESC); 1907 MODULE_LICENSE("GPL and additional rights"); 1908