1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/cc_platform.h> 42 #include <linux/fb.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 #include "amdgpu_dma_buf.h" 47 #include "amdgpu_sched.h" 48 #include "amdgpu_fdinfo.h" 49 #include "amdgpu_amdkfd.h" 50 51 #include "amdgpu_ras.h" 52 #include "amdgpu_xgmi.h" 53 #include "amdgpu_reset.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 */ 104 #define KMS_DRIVER_MAJOR 3 105 #define KMS_DRIVER_MINOR 44 106 #define KMS_DRIVER_PATCHLEVEL 0 107 108 int amdgpu_vram_limit; 109 int amdgpu_vis_vram_limit; 110 int amdgpu_gart_size = -1; /* auto */ 111 int amdgpu_gtt_size = -1; /* auto */ 112 int amdgpu_moverate = -1; /* auto */ 113 int amdgpu_benchmarking; 114 int amdgpu_testing; 115 int amdgpu_audio = -1; 116 int amdgpu_disp_priority; 117 int amdgpu_hw_i2c; 118 int amdgpu_pcie_gen2 = -1; 119 int amdgpu_msi = -1; 120 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 121 int amdgpu_dpm = -1; 122 int amdgpu_fw_load_type = -1; 123 int amdgpu_aspm = -1; 124 int amdgpu_runtime_pm = -1; 125 uint amdgpu_ip_block_mask = 0xffffffff; 126 int amdgpu_bapm = -1; 127 int amdgpu_deep_color; 128 int amdgpu_vm_size = -1; 129 int amdgpu_vm_fragment_size = -1; 130 int amdgpu_vm_block_size = -1; 131 int amdgpu_vm_fault_stop; 132 int amdgpu_vm_debug; 133 int amdgpu_vm_update_mode = -1; 134 int amdgpu_exp_hw_support; 135 int amdgpu_dc = -1; 136 int amdgpu_sched_jobs = 32; 137 int amdgpu_sched_hw_submission = 2; 138 uint amdgpu_pcie_gen_cap; 139 uint amdgpu_pcie_lane_cap; 140 uint amdgpu_cg_mask = 0xffffffff; 141 uint amdgpu_pg_mask = 0xffffffff; 142 uint amdgpu_sdma_phase_quantum = 32; 143 char *amdgpu_disable_cu = NULL; 144 char *amdgpu_virtual_display = NULL; 145 146 /* 147 * OverDrive(bit 14) disabled by default 148 * GFX DCS(bit 19) disabled by default 149 */ 150 uint amdgpu_pp_feature_mask = 0xfff7bfff; 151 uint amdgpu_force_long_training; 152 int amdgpu_job_hang_limit; 153 int amdgpu_lbpw = -1; 154 int amdgpu_compute_multipipe = -1; 155 int amdgpu_gpu_recovery = -1; /* auto */ 156 int amdgpu_emu_mode; 157 uint amdgpu_smu_memory_pool_size; 158 int amdgpu_smu_pptable_id = -1; 159 /* 160 * FBC (bit 0) disabled by default 161 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 162 * - With this, for multiple monitors in sync(e.g. with the same model), 163 * mclk switching will be allowed. And the mclk will be not foced to the 164 * highest. That helps saving some idle power. 165 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 166 * PSR (bit 3) disabled by default 167 * EDP NO POWER SEQUENCING (bit 4) disabled by default 168 */ 169 uint amdgpu_dc_feature_mask = 2; 170 uint amdgpu_dc_debug_mask; 171 int amdgpu_async_gfx_ring = 1; 172 int amdgpu_mcbp; 173 int amdgpu_discovery = -1; 174 int amdgpu_mes; 175 int amdgpu_noretry = -1; 176 int amdgpu_force_asic_type = -1; 177 int amdgpu_tmz = -1; /* auto */ 178 uint amdgpu_freesync_vid_mode; 179 int amdgpu_reset_method = -1; /* auto */ 180 int amdgpu_num_kcq = -1; 181 int amdgpu_smartshift_bias; 182 183 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 184 185 struct amdgpu_mgpu_info mgpu_info = { 186 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 187 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 188 mgpu_info.delayed_reset_work, 189 amdgpu_drv_delayed_reset_work_handler, 0), 190 }; 191 int amdgpu_ras_enable = -1; 192 uint amdgpu_ras_mask = 0xffffffff; 193 int amdgpu_bad_page_threshold = -1; 194 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 195 .timeout_fatal_disable = false, 196 .period = 0x0, /* default to 0x0 (timeout disable) */ 197 }; 198 199 /** 200 * DOC: vramlimit (int) 201 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 202 */ 203 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 204 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 205 206 /** 207 * DOC: vis_vramlimit (int) 208 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 209 */ 210 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 211 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 212 213 /** 214 * DOC: gartsize (uint) 215 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 216 */ 217 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 218 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 219 220 /** 221 * DOC: gttsize (int) 222 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 223 * otherwise 3/4 RAM size). 224 */ 225 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 226 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 227 228 /** 229 * DOC: moverate (int) 230 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 231 */ 232 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 233 module_param_named(moverate, amdgpu_moverate, int, 0600); 234 235 /** 236 * DOC: benchmark (int) 237 * Run benchmarks. The default is 0 (Skip benchmarks). 238 */ 239 MODULE_PARM_DESC(benchmark, "Run benchmark"); 240 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 241 242 /** 243 * DOC: test (int) 244 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 245 */ 246 MODULE_PARM_DESC(test, "Run tests"); 247 module_param_named(test, amdgpu_testing, int, 0444); 248 249 /** 250 * DOC: audio (int) 251 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 252 */ 253 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 254 module_param_named(audio, amdgpu_audio, int, 0444); 255 256 /** 257 * DOC: disp_priority (int) 258 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 259 */ 260 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 261 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 262 263 /** 264 * DOC: hw_i2c (int) 265 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 266 */ 267 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 268 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 269 270 /** 271 * DOC: pcie_gen2 (int) 272 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 273 */ 274 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 275 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 276 277 /** 278 * DOC: msi (int) 279 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 280 */ 281 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 282 module_param_named(msi, amdgpu_msi, int, 0444); 283 284 /** 285 * DOC: lockup_timeout (string) 286 * Set GPU scheduler timeout value in ms. 287 * 288 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 289 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 290 * to the default timeout. 291 * 292 * - With one value specified, the setting will apply to all non-compute jobs. 293 * - With multiple values specified, the first one will be for GFX. 294 * The second one is for Compute. The third and fourth ones are 295 * for SDMA and Video. 296 * 297 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 298 * jobs is 10000. The timeout for compute is 60000. 299 */ 300 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 301 "for passthrough or sriov, 10000 for all jobs." 302 " 0: keep default value. negative: infinity timeout), " 303 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 304 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 305 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 306 307 /** 308 * DOC: dpm (int) 309 * Override for dynamic power management setting 310 * (0 = disable, 1 = enable) 311 * The default is -1 (auto). 312 */ 313 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 314 module_param_named(dpm, amdgpu_dpm, int, 0444); 315 316 /** 317 * DOC: fw_load_type (int) 318 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 319 */ 320 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 321 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 322 323 /** 324 * DOC: aspm (int) 325 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 326 */ 327 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 328 module_param_named(aspm, amdgpu_aspm, int, 0444); 329 330 /** 331 * DOC: runpm (int) 332 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 333 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 334 * Setting the value to 0 disables this functionality. 335 */ 336 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 337 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 338 339 /** 340 * DOC: ip_block_mask (uint) 341 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 342 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 343 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 344 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 345 */ 346 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 347 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 348 349 /** 350 * DOC: bapm (int) 351 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 352 * The default -1 (auto, enabled) 353 */ 354 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 355 module_param_named(bapm, amdgpu_bapm, int, 0444); 356 357 /** 358 * DOC: deep_color (int) 359 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 360 */ 361 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 362 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 363 364 /** 365 * DOC: vm_size (int) 366 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 367 */ 368 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 369 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 370 371 /** 372 * DOC: vm_fragment_size (int) 373 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 374 */ 375 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 376 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 377 378 /** 379 * DOC: vm_block_size (int) 380 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 381 */ 382 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 383 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 384 385 /** 386 * DOC: vm_fault_stop (int) 387 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 388 */ 389 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 390 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 391 392 /** 393 * DOC: vm_debug (int) 394 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 395 */ 396 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 397 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 398 399 /** 400 * DOC: vm_update_mode (int) 401 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 402 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 403 */ 404 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 405 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 406 407 /** 408 * DOC: exp_hw_support (int) 409 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 410 */ 411 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 412 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 413 414 /** 415 * DOC: dc (int) 416 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 417 */ 418 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 419 module_param_named(dc, amdgpu_dc, int, 0444); 420 421 /** 422 * DOC: sched_jobs (int) 423 * Override the max number of jobs supported in the sw queue. The default is 32. 424 */ 425 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 426 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 427 428 /** 429 * DOC: sched_hw_submission (int) 430 * Override the max number of HW submissions. The default is 2. 431 */ 432 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 433 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 434 435 /** 436 * DOC: ppfeaturemask (hexint) 437 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 438 * The default is the current set of stable power features. 439 */ 440 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 441 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 442 443 /** 444 * DOC: forcelongtraining (uint) 445 * Force long memory training in resume. 446 * The default is zero, indicates short training in resume. 447 */ 448 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 449 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 450 451 /** 452 * DOC: pcie_gen_cap (uint) 453 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 454 * The default is 0 (automatic for each asic). 455 */ 456 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 457 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 458 459 /** 460 * DOC: pcie_lane_cap (uint) 461 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 462 * The default is 0 (automatic for each asic). 463 */ 464 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 465 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 466 467 /** 468 * DOC: cg_mask (uint) 469 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 470 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 471 */ 472 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 473 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 474 475 /** 476 * DOC: pg_mask (uint) 477 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 478 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 479 */ 480 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 481 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 482 483 /** 484 * DOC: sdma_phase_quantum (uint) 485 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 486 */ 487 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 488 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 489 490 /** 491 * DOC: disable_cu (charp) 492 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 493 */ 494 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 495 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 496 497 /** 498 * DOC: virtual_display (charp) 499 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 500 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 501 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 502 * device at 26:00.0. The default is NULL. 503 */ 504 MODULE_PARM_DESC(virtual_display, 505 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 506 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 507 508 /** 509 * DOC: job_hang_limit (int) 510 * Set how much time allow a job hang and not drop it. The default is 0. 511 */ 512 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 513 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 514 515 /** 516 * DOC: lbpw (int) 517 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 518 */ 519 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 520 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 521 522 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 523 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 524 525 /** 526 * DOC: gpu_recovery (int) 527 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 528 */ 529 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 530 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 531 532 /** 533 * DOC: emu_mode (int) 534 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 535 */ 536 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 537 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 538 539 /** 540 * DOC: ras_enable (int) 541 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 542 */ 543 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 544 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 545 546 /** 547 * DOC: ras_mask (uint) 548 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 549 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 550 */ 551 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 552 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 553 554 /** 555 * DOC: timeout_fatal_disable (bool) 556 * Disable Watchdog timeout fatal error event 557 */ 558 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 559 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 560 561 /** 562 * DOC: timeout_period (uint) 563 * Modify the watchdog timeout max_cycles as (1 << period) 564 */ 565 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 566 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 567 568 /** 569 * DOC: si_support (int) 570 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 571 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 572 * otherwise using amdgpu driver. 573 */ 574 #ifdef CONFIG_DRM_AMDGPU_SI 575 576 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 577 int amdgpu_si_support = 0; 578 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 579 #else 580 int amdgpu_si_support = 1; 581 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 582 #endif 583 584 module_param_named(si_support, amdgpu_si_support, int, 0444); 585 #endif 586 587 /** 588 * DOC: cik_support (int) 589 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 590 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 591 * otherwise using amdgpu driver. 592 */ 593 #ifdef CONFIG_DRM_AMDGPU_CIK 594 595 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 596 int amdgpu_cik_support = 0; 597 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 598 #else 599 int amdgpu_cik_support = 1; 600 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 601 #endif 602 603 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 604 #endif 605 606 /** 607 * DOC: smu_memory_pool_size (uint) 608 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 609 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 610 */ 611 MODULE_PARM_DESC(smu_memory_pool_size, 612 "reserve gtt for smu debug usage, 0 = disable," 613 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 614 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 615 616 /** 617 * DOC: async_gfx_ring (int) 618 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 619 */ 620 MODULE_PARM_DESC(async_gfx_ring, 621 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 622 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 623 624 /** 625 * DOC: mcbp (int) 626 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 627 */ 628 MODULE_PARM_DESC(mcbp, 629 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 630 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 631 632 /** 633 * DOC: discovery (int) 634 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 635 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 636 */ 637 MODULE_PARM_DESC(discovery, 638 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 639 module_param_named(discovery, amdgpu_discovery, int, 0444); 640 641 /** 642 * DOC: mes (int) 643 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 644 * (0 = disabled (default), 1 = enabled) 645 */ 646 MODULE_PARM_DESC(mes, 647 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 648 module_param_named(mes, amdgpu_mes, int, 0444); 649 650 /** 651 * DOC: noretry (int) 652 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 653 * do not support per-process XNACK this also disables retry page faults. 654 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 655 */ 656 MODULE_PARM_DESC(noretry, 657 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 658 module_param_named(noretry, amdgpu_noretry, int, 0644); 659 660 /** 661 * DOC: force_asic_type (int) 662 * A non negative value used to specify the asic type for all supported GPUs. 663 */ 664 MODULE_PARM_DESC(force_asic_type, 665 "A non negative value used to specify the asic type for all supported GPUs"); 666 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 667 668 669 670 #ifdef CONFIG_HSA_AMD 671 /** 672 * DOC: sched_policy (int) 673 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 674 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 675 * assigns queues to HQDs. 676 */ 677 int sched_policy = KFD_SCHED_POLICY_HWS; 678 module_param(sched_policy, int, 0444); 679 MODULE_PARM_DESC(sched_policy, 680 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 681 682 /** 683 * DOC: hws_max_conc_proc (int) 684 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 685 * number of VMIDs assigned to the HWS, which is also the default. 686 */ 687 int hws_max_conc_proc = 8; 688 module_param(hws_max_conc_proc, int, 0444); 689 MODULE_PARM_DESC(hws_max_conc_proc, 690 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 691 692 /** 693 * DOC: cwsr_enable (int) 694 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 695 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 696 * disables it. 697 */ 698 int cwsr_enable = 1; 699 module_param(cwsr_enable, int, 0444); 700 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 701 702 /** 703 * DOC: max_num_of_queues_per_device (int) 704 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 705 * is 4096. 706 */ 707 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 708 module_param(max_num_of_queues_per_device, int, 0444); 709 MODULE_PARM_DESC(max_num_of_queues_per_device, 710 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 711 712 /** 713 * DOC: send_sigterm (int) 714 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 715 * but just print errors on dmesg. Setting 1 enables sending sigterm. 716 */ 717 int send_sigterm; 718 module_param(send_sigterm, int, 0444); 719 MODULE_PARM_DESC(send_sigterm, 720 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 721 722 /** 723 * DOC: debug_largebar (int) 724 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 725 * system. This limits the VRAM size reported to ROCm applications to the visible 726 * size, usually 256MB. 727 * Default value is 0, diabled. 728 */ 729 int debug_largebar; 730 module_param(debug_largebar, int, 0444); 731 MODULE_PARM_DESC(debug_largebar, 732 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 733 734 /** 735 * DOC: ignore_crat (int) 736 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 737 * table to get information about AMD APUs. This option can serve as a workaround on 738 * systems with a broken CRAT table. 739 * 740 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 741 * whehter use CRAT) 742 */ 743 int ignore_crat; 744 module_param(ignore_crat, int, 0444); 745 MODULE_PARM_DESC(ignore_crat, 746 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 747 748 /** 749 * DOC: halt_if_hws_hang (int) 750 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 751 * Setting 1 enables halt on hang. 752 */ 753 int halt_if_hws_hang; 754 module_param(halt_if_hws_hang, int, 0644); 755 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 756 757 /** 758 * DOC: hws_gws_support(bool) 759 * Assume that HWS supports GWS barriers regardless of what firmware version 760 * check says. Default value: false (rely on MEC2 firmware version check). 761 */ 762 bool hws_gws_support; 763 module_param(hws_gws_support, bool, 0444); 764 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 765 766 /** 767 * DOC: queue_preemption_timeout_ms (int) 768 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 769 */ 770 int queue_preemption_timeout_ms = 9000; 771 module_param(queue_preemption_timeout_ms, int, 0644); 772 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 773 774 /** 775 * DOC: debug_evictions(bool) 776 * Enable extra debug messages to help determine the cause of evictions 777 */ 778 bool debug_evictions; 779 module_param(debug_evictions, bool, 0644); 780 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 781 782 /** 783 * DOC: no_system_mem_limit(bool) 784 * Disable system memory limit, to support multiple process shared memory 785 */ 786 bool no_system_mem_limit; 787 module_param(no_system_mem_limit, bool, 0644); 788 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 789 790 /** 791 * DOC: no_queue_eviction_on_vm_fault (int) 792 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 793 */ 794 int amdgpu_no_queue_eviction_on_vm_fault = 0; 795 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 796 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 797 #endif 798 799 /** 800 * DOC: dcfeaturemask (uint) 801 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 802 * The default is the current set of stable display features. 803 */ 804 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 805 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 806 807 /** 808 * DOC: dcdebugmask (uint) 809 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 810 */ 811 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 812 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 813 814 /** 815 * DOC: abmlevel (uint) 816 * Override the default ABM (Adaptive Backlight Management) level used for DC 817 * enabled hardware. Requires DMCU to be supported and loaded. 818 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 819 * default. Values 1-4 control the maximum allowable brightness reduction via 820 * the ABM algorithm, with 1 being the least reduction and 4 being the most 821 * reduction. 822 * 823 * Defaults to 0, or disabled. Userspace can still override this level later 824 * after boot. 825 */ 826 uint amdgpu_dm_abm_level; 827 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 828 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 829 830 int amdgpu_backlight = -1; 831 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 832 module_param_named(backlight, amdgpu_backlight, bint, 0444); 833 834 /** 835 * DOC: tmz (int) 836 * Trusted Memory Zone (TMZ) is a method to protect data being written 837 * to or read from memory. 838 * 839 * The default value: 0 (off). TODO: change to auto till it is completed. 840 */ 841 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 842 module_param_named(tmz, amdgpu_tmz, int, 0444); 843 844 /** 845 * DOC: freesync_video (uint) 846 * Enable the optimization to adjust front porch timing to achieve seamless 847 * mode change experience when setting a freesync supported mode for which full 848 * modeset is not needed. 849 * 850 * The Display Core will add a set of modes derived from the base FreeSync 851 * video mode into the corresponding connector's mode list based on commonly 852 * used refresh rates and VRR range of the connected display, when users enable 853 * this feature. From the userspace perspective, they can see a seamless mode 854 * change experience when the change between different refresh rates under the 855 * same resolution. Additionally, userspace applications such as Video playback 856 * can read this modeset list and change the refresh rate based on the video 857 * frame rate. Finally, the userspace can also derive an appropriate mode for a 858 * particular refresh rate based on the FreeSync Mode and add it to the 859 * connector's mode list. 860 * 861 * Note: This is an experimental feature. 862 * 863 * The default value: 0 (off). 864 */ 865 MODULE_PARM_DESC( 866 freesync_video, 867 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 868 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 869 870 /** 871 * DOC: reset_method (int) 872 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 873 */ 874 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 875 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 876 877 /** 878 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 879 * threshold value of faulty pages detected by RAS ECC, which may 880 * result in the GPU entering bad status when the number of total 881 * faulty pages by ECC exceeds the threshold value. 882 */ 883 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 884 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 885 886 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 887 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 888 889 /** 890 * DOC: smu_pptable_id (int) 891 * Used to override pptable id. id = 0 use VBIOS pptable. 892 * id > 0 use the soft pptable with specicfied id. 893 */ 894 MODULE_PARM_DESC(smu_pptable_id, 895 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 896 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 897 898 /* These devices are not supported by amdgpu. 899 * They are supported by the mach64, r128, radeon drivers 900 */ 901 static const u16 amdgpu_unsupported_pciidlist[] = { 902 /* mach64 */ 903 0x4354, 904 0x4358, 905 0x4554, 906 0x4742, 907 0x4744, 908 0x4749, 909 0x474C, 910 0x474D, 911 0x474E, 912 0x474F, 913 0x4750, 914 0x4751, 915 0x4752, 916 0x4753, 917 0x4754, 918 0x4755, 919 0x4756, 920 0x4757, 921 0x4758, 922 0x4759, 923 0x475A, 924 0x4C42, 925 0x4C44, 926 0x4C47, 927 0x4C49, 928 0x4C4D, 929 0x4C4E, 930 0x4C50, 931 0x4C51, 932 0x4C52, 933 0x4C53, 934 0x5654, 935 0x5655, 936 0x5656, 937 /* r128 */ 938 0x4c45, 939 0x4c46, 940 0x4d46, 941 0x4d4c, 942 0x5041, 943 0x5042, 944 0x5043, 945 0x5044, 946 0x5045, 947 0x5046, 948 0x5047, 949 0x5048, 950 0x5049, 951 0x504A, 952 0x504B, 953 0x504C, 954 0x504D, 955 0x504E, 956 0x504F, 957 0x5050, 958 0x5051, 959 0x5052, 960 0x5053, 961 0x5054, 962 0x5055, 963 0x5056, 964 0x5057, 965 0x5058, 966 0x5245, 967 0x5246, 968 0x5247, 969 0x524b, 970 0x524c, 971 0x534d, 972 0x5446, 973 0x544C, 974 0x5452, 975 /* radeon */ 976 0x3150, 977 0x3151, 978 0x3152, 979 0x3154, 980 0x3155, 981 0x3E50, 982 0x3E54, 983 0x4136, 984 0x4137, 985 0x4144, 986 0x4145, 987 0x4146, 988 0x4147, 989 0x4148, 990 0x4149, 991 0x414A, 992 0x414B, 993 0x4150, 994 0x4151, 995 0x4152, 996 0x4153, 997 0x4154, 998 0x4155, 999 0x4156, 1000 0x4237, 1001 0x4242, 1002 0x4336, 1003 0x4337, 1004 0x4437, 1005 0x4966, 1006 0x4967, 1007 0x4A48, 1008 0x4A49, 1009 0x4A4A, 1010 0x4A4B, 1011 0x4A4C, 1012 0x4A4D, 1013 0x4A4E, 1014 0x4A4F, 1015 0x4A50, 1016 0x4A54, 1017 0x4B48, 1018 0x4B49, 1019 0x4B4A, 1020 0x4B4B, 1021 0x4B4C, 1022 0x4C57, 1023 0x4C58, 1024 0x4C59, 1025 0x4C5A, 1026 0x4C64, 1027 0x4C66, 1028 0x4C67, 1029 0x4E44, 1030 0x4E45, 1031 0x4E46, 1032 0x4E47, 1033 0x4E48, 1034 0x4E49, 1035 0x4E4A, 1036 0x4E4B, 1037 0x4E50, 1038 0x4E51, 1039 0x4E52, 1040 0x4E53, 1041 0x4E54, 1042 0x4E56, 1043 0x5144, 1044 0x5145, 1045 0x5146, 1046 0x5147, 1047 0x5148, 1048 0x514C, 1049 0x514D, 1050 0x5157, 1051 0x5158, 1052 0x5159, 1053 0x515A, 1054 0x515E, 1055 0x5460, 1056 0x5462, 1057 0x5464, 1058 0x5548, 1059 0x5549, 1060 0x554A, 1061 0x554B, 1062 0x554C, 1063 0x554D, 1064 0x554E, 1065 0x554F, 1066 0x5550, 1067 0x5551, 1068 0x5552, 1069 0x5554, 1070 0x564A, 1071 0x564B, 1072 0x564F, 1073 0x5652, 1074 0x5653, 1075 0x5657, 1076 0x5834, 1077 0x5835, 1078 0x5954, 1079 0x5955, 1080 0x5974, 1081 0x5975, 1082 0x5960, 1083 0x5961, 1084 0x5962, 1085 0x5964, 1086 0x5965, 1087 0x5969, 1088 0x5a41, 1089 0x5a42, 1090 0x5a61, 1091 0x5a62, 1092 0x5b60, 1093 0x5b62, 1094 0x5b63, 1095 0x5b64, 1096 0x5b65, 1097 0x5c61, 1098 0x5c63, 1099 0x5d48, 1100 0x5d49, 1101 0x5d4a, 1102 0x5d4c, 1103 0x5d4d, 1104 0x5d4e, 1105 0x5d4f, 1106 0x5d50, 1107 0x5d52, 1108 0x5d57, 1109 0x5e48, 1110 0x5e4a, 1111 0x5e4b, 1112 0x5e4c, 1113 0x5e4d, 1114 0x5e4f, 1115 0x6700, 1116 0x6701, 1117 0x6702, 1118 0x6703, 1119 0x6704, 1120 0x6705, 1121 0x6706, 1122 0x6707, 1123 0x6708, 1124 0x6709, 1125 0x6718, 1126 0x6719, 1127 0x671c, 1128 0x671d, 1129 0x671f, 1130 0x6720, 1131 0x6721, 1132 0x6722, 1133 0x6723, 1134 0x6724, 1135 0x6725, 1136 0x6726, 1137 0x6727, 1138 0x6728, 1139 0x6729, 1140 0x6738, 1141 0x6739, 1142 0x673e, 1143 0x6740, 1144 0x6741, 1145 0x6742, 1146 0x6743, 1147 0x6744, 1148 0x6745, 1149 0x6746, 1150 0x6747, 1151 0x6748, 1152 0x6749, 1153 0x674A, 1154 0x6750, 1155 0x6751, 1156 0x6758, 1157 0x6759, 1158 0x675B, 1159 0x675D, 1160 0x675F, 1161 0x6760, 1162 0x6761, 1163 0x6762, 1164 0x6763, 1165 0x6764, 1166 0x6765, 1167 0x6766, 1168 0x6767, 1169 0x6768, 1170 0x6770, 1171 0x6771, 1172 0x6772, 1173 0x6778, 1174 0x6779, 1175 0x677B, 1176 0x6840, 1177 0x6841, 1178 0x6842, 1179 0x6843, 1180 0x6849, 1181 0x684C, 1182 0x6850, 1183 0x6858, 1184 0x6859, 1185 0x6880, 1186 0x6888, 1187 0x6889, 1188 0x688A, 1189 0x688C, 1190 0x688D, 1191 0x6898, 1192 0x6899, 1193 0x689b, 1194 0x689c, 1195 0x689d, 1196 0x689e, 1197 0x68a0, 1198 0x68a1, 1199 0x68a8, 1200 0x68a9, 1201 0x68b0, 1202 0x68b8, 1203 0x68b9, 1204 0x68ba, 1205 0x68be, 1206 0x68bf, 1207 0x68c0, 1208 0x68c1, 1209 0x68c7, 1210 0x68c8, 1211 0x68c9, 1212 0x68d8, 1213 0x68d9, 1214 0x68da, 1215 0x68de, 1216 0x68e0, 1217 0x68e1, 1218 0x68e4, 1219 0x68e5, 1220 0x68e8, 1221 0x68e9, 1222 0x68f1, 1223 0x68f2, 1224 0x68f8, 1225 0x68f9, 1226 0x68fa, 1227 0x68fe, 1228 0x7100, 1229 0x7101, 1230 0x7102, 1231 0x7103, 1232 0x7104, 1233 0x7105, 1234 0x7106, 1235 0x7108, 1236 0x7109, 1237 0x710A, 1238 0x710B, 1239 0x710C, 1240 0x710E, 1241 0x710F, 1242 0x7140, 1243 0x7141, 1244 0x7142, 1245 0x7143, 1246 0x7144, 1247 0x7145, 1248 0x7146, 1249 0x7147, 1250 0x7149, 1251 0x714A, 1252 0x714B, 1253 0x714C, 1254 0x714D, 1255 0x714E, 1256 0x714F, 1257 0x7151, 1258 0x7152, 1259 0x7153, 1260 0x715E, 1261 0x715F, 1262 0x7180, 1263 0x7181, 1264 0x7183, 1265 0x7186, 1266 0x7187, 1267 0x7188, 1268 0x718A, 1269 0x718B, 1270 0x718C, 1271 0x718D, 1272 0x718F, 1273 0x7193, 1274 0x7196, 1275 0x719B, 1276 0x719F, 1277 0x71C0, 1278 0x71C1, 1279 0x71C2, 1280 0x71C3, 1281 0x71C4, 1282 0x71C5, 1283 0x71C6, 1284 0x71C7, 1285 0x71CD, 1286 0x71CE, 1287 0x71D2, 1288 0x71D4, 1289 0x71D5, 1290 0x71D6, 1291 0x71DA, 1292 0x71DE, 1293 0x7200, 1294 0x7210, 1295 0x7211, 1296 0x7240, 1297 0x7243, 1298 0x7244, 1299 0x7245, 1300 0x7246, 1301 0x7247, 1302 0x7248, 1303 0x7249, 1304 0x724A, 1305 0x724B, 1306 0x724C, 1307 0x724D, 1308 0x724E, 1309 0x724F, 1310 0x7280, 1311 0x7281, 1312 0x7283, 1313 0x7284, 1314 0x7287, 1315 0x7288, 1316 0x7289, 1317 0x728B, 1318 0x728C, 1319 0x7290, 1320 0x7291, 1321 0x7293, 1322 0x7297, 1323 0x7834, 1324 0x7835, 1325 0x791e, 1326 0x791f, 1327 0x793f, 1328 0x7941, 1329 0x7942, 1330 0x796c, 1331 0x796d, 1332 0x796e, 1333 0x796f, 1334 0x9400, 1335 0x9401, 1336 0x9402, 1337 0x9403, 1338 0x9405, 1339 0x940A, 1340 0x940B, 1341 0x940F, 1342 0x94A0, 1343 0x94A1, 1344 0x94A3, 1345 0x94B1, 1346 0x94B3, 1347 0x94B4, 1348 0x94B5, 1349 0x94B9, 1350 0x9440, 1351 0x9441, 1352 0x9442, 1353 0x9443, 1354 0x9444, 1355 0x9446, 1356 0x944A, 1357 0x944B, 1358 0x944C, 1359 0x944E, 1360 0x9450, 1361 0x9452, 1362 0x9456, 1363 0x945A, 1364 0x945B, 1365 0x945E, 1366 0x9460, 1367 0x9462, 1368 0x946A, 1369 0x946B, 1370 0x947A, 1371 0x947B, 1372 0x9480, 1373 0x9487, 1374 0x9488, 1375 0x9489, 1376 0x948A, 1377 0x948F, 1378 0x9490, 1379 0x9491, 1380 0x9495, 1381 0x9498, 1382 0x949C, 1383 0x949E, 1384 0x949F, 1385 0x94C0, 1386 0x94C1, 1387 0x94C3, 1388 0x94C4, 1389 0x94C5, 1390 0x94C6, 1391 0x94C7, 1392 0x94C8, 1393 0x94C9, 1394 0x94CB, 1395 0x94CC, 1396 0x94CD, 1397 0x9500, 1398 0x9501, 1399 0x9504, 1400 0x9505, 1401 0x9506, 1402 0x9507, 1403 0x9508, 1404 0x9509, 1405 0x950F, 1406 0x9511, 1407 0x9515, 1408 0x9517, 1409 0x9519, 1410 0x9540, 1411 0x9541, 1412 0x9542, 1413 0x954E, 1414 0x954F, 1415 0x9552, 1416 0x9553, 1417 0x9555, 1418 0x9557, 1419 0x955f, 1420 0x9580, 1421 0x9581, 1422 0x9583, 1423 0x9586, 1424 0x9587, 1425 0x9588, 1426 0x9589, 1427 0x958A, 1428 0x958B, 1429 0x958C, 1430 0x958D, 1431 0x958E, 1432 0x958F, 1433 0x9590, 1434 0x9591, 1435 0x9593, 1436 0x9595, 1437 0x9596, 1438 0x9597, 1439 0x9598, 1440 0x9599, 1441 0x959B, 1442 0x95C0, 1443 0x95C2, 1444 0x95C4, 1445 0x95C5, 1446 0x95C6, 1447 0x95C7, 1448 0x95C9, 1449 0x95CC, 1450 0x95CD, 1451 0x95CE, 1452 0x95CF, 1453 0x9610, 1454 0x9611, 1455 0x9612, 1456 0x9613, 1457 0x9614, 1458 0x9615, 1459 0x9616, 1460 0x9640, 1461 0x9641, 1462 0x9642, 1463 0x9643, 1464 0x9644, 1465 0x9645, 1466 0x9647, 1467 0x9648, 1468 0x9649, 1469 0x964a, 1470 0x964b, 1471 0x964c, 1472 0x964e, 1473 0x964f, 1474 0x9710, 1475 0x9711, 1476 0x9712, 1477 0x9713, 1478 0x9714, 1479 0x9715, 1480 0x9802, 1481 0x9803, 1482 0x9804, 1483 0x9805, 1484 0x9806, 1485 0x9807, 1486 0x9808, 1487 0x9809, 1488 0x980A, 1489 0x9900, 1490 0x9901, 1491 0x9903, 1492 0x9904, 1493 0x9905, 1494 0x9906, 1495 0x9907, 1496 0x9908, 1497 0x9909, 1498 0x990A, 1499 0x990B, 1500 0x990C, 1501 0x990D, 1502 0x990E, 1503 0x990F, 1504 0x9910, 1505 0x9913, 1506 0x9917, 1507 0x9918, 1508 0x9919, 1509 0x9990, 1510 0x9991, 1511 0x9992, 1512 0x9993, 1513 0x9994, 1514 0x9995, 1515 0x9996, 1516 0x9997, 1517 0x9998, 1518 0x9999, 1519 0x999A, 1520 0x999B, 1521 0x999C, 1522 0x999D, 1523 0x99A0, 1524 0x99A2, 1525 0x99A4, 1526 }; 1527 1528 static const struct pci_device_id pciidlist[] = { 1529 #ifdef CONFIG_DRM_AMDGPU_SI 1530 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1531 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1532 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1533 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1534 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1535 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1536 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1537 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1538 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1539 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1540 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1541 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1542 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1543 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1544 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1545 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1546 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1547 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1548 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1549 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1550 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1551 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1552 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1553 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1554 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1555 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1556 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1557 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1558 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1559 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1560 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1561 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1562 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1563 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1564 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1565 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1566 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1567 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1568 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1569 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1570 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1571 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1572 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1573 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1574 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1575 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1576 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1577 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1578 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1579 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1580 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1581 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1582 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1583 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1584 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1585 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1586 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1587 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1588 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1589 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1590 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1591 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1592 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1593 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1594 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1595 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1596 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1597 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1598 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1599 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1600 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1601 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1602 #endif 1603 #ifdef CONFIG_DRM_AMDGPU_CIK 1604 /* Kaveri */ 1605 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1606 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1607 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1608 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1609 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1610 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1611 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1612 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1613 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1614 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1615 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1616 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1617 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1618 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1619 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1620 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1621 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1622 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1623 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1624 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1625 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1626 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1627 /* Bonaire */ 1628 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1630 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1631 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1632 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1633 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1634 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1635 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1636 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1637 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1638 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1639 /* Hawaii */ 1640 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1641 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1642 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1643 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1644 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1645 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1646 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1647 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1648 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1649 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1650 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1651 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1652 /* Kabini */ 1653 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1654 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1655 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1656 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1657 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1658 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1659 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1660 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1661 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1662 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1663 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1664 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1665 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1666 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1667 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1668 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1669 /* mullins */ 1670 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1671 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1672 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1673 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1674 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1675 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1676 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1677 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1678 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1679 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1680 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1681 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1682 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1683 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1684 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1685 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1686 #endif 1687 /* topaz */ 1688 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1689 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1690 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1691 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1692 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1693 /* tonga */ 1694 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1695 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1696 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1697 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1698 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1699 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1700 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1701 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1702 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1703 /* fiji */ 1704 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1705 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1706 /* carrizo */ 1707 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1708 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1709 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1710 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1711 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1712 /* stoney */ 1713 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1714 /* Polaris11 */ 1715 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1716 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1717 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1718 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1719 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1720 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1721 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1722 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1723 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1724 /* Polaris10 */ 1725 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1726 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1727 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1728 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1729 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1730 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1731 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1732 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1733 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1734 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1735 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1736 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1737 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1738 /* Polaris12 */ 1739 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1740 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1741 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1742 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1743 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1744 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1745 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1746 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1747 /* VEGAM */ 1748 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1749 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1750 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1751 /* Vega 10 */ 1752 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1753 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1754 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1755 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1756 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1757 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1758 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1759 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1760 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1761 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1762 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1763 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1764 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1765 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1766 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1767 /* Vega 12 */ 1768 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1769 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1770 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1771 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1772 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1773 /* Vega 20 */ 1774 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1775 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1776 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1777 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1778 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1779 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1780 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1781 /* Raven */ 1782 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1783 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1784 /* Arcturus */ 1785 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1786 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1787 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1788 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1789 /* Navi10 */ 1790 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1791 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1792 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1793 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1794 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1795 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1796 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1797 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1798 /* Navi14 */ 1799 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1800 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1801 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1802 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1803 1804 /* Renoir */ 1805 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1806 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1807 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1808 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1809 1810 /* Navi12 */ 1811 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1812 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1813 1814 /* Sienna_Cichlid */ 1815 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1816 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1817 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1818 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1819 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1820 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1821 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1822 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1823 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1824 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1825 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1826 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1827 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1828 1829 /* Van Gogh */ 1830 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1831 1832 /* Yellow Carp */ 1833 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1834 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1835 1836 /* Navy_Flounder */ 1837 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1838 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1839 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1840 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1841 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1842 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1843 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1844 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1845 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1846 1847 /* DIMGREY_CAVEFISH */ 1848 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1849 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1850 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1851 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1852 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1853 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1854 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1855 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1856 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1857 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1858 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1859 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1860 1861 /* Aldebaran */ 1862 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1863 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1864 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1865 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1866 1867 /* CYAN_SKILLFISH */ 1868 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1869 1870 /* BEIGE_GOBY */ 1871 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1872 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1873 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1874 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1875 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1876 1877 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1878 .class = PCI_CLASS_DISPLAY_VGA << 8, 1879 .class_mask = 0xffffff, 1880 .driver_data = CHIP_IP_DISCOVERY }, 1881 1882 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1883 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1884 .class_mask = 0xffffff, 1885 .driver_data = CHIP_IP_DISCOVERY }, 1886 1887 {0, 0, 0} 1888 }; 1889 1890 MODULE_DEVICE_TABLE(pci, pciidlist); 1891 1892 static const struct drm_driver amdgpu_kms_driver; 1893 1894 static bool amdgpu_is_fw_framebuffer(resource_size_t base, 1895 resource_size_t size) 1896 { 1897 bool found = false; 1898 #if IS_REACHABLE(CONFIG_FB) 1899 struct apertures_struct *a; 1900 1901 a = alloc_apertures(1); 1902 if (!a) 1903 return false; 1904 1905 a->ranges[0].base = base; 1906 a->ranges[0].size = size; 1907 1908 found = is_firmware_framebuffer(a); 1909 kfree(a); 1910 #endif 1911 return found; 1912 } 1913 1914 static int amdgpu_pci_probe(struct pci_dev *pdev, 1915 const struct pci_device_id *ent) 1916 { 1917 struct drm_device *ddev; 1918 struct amdgpu_device *adev; 1919 unsigned long flags = ent->driver_data; 1920 int ret, retry = 0, i; 1921 bool supports_atomic = false; 1922 bool is_fw_fb; 1923 resource_size_t base, size; 1924 1925 /* skip devices which are owned by radeon */ 1926 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1927 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 1928 return -ENODEV; 1929 } 1930 1931 if (flags == 0) { 1932 DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n"); 1933 return -ENODEV; 1934 } 1935 1936 if (amdgpu_virtual_display || 1937 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1938 supports_atomic = true; 1939 1940 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1941 DRM_INFO("This hardware requires experimental hardware support.\n" 1942 "See modparam exp_hw_support\n"); 1943 return -ENODEV; 1944 } 1945 1946 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1947 * however, SME requires an indirect IOMMU mapping because the encryption 1948 * bit is beyond the DMA mask of the chip. 1949 */ 1950 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 1951 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1952 dev_info(&pdev->dev, 1953 "SME is not compatible with RAVEN\n"); 1954 return -ENOTSUPP; 1955 } 1956 1957 #ifdef CONFIG_DRM_AMDGPU_SI 1958 if (!amdgpu_si_support) { 1959 switch (flags & AMD_ASIC_MASK) { 1960 case CHIP_TAHITI: 1961 case CHIP_PITCAIRN: 1962 case CHIP_VERDE: 1963 case CHIP_OLAND: 1964 case CHIP_HAINAN: 1965 dev_info(&pdev->dev, 1966 "SI support provided by radeon.\n"); 1967 dev_info(&pdev->dev, 1968 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1969 ); 1970 return -ENODEV; 1971 } 1972 } 1973 #endif 1974 #ifdef CONFIG_DRM_AMDGPU_CIK 1975 if (!amdgpu_cik_support) { 1976 switch (flags & AMD_ASIC_MASK) { 1977 case CHIP_KAVERI: 1978 case CHIP_BONAIRE: 1979 case CHIP_HAWAII: 1980 case CHIP_KABINI: 1981 case CHIP_MULLINS: 1982 dev_info(&pdev->dev, 1983 "CIK support provided by radeon.\n"); 1984 dev_info(&pdev->dev, 1985 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1986 ); 1987 return -ENODEV; 1988 } 1989 } 1990 #endif 1991 1992 base = pci_resource_start(pdev, 0); 1993 size = pci_resource_len(pdev, 0); 1994 is_fw_fb = amdgpu_is_fw_framebuffer(base, size); 1995 1996 /* Get rid of things like offb */ 1997 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 1998 if (ret) 1999 return ret; 2000 2001 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2002 if (IS_ERR(adev)) 2003 return PTR_ERR(adev); 2004 2005 adev->dev = &pdev->dev; 2006 adev->pdev = pdev; 2007 ddev = adev_to_drm(adev); 2008 adev->is_fw_fb = is_fw_fb; 2009 2010 if (!supports_atomic) 2011 ddev->driver_features &= ~DRIVER_ATOMIC; 2012 2013 ret = pci_enable_device(pdev); 2014 if (ret) 2015 return ret; 2016 2017 pci_set_drvdata(pdev, ddev); 2018 2019 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2020 if (ret) 2021 goto err_pci; 2022 2023 retry_init: 2024 ret = drm_dev_register(ddev, ent->driver_data); 2025 if (ret == -EAGAIN && ++retry <= 3) { 2026 DRM_INFO("retry init %d\n", retry); 2027 /* Don't request EX mode too frequently which is attacking */ 2028 msleep(5000); 2029 goto retry_init; 2030 } else if (ret) { 2031 goto err_pci; 2032 } 2033 2034 ret = amdgpu_debugfs_init(adev); 2035 if (ret) 2036 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2037 2038 return 0; 2039 2040 err_pci: 2041 pci_disable_device(pdev); 2042 return ret; 2043 } 2044 2045 static void 2046 amdgpu_pci_remove(struct pci_dev *pdev) 2047 { 2048 struct drm_device *dev = pci_get_drvdata(pdev); 2049 2050 drm_dev_unplug(dev); 2051 amdgpu_driver_unload_kms(dev); 2052 2053 /* 2054 * Flush any in flight DMA operations from device. 2055 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2056 * StatusTransactions Pending bit. 2057 */ 2058 pci_disable_device(pdev); 2059 pci_wait_for_pending_transaction(pdev); 2060 } 2061 2062 static void 2063 amdgpu_pci_shutdown(struct pci_dev *pdev) 2064 { 2065 struct drm_device *dev = pci_get_drvdata(pdev); 2066 struct amdgpu_device *adev = drm_to_adev(dev); 2067 2068 if (amdgpu_ras_intr_triggered()) 2069 return; 2070 2071 /* if we are running in a VM, make sure the device 2072 * torn down properly on reboot/shutdown. 2073 * unfortunately we can't detect certain 2074 * hypervisors so just do this all the time. 2075 */ 2076 if (!amdgpu_passthrough(adev)) 2077 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2078 amdgpu_device_ip_suspend(adev); 2079 adev->mp1_state = PP_MP1_STATE_NONE; 2080 } 2081 2082 /** 2083 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2084 * 2085 * @work: work_struct. 2086 */ 2087 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2088 { 2089 struct list_head device_list; 2090 struct amdgpu_device *adev; 2091 int i, r; 2092 struct amdgpu_reset_context reset_context; 2093 2094 memset(&reset_context, 0, sizeof(reset_context)); 2095 2096 mutex_lock(&mgpu_info.mutex); 2097 if (mgpu_info.pending_reset == true) { 2098 mutex_unlock(&mgpu_info.mutex); 2099 return; 2100 } 2101 mgpu_info.pending_reset = true; 2102 mutex_unlock(&mgpu_info.mutex); 2103 2104 /* Use a common context, just need to make sure full reset is done */ 2105 reset_context.method = AMD_RESET_METHOD_NONE; 2106 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2107 2108 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2109 adev = mgpu_info.gpu_ins[i].adev; 2110 reset_context.reset_req_dev = adev; 2111 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2112 if (r) { 2113 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2114 r, adev_to_drm(adev)->unique); 2115 } 2116 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2117 r = -EALREADY; 2118 } 2119 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2120 adev = mgpu_info.gpu_ins[i].adev; 2121 flush_work(&adev->xgmi_reset_work); 2122 adev->gmc.xgmi.pending_reset = false; 2123 } 2124 2125 /* reset function will rebuild the xgmi hive info , clear it now */ 2126 for (i = 0; i < mgpu_info.num_dgpu; i++) 2127 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2128 2129 INIT_LIST_HEAD(&device_list); 2130 2131 for (i = 0; i < mgpu_info.num_dgpu; i++) 2132 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2133 2134 /* unregister the GPU first, reset function will add them back */ 2135 list_for_each_entry(adev, &device_list, reset_list) 2136 amdgpu_unregister_gpu_instance(adev); 2137 2138 /* Use a common context, just need to make sure full reset is done */ 2139 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2140 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2141 2142 if (r) { 2143 DRM_ERROR("reinit gpus failure"); 2144 return; 2145 } 2146 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2147 adev = mgpu_info.gpu_ins[i].adev; 2148 if (!adev->kfd.init_complete) 2149 amdgpu_amdkfd_device_init(adev); 2150 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2151 } 2152 return; 2153 } 2154 2155 static int amdgpu_pmops_prepare(struct device *dev) 2156 { 2157 struct drm_device *drm_dev = dev_get_drvdata(dev); 2158 2159 /* Return a positive number here so 2160 * DPM_FLAG_SMART_SUSPEND works properly 2161 */ 2162 if (amdgpu_device_supports_boco(drm_dev)) 2163 return pm_runtime_suspended(dev) && 2164 pm_suspend_via_firmware(); 2165 2166 return 0; 2167 } 2168 2169 static void amdgpu_pmops_complete(struct device *dev) 2170 { 2171 /* nothing to do */ 2172 } 2173 2174 static int amdgpu_pmops_suspend(struct device *dev) 2175 { 2176 struct drm_device *drm_dev = dev_get_drvdata(dev); 2177 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2178 int r; 2179 2180 if (amdgpu_acpi_is_s0ix_active(adev)) 2181 adev->in_s0ix = true; 2182 adev->in_s3 = true; 2183 r = amdgpu_device_suspend(drm_dev, true); 2184 adev->in_s3 = false; 2185 if (r) 2186 return r; 2187 if (!adev->in_s0ix) 2188 r = amdgpu_asic_reset(adev); 2189 return r; 2190 } 2191 2192 static int amdgpu_pmops_resume(struct device *dev) 2193 { 2194 struct drm_device *drm_dev = dev_get_drvdata(dev); 2195 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2196 int r; 2197 2198 /* Avoids registers access if device is physically gone */ 2199 if (!pci_device_is_present(adev->pdev)) 2200 adev->no_hw_access = true; 2201 2202 r = amdgpu_device_resume(drm_dev, true); 2203 if (amdgpu_acpi_is_s0ix_active(adev)) 2204 adev->in_s0ix = false; 2205 return r; 2206 } 2207 2208 static int amdgpu_pmops_freeze(struct device *dev) 2209 { 2210 struct drm_device *drm_dev = dev_get_drvdata(dev); 2211 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2212 int r; 2213 2214 adev->in_s4 = true; 2215 r = amdgpu_device_suspend(drm_dev, true); 2216 adev->in_s4 = false; 2217 if (r) 2218 return r; 2219 return amdgpu_asic_reset(adev); 2220 } 2221 2222 static int amdgpu_pmops_thaw(struct device *dev) 2223 { 2224 struct drm_device *drm_dev = dev_get_drvdata(dev); 2225 2226 return amdgpu_device_resume(drm_dev, true); 2227 } 2228 2229 static int amdgpu_pmops_poweroff(struct device *dev) 2230 { 2231 struct drm_device *drm_dev = dev_get_drvdata(dev); 2232 2233 return amdgpu_device_suspend(drm_dev, true); 2234 } 2235 2236 static int amdgpu_pmops_restore(struct device *dev) 2237 { 2238 struct drm_device *drm_dev = dev_get_drvdata(dev); 2239 2240 return amdgpu_device_resume(drm_dev, true); 2241 } 2242 2243 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2244 { 2245 struct pci_dev *pdev = to_pci_dev(dev); 2246 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2247 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2248 int ret, i; 2249 2250 if (!adev->runpm) { 2251 pm_runtime_forbid(dev); 2252 return -EBUSY; 2253 } 2254 2255 /* wait for all rings to drain before suspending */ 2256 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2257 struct amdgpu_ring *ring = adev->rings[i]; 2258 if (ring && ring->sched.ready) { 2259 ret = amdgpu_fence_wait_empty(ring); 2260 if (ret) 2261 return -EBUSY; 2262 } 2263 } 2264 2265 adev->in_runpm = true; 2266 if (amdgpu_device_supports_px(drm_dev)) 2267 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2268 2269 /* 2270 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2271 * proper cleanups and put itself into a state ready for PNP. That 2272 * can address some random resuming failure observed on BOCO capable 2273 * platforms. 2274 * TODO: this may be also needed for PX capable platform. 2275 */ 2276 if (amdgpu_device_supports_boco(drm_dev)) 2277 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2278 2279 ret = amdgpu_device_suspend(drm_dev, false); 2280 if (ret) { 2281 adev->in_runpm = false; 2282 if (amdgpu_device_supports_boco(drm_dev)) 2283 adev->mp1_state = PP_MP1_STATE_NONE; 2284 return ret; 2285 } 2286 2287 if (amdgpu_device_supports_boco(drm_dev)) 2288 adev->mp1_state = PP_MP1_STATE_NONE; 2289 2290 if (amdgpu_device_supports_px(drm_dev)) { 2291 /* Only need to handle PCI state in the driver for ATPX 2292 * PCI core handles it for _PR3. 2293 */ 2294 amdgpu_device_cache_pci_state(pdev); 2295 pci_disable_device(pdev); 2296 pci_ignore_hotplug(pdev); 2297 pci_set_power_state(pdev, PCI_D3cold); 2298 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2299 } else if (amdgpu_device_supports_boco(drm_dev)) { 2300 /* nothing to do */ 2301 } else if (amdgpu_device_supports_baco(drm_dev)) { 2302 amdgpu_device_baco_enter(drm_dev); 2303 } 2304 2305 return 0; 2306 } 2307 2308 static int amdgpu_pmops_runtime_resume(struct device *dev) 2309 { 2310 struct pci_dev *pdev = to_pci_dev(dev); 2311 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2312 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2313 int ret; 2314 2315 if (!adev->runpm) 2316 return -EINVAL; 2317 2318 /* Avoids registers access if device is physically gone */ 2319 if (!pci_device_is_present(adev->pdev)) 2320 adev->no_hw_access = true; 2321 2322 if (amdgpu_device_supports_px(drm_dev)) { 2323 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2324 2325 /* Only need to handle PCI state in the driver for ATPX 2326 * PCI core handles it for _PR3. 2327 */ 2328 pci_set_power_state(pdev, PCI_D0); 2329 amdgpu_device_load_pci_state(pdev); 2330 ret = pci_enable_device(pdev); 2331 if (ret) 2332 return ret; 2333 pci_set_master(pdev); 2334 } else if (amdgpu_device_supports_boco(drm_dev)) { 2335 /* Only need to handle PCI state in the driver for ATPX 2336 * PCI core handles it for _PR3. 2337 */ 2338 pci_set_master(pdev); 2339 } else if (amdgpu_device_supports_baco(drm_dev)) { 2340 amdgpu_device_baco_exit(drm_dev); 2341 } 2342 ret = amdgpu_device_resume(drm_dev, false); 2343 if (ret) 2344 return ret; 2345 2346 if (amdgpu_device_supports_px(drm_dev)) 2347 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2348 adev->in_runpm = false; 2349 return 0; 2350 } 2351 2352 static int amdgpu_pmops_runtime_idle(struct device *dev) 2353 { 2354 struct drm_device *drm_dev = dev_get_drvdata(dev); 2355 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2356 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2357 int ret = 1; 2358 2359 if (!adev->runpm) { 2360 pm_runtime_forbid(dev); 2361 return -EBUSY; 2362 } 2363 2364 if (amdgpu_device_has_dc_support(adev)) { 2365 struct drm_crtc *crtc; 2366 2367 drm_for_each_crtc(crtc, drm_dev) { 2368 drm_modeset_lock(&crtc->mutex, NULL); 2369 if (crtc->state->active) 2370 ret = -EBUSY; 2371 drm_modeset_unlock(&crtc->mutex); 2372 if (ret < 0) 2373 break; 2374 } 2375 2376 } else { 2377 struct drm_connector *list_connector; 2378 struct drm_connector_list_iter iter; 2379 2380 mutex_lock(&drm_dev->mode_config.mutex); 2381 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2382 2383 drm_connector_list_iter_begin(drm_dev, &iter); 2384 drm_for_each_connector_iter(list_connector, &iter) { 2385 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2386 ret = -EBUSY; 2387 break; 2388 } 2389 } 2390 2391 drm_connector_list_iter_end(&iter); 2392 2393 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2394 mutex_unlock(&drm_dev->mode_config.mutex); 2395 } 2396 2397 if (ret == -EBUSY) 2398 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2399 2400 pm_runtime_mark_last_busy(dev); 2401 pm_runtime_autosuspend(dev); 2402 return ret; 2403 } 2404 2405 long amdgpu_drm_ioctl(struct file *filp, 2406 unsigned int cmd, unsigned long arg) 2407 { 2408 struct drm_file *file_priv = filp->private_data; 2409 struct drm_device *dev; 2410 long ret; 2411 dev = file_priv->minor->dev; 2412 ret = pm_runtime_get_sync(dev->dev); 2413 if (ret < 0) 2414 goto out; 2415 2416 ret = drm_ioctl(filp, cmd, arg); 2417 2418 pm_runtime_mark_last_busy(dev->dev); 2419 out: 2420 pm_runtime_put_autosuspend(dev->dev); 2421 return ret; 2422 } 2423 2424 static const struct dev_pm_ops amdgpu_pm_ops = { 2425 .prepare = amdgpu_pmops_prepare, 2426 .complete = amdgpu_pmops_complete, 2427 .suspend = amdgpu_pmops_suspend, 2428 .resume = amdgpu_pmops_resume, 2429 .freeze = amdgpu_pmops_freeze, 2430 .thaw = amdgpu_pmops_thaw, 2431 .poweroff = amdgpu_pmops_poweroff, 2432 .restore = amdgpu_pmops_restore, 2433 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2434 .runtime_resume = amdgpu_pmops_runtime_resume, 2435 .runtime_idle = amdgpu_pmops_runtime_idle, 2436 }; 2437 2438 static int amdgpu_flush(struct file *f, fl_owner_t id) 2439 { 2440 struct drm_file *file_priv = f->private_data; 2441 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2442 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2443 2444 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2445 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2446 2447 return timeout >= 0 ? 0 : timeout; 2448 } 2449 2450 static const struct file_operations amdgpu_driver_kms_fops = { 2451 .owner = THIS_MODULE, 2452 .open = drm_open, 2453 .flush = amdgpu_flush, 2454 .release = drm_release, 2455 .unlocked_ioctl = amdgpu_drm_ioctl, 2456 .mmap = drm_gem_mmap, 2457 .poll = drm_poll, 2458 .read = drm_read, 2459 #ifdef CONFIG_COMPAT 2460 .compat_ioctl = amdgpu_kms_compat_ioctl, 2461 #endif 2462 #ifdef CONFIG_PROC_FS 2463 .show_fdinfo = amdgpu_show_fdinfo 2464 #endif 2465 }; 2466 2467 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2468 { 2469 struct drm_file *file; 2470 2471 if (!filp) 2472 return -EINVAL; 2473 2474 if (filp->f_op != &amdgpu_driver_kms_fops) { 2475 return -EINVAL; 2476 } 2477 2478 file = filp->private_data; 2479 *fpriv = file->driver_priv; 2480 return 0; 2481 } 2482 2483 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2484 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2485 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2486 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2487 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2488 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2489 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2490 /* KMS */ 2491 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2492 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2493 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2494 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2495 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2496 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2497 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2498 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2499 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2500 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2501 }; 2502 2503 static const struct drm_driver amdgpu_kms_driver = { 2504 .driver_features = 2505 DRIVER_ATOMIC | 2506 DRIVER_GEM | 2507 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2508 DRIVER_SYNCOBJ_TIMELINE, 2509 .open = amdgpu_driver_open_kms, 2510 .postclose = amdgpu_driver_postclose_kms, 2511 .lastclose = amdgpu_driver_lastclose_kms, 2512 .ioctls = amdgpu_ioctls_kms, 2513 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2514 .dumb_create = amdgpu_mode_dumb_create, 2515 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2516 .fops = &amdgpu_driver_kms_fops, 2517 .release = &amdgpu_driver_release_kms, 2518 2519 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2520 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2521 .gem_prime_import = amdgpu_gem_prime_import, 2522 .gem_prime_mmap = drm_gem_prime_mmap, 2523 2524 .name = DRIVER_NAME, 2525 .desc = DRIVER_DESC, 2526 .date = DRIVER_DATE, 2527 .major = KMS_DRIVER_MAJOR, 2528 .minor = KMS_DRIVER_MINOR, 2529 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2530 }; 2531 2532 static struct pci_error_handlers amdgpu_pci_err_handler = { 2533 .error_detected = amdgpu_pci_error_detected, 2534 .mmio_enabled = amdgpu_pci_mmio_enabled, 2535 .slot_reset = amdgpu_pci_slot_reset, 2536 .resume = amdgpu_pci_resume, 2537 }; 2538 2539 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2540 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2541 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2542 2543 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2544 &amdgpu_vram_mgr_attr_group, 2545 &amdgpu_gtt_mgr_attr_group, 2546 &amdgpu_vbios_version_attr_group, 2547 NULL, 2548 }; 2549 2550 2551 static struct pci_driver amdgpu_kms_pci_driver = { 2552 .name = DRIVER_NAME, 2553 .id_table = pciidlist, 2554 .probe = amdgpu_pci_probe, 2555 .remove = amdgpu_pci_remove, 2556 .shutdown = amdgpu_pci_shutdown, 2557 .driver.pm = &amdgpu_pm_ops, 2558 .err_handler = &amdgpu_pci_err_handler, 2559 .dev_groups = amdgpu_sysfs_groups, 2560 }; 2561 2562 static int __init amdgpu_init(void) 2563 { 2564 int r; 2565 2566 if (vgacon_text_force()) { 2567 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 2568 return -EINVAL; 2569 } 2570 2571 r = amdgpu_sync_init(); 2572 if (r) 2573 goto error_sync; 2574 2575 r = amdgpu_fence_slab_init(); 2576 if (r) 2577 goto error_fence; 2578 2579 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2580 amdgpu_register_atpx_handler(); 2581 amdgpu_acpi_detect(); 2582 2583 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2584 amdgpu_amdkfd_init(); 2585 2586 /* let modprobe override vga console setting */ 2587 return pci_register_driver(&amdgpu_kms_pci_driver); 2588 2589 error_fence: 2590 amdgpu_sync_fini(); 2591 2592 error_sync: 2593 return r; 2594 } 2595 2596 static void __exit amdgpu_exit(void) 2597 { 2598 amdgpu_amdkfd_fini(); 2599 pci_unregister_driver(&amdgpu_kms_pci_driver); 2600 amdgpu_unregister_atpx_handler(); 2601 amdgpu_sync_fini(); 2602 amdgpu_fence_slab_fini(); 2603 mmu_notifier_synchronize(); 2604 } 2605 2606 module_init(amdgpu_init); 2607 module_exit(amdgpu_exit); 2608 2609 MODULE_AUTHOR(DRIVER_AUTHOR); 2610 MODULE_DESCRIPTION(DRIVER_DESC); 2611 MODULE_LICENSE("GPL and additional rights"); 2612