1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/console.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 40 #include "amdgpu.h" 41 #include "amdgpu_irq.h" 42 #include "amdgpu_dma_buf.h" 43 #include "amdgpu_sched.h" 44 45 #include "amdgpu_amdkfd.h" 46 47 #include "amdgpu_ras.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 * - 3.16.0 - Add reserved vmid support 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 70 * - 3.18.0 - Export gpu always on cu bitmap 71 * - 3.19.0 - Add support for UVD MJPEG decode 72 * - 3.20.0 - Add support for local BOs 73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 75 * - 3.23.0 - Add query for VRAM lost counter 76 * - 3.24.0 - Add high priority compute support for gfx9 77 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 78 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 79 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 80 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 81 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 82 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 83 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 84 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 85 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 86 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 87 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 88 * - 3.36.0 - Allow reading more status registers on si/cik 89 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 90 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 91 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 92 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 93 */ 94 #define KMS_DRIVER_MAJOR 3 95 #define KMS_DRIVER_MINOR 40 96 #define KMS_DRIVER_PATCHLEVEL 0 97 98 int amdgpu_vram_limit; 99 int amdgpu_vis_vram_limit; 100 int amdgpu_gart_size = -1; /* auto */ 101 int amdgpu_gtt_size = -1; /* auto */ 102 int amdgpu_moverate = -1; /* auto */ 103 int amdgpu_benchmarking; 104 int amdgpu_testing; 105 int amdgpu_audio = -1; 106 int amdgpu_disp_priority; 107 int amdgpu_hw_i2c; 108 int amdgpu_pcie_gen2 = -1; 109 int amdgpu_msi = -1; 110 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 111 int amdgpu_dpm = -1; 112 int amdgpu_fw_load_type = -1; 113 int amdgpu_aspm = -1; 114 int amdgpu_runtime_pm = -1; 115 uint amdgpu_ip_block_mask = 0xffffffff; 116 int amdgpu_bapm = -1; 117 int amdgpu_deep_color; 118 int amdgpu_vm_size = -1; 119 int amdgpu_vm_fragment_size = -1; 120 int amdgpu_vm_block_size = -1; 121 int amdgpu_vm_fault_stop; 122 int amdgpu_vm_debug; 123 int amdgpu_vm_update_mode = -1; 124 int amdgpu_exp_hw_support; 125 int amdgpu_dc = -1; 126 int amdgpu_sched_jobs = 32; 127 int amdgpu_sched_hw_submission = 2; 128 uint amdgpu_pcie_gen_cap; 129 uint amdgpu_pcie_lane_cap; 130 uint amdgpu_cg_mask = 0xffffffff; 131 uint amdgpu_pg_mask = 0xffffffff; 132 uint amdgpu_sdma_phase_quantum = 32; 133 char *amdgpu_disable_cu = NULL; 134 char *amdgpu_virtual_display = NULL; 135 136 /* 137 * OverDrive(bit 14) disabled by default 138 * GFX DCS(bit 19) disabled by default 139 */ 140 uint amdgpu_pp_feature_mask = 0xfff7bfff; 141 uint amdgpu_force_long_training; 142 int amdgpu_job_hang_limit; 143 int amdgpu_lbpw = -1; 144 int amdgpu_compute_multipipe = -1; 145 int amdgpu_gpu_recovery = -1; /* auto */ 146 int amdgpu_emu_mode; 147 uint amdgpu_smu_memory_pool_size; 148 /* 149 * FBC (bit 0) disabled by default 150 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 151 * - With this, for multiple monitors in sync(e.g. with the same model), 152 * mclk switching will be allowed. And the mclk will be not foced to the 153 * highest. That helps saving some idle power. 154 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 155 * PSR (bit 3) disabled by default 156 */ 157 uint amdgpu_dc_feature_mask = 2; 158 uint amdgpu_dc_debug_mask; 159 int amdgpu_async_gfx_ring = 1; 160 int amdgpu_mcbp; 161 int amdgpu_discovery = -1; 162 int amdgpu_mes; 163 int amdgpu_noretry = -1; 164 int amdgpu_force_asic_type = -1; 165 int amdgpu_tmz; 166 int amdgpu_reset_method = -1; /* auto */ 167 int amdgpu_num_kcq = -1; 168 169 struct amdgpu_mgpu_info mgpu_info = { 170 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 171 }; 172 int amdgpu_ras_enable = -1; 173 uint amdgpu_ras_mask = 0xffffffff; 174 int amdgpu_bad_page_threshold = -1; 175 176 /** 177 * DOC: vramlimit (int) 178 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 179 */ 180 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 181 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 182 183 /** 184 * DOC: vis_vramlimit (int) 185 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 186 */ 187 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 188 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 189 190 /** 191 * DOC: gartsize (uint) 192 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 193 */ 194 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 195 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 196 197 /** 198 * DOC: gttsize (int) 199 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 200 * otherwise 3/4 RAM size). 201 */ 202 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 203 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 204 205 /** 206 * DOC: moverate (int) 207 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 208 */ 209 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 210 module_param_named(moverate, amdgpu_moverate, int, 0600); 211 212 /** 213 * DOC: benchmark (int) 214 * Run benchmarks. The default is 0 (Skip benchmarks). 215 */ 216 MODULE_PARM_DESC(benchmark, "Run benchmark"); 217 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 218 219 /** 220 * DOC: test (int) 221 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 222 */ 223 MODULE_PARM_DESC(test, "Run tests"); 224 module_param_named(test, amdgpu_testing, int, 0444); 225 226 /** 227 * DOC: audio (int) 228 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 229 */ 230 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 231 module_param_named(audio, amdgpu_audio, int, 0444); 232 233 /** 234 * DOC: disp_priority (int) 235 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 236 */ 237 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 238 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 239 240 /** 241 * DOC: hw_i2c (int) 242 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 243 */ 244 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 245 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 246 247 /** 248 * DOC: pcie_gen2 (int) 249 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 250 */ 251 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 252 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 253 254 /** 255 * DOC: msi (int) 256 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 257 */ 258 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 259 module_param_named(msi, amdgpu_msi, int, 0444); 260 261 /** 262 * DOC: lockup_timeout (string) 263 * Set GPU scheduler timeout value in ms. 264 * 265 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 266 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 267 * to the default timeout. 268 * 269 * - With one value specified, the setting will apply to all non-compute jobs. 270 * - With multiple values specified, the first one will be for GFX. 271 * The second one is for Compute. The third and fourth ones are 272 * for SDMA and Video. 273 * 274 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 275 * jobs is 10000. And there is no timeout enforced on compute jobs. 276 */ 277 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 278 "for passthrough or sriov, 10000 for all jobs." 279 " 0: keep default value. negative: infinity timeout), " 280 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 281 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 282 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 283 284 /** 285 * DOC: dpm (int) 286 * Override for dynamic power management setting 287 * (0 = disable, 1 = enable) 288 * The default is -1 (auto). 289 */ 290 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 291 module_param_named(dpm, amdgpu_dpm, int, 0444); 292 293 /** 294 * DOC: fw_load_type (int) 295 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 296 */ 297 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 298 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 299 300 /** 301 * DOC: aspm (int) 302 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 303 */ 304 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 305 module_param_named(aspm, amdgpu_aspm, int, 0444); 306 307 /** 308 * DOC: runpm (int) 309 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 310 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 311 */ 312 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 313 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 314 315 /** 316 * DOC: ip_block_mask (uint) 317 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 318 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 319 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 320 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 321 */ 322 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 323 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 324 325 /** 326 * DOC: bapm (int) 327 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 328 * The default -1 (auto, enabled) 329 */ 330 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 331 module_param_named(bapm, amdgpu_bapm, int, 0444); 332 333 /** 334 * DOC: deep_color (int) 335 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 336 */ 337 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 338 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 339 340 /** 341 * DOC: vm_size (int) 342 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 343 */ 344 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 345 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 346 347 /** 348 * DOC: vm_fragment_size (int) 349 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 350 */ 351 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 352 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 353 354 /** 355 * DOC: vm_block_size (int) 356 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 357 */ 358 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 359 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 360 361 /** 362 * DOC: vm_fault_stop (int) 363 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 364 */ 365 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 366 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 367 368 /** 369 * DOC: vm_debug (int) 370 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 371 */ 372 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 373 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 374 375 /** 376 * DOC: vm_update_mode (int) 377 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 378 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 379 */ 380 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 381 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 382 383 /** 384 * DOC: exp_hw_support (int) 385 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 386 */ 387 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 388 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 389 390 /** 391 * DOC: dc (int) 392 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 393 */ 394 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 395 module_param_named(dc, amdgpu_dc, int, 0444); 396 397 /** 398 * DOC: sched_jobs (int) 399 * Override the max number of jobs supported in the sw queue. The default is 32. 400 */ 401 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 402 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 403 404 /** 405 * DOC: sched_hw_submission (int) 406 * Override the max number of HW submissions. The default is 2. 407 */ 408 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 409 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 410 411 /** 412 * DOC: ppfeaturemask (hexint) 413 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 414 * The default is the current set of stable power features. 415 */ 416 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 417 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 418 419 /** 420 * DOC: forcelongtraining (uint) 421 * Force long memory training in resume. 422 * The default is zero, indicates short training in resume. 423 */ 424 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 425 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 426 427 /** 428 * DOC: pcie_gen_cap (uint) 429 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 430 * The default is 0 (automatic for each asic). 431 */ 432 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 433 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 434 435 /** 436 * DOC: pcie_lane_cap (uint) 437 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 438 * The default is 0 (automatic for each asic). 439 */ 440 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 441 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 442 443 /** 444 * DOC: cg_mask (uint) 445 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 446 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 447 */ 448 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 449 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 450 451 /** 452 * DOC: pg_mask (uint) 453 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 454 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 455 */ 456 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 457 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 458 459 /** 460 * DOC: sdma_phase_quantum (uint) 461 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 462 */ 463 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 464 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 465 466 /** 467 * DOC: disable_cu (charp) 468 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 469 */ 470 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 471 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 472 473 /** 474 * DOC: virtual_display (charp) 475 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 476 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 477 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 478 * device at 26:00.0. The default is NULL. 479 */ 480 MODULE_PARM_DESC(virtual_display, 481 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 482 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 483 484 /** 485 * DOC: job_hang_limit (int) 486 * Set how much time allow a job hang and not drop it. The default is 0. 487 */ 488 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 489 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 490 491 /** 492 * DOC: lbpw (int) 493 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 494 */ 495 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 496 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 497 498 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 499 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 500 501 /** 502 * DOC: gpu_recovery (int) 503 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 504 */ 505 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 506 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 507 508 /** 509 * DOC: emu_mode (int) 510 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 511 */ 512 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 513 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 514 515 /** 516 * DOC: ras_enable (int) 517 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 518 */ 519 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 520 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 521 522 /** 523 * DOC: ras_mask (uint) 524 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 525 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 526 */ 527 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 528 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 529 530 /** 531 * DOC: si_support (int) 532 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 533 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 534 * otherwise using amdgpu driver. 535 */ 536 #ifdef CONFIG_DRM_AMDGPU_SI 537 538 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 539 int amdgpu_si_support = 0; 540 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 541 #else 542 int amdgpu_si_support = 1; 543 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 544 #endif 545 546 module_param_named(si_support, amdgpu_si_support, int, 0444); 547 #endif 548 549 /** 550 * DOC: cik_support (int) 551 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 552 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 553 * otherwise using amdgpu driver. 554 */ 555 #ifdef CONFIG_DRM_AMDGPU_CIK 556 557 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 558 int amdgpu_cik_support = 0; 559 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 560 #else 561 int amdgpu_cik_support = 1; 562 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 563 #endif 564 565 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 566 #endif 567 568 /** 569 * DOC: smu_memory_pool_size (uint) 570 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 571 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 572 */ 573 MODULE_PARM_DESC(smu_memory_pool_size, 574 "reserve gtt for smu debug usage, 0 = disable," 575 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 576 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 577 578 /** 579 * DOC: async_gfx_ring (int) 580 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 581 */ 582 MODULE_PARM_DESC(async_gfx_ring, 583 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 584 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 585 586 /** 587 * DOC: mcbp (int) 588 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 589 */ 590 MODULE_PARM_DESC(mcbp, 591 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 592 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 593 594 /** 595 * DOC: discovery (int) 596 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 597 * (-1 = auto (default), 0 = disabled, 1 = enabled) 598 */ 599 MODULE_PARM_DESC(discovery, 600 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 601 module_param_named(discovery, amdgpu_discovery, int, 0444); 602 603 /** 604 * DOC: mes (int) 605 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 606 * (0 = disabled (default), 1 = enabled) 607 */ 608 MODULE_PARM_DESC(mes, 609 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 610 module_param_named(mes, amdgpu_mes, int, 0444); 611 612 /** 613 * DOC: noretry (int) 614 * Disable retry faults in the GPU memory controller. 615 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 616 */ 617 MODULE_PARM_DESC(noretry, 618 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 619 module_param_named(noretry, amdgpu_noretry, int, 0644); 620 621 /** 622 * DOC: force_asic_type (int) 623 * A non negative value used to specify the asic type for all supported GPUs. 624 */ 625 MODULE_PARM_DESC(force_asic_type, 626 "A non negative value used to specify the asic type for all supported GPUs"); 627 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 628 629 630 631 #ifdef CONFIG_HSA_AMD 632 /** 633 * DOC: sched_policy (int) 634 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 635 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 636 * assigns queues to HQDs. 637 */ 638 int sched_policy = KFD_SCHED_POLICY_HWS; 639 module_param(sched_policy, int, 0444); 640 MODULE_PARM_DESC(sched_policy, 641 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 642 643 /** 644 * DOC: hws_max_conc_proc (int) 645 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 646 * number of VMIDs assigned to the HWS, which is also the default. 647 */ 648 int hws_max_conc_proc = 8; 649 module_param(hws_max_conc_proc, int, 0444); 650 MODULE_PARM_DESC(hws_max_conc_proc, 651 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 652 653 /** 654 * DOC: cwsr_enable (int) 655 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 656 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 657 * disables it. 658 */ 659 int cwsr_enable = 1; 660 module_param(cwsr_enable, int, 0444); 661 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 662 663 /** 664 * DOC: max_num_of_queues_per_device (int) 665 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 666 * is 4096. 667 */ 668 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 669 module_param(max_num_of_queues_per_device, int, 0444); 670 MODULE_PARM_DESC(max_num_of_queues_per_device, 671 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 672 673 /** 674 * DOC: send_sigterm (int) 675 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 676 * but just print errors on dmesg. Setting 1 enables sending sigterm. 677 */ 678 int send_sigterm; 679 module_param(send_sigterm, int, 0444); 680 MODULE_PARM_DESC(send_sigterm, 681 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 682 683 /** 684 * DOC: debug_largebar (int) 685 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 686 * system. This limits the VRAM size reported to ROCm applications to the visible 687 * size, usually 256MB. 688 * Default value is 0, diabled. 689 */ 690 int debug_largebar; 691 module_param(debug_largebar, int, 0444); 692 MODULE_PARM_DESC(debug_largebar, 693 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 694 695 /** 696 * DOC: ignore_crat (int) 697 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 698 * table to get information about AMD APUs. This option can serve as a workaround on 699 * systems with a broken CRAT table. 700 * 701 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 702 * whehter use CRAT) 703 */ 704 int ignore_crat; 705 module_param(ignore_crat, int, 0444); 706 MODULE_PARM_DESC(ignore_crat, 707 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 708 709 /** 710 * DOC: halt_if_hws_hang (int) 711 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 712 * Setting 1 enables halt on hang. 713 */ 714 int halt_if_hws_hang; 715 module_param(halt_if_hws_hang, int, 0644); 716 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 717 718 /** 719 * DOC: hws_gws_support(bool) 720 * Assume that HWS supports GWS barriers regardless of what firmware version 721 * check says. Default value: false (rely on MEC2 firmware version check). 722 */ 723 bool hws_gws_support; 724 module_param(hws_gws_support, bool, 0444); 725 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 726 727 /** 728 * DOC: queue_preemption_timeout_ms (int) 729 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 730 */ 731 int queue_preemption_timeout_ms = 9000; 732 module_param(queue_preemption_timeout_ms, int, 0644); 733 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 734 735 /** 736 * DOC: debug_evictions(bool) 737 * Enable extra debug messages to help determine the cause of evictions 738 */ 739 bool debug_evictions; 740 module_param(debug_evictions, bool, 0644); 741 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 742 743 /** 744 * DOC: no_system_mem_limit(bool) 745 * Disable system memory limit, to support multiple process shared memory 746 */ 747 bool no_system_mem_limit; 748 module_param(no_system_mem_limit, bool, 0644); 749 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 750 751 #endif 752 753 /** 754 * DOC: dcfeaturemask (uint) 755 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 756 * The default is the current set of stable display features. 757 */ 758 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 759 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 760 761 /** 762 * DOC: dcdebugmask (uint) 763 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 764 */ 765 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 766 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 767 768 /** 769 * DOC: abmlevel (uint) 770 * Override the default ABM (Adaptive Backlight Management) level used for DC 771 * enabled hardware. Requires DMCU to be supported and loaded. 772 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 773 * default. Values 1-4 control the maximum allowable brightness reduction via 774 * the ABM algorithm, with 1 being the least reduction and 4 being the most 775 * reduction. 776 * 777 * Defaults to 0, or disabled. Userspace can still override this level later 778 * after boot. 779 */ 780 uint amdgpu_dm_abm_level; 781 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 782 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 783 784 int amdgpu_backlight = -1; 785 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 786 module_param_named(backlight, amdgpu_backlight, bint, 0444); 787 788 /** 789 * DOC: tmz (int) 790 * Trusted Memory Zone (TMZ) is a method to protect data being written 791 * to or read from memory. 792 * 793 * The default value: 0 (off). TODO: change to auto till it is completed. 794 */ 795 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); 796 module_param_named(tmz, amdgpu_tmz, int, 0444); 797 798 /** 799 * DOC: reset_method (int) 800 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 801 */ 802 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 803 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 804 805 /** 806 * DOC: bad_page_threshold (int) 807 * Bad page threshold is to specify the threshold value of faulty pages 808 * detected by RAS ECC, that may result in GPU entering bad status if total 809 * faulty pages by ECC exceed threshold value and leave it for user's further 810 * check. 811 */ 812 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 813 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 814 815 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 816 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 817 818 static const struct pci_device_id pciidlist[] = { 819 #ifdef CONFIG_DRM_AMDGPU_SI 820 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 821 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 822 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 823 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 824 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 825 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 826 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 827 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 828 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 829 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 830 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 831 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 832 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 833 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 834 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 835 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 836 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 837 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 838 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 839 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 840 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 841 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 842 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 843 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 844 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 845 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 846 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 847 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 848 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 849 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 850 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 851 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 852 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 853 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 854 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 855 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 856 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 857 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 858 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 859 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 860 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 861 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 862 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 863 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 864 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 865 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 866 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 867 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 868 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 869 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 870 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 871 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 872 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 873 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 874 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 875 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 876 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 877 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 878 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 879 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 880 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 881 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 882 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 883 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 884 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 885 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 886 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 887 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 888 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 889 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 890 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 891 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 892 #endif 893 #ifdef CONFIG_DRM_AMDGPU_CIK 894 /* Kaveri */ 895 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 896 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 897 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 898 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 899 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 900 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 901 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 902 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 903 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 904 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 905 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 906 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 907 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 908 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 909 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 910 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 911 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 912 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 913 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 914 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 915 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 916 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 917 /* Bonaire */ 918 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 919 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 920 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 921 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 922 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 923 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 924 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 925 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 926 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 927 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 928 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 929 /* Hawaii */ 930 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 931 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 932 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 933 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 934 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 935 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 936 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 937 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 938 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 939 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 940 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 941 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 942 /* Kabini */ 943 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 944 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 945 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 946 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 947 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 948 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 949 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 950 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 951 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 952 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 953 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 954 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 955 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 956 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 957 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 958 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 959 /* mullins */ 960 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 961 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 962 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 963 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 964 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 965 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 966 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 967 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 968 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 969 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 970 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 971 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 972 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 973 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 974 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 975 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 976 #endif 977 /* topaz */ 978 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 979 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 980 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 981 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 982 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 983 /* tonga */ 984 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 985 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 986 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 987 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 988 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 989 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 990 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 991 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 992 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 993 /* fiji */ 994 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 995 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 996 /* carrizo */ 997 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 998 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 999 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1000 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1001 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1002 /* stoney */ 1003 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1004 /* Polaris11 */ 1005 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1006 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1007 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1008 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1009 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1010 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1011 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1012 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1013 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1014 /* Polaris10 */ 1015 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1016 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1017 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1018 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1019 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1020 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1021 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1022 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1023 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1024 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1025 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1026 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1027 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1028 /* Polaris12 */ 1029 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1030 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1031 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1032 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1033 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1034 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1035 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1036 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1037 /* VEGAM */ 1038 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1039 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1040 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1041 /* Vega 10 */ 1042 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1043 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1044 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1045 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1046 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1047 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1048 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1049 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1050 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1051 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1052 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1053 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1054 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1055 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1056 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1057 /* Vega 12 */ 1058 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1059 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1060 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1061 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1062 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1063 /* Vega 20 */ 1064 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1065 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1066 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1067 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1068 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1069 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1070 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1071 /* Raven */ 1072 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1073 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1074 /* Arcturus */ 1075 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1076 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1077 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1078 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1079 /* Navi10 */ 1080 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1081 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1082 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1083 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1084 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1085 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1086 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1087 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1088 /* Navi14 */ 1089 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1090 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1091 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1092 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1093 1094 /* Renoir */ 1095 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1096 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1097 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1098 1099 /* Navi12 */ 1100 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1101 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1102 1103 /* Sienna_Cichlid */ 1104 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1105 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1106 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1107 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1108 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1109 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1110 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1111 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1112 1113 /* Van Gogh */ 1114 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1115 1116 /* Navy_Flounder */ 1117 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1118 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1119 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1120 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1121 1122 /* DIMGREY_CAVEFISH */ 1123 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1124 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1125 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1126 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1127 1128 {0, 0, 0} 1129 }; 1130 1131 MODULE_DEVICE_TABLE(pci, pciidlist); 1132 1133 static const struct drm_driver amdgpu_kms_driver; 1134 1135 static int amdgpu_pci_probe(struct pci_dev *pdev, 1136 const struct pci_device_id *ent) 1137 { 1138 struct drm_device *ddev; 1139 struct amdgpu_device *adev; 1140 unsigned long flags = ent->driver_data; 1141 int ret, retry = 0; 1142 bool supports_atomic = false; 1143 1144 if (!amdgpu_virtual_display && 1145 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1146 supports_atomic = true; 1147 1148 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1149 DRM_INFO("This hardware requires experimental hardware support.\n" 1150 "See modparam exp_hw_support\n"); 1151 return -ENODEV; 1152 } 1153 1154 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1155 * however, SME requires an indirect IOMMU mapping because the encryption 1156 * bit is beyond the DMA mask of the chip. 1157 */ 1158 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1159 dev_info(&pdev->dev, 1160 "SME is not compatible with RAVEN\n"); 1161 return -ENOTSUPP; 1162 } 1163 1164 #ifdef CONFIG_DRM_AMDGPU_SI 1165 if (!amdgpu_si_support) { 1166 switch (flags & AMD_ASIC_MASK) { 1167 case CHIP_TAHITI: 1168 case CHIP_PITCAIRN: 1169 case CHIP_VERDE: 1170 case CHIP_OLAND: 1171 case CHIP_HAINAN: 1172 dev_info(&pdev->dev, 1173 "SI support provided by radeon.\n"); 1174 dev_info(&pdev->dev, 1175 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1176 ); 1177 return -ENODEV; 1178 } 1179 } 1180 #endif 1181 #ifdef CONFIG_DRM_AMDGPU_CIK 1182 if (!amdgpu_cik_support) { 1183 switch (flags & AMD_ASIC_MASK) { 1184 case CHIP_KAVERI: 1185 case CHIP_BONAIRE: 1186 case CHIP_HAWAII: 1187 case CHIP_KABINI: 1188 case CHIP_MULLINS: 1189 dev_info(&pdev->dev, 1190 "CIK support provided by radeon.\n"); 1191 dev_info(&pdev->dev, 1192 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1193 ); 1194 return -ENODEV; 1195 } 1196 } 1197 #endif 1198 1199 /* Get rid of things like offb */ 1200 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1201 if (ret) 1202 return ret; 1203 1204 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1205 if (IS_ERR(adev)) 1206 return PTR_ERR(adev); 1207 1208 adev->dev = &pdev->dev; 1209 adev->pdev = pdev; 1210 ddev = adev_to_drm(adev); 1211 1212 if (!supports_atomic) 1213 ddev->driver_features &= ~DRIVER_ATOMIC; 1214 1215 ret = pci_enable_device(pdev); 1216 if (ret) 1217 return ret; 1218 1219 pci_set_drvdata(pdev, ddev); 1220 1221 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1222 if (ret) 1223 goto err_pci; 1224 1225 retry_init: 1226 ret = drm_dev_register(ddev, ent->driver_data); 1227 if (ret == -EAGAIN && ++retry <= 3) { 1228 DRM_INFO("retry init %d\n", retry); 1229 /* Don't request EX mode too frequently which is attacking */ 1230 msleep(5000); 1231 goto retry_init; 1232 } else if (ret) { 1233 goto err_pci; 1234 } 1235 1236 ret = amdgpu_debugfs_init(adev); 1237 if (ret) 1238 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1239 1240 return 0; 1241 1242 err_pci: 1243 pci_disable_device(pdev); 1244 return ret; 1245 } 1246 1247 static void 1248 amdgpu_pci_remove(struct pci_dev *pdev) 1249 { 1250 struct drm_device *dev = pci_get_drvdata(pdev); 1251 1252 #ifdef MODULE 1253 if (THIS_MODULE->state != MODULE_STATE_GOING) 1254 #endif 1255 DRM_ERROR("Hotplug removal is not supported\n"); 1256 drm_dev_unplug(dev); 1257 amdgpu_driver_unload_kms(dev); 1258 pci_disable_device(pdev); 1259 pci_set_drvdata(pdev, NULL); 1260 } 1261 1262 static void 1263 amdgpu_pci_shutdown(struct pci_dev *pdev) 1264 { 1265 struct drm_device *dev = pci_get_drvdata(pdev); 1266 struct amdgpu_device *adev = drm_to_adev(dev); 1267 1268 if (amdgpu_ras_intr_triggered()) 1269 return; 1270 1271 /* if we are running in a VM, make sure the device 1272 * torn down properly on reboot/shutdown. 1273 * unfortunately we can't detect certain 1274 * hypervisors so just do this all the time. 1275 */ 1276 if (!amdgpu_passthrough(adev)) 1277 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1278 amdgpu_device_ip_suspend(adev); 1279 adev->mp1_state = PP_MP1_STATE_NONE; 1280 } 1281 1282 static int amdgpu_pmops_suspend(struct device *dev) 1283 { 1284 struct drm_device *drm_dev = dev_get_drvdata(dev); 1285 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1286 int r; 1287 1288 if (amdgpu_acpi_is_s0ix_supported(adev)) 1289 adev->in_s0ix = true; 1290 adev->in_s3 = true; 1291 r = amdgpu_device_suspend(drm_dev, true); 1292 adev->in_s3 = false; 1293 1294 return r; 1295 } 1296 1297 static int amdgpu_pmops_resume(struct device *dev) 1298 { 1299 struct drm_device *drm_dev = dev_get_drvdata(dev); 1300 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1301 int r; 1302 1303 r = amdgpu_device_resume(drm_dev, true); 1304 if (amdgpu_acpi_is_s0ix_supported(adev)) 1305 adev->in_s0ix = false; 1306 return r; 1307 } 1308 1309 static int amdgpu_pmops_freeze(struct device *dev) 1310 { 1311 struct drm_device *drm_dev = dev_get_drvdata(dev); 1312 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1313 int r; 1314 1315 adev->in_s4 = true; 1316 r = amdgpu_device_suspend(drm_dev, true); 1317 adev->in_s4 = false; 1318 if (r) 1319 return r; 1320 return amdgpu_asic_reset(adev); 1321 } 1322 1323 static int amdgpu_pmops_thaw(struct device *dev) 1324 { 1325 struct drm_device *drm_dev = dev_get_drvdata(dev); 1326 1327 return amdgpu_device_resume(drm_dev, true); 1328 } 1329 1330 static int amdgpu_pmops_poweroff(struct device *dev) 1331 { 1332 struct drm_device *drm_dev = dev_get_drvdata(dev); 1333 1334 return amdgpu_device_suspend(drm_dev, true); 1335 } 1336 1337 static int amdgpu_pmops_restore(struct device *dev) 1338 { 1339 struct drm_device *drm_dev = dev_get_drvdata(dev); 1340 1341 return amdgpu_device_resume(drm_dev, true); 1342 } 1343 1344 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1345 { 1346 struct pci_dev *pdev = to_pci_dev(dev); 1347 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1348 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1349 int ret, i; 1350 1351 if (!adev->runpm) { 1352 pm_runtime_forbid(dev); 1353 return -EBUSY; 1354 } 1355 1356 /* wait for all rings to drain before suspending */ 1357 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1358 struct amdgpu_ring *ring = adev->rings[i]; 1359 if (ring && ring->sched.ready) { 1360 ret = amdgpu_fence_wait_empty(ring); 1361 if (ret) 1362 return -EBUSY; 1363 } 1364 } 1365 1366 adev->in_runpm = true; 1367 if (amdgpu_device_supports_atpx(drm_dev)) 1368 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1369 1370 ret = amdgpu_device_suspend(drm_dev, false); 1371 if (ret) { 1372 adev->in_runpm = false; 1373 return ret; 1374 } 1375 1376 if (amdgpu_device_supports_atpx(drm_dev)) { 1377 /* Only need to handle PCI state in the driver for ATPX 1378 * PCI core handles it for _PR3. 1379 */ 1380 if (!amdgpu_is_atpx_hybrid()) { 1381 amdgpu_device_cache_pci_state(pdev); 1382 pci_disable_device(pdev); 1383 pci_ignore_hotplug(pdev); 1384 pci_set_power_state(pdev, PCI_D3cold); 1385 } 1386 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1387 } else if (amdgpu_device_supports_baco(drm_dev)) { 1388 amdgpu_device_baco_enter(drm_dev); 1389 } 1390 1391 return 0; 1392 } 1393 1394 static int amdgpu_pmops_runtime_resume(struct device *dev) 1395 { 1396 struct pci_dev *pdev = to_pci_dev(dev); 1397 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1398 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1399 int ret; 1400 1401 if (!adev->runpm) 1402 return -EINVAL; 1403 1404 if (amdgpu_device_supports_atpx(drm_dev)) { 1405 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1406 1407 /* Only need to handle PCI state in the driver for ATPX 1408 * PCI core handles it for _PR3. 1409 */ 1410 if (!amdgpu_is_atpx_hybrid()) { 1411 pci_set_power_state(pdev, PCI_D0); 1412 amdgpu_device_load_pci_state(pdev); 1413 ret = pci_enable_device(pdev); 1414 if (ret) 1415 return ret; 1416 } 1417 pci_set_master(pdev); 1418 } else if (amdgpu_device_supports_boco(drm_dev)) { 1419 /* Only need to handle PCI state in the driver for ATPX 1420 * PCI core handles it for _PR3. 1421 */ 1422 pci_set_master(pdev); 1423 } else if (amdgpu_device_supports_baco(drm_dev)) { 1424 amdgpu_device_baco_exit(drm_dev); 1425 } 1426 ret = amdgpu_device_resume(drm_dev, false); 1427 if (amdgpu_device_supports_atpx(drm_dev)) 1428 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1429 adev->in_runpm = false; 1430 return 0; 1431 } 1432 1433 static int amdgpu_pmops_runtime_idle(struct device *dev) 1434 { 1435 struct drm_device *drm_dev = dev_get_drvdata(dev); 1436 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1437 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1438 int ret = 1; 1439 1440 if (!adev->runpm) { 1441 pm_runtime_forbid(dev); 1442 return -EBUSY; 1443 } 1444 1445 if (amdgpu_device_has_dc_support(adev)) { 1446 struct drm_crtc *crtc; 1447 1448 drm_modeset_lock_all(drm_dev); 1449 1450 drm_for_each_crtc(crtc, drm_dev) { 1451 if (crtc->state->active) { 1452 ret = -EBUSY; 1453 break; 1454 } 1455 } 1456 1457 drm_modeset_unlock_all(drm_dev); 1458 1459 } else { 1460 struct drm_connector *list_connector; 1461 struct drm_connector_list_iter iter; 1462 1463 mutex_lock(&drm_dev->mode_config.mutex); 1464 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1465 1466 drm_connector_list_iter_begin(drm_dev, &iter); 1467 drm_for_each_connector_iter(list_connector, &iter) { 1468 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1469 ret = -EBUSY; 1470 break; 1471 } 1472 } 1473 1474 drm_connector_list_iter_end(&iter); 1475 1476 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1477 mutex_unlock(&drm_dev->mode_config.mutex); 1478 } 1479 1480 if (ret == -EBUSY) 1481 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1482 1483 pm_runtime_mark_last_busy(dev); 1484 pm_runtime_autosuspend(dev); 1485 return ret; 1486 } 1487 1488 long amdgpu_drm_ioctl(struct file *filp, 1489 unsigned int cmd, unsigned long arg) 1490 { 1491 struct drm_file *file_priv = filp->private_data; 1492 struct drm_device *dev; 1493 long ret; 1494 dev = file_priv->minor->dev; 1495 ret = pm_runtime_get_sync(dev->dev); 1496 if (ret < 0) 1497 goto out; 1498 1499 ret = drm_ioctl(filp, cmd, arg); 1500 1501 pm_runtime_mark_last_busy(dev->dev); 1502 out: 1503 pm_runtime_put_autosuspend(dev->dev); 1504 return ret; 1505 } 1506 1507 static const struct dev_pm_ops amdgpu_pm_ops = { 1508 .suspend = amdgpu_pmops_suspend, 1509 .resume = amdgpu_pmops_resume, 1510 .freeze = amdgpu_pmops_freeze, 1511 .thaw = amdgpu_pmops_thaw, 1512 .poweroff = amdgpu_pmops_poweroff, 1513 .restore = amdgpu_pmops_restore, 1514 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1515 .runtime_resume = amdgpu_pmops_runtime_resume, 1516 .runtime_idle = amdgpu_pmops_runtime_idle, 1517 }; 1518 1519 static int amdgpu_flush(struct file *f, fl_owner_t id) 1520 { 1521 struct drm_file *file_priv = f->private_data; 1522 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1523 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1524 1525 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1526 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1527 1528 return timeout >= 0 ? 0 : timeout; 1529 } 1530 1531 static const struct file_operations amdgpu_driver_kms_fops = { 1532 .owner = THIS_MODULE, 1533 .open = drm_open, 1534 .flush = amdgpu_flush, 1535 .release = drm_release, 1536 .unlocked_ioctl = amdgpu_drm_ioctl, 1537 .mmap = amdgpu_mmap, 1538 .poll = drm_poll, 1539 .read = drm_read, 1540 #ifdef CONFIG_COMPAT 1541 .compat_ioctl = amdgpu_kms_compat_ioctl, 1542 #endif 1543 }; 1544 1545 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1546 { 1547 struct drm_file *file; 1548 1549 if (!filp) 1550 return -EINVAL; 1551 1552 if (filp->f_op != &amdgpu_driver_kms_fops) { 1553 return -EINVAL; 1554 } 1555 1556 file = filp->private_data; 1557 *fpriv = file->driver_priv; 1558 return 0; 1559 } 1560 1561 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1562 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1563 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1564 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1565 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1566 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1567 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1568 /* KMS */ 1569 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1570 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1571 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1572 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1573 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1574 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1575 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1576 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1577 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1578 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1579 }; 1580 1581 static const struct drm_driver amdgpu_kms_driver = { 1582 .driver_features = 1583 DRIVER_ATOMIC | 1584 DRIVER_GEM | 1585 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1586 DRIVER_SYNCOBJ_TIMELINE, 1587 .open = amdgpu_driver_open_kms, 1588 .postclose = amdgpu_driver_postclose_kms, 1589 .lastclose = amdgpu_driver_lastclose_kms, 1590 .irq_handler = amdgpu_irq_handler, 1591 .ioctls = amdgpu_ioctls_kms, 1592 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1593 .dumb_create = amdgpu_mode_dumb_create, 1594 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1595 .fops = &amdgpu_driver_kms_fops, 1596 1597 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1598 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1599 .gem_prime_import = amdgpu_gem_prime_import, 1600 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1601 1602 .name = DRIVER_NAME, 1603 .desc = DRIVER_DESC, 1604 .date = DRIVER_DATE, 1605 .major = KMS_DRIVER_MAJOR, 1606 .minor = KMS_DRIVER_MINOR, 1607 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1608 }; 1609 1610 static struct pci_error_handlers amdgpu_pci_err_handler = { 1611 .error_detected = amdgpu_pci_error_detected, 1612 .mmio_enabled = amdgpu_pci_mmio_enabled, 1613 .slot_reset = amdgpu_pci_slot_reset, 1614 .resume = amdgpu_pci_resume, 1615 }; 1616 1617 static struct pci_driver amdgpu_kms_pci_driver = { 1618 .name = DRIVER_NAME, 1619 .id_table = pciidlist, 1620 .probe = amdgpu_pci_probe, 1621 .remove = amdgpu_pci_remove, 1622 .shutdown = amdgpu_pci_shutdown, 1623 .driver.pm = &amdgpu_pm_ops, 1624 .err_handler = &amdgpu_pci_err_handler, 1625 }; 1626 1627 static int __init amdgpu_init(void) 1628 { 1629 int r; 1630 1631 if (vgacon_text_force()) { 1632 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1633 return -EINVAL; 1634 } 1635 1636 r = amdgpu_sync_init(); 1637 if (r) 1638 goto error_sync; 1639 1640 r = amdgpu_fence_slab_init(); 1641 if (r) 1642 goto error_fence; 1643 1644 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1645 amdgpu_register_atpx_handler(); 1646 1647 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1648 amdgpu_amdkfd_init(); 1649 1650 /* let modprobe override vga console setting */ 1651 return pci_register_driver(&amdgpu_kms_pci_driver); 1652 1653 error_fence: 1654 amdgpu_sync_fini(); 1655 1656 error_sync: 1657 return r; 1658 } 1659 1660 static void __exit amdgpu_exit(void) 1661 { 1662 amdgpu_amdkfd_fini(); 1663 pci_unregister_driver(&amdgpu_kms_pci_driver); 1664 amdgpu_unregister_atpx_handler(); 1665 amdgpu_sync_fini(); 1666 amdgpu_fence_slab_fini(); 1667 mmu_notifier_synchronize(); 1668 } 1669 1670 module_init(amdgpu_init); 1671 module_exit(amdgpu_exit); 1672 1673 MODULE_AUTHOR(DRIVER_AUTHOR); 1674 MODULE_DESCRIPTION(DRIVER_DESC); 1675 MODULE_LICENSE("GPL and additional rights"); 1676