1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/console.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 40 #include "amdgpu.h" 41 #include "amdgpu_irq.h" 42 #include "amdgpu_dma_buf.h" 43 44 #include "amdgpu_amdkfd.h" 45 46 #include "amdgpu_ras.h" 47 48 /* 49 * KMS wrapper. 50 * - 3.0.0 - initial driver 51 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 52 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 53 * at the end of IBs. 54 * - 3.3.0 - Add VM support for UVD on supported hardware. 55 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 56 * - 3.5.0 - Add support for new UVD_NO_OP register. 57 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 58 * - 3.7.0 - Add support for VCE clock list packet 59 * - 3.8.0 - Add support raster config init in the kernel 60 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 61 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 62 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 63 * - 3.12.0 - Add query for double offchip LDS buffers 64 * - 3.13.0 - Add PRT support 65 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 66 * - 3.15.0 - Export more gpu info for gfx9 67 * - 3.16.0 - Add reserved vmid support 68 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 69 * - 3.18.0 - Export gpu always on cu bitmap 70 * - 3.19.0 - Add support for UVD MJPEG decode 71 * - 3.20.0 - Add support for local BOs 72 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 73 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 74 * - 3.23.0 - Add query for VRAM lost counter 75 * - 3.24.0 - Add high priority compute support for gfx9 76 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 77 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 78 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 79 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 80 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 81 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 82 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 83 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 84 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 85 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 86 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 87 * - 3.36.0 - Allow reading more status registers on si/cik 88 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 89 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 90 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 91 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 92 */ 93 #define KMS_DRIVER_MAJOR 3 94 #define KMS_DRIVER_MINOR 40 95 #define KMS_DRIVER_PATCHLEVEL 0 96 97 int amdgpu_vram_limit; 98 int amdgpu_vis_vram_limit; 99 int amdgpu_gart_size = -1; /* auto */ 100 int amdgpu_gtt_size = -1; /* auto */ 101 int amdgpu_moverate = -1; /* auto */ 102 int amdgpu_benchmarking; 103 int amdgpu_testing; 104 int amdgpu_audio = -1; 105 int amdgpu_disp_priority; 106 int amdgpu_hw_i2c; 107 int amdgpu_pcie_gen2 = -1; 108 int amdgpu_msi = -1; 109 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 110 int amdgpu_dpm = -1; 111 int amdgpu_fw_load_type = -1; 112 int amdgpu_aspm = -1; 113 int amdgpu_runtime_pm = -1; 114 uint amdgpu_ip_block_mask = 0xffffffff; 115 int amdgpu_bapm = -1; 116 int amdgpu_deep_color; 117 int amdgpu_vm_size = -1; 118 int amdgpu_vm_fragment_size = -1; 119 int amdgpu_vm_block_size = -1; 120 int amdgpu_vm_fault_stop; 121 int amdgpu_vm_debug; 122 int amdgpu_vm_update_mode = -1; 123 int amdgpu_exp_hw_support; 124 int amdgpu_dc = -1; 125 int amdgpu_sched_jobs = 32; 126 int amdgpu_sched_hw_submission = 2; 127 uint amdgpu_pcie_gen_cap; 128 uint amdgpu_pcie_lane_cap; 129 uint amdgpu_cg_mask = 0xffffffff; 130 uint amdgpu_pg_mask = 0xffffffff; 131 uint amdgpu_sdma_phase_quantum = 32; 132 char *amdgpu_disable_cu = NULL; 133 char *amdgpu_virtual_display = NULL; 134 /* OverDrive(bit 14) disabled by default*/ 135 uint amdgpu_pp_feature_mask = 0xffffbfff; 136 uint amdgpu_force_long_training; 137 int amdgpu_job_hang_limit; 138 int amdgpu_lbpw = -1; 139 int amdgpu_compute_multipipe = -1; 140 int amdgpu_gpu_recovery = -1; /* auto */ 141 int amdgpu_emu_mode; 142 uint amdgpu_smu_memory_pool_size; 143 /* 144 * FBC (bit 0) disabled by default 145 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 146 * - With this, for multiple monitors in sync(e.g. with the same model), 147 * mclk switching will be allowed. And the mclk will be not foced to the 148 * highest. That helps saving some idle power. 149 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 150 * PSR (bit 3) disabled by default 151 */ 152 uint amdgpu_dc_feature_mask = 2; 153 uint amdgpu_dc_debug_mask; 154 int amdgpu_async_gfx_ring = 1; 155 int amdgpu_mcbp; 156 int amdgpu_discovery = -1; 157 int amdgpu_mes; 158 int amdgpu_noretry = -1; 159 int amdgpu_force_asic_type = -1; 160 int amdgpu_tmz; 161 int amdgpu_reset_method = -1; /* auto */ 162 int amdgpu_num_kcq = -1; 163 164 struct amdgpu_mgpu_info mgpu_info = { 165 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 166 }; 167 int amdgpu_ras_enable = -1; 168 uint amdgpu_ras_mask = 0xffffffff; 169 int amdgpu_bad_page_threshold = -1; 170 171 /** 172 * DOC: vramlimit (int) 173 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 174 */ 175 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 176 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 177 178 /** 179 * DOC: vis_vramlimit (int) 180 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 181 */ 182 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 183 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 184 185 /** 186 * DOC: gartsize (uint) 187 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 188 */ 189 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 190 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 191 192 /** 193 * DOC: gttsize (int) 194 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 195 * otherwise 3/4 RAM size). 196 */ 197 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 198 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 199 200 /** 201 * DOC: moverate (int) 202 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 203 */ 204 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 205 module_param_named(moverate, amdgpu_moverate, int, 0600); 206 207 /** 208 * DOC: benchmark (int) 209 * Run benchmarks. The default is 0 (Skip benchmarks). 210 */ 211 MODULE_PARM_DESC(benchmark, "Run benchmark"); 212 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 213 214 /** 215 * DOC: test (int) 216 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 217 */ 218 MODULE_PARM_DESC(test, "Run tests"); 219 module_param_named(test, amdgpu_testing, int, 0444); 220 221 /** 222 * DOC: audio (int) 223 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 224 */ 225 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 226 module_param_named(audio, amdgpu_audio, int, 0444); 227 228 /** 229 * DOC: disp_priority (int) 230 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 231 */ 232 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 233 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 234 235 /** 236 * DOC: hw_i2c (int) 237 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 238 */ 239 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 240 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 241 242 /** 243 * DOC: pcie_gen2 (int) 244 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 245 */ 246 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 247 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 248 249 /** 250 * DOC: msi (int) 251 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 252 */ 253 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 254 module_param_named(msi, amdgpu_msi, int, 0444); 255 256 /** 257 * DOC: lockup_timeout (string) 258 * Set GPU scheduler timeout value in ms. 259 * 260 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 261 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 262 * to the default timeout. 263 * 264 * - With one value specified, the setting will apply to all non-compute jobs. 265 * - With multiple values specified, the first one will be for GFX. 266 * The second one is for Compute. The third and fourth ones are 267 * for SDMA and Video. 268 * 269 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 270 * jobs is 10000. And there is no timeout enforced on compute jobs. 271 */ 272 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 273 "for passthrough or sriov, 10000 for all jobs." 274 " 0: keep default value. negative: infinity timeout), " 275 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 276 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 277 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 278 279 /** 280 * DOC: dpm (int) 281 * Override for dynamic power management setting 282 * (0 = disable, 1 = enable) 283 * The default is -1 (auto). 284 */ 285 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 286 module_param_named(dpm, amdgpu_dpm, int, 0444); 287 288 /** 289 * DOC: fw_load_type (int) 290 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 291 */ 292 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 293 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 294 295 /** 296 * DOC: aspm (int) 297 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 298 */ 299 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 300 module_param_named(aspm, amdgpu_aspm, int, 0444); 301 302 /** 303 * DOC: runpm (int) 304 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 305 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 306 */ 307 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 308 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 309 310 /** 311 * DOC: ip_block_mask (uint) 312 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 313 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 314 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 315 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 316 */ 317 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 318 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 319 320 /** 321 * DOC: bapm (int) 322 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 323 * The default -1 (auto, enabled) 324 */ 325 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 326 module_param_named(bapm, amdgpu_bapm, int, 0444); 327 328 /** 329 * DOC: deep_color (int) 330 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 331 */ 332 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 333 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 334 335 /** 336 * DOC: vm_size (int) 337 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 338 */ 339 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 340 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 341 342 /** 343 * DOC: vm_fragment_size (int) 344 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 345 */ 346 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 347 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 348 349 /** 350 * DOC: vm_block_size (int) 351 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 352 */ 353 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 354 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 355 356 /** 357 * DOC: vm_fault_stop (int) 358 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 359 */ 360 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 361 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 362 363 /** 364 * DOC: vm_debug (int) 365 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 366 */ 367 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 368 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 369 370 /** 371 * DOC: vm_update_mode (int) 372 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 373 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 374 */ 375 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 376 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 377 378 /** 379 * DOC: exp_hw_support (int) 380 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 381 */ 382 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 383 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 384 385 /** 386 * DOC: dc (int) 387 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 388 */ 389 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 390 module_param_named(dc, amdgpu_dc, int, 0444); 391 392 /** 393 * DOC: sched_jobs (int) 394 * Override the max number of jobs supported in the sw queue. The default is 32. 395 */ 396 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 397 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 398 399 /** 400 * DOC: sched_hw_submission (int) 401 * Override the max number of HW submissions. The default is 2. 402 */ 403 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 404 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 405 406 /** 407 * DOC: ppfeaturemask (hexint) 408 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 409 * The default is the current set of stable power features. 410 */ 411 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 412 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 413 414 /** 415 * DOC: forcelongtraining (uint) 416 * Force long memory training in resume. 417 * The default is zero, indicates short training in resume. 418 */ 419 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 420 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 421 422 /** 423 * DOC: pcie_gen_cap (uint) 424 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 425 * The default is 0 (automatic for each asic). 426 */ 427 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 428 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 429 430 /** 431 * DOC: pcie_lane_cap (uint) 432 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 433 * The default is 0 (automatic for each asic). 434 */ 435 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 436 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 437 438 /** 439 * DOC: cg_mask (uint) 440 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 441 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 442 */ 443 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 444 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 445 446 /** 447 * DOC: pg_mask (uint) 448 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 449 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 450 */ 451 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 452 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 453 454 /** 455 * DOC: sdma_phase_quantum (uint) 456 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 457 */ 458 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 459 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 460 461 /** 462 * DOC: disable_cu (charp) 463 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 464 */ 465 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 466 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 467 468 /** 469 * DOC: virtual_display (charp) 470 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 471 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 472 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 473 * device at 26:00.0. The default is NULL. 474 */ 475 MODULE_PARM_DESC(virtual_display, 476 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 477 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 478 479 /** 480 * DOC: job_hang_limit (int) 481 * Set how much time allow a job hang and not drop it. The default is 0. 482 */ 483 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 484 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 485 486 /** 487 * DOC: lbpw (int) 488 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 489 */ 490 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 491 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 492 493 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 494 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 495 496 /** 497 * DOC: gpu_recovery (int) 498 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 499 */ 500 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 501 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 502 503 /** 504 * DOC: emu_mode (int) 505 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 506 */ 507 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 508 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 509 510 /** 511 * DOC: ras_enable (int) 512 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 513 */ 514 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 515 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 516 517 /** 518 * DOC: ras_mask (uint) 519 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 520 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 521 */ 522 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 523 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 524 525 /** 526 * DOC: si_support (int) 527 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 528 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 529 * otherwise using amdgpu driver. 530 */ 531 #ifdef CONFIG_DRM_AMDGPU_SI 532 533 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 534 int amdgpu_si_support = 0; 535 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 536 #else 537 int amdgpu_si_support = 1; 538 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 539 #endif 540 541 module_param_named(si_support, amdgpu_si_support, int, 0444); 542 #endif 543 544 /** 545 * DOC: cik_support (int) 546 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 547 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 548 * otherwise using amdgpu driver. 549 */ 550 #ifdef CONFIG_DRM_AMDGPU_CIK 551 552 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 553 int amdgpu_cik_support = 0; 554 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 555 #else 556 int amdgpu_cik_support = 1; 557 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 558 #endif 559 560 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 561 #endif 562 563 /** 564 * DOC: smu_memory_pool_size (uint) 565 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 566 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 567 */ 568 MODULE_PARM_DESC(smu_memory_pool_size, 569 "reserve gtt for smu debug usage, 0 = disable," 570 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 571 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 572 573 /** 574 * DOC: async_gfx_ring (int) 575 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 576 */ 577 MODULE_PARM_DESC(async_gfx_ring, 578 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 579 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 580 581 /** 582 * DOC: mcbp (int) 583 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 584 */ 585 MODULE_PARM_DESC(mcbp, 586 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 587 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 588 589 /** 590 * DOC: discovery (int) 591 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 592 * (-1 = auto (default), 0 = disabled, 1 = enabled) 593 */ 594 MODULE_PARM_DESC(discovery, 595 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 596 module_param_named(discovery, amdgpu_discovery, int, 0444); 597 598 /** 599 * DOC: mes (int) 600 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 601 * (0 = disabled (default), 1 = enabled) 602 */ 603 MODULE_PARM_DESC(mes, 604 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 605 module_param_named(mes, amdgpu_mes, int, 0444); 606 607 /** 608 * DOC: noretry (int) 609 * Disable retry faults in the GPU memory controller. 610 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 611 */ 612 MODULE_PARM_DESC(noretry, 613 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 614 module_param_named(noretry, amdgpu_noretry, int, 0644); 615 616 /** 617 * DOC: force_asic_type (int) 618 * A non negative value used to specify the asic type for all supported GPUs. 619 */ 620 MODULE_PARM_DESC(force_asic_type, 621 "A non negative value used to specify the asic type for all supported GPUs"); 622 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 623 624 625 626 #ifdef CONFIG_HSA_AMD 627 /** 628 * DOC: sched_policy (int) 629 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 630 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 631 * assigns queues to HQDs. 632 */ 633 int sched_policy = KFD_SCHED_POLICY_HWS; 634 module_param(sched_policy, int, 0444); 635 MODULE_PARM_DESC(sched_policy, 636 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 637 638 /** 639 * DOC: hws_max_conc_proc (int) 640 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 641 * number of VMIDs assigned to the HWS, which is also the default. 642 */ 643 int hws_max_conc_proc = 8; 644 module_param(hws_max_conc_proc, int, 0444); 645 MODULE_PARM_DESC(hws_max_conc_proc, 646 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 647 648 /** 649 * DOC: cwsr_enable (int) 650 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 651 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 652 * disables it. 653 */ 654 int cwsr_enable = 1; 655 module_param(cwsr_enable, int, 0444); 656 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 657 658 /** 659 * DOC: max_num_of_queues_per_device (int) 660 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 661 * is 4096. 662 */ 663 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 664 module_param(max_num_of_queues_per_device, int, 0444); 665 MODULE_PARM_DESC(max_num_of_queues_per_device, 666 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 667 668 /** 669 * DOC: send_sigterm (int) 670 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 671 * but just print errors on dmesg. Setting 1 enables sending sigterm. 672 */ 673 int send_sigterm; 674 module_param(send_sigterm, int, 0444); 675 MODULE_PARM_DESC(send_sigterm, 676 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 677 678 /** 679 * DOC: debug_largebar (int) 680 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 681 * system. This limits the VRAM size reported to ROCm applications to the visible 682 * size, usually 256MB. 683 * Default value is 0, diabled. 684 */ 685 int debug_largebar; 686 module_param(debug_largebar, int, 0444); 687 MODULE_PARM_DESC(debug_largebar, 688 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 689 690 /** 691 * DOC: ignore_crat (int) 692 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 693 * table to get information about AMD APUs. This option can serve as a workaround on 694 * systems with a broken CRAT table. 695 * 696 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 697 * whehter use CRAT) 698 */ 699 int ignore_crat; 700 module_param(ignore_crat, int, 0444); 701 MODULE_PARM_DESC(ignore_crat, 702 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 703 704 /** 705 * DOC: halt_if_hws_hang (int) 706 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 707 * Setting 1 enables halt on hang. 708 */ 709 int halt_if_hws_hang; 710 module_param(halt_if_hws_hang, int, 0644); 711 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 712 713 /** 714 * DOC: hws_gws_support(bool) 715 * Assume that HWS supports GWS barriers regardless of what firmware version 716 * check says. Default value: false (rely on MEC2 firmware version check). 717 */ 718 bool hws_gws_support; 719 module_param(hws_gws_support, bool, 0444); 720 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 721 722 /** 723 * DOC: queue_preemption_timeout_ms (int) 724 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 725 */ 726 int queue_preemption_timeout_ms = 9000; 727 module_param(queue_preemption_timeout_ms, int, 0644); 728 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 729 730 /** 731 * DOC: debug_evictions(bool) 732 * Enable extra debug messages to help determine the cause of evictions 733 */ 734 bool debug_evictions; 735 module_param(debug_evictions, bool, 0644); 736 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 737 738 /** 739 * DOC: no_system_mem_limit(bool) 740 * Disable system memory limit, to support multiple process shared memory 741 */ 742 bool no_system_mem_limit; 743 module_param(no_system_mem_limit, bool, 0644); 744 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 745 746 #endif 747 748 /** 749 * DOC: dcfeaturemask (uint) 750 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 751 * The default is the current set of stable display features. 752 */ 753 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 754 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 755 756 /** 757 * DOC: dcdebugmask (uint) 758 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 759 */ 760 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 761 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 762 763 /** 764 * DOC: abmlevel (uint) 765 * Override the default ABM (Adaptive Backlight Management) level used for DC 766 * enabled hardware. Requires DMCU to be supported and loaded. 767 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 768 * default. Values 1-4 control the maximum allowable brightness reduction via 769 * the ABM algorithm, with 1 being the least reduction and 4 being the most 770 * reduction. 771 * 772 * Defaults to 0, or disabled. Userspace can still override this level later 773 * after boot. 774 */ 775 uint amdgpu_dm_abm_level; 776 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 777 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 778 779 /** 780 * DOC: tmz (int) 781 * Trusted Memory Zone (TMZ) is a method to protect data being written 782 * to or read from memory. 783 * 784 * The default value: 0 (off). TODO: change to auto till it is completed. 785 */ 786 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); 787 module_param_named(tmz, amdgpu_tmz, int, 0444); 788 789 /** 790 * DOC: reset_method (int) 791 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 792 */ 793 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 794 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 795 796 /** 797 * DOC: bad_page_threshold (int) 798 * Bad page threshold is to specify the threshold value of faulty pages 799 * detected by RAS ECC, that may result in GPU entering bad status if total 800 * faulty pages by ECC exceed threshold value and leave it for user's further 801 * check. 802 */ 803 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 804 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 805 806 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 807 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 808 809 static const struct pci_device_id pciidlist[] = { 810 #ifdef CONFIG_DRM_AMDGPU_SI 811 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 812 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 813 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 814 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 815 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 816 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 817 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 818 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 819 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 820 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 821 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 822 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 823 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 824 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 825 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 826 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 827 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 828 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 829 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 830 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 831 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 832 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 833 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 834 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 835 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 836 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 837 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 838 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 839 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 840 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 841 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 842 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 843 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 844 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 845 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 846 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 847 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 848 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 849 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 850 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 851 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 852 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 853 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 854 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 855 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 856 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 857 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 858 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 859 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 860 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 861 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 862 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 863 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 864 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 865 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 866 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 867 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 868 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 869 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 870 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 871 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 872 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 873 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 874 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 875 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 876 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 877 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 878 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 879 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 880 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 881 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 882 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 883 #endif 884 #ifdef CONFIG_DRM_AMDGPU_CIK 885 /* Kaveri */ 886 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 888 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 889 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 890 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 891 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 892 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 893 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 894 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 895 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 896 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 897 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 898 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 899 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 900 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 901 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 902 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 903 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 904 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 905 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 906 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 907 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 908 /* Bonaire */ 909 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 910 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 911 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 912 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 913 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 914 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 915 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 916 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 917 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 918 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 919 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 920 /* Hawaii */ 921 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 922 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 923 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 924 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 925 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 926 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 927 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 928 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 929 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 930 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 931 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 932 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 933 /* Kabini */ 934 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 935 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 936 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 937 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 938 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 939 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 940 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 941 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 942 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 943 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 944 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 945 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 946 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 947 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 948 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 949 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 950 /* mullins */ 951 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 952 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 953 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 954 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 955 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 956 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 957 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 958 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 959 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 960 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 961 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 962 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 963 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 964 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 965 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 966 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 967 #endif 968 /* topaz */ 969 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 970 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 971 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 972 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 973 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 974 /* tonga */ 975 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 976 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 977 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 978 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 979 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 980 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 981 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 982 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 983 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 984 /* fiji */ 985 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 986 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 987 /* carrizo */ 988 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 989 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 990 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 991 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 992 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 993 /* stoney */ 994 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 995 /* Polaris11 */ 996 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 997 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 998 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 999 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1000 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1001 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1002 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1003 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1004 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1005 /* Polaris10 */ 1006 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1007 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1008 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1009 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1010 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1011 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1012 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1013 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1014 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1015 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1016 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1017 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1018 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1019 /* Polaris12 */ 1020 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1021 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1022 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1023 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1024 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1025 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1026 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1027 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1028 /* VEGAM */ 1029 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1030 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1031 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1032 /* Vega 10 */ 1033 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1034 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1035 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1036 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1037 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1038 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1039 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1040 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1041 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1042 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1043 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1044 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1045 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1046 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1047 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1048 /* Vega 12 */ 1049 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1050 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1051 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1052 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1053 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1054 /* Vega 20 */ 1055 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1056 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1057 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1058 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1059 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1060 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1061 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1062 /* Raven */ 1063 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1064 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1065 /* Arcturus */ 1066 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1067 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1068 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1069 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1070 /* Navi10 */ 1071 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1072 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1073 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1074 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1075 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1076 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1077 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1078 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1079 /* Navi14 */ 1080 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1081 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1082 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1083 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1084 1085 /* Renoir */ 1086 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1087 1088 /* Navi12 */ 1089 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1090 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1091 1092 /* Sienna_Cichlid */ 1093 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1094 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1095 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1096 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1097 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1098 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1099 1100 /* Van Gogh */ 1101 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1102 1103 /* Navy_Flounder */ 1104 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1105 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1106 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1107 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1108 1109 /* DIMGREY_CAVEFISH */ 1110 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1111 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1112 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1113 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1114 1115 {0, 0, 0} 1116 }; 1117 1118 MODULE_DEVICE_TABLE(pci, pciidlist); 1119 1120 static struct drm_driver kms_driver; 1121 1122 static int amdgpu_pci_probe(struct pci_dev *pdev, 1123 const struct pci_device_id *ent) 1124 { 1125 struct drm_device *ddev; 1126 struct amdgpu_device *adev; 1127 unsigned long flags = ent->driver_data; 1128 int ret, retry = 0; 1129 bool supports_atomic = false; 1130 1131 if (!amdgpu_virtual_display && 1132 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1133 supports_atomic = true; 1134 1135 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1136 DRM_INFO("This hardware requires experimental hardware support.\n" 1137 "See modparam exp_hw_support\n"); 1138 return -ENODEV; 1139 } 1140 1141 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1142 * however, SME requires an indirect IOMMU mapping because the encryption 1143 * bit is beyond the DMA mask of the chip. 1144 */ 1145 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1146 dev_info(&pdev->dev, 1147 "SME is not compatible with RAVEN\n"); 1148 return -ENOTSUPP; 1149 } 1150 1151 #ifdef CONFIG_DRM_AMDGPU_SI 1152 if (!amdgpu_si_support) { 1153 switch (flags & AMD_ASIC_MASK) { 1154 case CHIP_TAHITI: 1155 case CHIP_PITCAIRN: 1156 case CHIP_VERDE: 1157 case CHIP_OLAND: 1158 case CHIP_HAINAN: 1159 dev_info(&pdev->dev, 1160 "SI support provided by radeon.\n"); 1161 dev_info(&pdev->dev, 1162 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1163 ); 1164 return -ENODEV; 1165 } 1166 } 1167 #endif 1168 #ifdef CONFIG_DRM_AMDGPU_CIK 1169 if (!amdgpu_cik_support) { 1170 switch (flags & AMD_ASIC_MASK) { 1171 case CHIP_KAVERI: 1172 case CHIP_BONAIRE: 1173 case CHIP_HAWAII: 1174 case CHIP_KABINI: 1175 case CHIP_MULLINS: 1176 dev_info(&pdev->dev, 1177 "CIK support provided by radeon.\n"); 1178 dev_info(&pdev->dev, 1179 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1180 ); 1181 return -ENODEV; 1182 } 1183 } 1184 #endif 1185 1186 /* Get rid of things like offb */ 1187 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1188 if (ret) 1189 return ret; 1190 1191 adev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*adev), ddev); 1192 if (IS_ERR(adev)) 1193 return PTR_ERR(adev); 1194 1195 adev->dev = &pdev->dev; 1196 adev->pdev = pdev; 1197 ddev = adev_to_drm(adev); 1198 1199 if (!supports_atomic) 1200 ddev->driver_features &= ~DRIVER_ATOMIC; 1201 1202 ret = pci_enable_device(pdev); 1203 if (ret) 1204 return ret; 1205 1206 ddev->pdev = pdev; 1207 pci_set_drvdata(pdev, ddev); 1208 1209 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1210 if (ret) 1211 goto err_pci; 1212 1213 retry_init: 1214 ret = drm_dev_register(ddev, ent->driver_data); 1215 if (ret == -EAGAIN && ++retry <= 3) { 1216 DRM_INFO("retry init %d\n", retry); 1217 /* Don't request EX mode too frequently which is attacking */ 1218 msleep(5000); 1219 goto retry_init; 1220 } else if (ret) { 1221 goto err_pci; 1222 } 1223 1224 ret = amdgpu_debugfs_init(adev); 1225 if (ret) 1226 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1227 1228 return 0; 1229 1230 err_pci: 1231 pci_disable_device(pdev); 1232 return ret; 1233 } 1234 1235 static void 1236 amdgpu_pci_remove(struct pci_dev *pdev) 1237 { 1238 struct drm_device *dev = pci_get_drvdata(pdev); 1239 1240 #ifdef MODULE 1241 if (THIS_MODULE->state != MODULE_STATE_GOING) 1242 #endif 1243 DRM_ERROR("Hotplug removal is not supported\n"); 1244 drm_dev_unplug(dev); 1245 amdgpu_driver_unload_kms(dev); 1246 pci_disable_device(pdev); 1247 pci_set_drvdata(pdev, NULL); 1248 } 1249 1250 static void 1251 amdgpu_pci_shutdown(struct pci_dev *pdev) 1252 { 1253 struct drm_device *dev = pci_get_drvdata(pdev); 1254 struct amdgpu_device *adev = drm_to_adev(dev); 1255 1256 if (amdgpu_ras_intr_triggered()) 1257 return; 1258 1259 /* if we are running in a VM, make sure the device 1260 * torn down properly on reboot/shutdown. 1261 * unfortunately we can't detect certain 1262 * hypervisors so just do this all the time. 1263 */ 1264 if (!amdgpu_passthrough(adev)) 1265 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1266 amdgpu_device_ip_suspend(adev); 1267 adev->mp1_state = PP_MP1_STATE_NONE; 1268 } 1269 1270 static int amdgpu_pmops_suspend(struct device *dev) 1271 { 1272 struct drm_device *drm_dev = dev_get_drvdata(dev); 1273 1274 return amdgpu_device_suspend(drm_dev, true); 1275 } 1276 1277 static int amdgpu_pmops_resume(struct device *dev) 1278 { 1279 struct drm_device *drm_dev = dev_get_drvdata(dev); 1280 1281 return amdgpu_device_resume(drm_dev, true); 1282 } 1283 1284 static int amdgpu_pmops_freeze(struct device *dev) 1285 { 1286 struct drm_device *drm_dev = dev_get_drvdata(dev); 1287 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1288 int r; 1289 1290 adev->in_hibernate = true; 1291 r = amdgpu_device_suspend(drm_dev, true); 1292 adev->in_hibernate = false; 1293 if (r) 1294 return r; 1295 return amdgpu_asic_reset(adev); 1296 } 1297 1298 static int amdgpu_pmops_thaw(struct device *dev) 1299 { 1300 struct drm_device *drm_dev = dev_get_drvdata(dev); 1301 1302 return amdgpu_device_resume(drm_dev, true); 1303 } 1304 1305 static int amdgpu_pmops_poweroff(struct device *dev) 1306 { 1307 struct drm_device *drm_dev = dev_get_drvdata(dev); 1308 1309 return amdgpu_device_suspend(drm_dev, true); 1310 } 1311 1312 static int amdgpu_pmops_restore(struct device *dev) 1313 { 1314 struct drm_device *drm_dev = dev_get_drvdata(dev); 1315 1316 return amdgpu_device_resume(drm_dev, true); 1317 } 1318 1319 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1320 { 1321 struct pci_dev *pdev = to_pci_dev(dev); 1322 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1323 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1324 int ret, i; 1325 1326 if (!adev->runpm) { 1327 pm_runtime_forbid(dev); 1328 return -EBUSY; 1329 } 1330 1331 /* wait for all rings to drain before suspending */ 1332 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1333 struct amdgpu_ring *ring = adev->rings[i]; 1334 if (ring && ring->sched.ready) { 1335 ret = amdgpu_fence_wait_empty(ring); 1336 if (ret) 1337 return -EBUSY; 1338 } 1339 } 1340 1341 adev->in_runpm = true; 1342 if (amdgpu_device_supports_boco(drm_dev)) 1343 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1344 drm_kms_helper_poll_disable(drm_dev); 1345 1346 ret = amdgpu_device_suspend(drm_dev, false); 1347 if (ret) 1348 return ret; 1349 1350 if (amdgpu_device_supports_boco(drm_dev)) { 1351 /* Only need to handle PCI state in the driver for ATPX 1352 * PCI core handles it for _PR3. 1353 */ 1354 if (amdgpu_is_atpx_hybrid()) { 1355 pci_ignore_hotplug(pdev); 1356 } else { 1357 amdgpu_device_cache_pci_state(pdev); 1358 pci_disable_device(pdev); 1359 pci_ignore_hotplug(pdev); 1360 pci_set_power_state(pdev, PCI_D3cold); 1361 } 1362 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1363 } else if (amdgpu_device_supports_baco(drm_dev)) { 1364 amdgpu_device_baco_enter(drm_dev); 1365 } 1366 1367 return 0; 1368 } 1369 1370 static int amdgpu_pmops_runtime_resume(struct device *dev) 1371 { 1372 struct pci_dev *pdev = to_pci_dev(dev); 1373 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1374 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1375 int ret; 1376 1377 if (!adev->runpm) 1378 return -EINVAL; 1379 1380 if (amdgpu_device_supports_boco(drm_dev)) { 1381 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1382 1383 /* Only need to handle PCI state in the driver for ATPX 1384 * PCI core handles it for _PR3. 1385 */ 1386 if (amdgpu_is_atpx_hybrid()) { 1387 pci_set_master(pdev); 1388 } else { 1389 pci_set_power_state(pdev, PCI_D0); 1390 amdgpu_device_load_pci_state(pdev); 1391 ret = pci_enable_device(pdev); 1392 if (ret) 1393 return ret; 1394 pci_set_master(pdev); 1395 } 1396 } else if (amdgpu_device_supports_baco(drm_dev)) { 1397 amdgpu_device_baco_exit(drm_dev); 1398 } 1399 ret = amdgpu_device_resume(drm_dev, false); 1400 drm_kms_helper_poll_enable(drm_dev); 1401 if (amdgpu_device_supports_boco(drm_dev)) 1402 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1403 adev->in_runpm = false; 1404 return 0; 1405 } 1406 1407 static int amdgpu_pmops_runtime_idle(struct device *dev) 1408 { 1409 struct drm_device *drm_dev = dev_get_drvdata(dev); 1410 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1411 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1412 int ret = 1; 1413 1414 if (!adev->runpm) { 1415 pm_runtime_forbid(dev); 1416 return -EBUSY; 1417 } 1418 1419 if (amdgpu_device_has_dc_support(adev)) { 1420 struct drm_crtc *crtc; 1421 1422 drm_modeset_lock_all(drm_dev); 1423 1424 drm_for_each_crtc(crtc, drm_dev) { 1425 if (crtc->state->active) { 1426 ret = -EBUSY; 1427 break; 1428 } 1429 } 1430 1431 drm_modeset_unlock_all(drm_dev); 1432 1433 } else { 1434 struct drm_connector *list_connector; 1435 struct drm_connector_list_iter iter; 1436 1437 mutex_lock(&drm_dev->mode_config.mutex); 1438 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1439 1440 drm_connector_list_iter_begin(drm_dev, &iter); 1441 drm_for_each_connector_iter(list_connector, &iter) { 1442 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1443 ret = -EBUSY; 1444 break; 1445 } 1446 } 1447 1448 drm_connector_list_iter_end(&iter); 1449 1450 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1451 mutex_unlock(&drm_dev->mode_config.mutex); 1452 } 1453 1454 if (ret == -EBUSY) 1455 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1456 1457 pm_runtime_mark_last_busy(dev); 1458 pm_runtime_autosuspend(dev); 1459 return ret; 1460 } 1461 1462 long amdgpu_drm_ioctl(struct file *filp, 1463 unsigned int cmd, unsigned long arg) 1464 { 1465 struct drm_file *file_priv = filp->private_data; 1466 struct drm_device *dev; 1467 long ret; 1468 dev = file_priv->minor->dev; 1469 ret = pm_runtime_get_sync(dev->dev); 1470 if (ret < 0) 1471 goto out; 1472 1473 ret = drm_ioctl(filp, cmd, arg); 1474 1475 pm_runtime_mark_last_busy(dev->dev); 1476 out: 1477 pm_runtime_put_autosuspend(dev->dev); 1478 return ret; 1479 } 1480 1481 static const struct dev_pm_ops amdgpu_pm_ops = { 1482 .suspend = amdgpu_pmops_suspend, 1483 .resume = amdgpu_pmops_resume, 1484 .freeze = amdgpu_pmops_freeze, 1485 .thaw = amdgpu_pmops_thaw, 1486 .poweroff = amdgpu_pmops_poweroff, 1487 .restore = amdgpu_pmops_restore, 1488 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1489 .runtime_resume = amdgpu_pmops_runtime_resume, 1490 .runtime_idle = amdgpu_pmops_runtime_idle, 1491 }; 1492 1493 static int amdgpu_flush(struct file *f, fl_owner_t id) 1494 { 1495 struct drm_file *file_priv = f->private_data; 1496 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1497 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1498 1499 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1500 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1501 1502 return timeout >= 0 ? 0 : timeout; 1503 } 1504 1505 static const struct file_operations amdgpu_driver_kms_fops = { 1506 .owner = THIS_MODULE, 1507 .open = drm_open, 1508 .flush = amdgpu_flush, 1509 .release = drm_release, 1510 .unlocked_ioctl = amdgpu_drm_ioctl, 1511 .mmap = amdgpu_mmap, 1512 .poll = drm_poll, 1513 .read = drm_read, 1514 #ifdef CONFIG_COMPAT 1515 .compat_ioctl = amdgpu_kms_compat_ioctl, 1516 #endif 1517 }; 1518 1519 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1520 { 1521 struct drm_file *file; 1522 1523 if (!filp) 1524 return -EINVAL; 1525 1526 if (filp->f_op != &amdgpu_driver_kms_fops) { 1527 return -EINVAL; 1528 } 1529 1530 file = filp->private_data; 1531 *fpriv = file->driver_priv; 1532 return 0; 1533 } 1534 1535 static struct drm_driver kms_driver = { 1536 .driver_features = 1537 DRIVER_ATOMIC | 1538 DRIVER_GEM | 1539 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1540 DRIVER_SYNCOBJ_TIMELINE, 1541 .open = amdgpu_driver_open_kms, 1542 .postclose = amdgpu_driver_postclose_kms, 1543 .lastclose = amdgpu_driver_lastclose_kms, 1544 .irq_handler = amdgpu_irq_handler, 1545 .ioctls = amdgpu_ioctls_kms, 1546 .dumb_create = amdgpu_mode_dumb_create, 1547 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1548 .fops = &amdgpu_driver_kms_fops, 1549 1550 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1551 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1552 .gem_prime_import = amdgpu_gem_prime_import, 1553 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1554 1555 .name = DRIVER_NAME, 1556 .desc = DRIVER_DESC, 1557 .date = DRIVER_DATE, 1558 .major = KMS_DRIVER_MAJOR, 1559 .minor = KMS_DRIVER_MINOR, 1560 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1561 }; 1562 1563 static struct pci_error_handlers amdgpu_pci_err_handler = { 1564 .error_detected = amdgpu_pci_error_detected, 1565 .mmio_enabled = amdgpu_pci_mmio_enabled, 1566 .slot_reset = amdgpu_pci_slot_reset, 1567 .resume = amdgpu_pci_resume, 1568 }; 1569 1570 static struct pci_driver amdgpu_kms_pci_driver = { 1571 .name = DRIVER_NAME, 1572 .id_table = pciidlist, 1573 .probe = amdgpu_pci_probe, 1574 .remove = amdgpu_pci_remove, 1575 .shutdown = amdgpu_pci_shutdown, 1576 .driver.pm = &amdgpu_pm_ops, 1577 .err_handler = &amdgpu_pci_err_handler, 1578 }; 1579 1580 static int __init amdgpu_init(void) 1581 { 1582 int r; 1583 1584 if (vgacon_text_force()) { 1585 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1586 return -EINVAL; 1587 } 1588 1589 r = amdgpu_sync_init(); 1590 if (r) 1591 goto error_sync; 1592 1593 r = amdgpu_fence_slab_init(); 1594 if (r) 1595 goto error_fence; 1596 1597 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1598 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1599 amdgpu_register_atpx_handler(); 1600 1601 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1602 amdgpu_amdkfd_init(); 1603 1604 /* let modprobe override vga console setting */ 1605 return pci_register_driver(&amdgpu_kms_pci_driver); 1606 1607 error_fence: 1608 amdgpu_sync_fini(); 1609 1610 error_sync: 1611 return r; 1612 } 1613 1614 static void __exit amdgpu_exit(void) 1615 { 1616 amdgpu_amdkfd_fini(); 1617 pci_unregister_driver(&amdgpu_kms_pci_driver); 1618 amdgpu_unregister_atpx_handler(); 1619 amdgpu_sync_fini(); 1620 amdgpu_fence_slab_fini(); 1621 mmu_notifier_synchronize(); 1622 } 1623 1624 module_init(amdgpu_init); 1625 module_exit(amdgpu_exit); 1626 1627 MODULE_AUTHOR(DRIVER_AUTHOR); 1628 MODULE_DESCRIPTION(DRIVER_DESC); 1629 MODULE_LICENSE("GPL and additional rights"); 1630