1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include <drm/drm_crtc_helper.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 * - 3.16.0 - Add reserved vmid support 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 70 * - 3.18.0 - Export gpu always on cu bitmap 71 * - 3.19.0 - Add support for UVD MJPEG decode 72 * - 3.20.0 - Add support for local BOs 73 */ 74 #define KMS_DRIVER_MAJOR 3 75 #define KMS_DRIVER_MINOR 20 76 #define KMS_DRIVER_PATCHLEVEL 0 77 78 int amdgpu_vram_limit = 0; 79 int amdgpu_vis_vram_limit = 0; 80 int amdgpu_gart_size = -1; /* auto */ 81 int amdgpu_gtt_size = -1; /* auto */ 82 int amdgpu_moverate = -1; /* auto */ 83 int amdgpu_benchmarking = 0; 84 int amdgpu_testing = 0; 85 int amdgpu_audio = -1; 86 int amdgpu_disp_priority = 0; 87 int amdgpu_hw_i2c = 0; 88 int amdgpu_pcie_gen2 = -1; 89 int amdgpu_msi = -1; 90 int amdgpu_lockup_timeout = 0; 91 int amdgpu_dpm = -1; 92 int amdgpu_fw_load_type = -1; 93 int amdgpu_aspm = -1; 94 int amdgpu_runtime_pm = -1; 95 uint amdgpu_ip_block_mask = 0xffffffff; 96 int amdgpu_bapm = -1; 97 int amdgpu_deep_color = 0; 98 int amdgpu_vm_size = -1; 99 int amdgpu_vm_fragment_size = -1; 100 int amdgpu_vm_block_size = -1; 101 int amdgpu_vm_fault_stop = 0; 102 int amdgpu_vm_debug = 0; 103 int amdgpu_vram_page_split = 512; 104 int amdgpu_vm_update_mode = -1; 105 int amdgpu_exp_hw_support = 0; 106 int amdgpu_dc = -1; 107 int amdgpu_dc_log = 0; 108 int amdgpu_sched_jobs = 32; 109 int amdgpu_sched_hw_submission = 2; 110 int amdgpu_no_evict = 0; 111 int amdgpu_direct_gma_size = 0; 112 uint amdgpu_pcie_gen_cap = 0; 113 uint amdgpu_pcie_lane_cap = 0; 114 uint amdgpu_cg_mask = 0xffffffff; 115 uint amdgpu_pg_mask = 0xffffffff; 116 uint amdgpu_sdma_phase_quantum = 32; 117 char *amdgpu_disable_cu = NULL; 118 char *amdgpu_virtual_display = NULL; 119 uint amdgpu_pp_feature_mask = 0xffffffff; 120 int amdgpu_ngg = 0; 121 int amdgpu_prim_buf_per_se = 0; 122 int amdgpu_pos_buf_per_se = 0; 123 int amdgpu_cntl_sb_buf_per_se = 0; 124 int amdgpu_param_buf_per_se = 0; 125 int amdgpu_job_hang_limit = 0; 126 int amdgpu_lbpw = -1; 127 128 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 129 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 130 131 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 132 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 133 134 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 135 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 136 137 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 138 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 139 140 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 141 module_param_named(moverate, amdgpu_moverate, int, 0600); 142 143 MODULE_PARM_DESC(benchmark, "Run benchmark"); 144 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 145 146 MODULE_PARM_DESC(test, "Run tests"); 147 module_param_named(test, amdgpu_testing, int, 0444); 148 149 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 150 module_param_named(audio, amdgpu_audio, int, 0444); 151 152 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 153 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 154 155 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 156 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 157 158 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 159 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 160 161 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 162 module_param_named(msi, amdgpu_msi, int, 0444); 163 164 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 165 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 166 167 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 168 module_param_named(dpm, amdgpu_dpm, int, 0444); 169 170 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 171 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 172 173 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 174 module_param_named(aspm, amdgpu_aspm, int, 0444); 175 176 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 177 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 178 179 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 180 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 181 182 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 183 module_param_named(bapm, amdgpu_bapm, int, 0444); 184 185 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 186 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 187 188 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 189 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 190 191 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 192 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 193 194 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 195 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 196 197 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 198 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 199 200 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 201 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 202 203 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 204 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 205 206 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); 207 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 208 209 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 210 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 211 212 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 213 module_param_named(dc, amdgpu_dc, int, 0444); 214 215 MODULE_PARM_DESC(dc, "Display Core Log Level (0 = minimal (default), 1 = chatty"); 216 module_param_named(dc_log, amdgpu_dc_log, int, 0444); 217 218 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 219 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 220 221 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 222 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 223 224 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 225 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 226 227 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); 228 module_param_named(no_evict, amdgpu_no_evict, int, 0444); 229 230 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); 231 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); 232 233 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 234 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 235 236 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 237 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 238 239 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 240 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 241 242 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 243 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 244 245 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 246 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 247 248 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 249 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 250 251 MODULE_PARM_DESC(virtual_display, 252 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 253 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 254 255 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 256 module_param_named(ngg, amdgpu_ngg, int, 0444); 257 258 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 259 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 260 261 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 262 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 263 264 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 265 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 266 267 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); 268 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 269 270 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 271 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 272 273 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 274 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 275 276 #ifdef CONFIG_DRM_AMDGPU_SI 277 278 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 279 int amdgpu_si_support = 0; 280 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 281 #else 282 int amdgpu_si_support = 1; 283 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 284 #endif 285 286 module_param_named(si_support, amdgpu_si_support, int, 0444); 287 #endif 288 289 #ifdef CONFIG_DRM_AMDGPU_CIK 290 291 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 292 int amdgpu_cik_support = 0; 293 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 294 #else 295 int amdgpu_cik_support = 1; 296 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 297 #endif 298 299 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 300 #endif 301 302 303 static const struct pci_device_id pciidlist[] = { 304 #ifdef CONFIG_DRM_AMDGPU_SI 305 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 306 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 307 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 308 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 309 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 310 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 311 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 312 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 313 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 314 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 315 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 316 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 317 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 318 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 319 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 320 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 321 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 322 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 323 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 324 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 325 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 326 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 327 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 328 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 329 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 330 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 331 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 332 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 333 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 334 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 335 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 336 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 337 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 338 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 339 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 340 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 341 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 342 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 343 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 344 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 345 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 346 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 347 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 348 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 349 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 350 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 351 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 352 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 353 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 354 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 355 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 356 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 357 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 358 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 359 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 360 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 361 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 362 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 363 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 364 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 365 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 366 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 367 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 368 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 369 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 370 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 371 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 372 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 373 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 374 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 375 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 376 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 377 #endif 378 #ifdef CONFIG_DRM_AMDGPU_CIK 379 /* Kaveri */ 380 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 381 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 382 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 383 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 384 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 385 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 386 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 387 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 388 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 389 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 390 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 391 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 392 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 393 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 394 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 395 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 396 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 397 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 398 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 399 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 400 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 401 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 402 /* Bonaire */ 403 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 404 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 405 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 406 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 407 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 408 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 409 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 410 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 411 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 412 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 413 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 414 /* Hawaii */ 415 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 416 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 417 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 418 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 419 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 420 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 421 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 422 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 423 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 424 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 425 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 426 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 427 /* Kabini */ 428 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 429 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 430 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 431 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 432 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 433 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 434 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 435 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 436 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 437 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 438 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 439 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 440 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 441 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 442 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 443 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 444 /* mullins */ 445 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 446 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 447 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 448 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 449 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 450 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 451 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 452 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 453 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 454 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 455 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 456 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 457 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 458 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 459 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 460 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 461 #endif 462 /* topaz */ 463 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 464 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 465 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 466 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 467 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 468 /* tonga */ 469 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 470 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 471 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 472 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 473 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 474 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 475 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 476 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 477 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 478 /* fiji */ 479 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 480 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 481 /* carrizo */ 482 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 483 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 484 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 485 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 486 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 487 /* stoney */ 488 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 489 /* Polaris11 */ 490 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 491 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 492 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 493 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 494 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 495 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 496 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 497 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 498 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 499 /* Polaris10 */ 500 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 501 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 502 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 503 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 504 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 505 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 506 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 507 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 508 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 509 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 510 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 511 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 512 /* Polaris12 */ 513 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 514 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 515 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 516 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 517 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 518 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 519 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 520 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 521 /* Vega 10 */ 522 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 523 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 524 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 525 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 526 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 527 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 528 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 529 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 530 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 531 /* Raven */ 532 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, 533 534 {0, 0, 0} 535 }; 536 537 MODULE_DEVICE_TABLE(pci, pciidlist); 538 539 static struct drm_driver kms_driver; 540 541 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 542 { 543 struct apertures_struct *ap; 544 bool primary = false; 545 546 ap = alloc_apertures(1); 547 if (!ap) 548 return -ENOMEM; 549 550 ap->ranges[0].base = pci_resource_start(pdev, 0); 551 ap->ranges[0].size = pci_resource_len(pdev, 0); 552 553 #ifdef CONFIG_X86 554 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 555 #endif 556 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 557 kfree(ap); 558 559 return 0; 560 } 561 562 static int amdgpu_pci_probe(struct pci_dev *pdev, 563 const struct pci_device_id *ent) 564 { 565 struct drm_device *dev; 566 unsigned long flags = ent->driver_data; 567 int ret; 568 569 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 570 DRM_INFO("This hardware requires experimental hardware support.\n" 571 "See modparam exp_hw_support\n"); 572 return -ENODEV; 573 } 574 575 /* 576 * Initialize amdkfd before starting radeon. If it was not loaded yet, 577 * defer radeon probing 578 */ 579 ret = amdgpu_amdkfd_init(); 580 if (ret == -EPROBE_DEFER) 581 return ret; 582 583 /* Get rid of things like offb */ 584 ret = amdgpu_kick_out_firmware_fb(pdev); 585 if (ret) 586 return ret; 587 588 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 589 if (IS_ERR(dev)) 590 return PTR_ERR(dev); 591 592 ret = pci_enable_device(pdev); 593 if (ret) 594 goto err_free; 595 596 dev->pdev = pdev; 597 598 pci_set_drvdata(pdev, dev); 599 600 ret = drm_dev_register(dev, ent->driver_data); 601 if (ret) 602 goto err_pci; 603 604 return 0; 605 606 err_pci: 607 pci_disable_device(pdev); 608 err_free: 609 drm_dev_unref(dev); 610 return ret; 611 } 612 613 static void 614 amdgpu_pci_remove(struct pci_dev *pdev) 615 { 616 struct drm_device *dev = pci_get_drvdata(pdev); 617 618 drm_dev_unregister(dev); 619 drm_dev_unref(dev); 620 pci_disable_device(pdev); 621 pci_set_drvdata(pdev, NULL); 622 } 623 624 static void 625 amdgpu_pci_shutdown(struct pci_dev *pdev) 626 { 627 struct drm_device *dev = pci_get_drvdata(pdev); 628 struct amdgpu_device *adev = dev->dev_private; 629 630 /* if we are running in a VM, make sure the device 631 * torn down properly on reboot/shutdown. 632 * unfortunately we can't detect certain 633 * hypervisors so just do this all the time. 634 */ 635 amdgpu_suspend(adev); 636 } 637 638 static int amdgpu_pmops_suspend(struct device *dev) 639 { 640 struct pci_dev *pdev = to_pci_dev(dev); 641 642 struct drm_device *drm_dev = pci_get_drvdata(pdev); 643 return amdgpu_device_suspend(drm_dev, true, true); 644 } 645 646 static int amdgpu_pmops_resume(struct device *dev) 647 { 648 struct pci_dev *pdev = to_pci_dev(dev); 649 struct drm_device *drm_dev = pci_get_drvdata(pdev); 650 651 /* GPU comes up enabled by the bios on resume */ 652 if (amdgpu_device_is_px(drm_dev)) { 653 pm_runtime_disable(dev); 654 pm_runtime_set_active(dev); 655 pm_runtime_enable(dev); 656 } 657 658 return amdgpu_device_resume(drm_dev, true, true); 659 } 660 661 static int amdgpu_pmops_freeze(struct device *dev) 662 { 663 struct pci_dev *pdev = to_pci_dev(dev); 664 665 struct drm_device *drm_dev = pci_get_drvdata(pdev); 666 return amdgpu_device_suspend(drm_dev, false, true); 667 } 668 669 static int amdgpu_pmops_thaw(struct device *dev) 670 { 671 struct pci_dev *pdev = to_pci_dev(dev); 672 673 struct drm_device *drm_dev = pci_get_drvdata(pdev); 674 return amdgpu_device_resume(drm_dev, false, true); 675 } 676 677 static int amdgpu_pmops_poweroff(struct device *dev) 678 { 679 struct pci_dev *pdev = to_pci_dev(dev); 680 681 struct drm_device *drm_dev = pci_get_drvdata(pdev); 682 return amdgpu_device_suspend(drm_dev, true, true); 683 } 684 685 static int amdgpu_pmops_restore(struct device *dev) 686 { 687 struct pci_dev *pdev = to_pci_dev(dev); 688 689 struct drm_device *drm_dev = pci_get_drvdata(pdev); 690 return amdgpu_device_resume(drm_dev, false, true); 691 } 692 693 static int amdgpu_pmops_runtime_suspend(struct device *dev) 694 { 695 struct pci_dev *pdev = to_pci_dev(dev); 696 struct drm_device *drm_dev = pci_get_drvdata(pdev); 697 int ret; 698 699 if (!amdgpu_device_is_px(drm_dev)) { 700 pm_runtime_forbid(dev); 701 return -EBUSY; 702 } 703 704 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 705 drm_kms_helper_poll_disable(drm_dev); 706 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 707 708 ret = amdgpu_device_suspend(drm_dev, false, false); 709 pci_save_state(pdev); 710 pci_disable_device(pdev); 711 pci_ignore_hotplug(pdev); 712 if (amdgpu_is_atpx_hybrid()) 713 pci_set_power_state(pdev, PCI_D3cold); 714 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 715 pci_set_power_state(pdev, PCI_D3hot); 716 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 717 718 return 0; 719 } 720 721 static int amdgpu_pmops_runtime_resume(struct device *dev) 722 { 723 struct pci_dev *pdev = to_pci_dev(dev); 724 struct drm_device *drm_dev = pci_get_drvdata(pdev); 725 int ret; 726 727 if (!amdgpu_device_is_px(drm_dev)) 728 return -EINVAL; 729 730 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 731 732 if (amdgpu_is_atpx_hybrid() || 733 !amdgpu_has_atpx_dgpu_power_cntl()) 734 pci_set_power_state(pdev, PCI_D0); 735 pci_restore_state(pdev); 736 ret = pci_enable_device(pdev); 737 if (ret) 738 return ret; 739 pci_set_master(pdev); 740 741 ret = amdgpu_device_resume(drm_dev, false, false); 742 drm_kms_helper_poll_enable(drm_dev); 743 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 744 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 745 return 0; 746 } 747 748 static int amdgpu_pmops_runtime_idle(struct device *dev) 749 { 750 struct pci_dev *pdev = to_pci_dev(dev); 751 struct drm_device *drm_dev = pci_get_drvdata(pdev); 752 struct drm_crtc *crtc; 753 754 if (!amdgpu_device_is_px(drm_dev)) { 755 pm_runtime_forbid(dev); 756 return -EBUSY; 757 } 758 759 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 760 if (crtc->enabled) { 761 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 762 return -EBUSY; 763 } 764 } 765 766 pm_runtime_mark_last_busy(dev); 767 pm_runtime_autosuspend(dev); 768 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 769 return 1; 770 } 771 772 long amdgpu_drm_ioctl(struct file *filp, 773 unsigned int cmd, unsigned long arg) 774 { 775 struct drm_file *file_priv = filp->private_data; 776 struct drm_device *dev; 777 long ret; 778 dev = file_priv->minor->dev; 779 ret = pm_runtime_get_sync(dev->dev); 780 if (ret < 0) 781 return ret; 782 783 ret = drm_ioctl(filp, cmd, arg); 784 785 pm_runtime_mark_last_busy(dev->dev); 786 pm_runtime_put_autosuspend(dev->dev); 787 return ret; 788 } 789 790 static const struct dev_pm_ops amdgpu_pm_ops = { 791 .suspend = amdgpu_pmops_suspend, 792 .resume = amdgpu_pmops_resume, 793 .freeze = amdgpu_pmops_freeze, 794 .thaw = amdgpu_pmops_thaw, 795 .poweroff = amdgpu_pmops_poweroff, 796 .restore = amdgpu_pmops_restore, 797 .runtime_suspend = amdgpu_pmops_runtime_suspend, 798 .runtime_resume = amdgpu_pmops_runtime_resume, 799 .runtime_idle = amdgpu_pmops_runtime_idle, 800 }; 801 802 static const struct file_operations amdgpu_driver_kms_fops = { 803 .owner = THIS_MODULE, 804 .open = drm_open, 805 .release = drm_release, 806 .unlocked_ioctl = amdgpu_drm_ioctl, 807 .mmap = amdgpu_mmap, 808 .poll = drm_poll, 809 .read = drm_read, 810 #ifdef CONFIG_COMPAT 811 .compat_ioctl = amdgpu_kms_compat_ioctl, 812 #endif 813 }; 814 815 static bool 816 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 817 bool in_vblank_irq, int *vpos, int *hpos, 818 ktime_t *stime, ktime_t *etime, 819 const struct drm_display_mode *mode) 820 { 821 return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 822 stime, etime, mode); 823 } 824 825 static struct drm_driver kms_driver = { 826 .driver_features = 827 DRIVER_USE_AGP | 828 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 829 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 830 .load = amdgpu_driver_load_kms, 831 .open = amdgpu_driver_open_kms, 832 .postclose = amdgpu_driver_postclose_kms, 833 .lastclose = amdgpu_driver_lastclose_kms, 834 .unload = amdgpu_driver_unload_kms, 835 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 836 .enable_vblank = amdgpu_enable_vblank_kms, 837 .disable_vblank = amdgpu_disable_vblank_kms, 838 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 839 .get_scanout_position = amdgpu_get_crtc_scanout_position, 840 #if defined(CONFIG_DEBUG_FS) 841 .debugfs_init = amdgpu_debugfs_init, 842 #endif 843 .irq_preinstall = amdgpu_irq_preinstall, 844 .irq_postinstall = amdgpu_irq_postinstall, 845 .irq_uninstall = amdgpu_irq_uninstall, 846 .irq_handler = amdgpu_irq_handler, 847 .ioctls = amdgpu_ioctls_kms, 848 .gem_free_object_unlocked = amdgpu_gem_object_free, 849 .gem_open_object = amdgpu_gem_object_open, 850 .gem_close_object = amdgpu_gem_object_close, 851 .dumb_create = amdgpu_mode_dumb_create, 852 .dumb_map_offset = amdgpu_mode_dumb_mmap, 853 .fops = &amdgpu_driver_kms_fops, 854 855 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 856 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 857 .gem_prime_export = amdgpu_gem_prime_export, 858 .gem_prime_import = drm_gem_prime_import, 859 .gem_prime_pin = amdgpu_gem_prime_pin, 860 .gem_prime_unpin = amdgpu_gem_prime_unpin, 861 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 862 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 863 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 864 .gem_prime_vmap = amdgpu_gem_prime_vmap, 865 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 866 .gem_prime_mmap = amdgpu_gem_prime_mmap, 867 868 .name = DRIVER_NAME, 869 .desc = DRIVER_DESC, 870 .date = DRIVER_DATE, 871 .major = KMS_DRIVER_MAJOR, 872 .minor = KMS_DRIVER_MINOR, 873 .patchlevel = KMS_DRIVER_PATCHLEVEL, 874 }; 875 876 static struct drm_driver *driver; 877 static struct pci_driver *pdriver; 878 879 static struct pci_driver amdgpu_kms_pci_driver = { 880 .name = DRIVER_NAME, 881 .id_table = pciidlist, 882 .probe = amdgpu_pci_probe, 883 .remove = amdgpu_pci_remove, 884 .shutdown = amdgpu_pci_shutdown, 885 .driver.pm = &amdgpu_pm_ops, 886 }; 887 888 889 890 static int __init amdgpu_init(void) 891 { 892 int r; 893 894 r = amdgpu_sync_init(); 895 if (r) 896 goto error_sync; 897 898 r = amdgpu_fence_slab_init(); 899 if (r) 900 goto error_fence; 901 902 r = amd_sched_fence_slab_init(); 903 if (r) 904 goto error_sched; 905 906 if (vgacon_text_force()) { 907 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 908 return -EINVAL; 909 } 910 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 911 driver = &kms_driver; 912 pdriver = &amdgpu_kms_pci_driver; 913 driver->num_ioctls = amdgpu_max_kms_ioctl; 914 amdgpu_register_atpx_handler(); 915 /* let modprobe override vga console setting */ 916 return pci_register_driver(pdriver); 917 918 error_sched: 919 amdgpu_fence_slab_fini(); 920 921 error_fence: 922 amdgpu_sync_fini(); 923 924 error_sync: 925 return r; 926 } 927 928 static void __exit amdgpu_exit(void) 929 { 930 amdgpu_amdkfd_fini(); 931 pci_unregister_driver(pdriver); 932 amdgpu_unregister_atpx_handler(); 933 amdgpu_sync_fini(); 934 amd_sched_fence_slab_fini(); 935 amdgpu_fence_slab_fini(); 936 } 937 938 module_init(amdgpu_init); 939 module_exit(amdgpu_exit); 940 941 MODULE_AUTHOR(DRIVER_AUTHOR); 942 MODULE_DESCRIPTION(DRIVER_DESC); 943 MODULE_LICENSE("GPL and additional rights"); 944