1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/fb.h> 42 #include <linux/dynamic_debug.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 #include "amdgpu_dma_buf.h" 47 #include "amdgpu_sched.h" 48 #include "amdgpu_fdinfo.h" 49 #include "amdgpu_amdkfd.h" 50 51 #include "amdgpu_ras.h" 52 #include "amdgpu_xgmi.h" 53 #include "amdgpu_reset.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 */ 108 #define KMS_DRIVER_MAJOR 3 109 #define KMS_DRIVER_MINOR 48 110 #define KMS_DRIVER_PATCHLEVEL 0 111 112 int amdgpu_vram_limit; 113 int amdgpu_vis_vram_limit; 114 int amdgpu_gart_size = -1; /* auto */ 115 int amdgpu_gtt_size = -1; /* auto */ 116 int amdgpu_moverate = -1; /* auto */ 117 int amdgpu_audio = -1; 118 int amdgpu_disp_priority; 119 int amdgpu_hw_i2c; 120 int amdgpu_pcie_gen2 = -1; 121 int amdgpu_msi = -1; 122 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 123 int amdgpu_dpm = -1; 124 int amdgpu_fw_load_type = -1; 125 int amdgpu_aspm = -1; 126 int amdgpu_runtime_pm = -1; 127 uint amdgpu_ip_block_mask = 0xffffffff; 128 int amdgpu_bapm = -1; 129 int amdgpu_deep_color; 130 int amdgpu_vm_size = -1; 131 int amdgpu_vm_fragment_size = -1; 132 int amdgpu_vm_block_size = -1; 133 int amdgpu_vm_fault_stop; 134 int amdgpu_vm_debug; 135 int amdgpu_vm_update_mode = -1; 136 int amdgpu_exp_hw_support; 137 int amdgpu_dc = -1; 138 int amdgpu_sched_jobs = 32; 139 int amdgpu_sched_hw_submission = 2; 140 uint amdgpu_pcie_gen_cap; 141 uint amdgpu_pcie_lane_cap; 142 u64 amdgpu_cg_mask = 0xffffffffffffffff; 143 uint amdgpu_pg_mask = 0xffffffff; 144 uint amdgpu_sdma_phase_quantum = 32; 145 char *amdgpu_disable_cu = NULL; 146 char *amdgpu_virtual_display = NULL; 147 148 /* 149 * OverDrive(bit 14) disabled by default 150 * GFX DCS(bit 19) disabled by default 151 */ 152 uint amdgpu_pp_feature_mask = 0xfff7bfff; 153 uint amdgpu_force_long_training; 154 int amdgpu_job_hang_limit; 155 int amdgpu_lbpw = -1; 156 int amdgpu_compute_multipipe = -1; 157 int amdgpu_gpu_recovery = -1; /* auto */ 158 int amdgpu_emu_mode; 159 uint amdgpu_smu_memory_pool_size; 160 int amdgpu_smu_pptable_id = -1; 161 /* 162 * FBC (bit 0) disabled by default 163 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 164 * - With this, for multiple monitors in sync(e.g. with the same model), 165 * mclk switching will be allowed. And the mclk will be not foced to the 166 * highest. That helps saving some idle power. 167 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 168 * PSR (bit 3) disabled by default 169 * EDP NO POWER SEQUENCING (bit 4) disabled by default 170 */ 171 uint amdgpu_dc_feature_mask = 2; 172 uint amdgpu_dc_debug_mask; 173 uint amdgpu_dc_visual_confirm; 174 int amdgpu_async_gfx_ring = 1; 175 int amdgpu_mcbp; 176 int amdgpu_discovery = -1; 177 int amdgpu_mes; 178 int amdgpu_mes_kiq; 179 int amdgpu_noretry = -1; 180 int amdgpu_force_asic_type = -1; 181 int amdgpu_tmz = -1; /* auto */ 182 int amdgpu_reset_method = -1; /* auto */ 183 int amdgpu_num_kcq = -1; 184 int amdgpu_smartshift_bias; 185 int amdgpu_use_xgmi_p2p = 1; 186 int amdgpu_vcnfw_log; 187 188 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 189 190 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 191 "DRM_UT_CORE", 192 "DRM_UT_DRIVER", 193 "DRM_UT_KMS", 194 "DRM_UT_PRIME", 195 "DRM_UT_ATOMIC", 196 "DRM_UT_VBL", 197 "DRM_UT_STATE", 198 "DRM_UT_LEASE", 199 "DRM_UT_DP", 200 "DRM_UT_DRMRES"); 201 202 struct amdgpu_mgpu_info mgpu_info = { 203 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 204 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 205 mgpu_info.delayed_reset_work, 206 amdgpu_drv_delayed_reset_work_handler, 0), 207 }; 208 int amdgpu_ras_enable = -1; 209 uint amdgpu_ras_mask = 0xffffffff; 210 int amdgpu_bad_page_threshold = -1; 211 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 212 .timeout_fatal_disable = false, 213 .period = 0x0, /* default to 0x0 (timeout disable) */ 214 }; 215 216 /** 217 * DOC: vramlimit (int) 218 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 219 */ 220 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 221 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 222 223 /** 224 * DOC: vis_vramlimit (int) 225 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 226 */ 227 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 228 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 229 230 /** 231 * DOC: gartsize (uint) 232 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 233 */ 234 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 235 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 236 237 /** 238 * DOC: gttsize (int) 239 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 240 * otherwise 3/4 RAM size). 241 */ 242 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 243 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 244 245 /** 246 * DOC: moverate (int) 247 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 248 */ 249 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 250 module_param_named(moverate, amdgpu_moverate, int, 0600); 251 252 /** 253 * DOC: audio (int) 254 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 255 */ 256 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 257 module_param_named(audio, amdgpu_audio, int, 0444); 258 259 /** 260 * DOC: disp_priority (int) 261 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 262 */ 263 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 264 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 265 266 /** 267 * DOC: hw_i2c (int) 268 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 269 */ 270 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 271 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 272 273 /** 274 * DOC: pcie_gen2 (int) 275 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 276 */ 277 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 278 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 279 280 /** 281 * DOC: msi (int) 282 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 283 */ 284 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 285 module_param_named(msi, amdgpu_msi, int, 0444); 286 287 /** 288 * DOC: lockup_timeout (string) 289 * Set GPU scheduler timeout value in ms. 290 * 291 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 292 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 293 * to the default timeout. 294 * 295 * - With one value specified, the setting will apply to all non-compute jobs. 296 * - With multiple values specified, the first one will be for GFX. 297 * The second one is for Compute. The third and fourth ones are 298 * for SDMA and Video. 299 * 300 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 301 * jobs is 10000. The timeout for compute is 60000. 302 */ 303 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 304 "for passthrough or sriov, 10000 for all jobs." 305 " 0: keep default value. negative: infinity timeout), " 306 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 307 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 308 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 309 310 /** 311 * DOC: dpm (int) 312 * Override for dynamic power management setting 313 * (0 = disable, 1 = enable) 314 * The default is -1 (auto). 315 */ 316 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 317 module_param_named(dpm, amdgpu_dpm, int, 0444); 318 319 /** 320 * DOC: fw_load_type (int) 321 * Set different firmware loading type for debugging, if supported. 322 * Set to 0 to force direct loading if supported by the ASIC. Set 323 * to -1 to select the default loading mode for the ASIC, as defined 324 * by the driver. The default is -1 (auto). 325 */ 326 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 327 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 328 329 /** 330 * DOC: aspm (int) 331 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 332 */ 333 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 334 module_param_named(aspm, amdgpu_aspm, int, 0444); 335 336 /** 337 * DOC: runpm (int) 338 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 339 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 340 * Setting the value to 0 disables this functionality. 341 */ 342 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 343 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 344 345 /** 346 * DOC: ip_block_mask (uint) 347 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 348 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 349 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 350 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 351 */ 352 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 353 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 354 355 /** 356 * DOC: bapm (int) 357 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 358 * The default -1 (auto, enabled) 359 */ 360 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 361 module_param_named(bapm, amdgpu_bapm, int, 0444); 362 363 /** 364 * DOC: deep_color (int) 365 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 366 */ 367 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 368 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 369 370 /** 371 * DOC: vm_size (int) 372 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 373 */ 374 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 375 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 376 377 /** 378 * DOC: vm_fragment_size (int) 379 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 380 */ 381 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 382 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 383 384 /** 385 * DOC: vm_block_size (int) 386 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 387 */ 388 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 389 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 390 391 /** 392 * DOC: vm_fault_stop (int) 393 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 394 */ 395 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 396 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 397 398 /** 399 * DOC: vm_debug (int) 400 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 401 */ 402 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 403 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 404 405 /** 406 * DOC: vm_update_mode (int) 407 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 408 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 409 */ 410 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 411 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 412 413 /** 414 * DOC: exp_hw_support (int) 415 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 416 */ 417 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 418 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 419 420 /** 421 * DOC: dc (int) 422 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 423 */ 424 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 425 module_param_named(dc, amdgpu_dc, int, 0444); 426 427 /** 428 * DOC: sched_jobs (int) 429 * Override the max number of jobs supported in the sw queue. The default is 32. 430 */ 431 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 432 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 433 434 /** 435 * DOC: sched_hw_submission (int) 436 * Override the max number of HW submissions. The default is 2. 437 */ 438 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 439 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 440 441 /** 442 * DOC: ppfeaturemask (hexint) 443 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 444 * The default is the current set of stable power features. 445 */ 446 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 447 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 448 449 /** 450 * DOC: forcelongtraining (uint) 451 * Force long memory training in resume. 452 * The default is zero, indicates short training in resume. 453 */ 454 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 455 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 456 457 /** 458 * DOC: pcie_gen_cap (uint) 459 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 460 * The default is 0 (automatic for each asic). 461 */ 462 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 463 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 464 465 /** 466 * DOC: pcie_lane_cap (uint) 467 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 468 * The default is 0 (automatic for each asic). 469 */ 470 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 471 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 472 473 /** 474 * DOC: cg_mask (ullong) 475 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 476 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 477 */ 478 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 479 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 480 481 /** 482 * DOC: pg_mask (uint) 483 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 484 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 485 */ 486 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 487 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 488 489 /** 490 * DOC: sdma_phase_quantum (uint) 491 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 492 */ 493 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 494 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 495 496 /** 497 * DOC: disable_cu (charp) 498 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 499 */ 500 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 501 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 502 503 /** 504 * DOC: virtual_display (charp) 505 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 506 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 507 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 508 * device at 26:00.0. The default is NULL. 509 */ 510 MODULE_PARM_DESC(virtual_display, 511 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 512 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 513 514 /** 515 * DOC: job_hang_limit (int) 516 * Set how much time allow a job hang and not drop it. The default is 0. 517 */ 518 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 519 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 520 521 /** 522 * DOC: lbpw (int) 523 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 524 */ 525 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 526 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 527 528 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 529 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 530 531 /** 532 * DOC: gpu_recovery (int) 533 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 534 */ 535 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 536 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 537 538 /** 539 * DOC: emu_mode (int) 540 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 541 */ 542 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 543 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 544 545 /** 546 * DOC: ras_enable (int) 547 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 548 */ 549 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 550 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 551 552 /** 553 * DOC: ras_mask (uint) 554 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 555 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 556 */ 557 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 558 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 559 560 /** 561 * DOC: timeout_fatal_disable (bool) 562 * Disable Watchdog timeout fatal error event 563 */ 564 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 565 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 566 567 /** 568 * DOC: timeout_period (uint) 569 * Modify the watchdog timeout max_cycles as (1 << period) 570 */ 571 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 572 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 573 574 /** 575 * DOC: si_support (int) 576 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 577 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 578 * otherwise using amdgpu driver. 579 */ 580 #ifdef CONFIG_DRM_AMDGPU_SI 581 582 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 583 int amdgpu_si_support = 0; 584 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 585 #else 586 int amdgpu_si_support = 1; 587 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 588 #endif 589 590 module_param_named(si_support, amdgpu_si_support, int, 0444); 591 #endif 592 593 /** 594 * DOC: cik_support (int) 595 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 596 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 597 * otherwise using amdgpu driver. 598 */ 599 #ifdef CONFIG_DRM_AMDGPU_CIK 600 601 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 602 int amdgpu_cik_support = 0; 603 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 604 #else 605 int amdgpu_cik_support = 1; 606 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 607 #endif 608 609 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 610 #endif 611 612 /** 613 * DOC: smu_memory_pool_size (uint) 614 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 615 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 616 */ 617 MODULE_PARM_DESC(smu_memory_pool_size, 618 "reserve gtt for smu debug usage, 0 = disable," 619 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 620 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 621 622 /** 623 * DOC: async_gfx_ring (int) 624 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 625 */ 626 MODULE_PARM_DESC(async_gfx_ring, 627 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 628 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 629 630 /** 631 * DOC: mcbp (int) 632 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 633 */ 634 MODULE_PARM_DESC(mcbp, 635 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 636 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 637 638 /** 639 * DOC: discovery (int) 640 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 641 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 642 */ 643 MODULE_PARM_DESC(discovery, 644 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 645 module_param_named(discovery, amdgpu_discovery, int, 0444); 646 647 /** 648 * DOC: mes (int) 649 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 650 * (0 = disabled (default), 1 = enabled) 651 */ 652 MODULE_PARM_DESC(mes, 653 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 654 module_param_named(mes, amdgpu_mes, int, 0444); 655 656 /** 657 * DOC: mes_kiq (int) 658 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 659 * (0 = disabled (default), 1 = enabled) 660 */ 661 MODULE_PARM_DESC(mes_kiq, 662 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 663 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 664 665 /** 666 * DOC: noretry (int) 667 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 668 * do not support per-process XNACK this also disables retry page faults. 669 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 670 */ 671 MODULE_PARM_DESC(noretry, 672 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 673 module_param_named(noretry, amdgpu_noretry, int, 0644); 674 675 /** 676 * DOC: force_asic_type (int) 677 * A non negative value used to specify the asic type for all supported GPUs. 678 */ 679 MODULE_PARM_DESC(force_asic_type, 680 "A non negative value used to specify the asic type for all supported GPUs"); 681 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 682 683 /** 684 * DOC: use_xgmi_p2p (int) 685 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 686 */ 687 MODULE_PARM_DESC(use_xgmi_p2p, 688 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 689 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 690 691 692 #ifdef CONFIG_HSA_AMD 693 /** 694 * DOC: sched_policy (int) 695 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 696 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 697 * assigns queues to HQDs. 698 */ 699 int sched_policy = KFD_SCHED_POLICY_HWS; 700 module_param(sched_policy, int, 0444); 701 MODULE_PARM_DESC(sched_policy, 702 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 703 704 /** 705 * DOC: hws_max_conc_proc (int) 706 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 707 * number of VMIDs assigned to the HWS, which is also the default. 708 */ 709 int hws_max_conc_proc = -1; 710 module_param(hws_max_conc_proc, int, 0444); 711 MODULE_PARM_DESC(hws_max_conc_proc, 712 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 713 714 /** 715 * DOC: cwsr_enable (int) 716 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 717 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 718 * disables it. 719 */ 720 int cwsr_enable = 1; 721 module_param(cwsr_enable, int, 0444); 722 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 723 724 /** 725 * DOC: max_num_of_queues_per_device (int) 726 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 727 * is 4096. 728 */ 729 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 730 module_param(max_num_of_queues_per_device, int, 0444); 731 MODULE_PARM_DESC(max_num_of_queues_per_device, 732 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 733 734 /** 735 * DOC: send_sigterm (int) 736 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 737 * but just print errors on dmesg. Setting 1 enables sending sigterm. 738 */ 739 int send_sigterm; 740 module_param(send_sigterm, int, 0444); 741 MODULE_PARM_DESC(send_sigterm, 742 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 743 744 /** 745 * DOC: debug_largebar (int) 746 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 747 * system. This limits the VRAM size reported to ROCm applications to the visible 748 * size, usually 256MB. 749 * Default value is 0, diabled. 750 */ 751 int debug_largebar; 752 module_param(debug_largebar, int, 0444); 753 MODULE_PARM_DESC(debug_largebar, 754 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 755 756 /** 757 * DOC: ignore_crat (int) 758 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 759 * table to get information about AMD APUs. This option can serve as a workaround on 760 * systems with a broken CRAT table. 761 * 762 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 763 * whether use CRAT) 764 */ 765 int ignore_crat; 766 module_param(ignore_crat, int, 0444); 767 MODULE_PARM_DESC(ignore_crat, 768 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 769 770 /** 771 * DOC: halt_if_hws_hang (int) 772 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 773 * Setting 1 enables halt on hang. 774 */ 775 int halt_if_hws_hang; 776 module_param(halt_if_hws_hang, int, 0644); 777 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 778 779 /** 780 * DOC: hws_gws_support(bool) 781 * Assume that HWS supports GWS barriers regardless of what firmware version 782 * check says. Default value: false (rely on MEC2 firmware version check). 783 */ 784 bool hws_gws_support; 785 module_param(hws_gws_support, bool, 0444); 786 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 787 788 /** 789 * DOC: queue_preemption_timeout_ms (int) 790 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 791 */ 792 int queue_preemption_timeout_ms = 9000; 793 module_param(queue_preemption_timeout_ms, int, 0644); 794 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 795 796 /** 797 * DOC: debug_evictions(bool) 798 * Enable extra debug messages to help determine the cause of evictions 799 */ 800 bool debug_evictions; 801 module_param(debug_evictions, bool, 0644); 802 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 803 804 /** 805 * DOC: no_system_mem_limit(bool) 806 * Disable system memory limit, to support multiple process shared memory 807 */ 808 bool no_system_mem_limit; 809 module_param(no_system_mem_limit, bool, 0644); 810 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 811 812 /** 813 * DOC: no_queue_eviction_on_vm_fault (int) 814 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 815 */ 816 int amdgpu_no_queue_eviction_on_vm_fault = 0; 817 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 818 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 819 #endif 820 821 /** 822 * DOC: pcie_p2p (bool) 823 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 824 */ 825 #ifdef CONFIG_HSA_AMD_P2P 826 bool pcie_p2p = true; 827 module_param(pcie_p2p, bool, 0444); 828 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 829 #endif 830 831 /** 832 * DOC: dcfeaturemask (uint) 833 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 834 * The default is the current set of stable display features. 835 */ 836 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 837 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 838 839 /** 840 * DOC: dcdebugmask (uint) 841 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 842 */ 843 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 844 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 845 846 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 847 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 848 849 /** 850 * DOC: abmlevel (uint) 851 * Override the default ABM (Adaptive Backlight Management) level used for DC 852 * enabled hardware. Requires DMCU to be supported and loaded. 853 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 854 * default. Values 1-4 control the maximum allowable brightness reduction via 855 * the ABM algorithm, with 1 being the least reduction and 4 being the most 856 * reduction. 857 * 858 * Defaults to 0, or disabled. Userspace can still override this level later 859 * after boot. 860 */ 861 uint amdgpu_dm_abm_level; 862 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 863 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 864 865 int amdgpu_backlight = -1; 866 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 867 module_param_named(backlight, amdgpu_backlight, bint, 0444); 868 869 /** 870 * DOC: tmz (int) 871 * Trusted Memory Zone (TMZ) is a method to protect data being written 872 * to or read from memory. 873 * 874 * The default value: 0 (off). TODO: change to auto till it is completed. 875 */ 876 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 877 module_param_named(tmz, amdgpu_tmz, int, 0444); 878 879 /** 880 * DOC: reset_method (int) 881 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 882 */ 883 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 884 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 885 886 /** 887 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 888 * threshold value of faulty pages detected by RAS ECC, which may 889 * result in the GPU entering bad status when the number of total 890 * faulty pages by ECC exceeds the threshold value. 891 */ 892 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 893 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 894 895 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 896 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 897 898 /** 899 * DOC: vcnfw_log (int) 900 * Enable vcnfw log output for debugging, the default is disabled. 901 */ 902 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 903 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 904 905 /** 906 * DOC: smu_pptable_id (int) 907 * Used to override pptable id. id = 0 use VBIOS pptable. 908 * id > 0 use the soft pptable with specicfied id. 909 */ 910 MODULE_PARM_DESC(smu_pptable_id, 911 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 912 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 913 914 /* These devices are not supported by amdgpu. 915 * They are supported by the mach64, r128, radeon drivers 916 */ 917 static const u16 amdgpu_unsupported_pciidlist[] = { 918 /* mach64 */ 919 0x4354, 920 0x4358, 921 0x4554, 922 0x4742, 923 0x4744, 924 0x4749, 925 0x474C, 926 0x474D, 927 0x474E, 928 0x474F, 929 0x4750, 930 0x4751, 931 0x4752, 932 0x4753, 933 0x4754, 934 0x4755, 935 0x4756, 936 0x4757, 937 0x4758, 938 0x4759, 939 0x475A, 940 0x4C42, 941 0x4C44, 942 0x4C47, 943 0x4C49, 944 0x4C4D, 945 0x4C4E, 946 0x4C50, 947 0x4C51, 948 0x4C52, 949 0x4C53, 950 0x5654, 951 0x5655, 952 0x5656, 953 /* r128 */ 954 0x4c45, 955 0x4c46, 956 0x4d46, 957 0x4d4c, 958 0x5041, 959 0x5042, 960 0x5043, 961 0x5044, 962 0x5045, 963 0x5046, 964 0x5047, 965 0x5048, 966 0x5049, 967 0x504A, 968 0x504B, 969 0x504C, 970 0x504D, 971 0x504E, 972 0x504F, 973 0x5050, 974 0x5051, 975 0x5052, 976 0x5053, 977 0x5054, 978 0x5055, 979 0x5056, 980 0x5057, 981 0x5058, 982 0x5245, 983 0x5246, 984 0x5247, 985 0x524b, 986 0x524c, 987 0x534d, 988 0x5446, 989 0x544C, 990 0x5452, 991 /* radeon */ 992 0x3150, 993 0x3151, 994 0x3152, 995 0x3154, 996 0x3155, 997 0x3E50, 998 0x3E54, 999 0x4136, 1000 0x4137, 1001 0x4144, 1002 0x4145, 1003 0x4146, 1004 0x4147, 1005 0x4148, 1006 0x4149, 1007 0x414A, 1008 0x414B, 1009 0x4150, 1010 0x4151, 1011 0x4152, 1012 0x4153, 1013 0x4154, 1014 0x4155, 1015 0x4156, 1016 0x4237, 1017 0x4242, 1018 0x4336, 1019 0x4337, 1020 0x4437, 1021 0x4966, 1022 0x4967, 1023 0x4A48, 1024 0x4A49, 1025 0x4A4A, 1026 0x4A4B, 1027 0x4A4C, 1028 0x4A4D, 1029 0x4A4E, 1030 0x4A4F, 1031 0x4A50, 1032 0x4A54, 1033 0x4B48, 1034 0x4B49, 1035 0x4B4A, 1036 0x4B4B, 1037 0x4B4C, 1038 0x4C57, 1039 0x4C58, 1040 0x4C59, 1041 0x4C5A, 1042 0x4C64, 1043 0x4C66, 1044 0x4C67, 1045 0x4E44, 1046 0x4E45, 1047 0x4E46, 1048 0x4E47, 1049 0x4E48, 1050 0x4E49, 1051 0x4E4A, 1052 0x4E4B, 1053 0x4E50, 1054 0x4E51, 1055 0x4E52, 1056 0x4E53, 1057 0x4E54, 1058 0x4E56, 1059 0x5144, 1060 0x5145, 1061 0x5146, 1062 0x5147, 1063 0x5148, 1064 0x514C, 1065 0x514D, 1066 0x5157, 1067 0x5158, 1068 0x5159, 1069 0x515A, 1070 0x515E, 1071 0x5460, 1072 0x5462, 1073 0x5464, 1074 0x5548, 1075 0x5549, 1076 0x554A, 1077 0x554B, 1078 0x554C, 1079 0x554D, 1080 0x554E, 1081 0x554F, 1082 0x5550, 1083 0x5551, 1084 0x5552, 1085 0x5554, 1086 0x564A, 1087 0x564B, 1088 0x564F, 1089 0x5652, 1090 0x5653, 1091 0x5657, 1092 0x5834, 1093 0x5835, 1094 0x5954, 1095 0x5955, 1096 0x5974, 1097 0x5975, 1098 0x5960, 1099 0x5961, 1100 0x5962, 1101 0x5964, 1102 0x5965, 1103 0x5969, 1104 0x5a41, 1105 0x5a42, 1106 0x5a61, 1107 0x5a62, 1108 0x5b60, 1109 0x5b62, 1110 0x5b63, 1111 0x5b64, 1112 0x5b65, 1113 0x5c61, 1114 0x5c63, 1115 0x5d48, 1116 0x5d49, 1117 0x5d4a, 1118 0x5d4c, 1119 0x5d4d, 1120 0x5d4e, 1121 0x5d4f, 1122 0x5d50, 1123 0x5d52, 1124 0x5d57, 1125 0x5e48, 1126 0x5e4a, 1127 0x5e4b, 1128 0x5e4c, 1129 0x5e4d, 1130 0x5e4f, 1131 0x6700, 1132 0x6701, 1133 0x6702, 1134 0x6703, 1135 0x6704, 1136 0x6705, 1137 0x6706, 1138 0x6707, 1139 0x6708, 1140 0x6709, 1141 0x6718, 1142 0x6719, 1143 0x671c, 1144 0x671d, 1145 0x671f, 1146 0x6720, 1147 0x6721, 1148 0x6722, 1149 0x6723, 1150 0x6724, 1151 0x6725, 1152 0x6726, 1153 0x6727, 1154 0x6728, 1155 0x6729, 1156 0x6738, 1157 0x6739, 1158 0x673e, 1159 0x6740, 1160 0x6741, 1161 0x6742, 1162 0x6743, 1163 0x6744, 1164 0x6745, 1165 0x6746, 1166 0x6747, 1167 0x6748, 1168 0x6749, 1169 0x674A, 1170 0x6750, 1171 0x6751, 1172 0x6758, 1173 0x6759, 1174 0x675B, 1175 0x675D, 1176 0x675F, 1177 0x6760, 1178 0x6761, 1179 0x6762, 1180 0x6763, 1181 0x6764, 1182 0x6765, 1183 0x6766, 1184 0x6767, 1185 0x6768, 1186 0x6770, 1187 0x6771, 1188 0x6772, 1189 0x6778, 1190 0x6779, 1191 0x677B, 1192 0x6840, 1193 0x6841, 1194 0x6842, 1195 0x6843, 1196 0x6849, 1197 0x684C, 1198 0x6850, 1199 0x6858, 1200 0x6859, 1201 0x6880, 1202 0x6888, 1203 0x6889, 1204 0x688A, 1205 0x688C, 1206 0x688D, 1207 0x6898, 1208 0x6899, 1209 0x689b, 1210 0x689c, 1211 0x689d, 1212 0x689e, 1213 0x68a0, 1214 0x68a1, 1215 0x68a8, 1216 0x68a9, 1217 0x68b0, 1218 0x68b8, 1219 0x68b9, 1220 0x68ba, 1221 0x68be, 1222 0x68bf, 1223 0x68c0, 1224 0x68c1, 1225 0x68c7, 1226 0x68c8, 1227 0x68c9, 1228 0x68d8, 1229 0x68d9, 1230 0x68da, 1231 0x68de, 1232 0x68e0, 1233 0x68e1, 1234 0x68e4, 1235 0x68e5, 1236 0x68e8, 1237 0x68e9, 1238 0x68f1, 1239 0x68f2, 1240 0x68f8, 1241 0x68f9, 1242 0x68fa, 1243 0x68fe, 1244 0x7100, 1245 0x7101, 1246 0x7102, 1247 0x7103, 1248 0x7104, 1249 0x7105, 1250 0x7106, 1251 0x7108, 1252 0x7109, 1253 0x710A, 1254 0x710B, 1255 0x710C, 1256 0x710E, 1257 0x710F, 1258 0x7140, 1259 0x7141, 1260 0x7142, 1261 0x7143, 1262 0x7144, 1263 0x7145, 1264 0x7146, 1265 0x7147, 1266 0x7149, 1267 0x714A, 1268 0x714B, 1269 0x714C, 1270 0x714D, 1271 0x714E, 1272 0x714F, 1273 0x7151, 1274 0x7152, 1275 0x7153, 1276 0x715E, 1277 0x715F, 1278 0x7180, 1279 0x7181, 1280 0x7183, 1281 0x7186, 1282 0x7187, 1283 0x7188, 1284 0x718A, 1285 0x718B, 1286 0x718C, 1287 0x718D, 1288 0x718F, 1289 0x7193, 1290 0x7196, 1291 0x719B, 1292 0x719F, 1293 0x71C0, 1294 0x71C1, 1295 0x71C2, 1296 0x71C3, 1297 0x71C4, 1298 0x71C5, 1299 0x71C6, 1300 0x71C7, 1301 0x71CD, 1302 0x71CE, 1303 0x71D2, 1304 0x71D4, 1305 0x71D5, 1306 0x71D6, 1307 0x71DA, 1308 0x71DE, 1309 0x7200, 1310 0x7210, 1311 0x7211, 1312 0x7240, 1313 0x7243, 1314 0x7244, 1315 0x7245, 1316 0x7246, 1317 0x7247, 1318 0x7248, 1319 0x7249, 1320 0x724A, 1321 0x724B, 1322 0x724C, 1323 0x724D, 1324 0x724E, 1325 0x724F, 1326 0x7280, 1327 0x7281, 1328 0x7283, 1329 0x7284, 1330 0x7287, 1331 0x7288, 1332 0x7289, 1333 0x728B, 1334 0x728C, 1335 0x7290, 1336 0x7291, 1337 0x7293, 1338 0x7297, 1339 0x7834, 1340 0x7835, 1341 0x791e, 1342 0x791f, 1343 0x793f, 1344 0x7941, 1345 0x7942, 1346 0x796c, 1347 0x796d, 1348 0x796e, 1349 0x796f, 1350 0x9400, 1351 0x9401, 1352 0x9402, 1353 0x9403, 1354 0x9405, 1355 0x940A, 1356 0x940B, 1357 0x940F, 1358 0x94A0, 1359 0x94A1, 1360 0x94A3, 1361 0x94B1, 1362 0x94B3, 1363 0x94B4, 1364 0x94B5, 1365 0x94B9, 1366 0x9440, 1367 0x9441, 1368 0x9442, 1369 0x9443, 1370 0x9444, 1371 0x9446, 1372 0x944A, 1373 0x944B, 1374 0x944C, 1375 0x944E, 1376 0x9450, 1377 0x9452, 1378 0x9456, 1379 0x945A, 1380 0x945B, 1381 0x945E, 1382 0x9460, 1383 0x9462, 1384 0x946A, 1385 0x946B, 1386 0x947A, 1387 0x947B, 1388 0x9480, 1389 0x9487, 1390 0x9488, 1391 0x9489, 1392 0x948A, 1393 0x948F, 1394 0x9490, 1395 0x9491, 1396 0x9495, 1397 0x9498, 1398 0x949C, 1399 0x949E, 1400 0x949F, 1401 0x94C0, 1402 0x94C1, 1403 0x94C3, 1404 0x94C4, 1405 0x94C5, 1406 0x94C6, 1407 0x94C7, 1408 0x94C8, 1409 0x94C9, 1410 0x94CB, 1411 0x94CC, 1412 0x94CD, 1413 0x9500, 1414 0x9501, 1415 0x9504, 1416 0x9505, 1417 0x9506, 1418 0x9507, 1419 0x9508, 1420 0x9509, 1421 0x950F, 1422 0x9511, 1423 0x9515, 1424 0x9517, 1425 0x9519, 1426 0x9540, 1427 0x9541, 1428 0x9542, 1429 0x954E, 1430 0x954F, 1431 0x9552, 1432 0x9553, 1433 0x9555, 1434 0x9557, 1435 0x955f, 1436 0x9580, 1437 0x9581, 1438 0x9583, 1439 0x9586, 1440 0x9587, 1441 0x9588, 1442 0x9589, 1443 0x958A, 1444 0x958B, 1445 0x958C, 1446 0x958D, 1447 0x958E, 1448 0x958F, 1449 0x9590, 1450 0x9591, 1451 0x9593, 1452 0x9595, 1453 0x9596, 1454 0x9597, 1455 0x9598, 1456 0x9599, 1457 0x959B, 1458 0x95C0, 1459 0x95C2, 1460 0x95C4, 1461 0x95C5, 1462 0x95C6, 1463 0x95C7, 1464 0x95C9, 1465 0x95CC, 1466 0x95CD, 1467 0x95CE, 1468 0x95CF, 1469 0x9610, 1470 0x9611, 1471 0x9612, 1472 0x9613, 1473 0x9614, 1474 0x9615, 1475 0x9616, 1476 0x9640, 1477 0x9641, 1478 0x9642, 1479 0x9643, 1480 0x9644, 1481 0x9645, 1482 0x9647, 1483 0x9648, 1484 0x9649, 1485 0x964a, 1486 0x964b, 1487 0x964c, 1488 0x964e, 1489 0x964f, 1490 0x9710, 1491 0x9711, 1492 0x9712, 1493 0x9713, 1494 0x9714, 1495 0x9715, 1496 0x9802, 1497 0x9803, 1498 0x9804, 1499 0x9805, 1500 0x9806, 1501 0x9807, 1502 0x9808, 1503 0x9809, 1504 0x980A, 1505 0x9900, 1506 0x9901, 1507 0x9903, 1508 0x9904, 1509 0x9905, 1510 0x9906, 1511 0x9907, 1512 0x9908, 1513 0x9909, 1514 0x990A, 1515 0x990B, 1516 0x990C, 1517 0x990D, 1518 0x990E, 1519 0x990F, 1520 0x9910, 1521 0x9913, 1522 0x9917, 1523 0x9918, 1524 0x9919, 1525 0x9990, 1526 0x9991, 1527 0x9992, 1528 0x9993, 1529 0x9994, 1530 0x9995, 1531 0x9996, 1532 0x9997, 1533 0x9998, 1534 0x9999, 1535 0x999A, 1536 0x999B, 1537 0x999C, 1538 0x999D, 1539 0x99A0, 1540 0x99A2, 1541 0x99A4, 1542 /* radeon secondary ids */ 1543 0x3171, 1544 0x3e70, 1545 0x4164, 1546 0x4165, 1547 0x4166, 1548 0x4168, 1549 0x4170, 1550 0x4171, 1551 0x4172, 1552 0x4173, 1553 0x496e, 1554 0x4a69, 1555 0x4a6a, 1556 0x4a6b, 1557 0x4a70, 1558 0x4a74, 1559 0x4b69, 1560 0x4b6b, 1561 0x4b6c, 1562 0x4c6e, 1563 0x4e64, 1564 0x4e65, 1565 0x4e66, 1566 0x4e67, 1567 0x4e68, 1568 0x4e69, 1569 0x4e6a, 1570 0x4e71, 1571 0x4f73, 1572 0x5569, 1573 0x556b, 1574 0x556d, 1575 0x556f, 1576 0x5571, 1577 0x5854, 1578 0x5874, 1579 0x5940, 1580 0x5941, 1581 0x5b72, 1582 0x5b73, 1583 0x5b74, 1584 0x5b75, 1585 0x5d44, 1586 0x5d45, 1587 0x5d6d, 1588 0x5d6f, 1589 0x5d72, 1590 0x5d77, 1591 0x5e6b, 1592 0x5e6d, 1593 0x7120, 1594 0x7124, 1595 0x7129, 1596 0x712e, 1597 0x712f, 1598 0x7162, 1599 0x7163, 1600 0x7166, 1601 0x7167, 1602 0x7172, 1603 0x7173, 1604 0x71a0, 1605 0x71a1, 1606 0x71a3, 1607 0x71a7, 1608 0x71bb, 1609 0x71e0, 1610 0x71e1, 1611 0x71e2, 1612 0x71e6, 1613 0x71e7, 1614 0x71f2, 1615 0x7269, 1616 0x726b, 1617 0x726e, 1618 0x72a0, 1619 0x72a8, 1620 0x72b1, 1621 0x72b3, 1622 0x793f, 1623 }; 1624 1625 static const struct pci_device_id pciidlist[] = { 1626 #ifdef CONFIG_DRM_AMDGPU_SI 1627 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1628 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1629 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1630 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1631 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1632 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1633 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1634 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1635 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1636 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1637 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1638 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1639 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1640 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1641 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1642 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1643 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1644 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1645 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1646 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1647 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1648 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1649 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1650 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1651 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1652 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1653 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1654 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1658 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1659 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1660 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1661 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1662 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1663 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1664 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1665 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1666 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1667 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1668 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1669 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1670 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1671 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1674 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1675 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1676 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1677 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1678 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1679 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1680 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1681 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1682 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1683 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1684 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1685 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1687 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1688 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1689 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1690 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1691 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1692 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1693 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1694 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1698 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1699 #endif 1700 #ifdef CONFIG_DRM_AMDGPU_CIK 1701 /* Kaveri */ 1702 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1703 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1704 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1705 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1706 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1707 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1708 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1709 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1710 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1711 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1713 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1714 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1715 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1716 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1717 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1718 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1719 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1720 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1721 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1722 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1723 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1724 /* Bonaire */ 1725 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1729 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1730 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1731 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1732 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1733 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1734 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1735 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1736 /* Hawaii */ 1737 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1738 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1739 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1740 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1741 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1742 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1743 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1744 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1745 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1746 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1747 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1748 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1749 /* Kabini */ 1750 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1752 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1753 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1754 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1755 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1756 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1757 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1758 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1761 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1763 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1764 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1765 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1766 /* mullins */ 1767 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1768 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1769 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1770 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1772 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1774 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1775 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1776 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1777 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1778 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1779 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1783 #endif 1784 /* topaz */ 1785 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1786 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1787 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1788 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1789 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1790 /* tonga */ 1791 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1792 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1793 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1794 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1795 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1796 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1797 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1798 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1799 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1800 /* fiji */ 1801 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1802 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1803 /* carrizo */ 1804 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1805 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1806 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1807 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1808 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1809 /* stoney */ 1810 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1811 /* Polaris11 */ 1812 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1813 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1814 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1815 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1816 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1817 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1818 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1819 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1820 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1821 /* Polaris10 */ 1822 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1823 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1824 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1825 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1826 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1827 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1828 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1829 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1830 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1831 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1832 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1833 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1834 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1835 /* Polaris12 */ 1836 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1837 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1838 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1839 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1840 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1841 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1842 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1843 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1844 /* VEGAM */ 1845 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1846 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1847 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1848 /* Vega 10 */ 1849 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1850 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1851 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1852 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1853 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1854 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1855 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1856 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1857 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1858 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1859 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1860 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1861 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1862 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1863 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1864 /* Vega 12 */ 1865 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1866 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1867 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1868 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1869 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1870 /* Vega 20 */ 1871 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1872 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1873 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1874 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1875 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1876 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1877 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1878 /* Raven */ 1879 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1880 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1881 /* Arcturus */ 1882 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1883 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1884 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1885 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1886 /* Navi10 */ 1887 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1888 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1889 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1890 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1891 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1892 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1893 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1894 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1895 /* Navi14 */ 1896 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1897 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1898 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1899 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1900 1901 /* Renoir */ 1902 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1903 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1904 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1905 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1906 1907 /* Navi12 */ 1908 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1909 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1910 1911 /* Sienna_Cichlid */ 1912 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1913 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1914 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1915 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1916 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1917 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1918 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1919 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1920 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1921 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1922 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1923 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1924 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1925 1926 /* Van Gogh */ 1927 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1928 1929 /* Yellow Carp */ 1930 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1931 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1932 1933 /* Navy_Flounder */ 1934 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1935 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1936 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1937 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1938 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1939 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1940 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1941 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1942 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1943 1944 /* DIMGREY_CAVEFISH */ 1945 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1946 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1947 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1948 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1949 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1950 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1951 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1952 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1953 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1954 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1955 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1956 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1957 1958 /* Aldebaran */ 1959 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1960 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1961 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1962 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1963 1964 /* CYAN_SKILLFISH */ 1965 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1966 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1967 1968 /* BEIGE_GOBY */ 1969 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1970 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1971 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1972 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1973 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1974 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1975 1976 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1977 .class = PCI_CLASS_DISPLAY_VGA << 8, 1978 .class_mask = 0xffffff, 1979 .driver_data = CHIP_IP_DISCOVERY }, 1980 1981 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1982 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1983 .class_mask = 0xffffff, 1984 .driver_data = CHIP_IP_DISCOVERY }, 1985 1986 {0, 0, 0} 1987 }; 1988 1989 MODULE_DEVICE_TABLE(pci, pciidlist); 1990 1991 static const struct drm_driver amdgpu_kms_driver; 1992 1993 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1994 { 1995 struct pci_dev *p = NULL; 1996 int i; 1997 1998 /* 0 - GPU 1999 * 1 - audio 2000 * 2 - USB 2001 * 3 - UCSI 2002 */ 2003 for (i = 1; i < 4; i++) { 2004 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2005 adev->pdev->bus->number, i); 2006 if (p) { 2007 pm_runtime_get_sync(&p->dev); 2008 pm_runtime_mark_last_busy(&p->dev); 2009 pm_runtime_put_autosuspend(&p->dev); 2010 pci_dev_put(p); 2011 } 2012 } 2013 } 2014 2015 static int amdgpu_pci_probe(struct pci_dev *pdev, 2016 const struct pci_device_id *ent) 2017 { 2018 struct drm_device *ddev; 2019 struct amdgpu_device *adev; 2020 unsigned long flags = ent->driver_data; 2021 int ret, retry = 0, i; 2022 bool supports_atomic = false; 2023 2024 /* skip devices which are owned by radeon */ 2025 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2026 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2027 return -ENODEV; 2028 } 2029 2030 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2031 amdgpu_aspm = 0; 2032 2033 if (amdgpu_virtual_display || 2034 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2035 supports_atomic = true; 2036 2037 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2038 DRM_INFO("This hardware requires experimental hardware support.\n" 2039 "See modparam exp_hw_support\n"); 2040 return -ENODEV; 2041 } 2042 2043 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2044 * however, SME requires an indirect IOMMU mapping because the encryption 2045 * bit is beyond the DMA mask of the chip. 2046 */ 2047 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2048 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2049 dev_info(&pdev->dev, 2050 "SME is not compatible with RAVEN\n"); 2051 return -ENOTSUPP; 2052 } 2053 2054 #ifdef CONFIG_DRM_AMDGPU_SI 2055 if (!amdgpu_si_support) { 2056 switch (flags & AMD_ASIC_MASK) { 2057 case CHIP_TAHITI: 2058 case CHIP_PITCAIRN: 2059 case CHIP_VERDE: 2060 case CHIP_OLAND: 2061 case CHIP_HAINAN: 2062 dev_info(&pdev->dev, 2063 "SI support provided by radeon.\n"); 2064 dev_info(&pdev->dev, 2065 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2066 ); 2067 return -ENODEV; 2068 } 2069 } 2070 #endif 2071 #ifdef CONFIG_DRM_AMDGPU_CIK 2072 if (!amdgpu_cik_support) { 2073 switch (flags & AMD_ASIC_MASK) { 2074 case CHIP_KAVERI: 2075 case CHIP_BONAIRE: 2076 case CHIP_HAWAII: 2077 case CHIP_KABINI: 2078 case CHIP_MULLINS: 2079 dev_info(&pdev->dev, 2080 "CIK support provided by radeon.\n"); 2081 dev_info(&pdev->dev, 2082 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2083 ); 2084 return -ENODEV; 2085 } 2086 } 2087 #endif 2088 2089 /* Get rid of things like offb */ 2090 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2091 if (ret) 2092 return ret; 2093 2094 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2095 if (IS_ERR(adev)) 2096 return PTR_ERR(adev); 2097 2098 adev->dev = &pdev->dev; 2099 adev->pdev = pdev; 2100 ddev = adev_to_drm(adev); 2101 2102 if (!supports_atomic) 2103 ddev->driver_features &= ~DRIVER_ATOMIC; 2104 2105 ret = pci_enable_device(pdev); 2106 if (ret) 2107 return ret; 2108 2109 pci_set_drvdata(pdev, ddev); 2110 2111 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2112 if (ret) 2113 goto err_pci; 2114 2115 retry_init: 2116 ret = drm_dev_register(ddev, ent->driver_data); 2117 if (ret == -EAGAIN && ++retry <= 3) { 2118 DRM_INFO("retry init %d\n", retry); 2119 /* Don't request EX mode too frequently which is attacking */ 2120 msleep(5000); 2121 goto retry_init; 2122 } else if (ret) { 2123 goto err_pci; 2124 } 2125 2126 /* 2127 * 1. don't init fbdev on hw without DCE 2128 * 2. don't init fbdev if there are no connectors 2129 */ 2130 if (adev->mode_info.mode_config_initialized && 2131 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2132 /* select 8 bpp console on low vram cards */ 2133 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2134 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2135 else 2136 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2137 } 2138 2139 ret = amdgpu_debugfs_init(adev); 2140 if (ret) 2141 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2142 2143 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2144 /* only need to skip on ATPX */ 2145 if (amdgpu_device_supports_px(ddev)) 2146 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2147 /* we want direct complete for BOCO */ 2148 if (amdgpu_device_supports_boco(ddev)) 2149 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2150 DPM_FLAG_SMART_SUSPEND | 2151 DPM_FLAG_MAY_SKIP_RESUME); 2152 pm_runtime_use_autosuspend(ddev->dev); 2153 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2154 2155 pm_runtime_allow(ddev->dev); 2156 2157 pm_runtime_mark_last_busy(ddev->dev); 2158 pm_runtime_put_autosuspend(ddev->dev); 2159 2160 /* 2161 * For runpm implemented via BACO, PMFW will handle the 2162 * timing for BACO in and out: 2163 * - put ASIC into BACO state only when both video and 2164 * audio functions are in D3 state. 2165 * - pull ASIC out of BACO state when either video or 2166 * audio function is in D0 state. 2167 * Also, at startup, PMFW assumes both functions are in 2168 * D0 state. 2169 * 2170 * So if snd driver was loaded prior to amdgpu driver 2171 * and audio function was put into D3 state, there will 2172 * be no PMFW-aware D-state transition(D0->D3) on runpm 2173 * suspend. Thus the BACO will be not correctly kicked in. 2174 * 2175 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2176 * into D0 state. Then there will be a PMFW-aware D-state 2177 * transition(D0->D3) on runpm suspend. 2178 */ 2179 if (amdgpu_device_supports_baco(ddev) && 2180 !(adev->flags & AMD_IS_APU) && 2181 (adev->asic_type >= CHIP_NAVI10)) 2182 amdgpu_get_secondary_funcs(adev); 2183 } 2184 2185 return 0; 2186 2187 err_pci: 2188 pci_disable_device(pdev); 2189 return ret; 2190 } 2191 2192 static void 2193 amdgpu_pci_remove(struct pci_dev *pdev) 2194 { 2195 struct drm_device *dev = pci_get_drvdata(pdev); 2196 struct amdgpu_device *adev = drm_to_adev(dev); 2197 2198 drm_dev_unplug(dev); 2199 2200 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2201 pm_runtime_get_sync(dev->dev); 2202 pm_runtime_forbid(dev->dev); 2203 } 2204 2205 amdgpu_driver_unload_kms(dev); 2206 2207 /* 2208 * Flush any in flight DMA operations from device. 2209 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2210 * StatusTransactions Pending bit. 2211 */ 2212 pci_disable_device(pdev); 2213 pci_wait_for_pending_transaction(pdev); 2214 } 2215 2216 static void 2217 amdgpu_pci_shutdown(struct pci_dev *pdev) 2218 { 2219 struct drm_device *dev = pci_get_drvdata(pdev); 2220 struct amdgpu_device *adev = drm_to_adev(dev); 2221 2222 if (amdgpu_ras_intr_triggered()) 2223 return; 2224 2225 /* if we are running in a VM, make sure the device 2226 * torn down properly on reboot/shutdown. 2227 * unfortunately we can't detect certain 2228 * hypervisors so just do this all the time. 2229 */ 2230 if (!amdgpu_passthrough(adev)) 2231 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2232 amdgpu_device_ip_suspend(adev); 2233 adev->mp1_state = PP_MP1_STATE_NONE; 2234 } 2235 2236 /** 2237 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2238 * 2239 * @work: work_struct. 2240 */ 2241 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2242 { 2243 struct list_head device_list; 2244 struct amdgpu_device *adev; 2245 int i, r; 2246 struct amdgpu_reset_context reset_context; 2247 2248 memset(&reset_context, 0, sizeof(reset_context)); 2249 2250 mutex_lock(&mgpu_info.mutex); 2251 if (mgpu_info.pending_reset == true) { 2252 mutex_unlock(&mgpu_info.mutex); 2253 return; 2254 } 2255 mgpu_info.pending_reset = true; 2256 mutex_unlock(&mgpu_info.mutex); 2257 2258 /* Use a common context, just need to make sure full reset is done */ 2259 reset_context.method = AMD_RESET_METHOD_NONE; 2260 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2261 2262 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2263 adev = mgpu_info.gpu_ins[i].adev; 2264 reset_context.reset_req_dev = adev; 2265 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2266 if (r) { 2267 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2268 r, adev_to_drm(adev)->unique); 2269 } 2270 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2271 r = -EALREADY; 2272 } 2273 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2274 adev = mgpu_info.gpu_ins[i].adev; 2275 flush_work(&adev->xgmi_reset_work); 2276 adev->gmc.xgmi.pending_reset = false; 2277 } 2278 2279 /* reset function will rebuild the xgmi hive info , clear it now */ 2280 for (i = 0; i < mgpu_info.num_dgpu; i++) 2281 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2282 2283 INIT_LIST_HEAD(&device_list); 2284 2285 for (i = 0; i < mgpu_info.num_dgpu; i++) 2286 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2287 2288 /* unregister the GPU first, reset function will add them back */ 2289 list_for_each_entry(adev, &device_list, reset_list) 2290 amdgpu_unregister_gpu_instance(adev); 2291 2292 /* Use a common context, just need to make sure full reset is done */ 2293 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2294 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2295 2296 if (r) { 2297 DRM_ERROR("reinit gpus failure"); 2298 return; 2299 } 2300 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2301 adev = mgpu_info.gpu_ins[i].adev; 2302 if (!adev->kfd.init_complete) 2303 amdgpu_amdkfd_device_init(adev); 2304 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2305 } 2306 return; 2307 } 2308 2309 static int amdgpu_pmops_prepare(struct device *dev) 2310 { 2311 struct drm_device *drm_dev = dev_get_drvdata(dev); 2312 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2313 2314 /* Return a positive number here so 2315 * DPM_FLAG_SMART_SUSPEND works properly 2316 */ 2317 if (amdgpu_device_supports_boco(drm_dev)) 2318 return pm_runtime_suspended(dev); 2319 2320 /* if we will not support s3 or s2i for the device 2321 * then skip suspend 2322 */ 2323 if (!amdgpu_acpi_is_s0ix_active(adev) && 2324 !amdgpu_acpi_is_s3_active(adev)) 2325 return 1; 2326 2327 return 0; 2328 } 2329 2330 static void amdgpu_pmops_complete(struct device *dev) 2331 { 2332 /* nothing to do */ 2333 } 2334 2335 static int amdgpu_pmops_suspend(struct device *dev) 2336 { 2337 struct drm_device *drm_dev = dev_get_drvdata(dev); 2338 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2339 2340 if (amdgpu_acpi_is_s0ix_active(adev)) 2341 adev->in_s0ix = true; 2342 else 2343 adev->in_s3 = true; 2344 return amdgpu_device_suspend(drm_dev, true); 2345 } 2346 2347 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2348 { 2349 struct drm_device *drm_dev = dev_get_drvdata(dev); 2350 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2351 2352 if (amdgpu_acpi_should_gpu_reset(adev)) 2353 return amdgpu_asic_reset(adev); 2354 2355 return 0; 2356 } 2357 2358 static int amdgpu_pmops_resume(struct device *dev) 2359 { 2360 struct drm_device *drm_dev = dev_get_drvdata(dev); 2361 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2362 int r; 2363 2364 /* Avoids registers access if device is physically gone */ 2365 if (!pci_device_is_present(adev->pdev)) 2366 adev->no_hw_access = true; 2367 2368 r = amdgpu_device_resume(drm_dev, true); 2369 if (amdgpu_acpi_is_s0ix_active(adev)) 2370 adev->in_s0ix = false; 2371 else 2372 adev->in_s3 = false; 2373 return r; 2374 } 2375 2376 static int amdgpu_pmops_freeze(struct device *dev) 2377 { 2378 struct drm_device *drm_dev = dev_get_drvdata(dev); 2379 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2380 int r; 2381 2382 adev->in_s4 = true; 2383 r = amdgpu_device_suspend(drm_dev, true); 2384 adev->in_s4 = false; 2385 if (r) 2386 return r; 2387 return amdgpu_asic_reset(adev); 2388 } 2389 2390 static int amdgpu_pmops_thaw(struct device *dev) 2391 { 2392 struct drm_device *drm_dev = dev_get_drvdata(dev); 2393 2394 return amdgpu_device_resume(drm_dev, true); 2395 } 2396 2397 static int amdgpu_pmops_poweroff(struct device *dev) 2398 { 2399 struct drm_device *drm_dev = dev_get_drvdata(dev); 2400 2401 return amdgpu_device_suspend(drm_dev, true); 2402 } 2403 2404 static int amdgpu_pmops_restore(struct device *dev) 2405 { 2406 struct drm_device *drm_dev = dev_get_drvdata(dev); 2407 2408 return amdgpu_device_resume(drm_dev, true); 2409 } 2410 2411 static int amdgpu_runtime_idle_check_display(struct device *dev) 2412 { 2413 struct pci_dev *pdev = to_pci_dev(dev); 2414 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2415 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2416 2417 if (adev->mode_info.num_crtc) { 2418 struct drm_connector *list_connector; 2419 struct drm_connector_list_iter iter; 2420 int ret = 0; 2421 2422 /* XXX: Return busy if any displays are connected to avoid 2423 * possible display wakeups after runtime resume due to 2424 * hotplug events in case any displays were connected while 2425 * the GPU was in suspend. Remove this once that is fixed. 2426 */ 2427 mutex_lock(&drm_dev->mode_config.mutex); 2428 drm_connector_list_iter_begin(drm_dev, &iter); 2429 drm_for_each_connector_iter(list_connector, &iter) { 2430 if (list_connector->status == connector_status_connected) { 2431 ret = -EBUSY; 2432 break; 2433 } 2434 } 2435 drm_connector_list_iter_end(&iter); 2436 mutex_unlock(&drm_dev->mode_config.mutex); 2437 2438 if (ret) 2439 return ret; 2440 2441 if (amdgpu_device_has_dc_support(adev)) { 2442 struct drm_crtc *crtc; 2443 2444 drm_for_each_crtc(crtc, drm_dev) { 2445 drm_modeset_lock(&crtc->mutex, NULL); 2446 if (crtc->state->active) 2447 ret = -EBUSY; 2448 drm_modeset_unlock(&crtc->mutex); 2449 if (ret < 0) 2450 break; 2451 } 2452 } else { 2453 mutex_lock(&drm_dev->mode_config.mutex); 2454 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2455 2456 drm_connector_list_iter_begin(drm_dev, &iter); 2457 drm_for_each_connector_iter(list_connector, &iter) { 2458 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2459 ret = -EBUSY; 2460 break; 2461 } 2462 } 2463 2464 drm_connector_list_iter_end(&iter); 2465 2466 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2467 mutex_unlock(&drm_dev->mode_config.mutex); 2468 } 2469 if (ret) 2470 return ret; 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2477 { 2478 struct pci_dev *pdev = to_pci_dev(dev); 2479 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2480 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2481 int ret, i; 2482 2483 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2484 pm_runtime_forbid(dev); 2485 return -EBUSY; 2486 } 2487 2488 ret = amdgpu_runtime_idle_check_display(dev); 2489 if (ret) 2490 return ret; 2491 2492 /* wait for all rings to drain before suspending */ 2493 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2494 struct amdgpu_ring *ring = adev->rings[i]; 2495 if (ring && ring->sched.ready) { 2496 ret = amdgpu_fence_wait_empty(ring); 2497 if (ret) 2498 return -EBUSY; 2499 } 2500 } 2501 2502 adev->in_runpm = true; 2503 if (amdgpu_device_supports_px(drm_dev)) 2504 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2505 2506 /* 2507 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2508 * proper cleanups and put itself into a state ready for PNP. That 2509 * can address some random resuming failure observed on BOCO capable 2510 * platforms. 2511 * TODO: this may be also needed for PX capable platform. 2512 */ 2513 if (amdgpu_device_supports_boco(drm_dev)) 2514 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2515 2516 ret = amdgpu_device_suspend(drm_dev, false); 2517 if (ret) { 2518 adev->in_runpm = false; 2519 if (amdgpu_device_supports_boco(drm_dev)) 2520 adev->mp1_state = PP_MP1_STATE_NONE; 2521 return ret; 2522 } 2523 2524 if (amdgpu_device_supports_boco(drm_dev)) 2525 adev->mp1_state = PP_MP1_STATE_NONE; 2526 2527 if (amdgpu_device_supports_px(drm_dev)) { 2528 /* Only need to handle PCI state in the driver for ATPX 2529 * PCI core handles it for _PR3. 2530 */ 2531 amdgpu_device_cache_pci_state(pdev); 2532 pci_disable_device(pdev); 2533 pci_ignore_hotplug(pdev); 2534 pci_set_power_state(pdev, PCI_D3cold); 2535 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2536 } else if (amdgpu_device_supports_boco(drm_dev)) { 2537 /* nothing to do */ 2538 } else if (amdgpu_device_supports_baco(drm_dev)) { 2539 amdgpu_device_baco_enter(drm_dev); 2540 } 2541 2542 return 0; 2543 } 2544 2545 static int amdgpu_pmops_runtime_resume(struct device *dev) 2546 { 2547 struct pci_dev *pdev = to_pci_dev(dev); 2548 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2549 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2550 int ret; 2551 2552 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2553 return -EINVAL; 2554 2555 /* Avoids registers access if device is physically gone */ 2556 if (!pci_device_is_present(adev->pdev)) 2557 adev->no_hw_access = true; 2558 2559 if (amdgpu_device_supports_px(drm_dev)) { 2560 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2561 2562 /* Only need to handle PCI state in the driver for ATPX 2563 * PCI core handles it for _PR3. 2564 */ 2565 pci_set_power_state(pdev, PCI_D0); 2566 amdgpu_device_load_pci_state(pdev); 2567 ret = pci_enable_device(pdev); 2568 if (ret) 2569 return ret; 2570 pci_set_master(pdev); 2571 } else if (amdgpu_device_supports_boco(drm_dev)) { 2572 /* Only need to handle PCI state in the driver for ATPX 2573 * PCI core handles it for _PR3. 2574 */ 2575 pci_set_master(pdev); 2576 } else if (amdgpu_device_supports_baco(drm_dev)) { 2577 amdgpu_device_baco_exit(drm_dev); 2578 } 2579 ret = amdgpu_device_resume(drm_dev, false); 2580 if (ret) 2581 return ret; 2582 2583 if (amdgpu_device_supports_px(drm_dev)) 2584 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2585 adev->in_runpm = false; 2586 return 0; 2587 } 2588 2589 static int amdgpu_pmops_runtime_idle(struct device *dev) 2590 { 2591 struct drm_device *drm_dev = dev_get_drvdata(dev); 2592 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2593 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2594 int ret = 1; 2595 2596 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2597 pm_runtime_forbid(dev); 2598 return -EBUSY; 2599 } 2600 2601 ret = amdgpu_runtime_idle_check_display(dev); 2602 2603 pm_runtime_mark_last_busy(dev); 2604 pm_runtime_autosuspend(dev); 2605 return ret; 2606 } 2607 2608 long amdgpu_drm_ioctl(struct file *filp, 2609 unsigned int cmd, unsigned long arg) 2610 { 2611 struct drm_file *file_priv = filp->private_data; 2612 struct drm_device *dev; 2613 long ret; 2614 dev = file_priv->minor->dev; 2615 ret = pm_runtime_get_sync(dev->dev); 2616 if (ret < 0) 2617 goto out; 2618 2619 ret = drm_ioctl(filp, cmd, arg); 2620 2621 pm_runtime_mark_last_busy(dev->dev); 2622 out: 2623 pm_runtime_put_autosuspend(dev->dev); 2624 return ret; 2625 } 2626 2627 static const struct dev_pm_ops amdgpu_pm_ops = { 2628 .prepare = amdgpu_pmops_prepare, 2629 .complete = amdgpu_pmops_complete, 2630 .suspend = amdgpu_pmops_suspend, 2631 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2632 .resume = amdgpu_pmops_resume, 2633 .freeze = amdgpu_pmops_freeze, 2634 .thaw = amdgpu_pmops_thaw, 2635 .poweroff = amdgpu_pmops_poweroff, 2636 .restore = amdgpu_pmops_restore, 2637 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2638 .runtime_resume = amdgpu_pmops_runtime_resume, 2639 .runtime_idle = amdgpu_pmops_runtime_idle, 2640 }; 2641 2642 static int amdgpu_flush(struct file *f, fl_owner_t id) 2643 { 2644 struct drm_file *file_priv = f->private_data; 2645 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2646 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2647 2648 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2649 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2650 2651 return timeout >= 0 ? 0 : timeout; 2652 } 2653 2654 static const struct file_operations amdgpu_driver_kms_fops = { 2655 .owner = THIS_MODULE, 2656 .open = drm_open, 2657 .flush = amdgpu_flush, 2658 .release = drm_release, 2659 .unlocked_ioctl = amdgpu_drm_ioctl, 2660 .mmap = drm_gem_mmap, 2661 .poll = drm_poll, 2662 .read = drm_read, 2663 #ifdef CONFIG_COMPAT 2664 .compat_ioctl = amdgpu_kms_compat_ioctl, 2665 #endif 2666 #ifdef CONFIG_PROC_FS 2667 .show_fdinfo = amdgpu_show_fdinfo 2668 #endif 2669 }; 2670 2671 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2672 { 2673 struct drm_file *file; 2674 2675 if (!filp) 2676 return -EINVAL; 2677 2678 if (filp->f_op != &amdgpu_driver_kms_fops) { 2679 return -EINVAL; 2680 } 2681 2682 file = filp->private_data; 2683 *fpriv = file->driver_priv; 2684 return 0; 2685 } 2686 2687 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2688 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2689 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2690 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2691 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2692 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2693 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2694 /* KMS */ 2695 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2696 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2697 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2698 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2699 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2700 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2701 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2702 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2703 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2704 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2705 }; 2706 2707 static const struct drm_driver amdgpu_kms_driver = { 2708 .driver_features = 2709 DRIVER_ATOMIC | 2710 DRIVER_GEM | 2711 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2712 DRIVER_SYNCOBJ_TIMELINE, 2713 .open = amdgpu_driver_open_kms, 2714 .postclose = amdgpu_driver_postclose_kms, 2715 .lastclose = amdgpu_driver_lastclose_kms, 2716 .ioctls = amdgpu_ioctls_kms, 2717 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2718 .dumb_create = amdgpu_mode_dumb_create, 2719 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2720 .fops = &amdgpu_driver_kms_fops, 2721 .release = &amdgpu_driver_release_kms, 2722 2723 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2724 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2725 .gem_prime_import = amdgpu_gem_prime_import, 2726 .gem_prime_mmap = drm_gem_prime_mmap, 2727 2728 .name = DRIVER_NAME, 2729 .desc = DRIVER_DESC, 2730 .date = DRIVER_DATE, 2731 .major = KMS_DRIVER_MAJOR, 2732 .minor = KMS_DRIVER_MINOR, 2733 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2734 }; 2735 2736 static struct pci_error_handlers amdgpu_pci_err_handler = { 2737 .error_detected = amdgpu_pci_error_detected, 2738 .mmio_enabled = amdgpu_pci_mmio_enabled, 2739 .slot_reset = amdgpu_pci_slot_reset, 2740 .resume = amdgpu_pci_resume, 2741 }; 2742 2743 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2744 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2745 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2746 2747 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2748 &amdgpu_vram_mgr_attr_group, 2749 &amdgpu_gtt_mgr_attr_group, 2750 &amdgpu_vbios_version_attr_group, 2751 NULL, 2752 }; 2753 2754 2755 static struct pci_driver amdgpu_kms_pci_driver = { 2756 .name = DRIVER_NAME, 2757 .id_table = pciidlist, 2758 .probe = amdgpu_pci_probe, 2759 .remove = amdgpu_pci_remove, 2760 .shutdown = amdgpu_pci_shutdown, 2761 .driver.pm = &amdgpu_pm_ops, 2762 .err_handler = &amdgpu_pci_err_handler, 2763 .dev_groups = amdgpu_sysfs_groups, 2764 }; 2765 2766 static int __init amdgpu_init(void) 2767 { 2768 int r; 2769 2770 if (drm_firmware_drivers_only()) 2771 return -EINVAL; 2772 2773 r = amdgpu_sync_init(); 2774 if (r) 2775 goto error_sync; 2776 2777 r = amdgpu_fence_slab_init(); 2778 if (r) 2779 goto error_fence; 2780 2781 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2782 amdgpu_register_atpx_handler(); 2783 amdgpu_acpi_detect(); 2784 2785 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2786 amdgpu_amdkfd_init(); 2787 2788 /* let modprobe override vga console setting */ 2789 return pci_register_driver(&amdgpu_kms_pci_driver); 2790 2791 error_fence: 2792 amdgpu_sync_fini(); 2793 2794 error_sync: 2795 return r; 2796 } 2797 2798 static void __exit amdgpu_exit(void) 2799 { 2800 amdgpu_amdkfd_fini(); 2801 pci_unregister_driver(&amdgpu_kms_pci_driver); 2802 amdgpu_unregister_atpx_handler(); 2803 amdgpu_sync_fini(); 2804 amdgpu_fence_slab_fini(); 2805 mmu_notifier_synchronize(); 2806 } 2807 2808 module_init(amdgpu_init); 2809 module_exit(amdgpu_exit); 2810 2811 MODULE_AUTHOR(DRIVER_AUTHOR); 2812 MODULE_DESCRIPTION(DRIVER_DESC); 2813 MODULE_LICENSE("GPL and additional rights"); 2814