1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 105 * - 3.48.0 - Add IP discovery version info to HW INFO 106 * - 3.49.0 - Add gang submit into CS IOCTL 107 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 108 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 109 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 110 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 111 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 112 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 113 * 3.53.0 - Support for GFX11 CP GFX shadowing 114 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 115 */ 116 #define KMS_DRIVER_MAJOR 3 117 #define KMS_DRIVER_MINOR 54 118 #define KMS_DRIVER_PATCHLEVEL 0 119 120 unsigned int amdgpu_vram_limit = UINT_MAX; 121 int amdgpu_vis_vram_limit; 122 int amdgpu_gart_size = -1; /* auto */ 123 int amdgpu_gtt_size = -1; /* auto */ 124 int amdgpu_moverate = -1; /* auto */ 125 int amdgpu_audio = -1; 126 int amdgpu_disp_priority; 127 int amdgpu_hw_i2c; 128 int amdgpu_pcie_gen2 = -1; 129 int amdgpu_msi = -1; 130 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 131 int amdgpu_dpm = -1; 132 int amdgpu_fw_load_type = -1; 133 int amdgpu_aspm = -1; 134 int amdgpu_runtime_pm = -1; 135 uint amdgpu_ip_block_mask = 0xffffffff; 136 int amdgpu_bapm = -1; 137 int amdgpu_deep_color; 138 int amdgpu_vm_size = -1; 139 int amdgpu_vm_fragment_size = -1; 140 int amdgpu_vm_block_size = -1; 141 int amdgpu_vm_fault_stop; 142 int amdgpu_vm_debug; 143 int amdgpu_vm_update_mode = -1; 144 int amdgpu_exp_hw_support; 145 int amdgpu_dc = -1; 146 int amdgpu_sched_jobs = 32; 147 int amdgpu_sched_hw_submission = 2; 148 uint amdgpu_pcie_gen_cap; 149 uint amdgpu_pcie_lane_cap; 150 u64 amdgpu_cg_mask = 0xffffffffffffffff; 151 uint amdgpu_pg_mask = 0xffffffff; 152 uint amdgpu_sdma_phase_quantum = 32; 153 char *amdgpu_disable_cu; 154 char *amdgpu_virtual_display; 155 156 /* 157 * OverDrive(bit 14) disabled by default 158 * GFX DCS(bit 19) disabled by default 159 */ 160 uint amdgpu_pp_feature_mask = 0xfff7bfff; 161 uint amdgpu_force_long_training; 162 int amdgpu_lbpw = -1; 163 int amdgpu_compute_multipipe = -1; 164 int amdgpu_gpu_recovery = -1; /* auto */ 165 int amdgpu_emu_mode; 166 uint amdgpu_smu_memory_pool_size; 167 int amdgpu_smu_pptable_id = -1; 168 /* 169 * FBC (bit 0) disabled by default 170 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 171 * - With this, for multiple monitors in sync(e.g. with the same model), 172 * mclk switching will be allowed. And the mclk will be not foced to the 173 * highest. That helps saving some idle power. 174 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 175 * PSR (bit 3) disabled by default 176 * EDP NO POWER SEQUENCING (bit 4) disabled by default 177 */ 178 uint amdgpu_dc_feature_mask = 2; 179 uint amdgpu_dc_debug_mask; 180 uint amdgpu_dc_visual_confirm; 181 int amdgpu_async_gfx_ring = 1; 182 int amdgpu_mcbp; 183 int amdgpu_discovery = -1; 184 int amdgpu_mes; 185 int amdgpu_mes_kiq; 186 int amdgpu_noretry = -1; 187 int amdgpu_force_asic_type = -1; 188 int amdgpu_tmz = -1; /* auto */ 189 uint amdgpu_freesync_vid_mode; 190 int amdgpu_reset_method = -1; /* auto */ 191 int amdgpu_num_kcq = -1; 192 int amdgpu_smartshift_bias; 193 int amdgpu_use_xgmi_p2p = 1; 194 int amdgpu_vcnfw_log; 195 int amdgpu_sg_display = -1; /* auto */ 196 197 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 198 199 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 200 "DRM_UT_CORE", 201 "DRM_UT_DRIVER", 202 "DRM_UT_KMS", 203 "DRM_UT_PRIME", 204 "DRM_UT_ATOMIC", 205 "DRM_UT_VBL", 206 "DRM_UT_STATE", 207 "DRM_UT_LEASE", 208 "DRM_UT_DP", 209 "DRM_UT_DRMRES"); 210 211 struct amdgpu_mgpu_info mgpu_info = { 212 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 213 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 214 mgpu_info.delayed_reset_work, 215 amdgpu_drv_delayed_reset_work_handler, 0), 216 }; 217 int amdgpu_ras_enable = -1; 218 uint amdgpu_ras_mask = 0xffffffff; 219 int amdgpu_bad_page_threshold = -1; 220 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 221 .timeout_fatal_disable = false, 222 .period = 0x0, /* default to 0x0 (timeout disable) */ 223 }; 224 225 /** 226 * DOC: vramlimit (int) 227 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 228 */ 229 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 230 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 231 232 /** 233 * DOC: vis_vramlimit (int) 234 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 235 */ 236 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 237 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 238 239 /** 240 * DOC: gartsize (uint) 241 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 242 * The default is -1 (The size depends on asic). 243 */ 244 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 245 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 246 247 /** 248 * DOC: gttsize (int) 249 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 250 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 251 */ 252 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 253 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 254 255 /** 256 * DOC: moverate (int) 257 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 258 */ 259 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 260 module_param_named(moverate, amdgpu_moverate, int, 0600); 261 262 /** 263 * DOC: audio (int) 264 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 265 */ 266 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 267 module_param_named(audio, amdgpu_audio, int, 0444); 268 269 /** 270 * DOC: disp_priority (int) 271 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 272 */ 273 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 274 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 275 276 /** 277 * DOC: hw_i2c (int) 278 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 279 */ 280 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 281 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 282 283 /** 284 * DOC: pcie_gen2 (int) 285 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 286 */ 287 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 288 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 289 290 /** 291 * DOC: msi (int) 292 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 293 */ 294 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 295 module_param_named(msi, amdgpu_msi, int, 0444); 296 297 /** 298 * DOC: lockup_timeout (string) 299 * Set GPU scheduler timeout value in ms. 300 * 301 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 302 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 303 * to the default timeout. 304 * 305 * - With one value specified, the setting will apply to all non-compute jobs. 306 * - With multiple values specified, the first one will be for GFX. 307 * The second one is for Compute. The third and fourth ones are 308 * for SDMA and Video. 309 * 310 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 311 * jobs is 10000. The timeout for compute is 60000. 312 */ 313 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 314 "for passthrough or sriov, 10000 for all jobs." 315 " 0: keep default value. negative: infinity timeout), " 316 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 317 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 318 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 319 320 /** 321 * DOC: dpm (int) 322 * Override for dynamic power management setting 323 * (0 = disable, 1 = enable) 324 * The default is -1 (auto). 325 */ 326 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 327 module_param_named(dpm, amdgpu_dpm, int, 0444); 328 329 /** 330 * DOC: fw_load_type (int) 331 * Set different firmware loading type for debugging, if supported. 332 * Set to 0 to force direct loading if supported by the ASIC. Set 333 * to -1 to select the default loading mode for the ASIC, as defined 334 * by the driver. The default is -1 (auto). 335 */ 336 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 337 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 338 339 /** 340 * DOC: aspm (int) 341 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 342 */ 343 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 344 module_param_named(aspm, amdgpu_aspm, int, 0444); 345 346 /** 347 * DOC: runpm (int) 348 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 349 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 350 * Setting the value to 0 disables this functionality. 351 */ 352 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 353 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 354 355 /** 356 * DOC: ip_block_mask (uint) 357 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 358 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 359 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 360 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 361 */ 362 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 363 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 364 365 /** 366 * DOC: bapm (int) 367 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 368 * The default -1 (auto, enabled) 369 */ 370 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 371 module_param_named(bapm, amdgpu_bapm, int, 0444); 372 373 /** 374 * DOC: deep_color (int) 375 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 376 */ 377 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 378 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 379 380 /** 381 * DOC: vm_size (int) 382 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 383 */ 384 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 385 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 386 387 /** 388 * DOC: vm_fragment_size (int) 389 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 390 */ 391 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 392 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 393 394 /** 395 * DOC: vm_block_size (int) 396 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 397 */ 398 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 399 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 400 401 /** 402 * DOC: vm_fault_stop (int) 403 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 404 */ 405 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 406 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 407 408 /** 409 * DOC: vm_debug (int) 410 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 411 */ 412 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 413 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 414 415 /** 416 * DOC: vm_update_mode (int) 417 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 418 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 419 */ 420 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 421 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 422 423 /** 424 * DOC: exp_hw_support (int) 425 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 426 */ 427 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 428 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 429 430 /** 431 * DOC: dc (int) 432 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 433 */ 434 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 435 module_param_named(dc, amdgpu_dc, int, 0444); 436 437 /** 438 * DOC: sched_jobs (int) 439 * Override the max number of jobs supported in the sw queue. The default is 32. 440 */ 441 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 442 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 443 444 /** 445 * DOC: sched_hw_submission (int) 446 * Override the max number of HW submissions. The default is 2. 447 */ 448 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 449 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 450 451 /** 452 * DOC: ppfeaturemask (hexint) 453 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 454 * The default is the current set of stable power features. 455 */ 456 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 457 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 458 459 /** 460 * DOC: forcelongtraining (uint) 461 * Force long memory training in resume. 462 * The default is zero, indicates short training in resume. 463 */ 464 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 465 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 466 467 /** 468 * DOC: pcie_gen_cap (uint) 469 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 470 * The default is 0 (automatic for each asic). 471 */ 472 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 473 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 474 475 /** 476 * DOC: pcie_lane_cap (uint) 477 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 478 * The default is 0 (automatic for each asic). 479 */ 480 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 481 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 482 483 /** 484 * DOC: cg_mask (ullong) 485 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 486 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 487 */ 488 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 489 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 490 491 /** 492 * DOC: pg_mask (uint) 493 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 494 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 495 */ 496 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 497 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 498 499 /** 500 * DOC: sdma_phase_quantum (uint) 501 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 502 */ 503 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 504 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 505 506 /** 507 * DOC: disable_cu (charp) 508 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 509 */ 510 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 511 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 512 513 /** 514 * DOC: virtual_display (charp) 515 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 516 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 517 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 518 * device at 26:00.0. The default is NULL. 519 */ 520 MODULE_PARM_DESC(virtual_display, 521 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 522 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 523 524 /** 525 * DOC: lbpw (int) 526 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 527 */ 528 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 529 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 530 531 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 532 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 533 534 /** 535 * DOC: gpu_recovery (int) 536 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 537 */ 538 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 539 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 540 541 /** 542 * DOC: emu_mode (int) 543 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 544 */ 545 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 546 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 547 548 /** 549 * DOC: ras_enable (int) 550 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 551 */ 552 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 553 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 554 555 /** 556 * DOC: ras_mask (uint) 557 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 558 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 559 */ 560 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 561 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 562 563 /** 564 * DOC: timeout_fatal_disable (bool) 565 * Disable Watchdog timeout fatal error event 566 */ 567 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 568 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 569 570 /** 571 * DOC: timeout_period (uint) 572 * Modify the watchdog timeout max_cycles as (1 << period) 573 */ 574 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 575 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 576 577 /** 578 * DOC: si_support (int) 579 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 581 * otherwise using amdgpu driver. 582 */ 583 #ifdef CONFIG_DRM_AMDGPU_SI 584 585 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 586 int amdgpu_si_support = 0; 587 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 588 #else 589 int amdgpu_si_support = 1; 590 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 591 #endif 592 593 module_param_named(si_support, amdgpu_si_support, int, 0444); 594 #endif 595 596 /** 597 * DOC: cik_support (int) 598 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 599 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 600 * otherwise using amdgpu driver. 601 */ 602 #ifdef CONFIG_DRM_AMDGPU_CIK 603 604 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 605 int amdgpu_cik_support = 0; 606 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 607 #else 608 int amdgpu_cik_support = 1; 609 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 610 #endif 611 612 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 613 #endif 614 615 /** 616 * DOC: smu_memory_pool_size (uint) 617 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 618 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 619 */ 620 MODULE_PARM_DESC(smu_memory_pool_size, 621 "reserve gtt for smu debug usage, 0 = disable," 622 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 623 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 624 625 /** 626 * DOC: async_gfx_ring (int) 627 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 628 */ 629 MODULE_PARM_DESC(async_gfx_ring, 630 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 631 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 632 633 /** 634 * DOC: mcbp (int) 635 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 636 */ 637 MODULE_PARM_DESC(mcbp, 638 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 639 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 640 641 /** 642 * DOC: discovery (int) 643 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 644 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 645 */ 646 MODULE_PARM_DESC(discovery, 647 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 648 module_param_named(discovery, amdgpu_discovery, int, 0444); 649 650 /** 651 * DOC: mes (int) 652 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 653 * (0 = disabled (default), 1 = enabled) 654 */ 655 MODULE_PARM_DESC(mes, 656 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 657 module_param_named(mes, amdgpu_mes, int, 0444); 658 659 /** 660 * DOC: mes_kiq (int) 661 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 662 * (0 = disabled (default), 1 = enabled) 663 */ 664 MODULE_PARM_DESC(mes_kiq, 665 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 666 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 667 668 /** 669 * DOC: noretry (int) 670 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 671 * do not support per-process XNACK this also disables retry page faults. 672 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 673 */ 674 MODULE_PARM_DESC(noretry, 675 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 676 module_param_named(noretry, amdgpu_noretry, int, 0644); 677 678 /** 679 * DOC: force_asic_type (int) 680 * A non negative value used to specify the asic type for all supported GPUs. 681 */ 682 MODULE_PARM_DESC(force_asic_type, 683 "A non negative value used to specify the asic type for all supported GPUs"); 684 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 685 686 /** 687 * DOC: use_xgmi_p2p (int) 688 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 689 */ 690 MODULE_PARM_DESC(use_xgmi_p2p, 691 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 692 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 693 694 695 #ifdef CONFIG_HSA_AMD 696 /** 697 * DOC: sched_policy (int) 698 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 699 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 700 * assigns queues to HQDs. 701 */ 702 int sched_policy = KFD_SCHED_POLICY_HWS; 703 module_param(sched_policy, int, 0444); 704 MODULE_PARM_DESC(sched_policy, 705 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 706 707 /** 708 * DOC: hws_max_conc_proc (int) 709 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 710 * number of VMIDs assigned to the HWS, which is also the default. 711 */ 712 int hws_max_conc_proc = -1; 713 module_param(hws_max_conc_proc, int, 0444); 714 MODULE_PARM_DESC(hws_max_conc_proc, 715 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 716 717 /** 718 * DOC: cwsr_enable (int) 719 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 720 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 721 * disables it. 722 */ 723 int cwsr_enable = 1; 724 module_param(cwsr_enable, int, 0444); 725 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 726 727 /** 728 * DOC: max_num_of_queues_per_device (int) 729 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 730 * is 4096. 731 */ 732 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 733 module_param(max_num_of_queues_per_device, int, 0444); 734 MODULE_PARM_DESC(max_num_of_queues_per_device, 735 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 736 737 /** 738 * DOC: send_sigterm (int) 739 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 740 * but just print errors on dmesg. Setting 1 enables sending sigterm. 741 */ 742 int send_sigterm; 743 module_param(send_sigterm, int, 0444); 744 MODULE_PARM_DESC(send_sigterm, 745 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 746 747 /** 748 * DOC: debug_largebar (int) 749 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 750 * system. This limits the VRAM size reported to ROCm applications to the visible 751 * size, usually 256MB. 752 * Default value is 0, diabled. 753 */ 754 int debug_largebar; 755 module_param(debug_largebar, int, 0444); 756 MODULE_PARM_DESC(debug_largebar, 757 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 758 759 /** 760 * DOC: ignore_crat (int) 761 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 762 * table to get information about AMD APUs. This option can serve as a workaround on 763 * systems with a broken CRAT table. 764 * 765 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 766 * whether use CRAT) 767 */ 768 int ignore_crat; 769 module_param(ignore_crat, int, 0444); 770 MODULE_PARM_DESC(ignore_crat, 771 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 772 773 /** 774 * DOC: halt_if_hws_hang (int) 775 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 776 * Setting 1 enables halt on hang. 777 */ 778 int halt_if_hws_hang; 779 module_param(halt_if_hws_hang, int, 0644); 780 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 781 782 /** 783 * DOC: hws_gws_support(bool) 784 * Assume that HWS supports GWS barriers regardless of what firmware version 785 * check says. Default value: false (rely on MEC2 firmware version check). 786 */ 787 bool hws_gws_support; 788 module_param(hws_gws_support, bool, 0444); 789 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 790 791 /** 792 * DOC: queue_preemption_timeout_ms (int) 793 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 794 */ 795 int queue_preemption_timeout_ms = 9000; 796 module_param(queue_preemption_timeout_ms, int, 0644); 797 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 798 799 /** 800 * DOC: debug_evictions(bool) 801 * Enable extra debug messages to help determine the cause of evictions 802 */ 803 bool debug_evictions; 804 module_param(debug_evictions, bool, 0644); 805 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 806 807 /** 808 * DOC: no_system_mem_limit(bool) 809 * Disable system memory limit, to support multiple process shared memory 810 */ 811 bool no_system_mem_limit; 812 module_param(no_system_mem_limit, bool, 0644); 813 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 814 815 /** 816 * DOC: no_queue_eviction_on_vm_fault (int) 817 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 818 */ 819 int amdgpu_no_queue_eviction_on_vm_fault; 820 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 821 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 822 #endif 823 824 /** 825 * DOC: pcie_p2p (bool) 826 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 827 */ 828 #ifdef CONFIG_HSA_AMD_P2P 829 bool pcie_p2p = true; 830 module_param(pcie_p2p, bool, 0444); 831 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 832 #endif 833 834 /** 835 * DOC: dcfeaturemask (uint) 836 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 837 * The default is the current set of stable display features. 838 */ 839 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 840 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 841 842 /** 843 * DOC: dcdebugmask (uint) 844 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 845 */ 846 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 847 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 848 849 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 850 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 851 852 /** 853 * DOC: abmlevel (uint) 854 * Override the default ABM (Adaptive Backlight Management) level used for DC 855 * enabled hardware. Requires DMCU to be supported and loaded. 856 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 857 * default. Values 1-4 control the maximum allowable brightness reduction via 858 * the ABM algorithm, with 1 being the least reduction and 4 being the most 859 * reduction. 860 * 861 * Defaults to 0, or disabled. Userspace can still override this level later 862 * after boot. 863 */ 864 uint amdgpu_dm_abm_level; 865 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 866 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 867 868 int amdgpu_backlight = -1; 869 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 870 module_param_named(backlight, amdgpu_backlight, bint, 0444); 871 872 /** 873 * DOC: tmz (int) 874 * Trusted Memory Zone (TMZ) is a method to protect data being written 875 * to or read from memory. 876 * 877 * The default value: 0 (off). TODO: change to auto till it is completed. 878 */ 879 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 880 module_param_named(tmz, amdgpu_tmz, int, 0444); 881 882 /** 883 * DOC: freesync_video (uint) 884 * Enable the optimization to adjust front porch timing to achieve seamless 885 * mode change experience when setting a freesync supported mode for which full 886 * modeset is not needed. 887 * 888 * The Display Core will add a set of modes derived from the base FreeSync 889 * video mode into the corresponding connector's mode list based on commonly 890 * used refresh rates and VRR range of the connected display, when users enable 891 * this feature. From the userspace perspective, they can see a seamless mode 892 * change experience when the change between different refresh rates under the 893 * same resolution. Additionally, userspace applications such as Video playback 894 * can read this modeset list and change the refresh rate based on the video 895 * frame rate. Finally, the userspace can also derive an appropriate mode for a 896 * particular refresh rate based on the FreeSync Mode and add it to the 897 * connector's mode list. 898 * 899 * Note: This is an experimental feature. 900 * 901 * The default value: 0 (off). 902 */ 903 MODULE_PARM_DESC( 904 freesync_video, 905 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 906 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 907 908 /** 909 * DOC: reset_method (int) 910 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 911 */ 912 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 913 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 914 915 /** 916 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 917 * threshold value of faulty pages detected by RAS ECC, which may 918 * result in the GPU entering bad status when the number of total 919 * faulty pages by ECC exceeds the threshold value. 920 */ 921 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 922 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 923 924 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 925 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 926 927 /** 928 * DOC: vcnfw_log (int) 929 * Enable vcnfw log output for debugging, the default is disabled. 930 */ 931 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 932 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 933 934 /** 935 * DOC: sg_display (int) 936 * Disable S/G (scatter/gather) display (i.e., display from system memory). 937 * This option is only relevant on APUs. Set this option to 0 to disable 938 * S/G display if you experience flickering or other issues under memory 939 * pressure and report the issue. 940 */ 941 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 942 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 943 944 /** 945 * DOC: smu_pptable_id (int) 946 * Used to override pptable id. id = 0 use VBIOS pptable. 947 * id > 0 use the soft pptable with specicfied id. 948 */ 949 MODULE_PARM_DESC(smu_pptable_id, 950 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 951 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 952 953 /* These devices are not supported by amdgpu. 954 * They are supported by the mach64, r128, radeon drivers 955 */ 956 static const u16 amdgpu_unsupported_pciidlist[] = { 957 /* mach64 */ 958 0x4354, 959 0x4358, 960 0x4554, 961 0x4742, 962 0x4744, 963 0x4749, 964 0x474C, 965 0x474D, 966 0x474E, 967 0x474F, 968 0x4750, 969 0x4751, 970 0x4752, 971 0x4753, 972 0x4754, 973 0x4755, 974 0x4756, 975 0x4757, 976 0x4758, 977 0x4759, 978 0x475A, 979 0x4C42, 980 0x4C44, 981 0x4C47, 982 0x4C49, 983 0x4C4D, 984 0x4C4E, 985 0x4C50, 986 0x4C51, 987 0x4C52, 988 0x4C53, 989 0x5654, 990 0x5655, 991 0x5656, 992 /* r128 */ 993 0x4c45, 994 0x4c46, 995 0x4d46, 996 0x4d4c, 997 0x5041, 998 0x5042, 999 0x5043, 1000 0x5044, 1001 0x5045, 1002 0x5046, 1003 0x5047, 1004 0x5048, 1005 0x5049, 1006 0x504A, 1007 0x504B, 1008 0x504C, 1009 0x504D, 1010 0x504E, 1011 0x504F, 1012 0x5050, 1013 0x5051, 1014 0x5052, 1015 0x5053, 1016 0x5054, 1017 0x5055, 1018 0x5056, 1019 0x5057, 1020 0x5058, 1021 0x5245, 1022 0x5246, 1023 0x5247, 1024 0x524b, 1025 0x524c, 1026 0x534d, 1027 0x5446, 1028 0x544C, 1029 0x5452, 1030 /* radeon */ 1031 0x3150, 1032 0x3151, 1033 0x3152, 1034 0x3154, 1035 0x3155, 1036 0x3E50, 1037 0x3E54, 1038 0x4136, 1039 0x4137, 1040 0x4144, 1041 0x4145, 1042 0x4146, 1043 0x4147, 1044 0x4148, 1045 0x4149, 1046 0x414A, 1047 0x414B, 1048 0x4150, 1049 0x4151, 1050 0x4152, 1051 0x4153, 1052 0x4154, 1053 0x4155, 1054 0x4156, 1055 0x4237, 1056 0x4242, 1057 0x4336, 1058 0x4337, 1059 0x4437, 1060 0x4966, 1061 0x4967, 1062 0x4A48, 1063 0x4A49, 1064 0x4A4A, 1065 0x4A4B, 1066 0x4A4C, 1067 0x4A4D, 1068 0x4A4E, 1069 0x4A4F, 1070 0x4A50, 1071 0x4A54, 1072 0x4B48, 1073 0x4B49, 1074 0x4B4A, 1075 0x4B4B, 1076 0x4B4C, 1077 0x4C57, 1078 0x4C58, 1079 0x4C59, 1080 0x4C5A, 1081 0x4C64, 1082 0x4C66, 1083 0x4C67, 1084 0x4E44, 1085 0x4E45, 1086 0x4E46, 1087 0x4E47, 1088 0x4E48, 1089 0x4E49, 1090 0x4E4A, 1091 0x4E4B, 1092 0x4E50, 1093 0x4E51, 1094 0x4E52, 1095 0x4E53, 1096 0x4E54, 1097 0x4E56, 1098 0x5144, 1099 0x5145, 1100 0x5146, 1101 0x5147, 1102 0x5148, 1103 0x514C, 1104 0x514D, 1105 0x5157, 1106 0x5158, 1107 0x5159, 1108 0x515A, 1109 0x515E, 1110 0x5460, 1111 0x5462, 1112 0x5464, 1113 0x5548, 1114 0x5549, 1115 0x554A, 1116 0x554B, 1117 0x554C, 1118 0x554D, 1119 0x554E, 1120 0x554F, 1121 0x5550, 1122 0x5551, 1123 0x5552, 1124 0x5554, 1125 0x564A, 1126 0x564B, 1127 0x564F, 1128 0x5652, 1129 0x5653, 1130 0x5657, 1131 0x5834, 1132 0x5835, 1133 0x5954, 1134 0x5955, 1135 0x5974, 1136 0x5975, 1137 0x5960, 1138 0x5961, 1139 0x5962, 1140 0x5964, 1141 0x5965, 1142 0x5969, 1143 0x5a41, 1144 0x5a42, 1145 0x5a61, 1146 0x5a62, 1147 0x5b60, 1148 0x5b62, 1149 0x5b63, 1150 0x5b64, 1151 0x5b65, 1152 0x5c61, 1153 0x5c63, 1154 0x5d48, 1155 0x5d49, 1156 0x5d4a, 1157 0x5d4c, 1158 0x5d4d, 1159 0x5d4e, 1160 0x5d4f, 1161 0x5d50, 1162 0x5d52, 1163 0x5d57, 1164 0x5e48, 1165 0x5e4a, 1166 0x5e4b, 1167 0x5e4c, 1168 0x5e4d, 1169 0x5e4f, 1170 0x6700, 1171 0x6701, 1172 0x6702, 1173 0x6703, 1174 0x6704, 1175 0x6705, 1176 0x6706, 1177 0x6707, 1178 0x6708, 1179 0x6709, 1180 0x6718, 1181 0x6719, 1182 0x671c, 1183 0x671d, 1184 0x671f, 1185 0x6720, 1186 0x6721, 1187 0x6722, 1188 0x6723, 1189 0x6724, 1190 0x6725, 1191 0x6726, 1192 0x6727, 1193 0x6728, 1194 0x6729, 1195 0x6738, 1196 0x6739, 1197 0x673e, 1198 0x6740, 1199 0x6741, 1200 0x6742, 1201 0x6743, 1202 0x6744, 1203 0x6745, 1204 0x6746, 1205 0x6747, 1206 0x6748, 1207 0x6749, 1208 0x674A, 1209 0x6750, 1210 0x6751, 1211 0x6758, 1212 0x6759, 1213 0x675B, 1214 0x675D, 1215 0x675F, 1216 0x6760, 1217 0x6761, 1218 0x6762, 1219 0x6763, 1220 0x6764, 1221 0x6765, 1222 0x6766, 1223 0x6767, 1224 0x6768, 1225 0x6770, 1226 0x6771, 1227 0x6772, 1228 0x6778, 1229 0x6779, 1230 0x677B, 1231 0x6840, 1232 0x6841, 1233 0x6842, 1234 0x6843, 1235 0x6849, 1236 0x684C, 1237 0x6850, 1238 0x6858, 1239 0x6859, 1240 0x6880, 1241 0x6888, 1242 0x6889, 1243 0x688A, 1244 0x688C, 1245 0x688D, 1246 0x6898, 1247 0x6899, 1248 0x689b, 1249 0x689c, 1250 0x689d, 1251 0x689e, 1252 0x68a0, 1253 0x68a1, 1254 0x68a8, 1255 0x68a9, 1256 0x68b0, 1257 0x68b8, 1258 0x68b9, 1259 0x68ba, 1260 0x68be, 1261 0x68bf, 1262 0x68c0, 1263 0x68c1, 1264 0x68c7, 1265 0x68c8, 1266 0x68c9, 1267 0x68d8, 1268 0x68d9, 1269 0x68da, 1270 0x68de, 1271 0x68e0, 1272 0x68e1, 1273 0x68e4, 1274 0x68e5, 1275 0x68e8, 1276 0x68e9, 1277 0x68f1, 1278 0x68f2, 1279 0x68f8, 1280 0x68f9, 1281 0x68fa, 1282 0x68fe, 1283 0x7100, 1284 0x7101, 1285 0x7102, 1286 0x7103, 1287 0x7104, 1288 0x7105, 1289 0x7106, 1290 0x7108, 1291 0x7109, 1292 0x710A, 1293 0x710B, 1294 0x710C, 1295 0x710E, 1296 0x710F, 1297 0x7140, 1298 0x7141, 1299 0x7142, 1300 0x7143, 1301 0x7144, 1302 0x7145, 1303 0x7146, 1304 0x7147, 1305 0x7149, 1306 0x714A, 1307 0x714B, 1308 0x714C, 1309 0x714D, 1310 0x714E, 1311 0x714F, 1312 0x7151, 1313 0x7152, 1314 0x7153, 1315 0x715E, 1316 0x715F, 1317 0x7180, 1318 0x7181, 1319 0x7183, 1320 0x7186, 1321 0x7187, 1322 0x7188, 1323 0x718A, 1324 0x718B, 1325 0x718C, 1326 0x718D, 1327 0x718F, 1328 0x7193, 1329 0x7196, 1330 0x719B, 1331 0x719F, 1332 0x71C0, 1333 0x71C1, 1334 0x71C2, 1335 0x71C3, 1336 0x71C4, 1337 0x71C5, 1338 0x71C6, 1339 0x71C7, 1340 0x71CD, 1341 0x71CE, 1342 0x71D2, 1343 0x71D4, 1344 0x71D5, 1345 0x71D6, 1346 0x71DA, 1347 0x71DE, 1348 0x7200, 1349 0x7210, 1350 0x7211, 1351 0x7240, 1352 0x7243, 1353 0x7244, 1354 0x7245, 1355 0x7246, 1356 0x7247, 1357 0x7248, 1358 0x7249, 1359 0x724A, 1360 0x724B, 1361 0x724C, 1362 0x724D, 1363 0x724E, 1364 0x724F, 1365 0x7280, 1366 0x7281, 1367 0x7283, 1368 0x7284, 1369 0x7287, 1370 0x7288, 1371 0x7289, 1372 0x728B, 1373 0x728C, 1374 0x7290, 1375 0x7291, 1376 0x7293, 1377 0x7297, 1378 0x7834, 1379 0x7835, 1380 0x791e, 1381 0x791f, 1382 0x793f, 1383 0x7941, 1384 0x7942, 1385 0x796c, 1386 0x796d, 1387 0x796e, 1388 0x796f, 1389 0x9400, 1390 0x9401, 1391 0x9402, 1392 0x9403, 1393 0x9405, 1394 0x940A, 1395 0x940B, 1396 0x940F, 1397 0x94A0, 1398 0x94A1, 1399 0x94A3, 1400 0x94B1, 1401 0x94B3, 1402 0x94B4, 1403 0x94B5, 1404 0x94B9, 1405 0x9440, 1406 0x9441, 1407 0x9442, 1408 0x9443, 1409 0x9444, 1410 0x9446, 1411 0x944A, 1412 0x944B, 1413 0x944C, 1414 0x944E, 1415 0x9450, 1416 0x9452, 1417 0x9456, 1418 0x945A, 1419 0x945B, 1420 0x945E, 1421 0x9460, 1422 0x9462, 1423 0x946A, 1424 0x946B, 1425 0x947A, 1426 0x947B, 1427 0x9480, 1428 0x9487, 1429 0x9488, 1430 0x9489, 1431 0x948A, 1432 0x948F, 1433 0x9490, 1434 0x9491, 1435 0x9495, 1436 0x9498, 1437 0x949C, 1438 0x949E, 1439 0x949F, 1440 0x94C0, 1441 0x94C1, 1442 0x94C3, 1443 0x94C4, 1444 0x94C5, 1445 0x94C6, 1446 0x94C7, 1447 0x94C8, 1448 0x94C9, 1449 0x94CB, 1450 0x94CC, 1451 0x94CD, 1452 0x9500, 1453 0x9501, 1454 0x9504, 1455 0x9505, 1456 0x9506, 1457 0x9507, 1458 0x9508, 1459 0x9509, 1460 0x950F, 1461 0x9511, 1462 0x9515, 1463 0x9517, 1464 0x9519, 1465 0x9540, 1466 0x9541, 1467 0x9542, 1468 0x954E, 1469 0x954F, 1470 0x9552, 1471 0x9553, 1472 0x9555, 1473 0x9557, 1474 0x955f, 1475 0x9580, 1476 0x9581, 1477 0x9583, 1478 0x9586, 1479 0x9587, 1480 0x9588, 1481 0x9589, 1482 0x958A, 1483 0x958B, 1484 0x958C, 1485 0x958D, 1486 0x958E, 1487 0x958F, 1488 0x9590, 1489 0x9591, 1490 0x9593, 1491 0x9595, 1492 0x9596, 1493 0x9597, 1494 0x9598, 1495 0x9599, 1496 0x959B, 1497 0x95C0, 1498 0x95C2, 1499 0x95C4, 1500 0x95C5, 1501 0x95C6, 1502 0x95C7, 1503 0x95C9, 1504 0x95CC, 1505 0x95CD, 1506 0x95CE, 1507 0x95CF, 1508 0x9610, 1509 0x9611, 1510 0x9612, 1511 0x9613, 1512 0x9614, 1513 0x9615, 1514 0x9616, 1515 0x9640, 1516 0x9641, 1517 0x9642, 1518 0x9643, 1519 0x9644, 1520 0x9645, 1521 0x9647, 1522 0x9648, 1523 0x9649, 1524 0x964a, 1525 0x964b, 1526 0x964c, 1527 0x964e, 1528 0x964f, 1529 0x9710, 1530 0x9711, 1531 0x9712, 1532 0x9713, 1533 0x9714, 1534 0x9715, 1535 0x9802, 1536 0x9803, 1537 0x9804, 1538 0x9805, 1539 0x9806, 1540 0x9807, 1541 0x9808, 1542 0x9809, 1543 0x980A, 1544 0x9900, 1545 0x9901, 1546 0x9903, 1547 0x9904, 1548 0x9905, 1549 0x9906, 1550 0x9907, 1551 0x9908, 1552 0x9909, 1553 0x990A, 1554 0x990B, 1555 0x990C, 1556 0x990D, 1557 0x990E, 1558 0x990F, 1559 0x9910, 1560 0x9913, 1561 0x9917, 1562 0x9918, 1563 0x9919, 1564 0x9990, 1565 0x9991, 1566 0x9992, 1567 0x9993, 1568 0x9994, 1569 0x9995, 1570 0x9996, 1571 0x9997, 1572 0x9998, 1573 0x9999, 1574 0x999A, 1575 0x999B, 1576 0x999C, 1577 0x999D, 1578 0x99A0, 1579 0x99A2, 1580 0x99A4, 1581 /* radeon secondary ids */ 1582 0x3171, 1583 0x3e70, 1584 0x4164, 1585 0x4165, 1586 0x4166, 1587 0x4168, 1588 0x4170, 1589 0x4171, 1590 0x4172, 1591 0x4173, 1592 0x496e, 1593 0x4a69, 1594 0x4a6a, 1595 0x4a6b, 1596 0x4a70, 1597 0x4a74, 1598 0x4b69, 1599 0x4b6b, 1600 0x4b6c, 1601 0x4c6e, 1602 0x4e64, 1603 0x4e65, 1604 0x4e66, 1605 0x4e67, 1606 0x4e68, 1607 0x4e69, 1608 0x4e6a, 1609 0x4e71, 1610 0x4f73, 1611 0x5569, 1612 0x556b, 1613 0x556d, 1614 0x556f, 1615 0x5571, 1616 0x5854, 1617 0x5874, 1618 0x5940, 1619 0x5941, 1620 0x5b72, 1621 0x5b73, 1622 0x5b74, 1623 0x5b75, 1624 0x5d44, 1625 0x5d45, 1626 0x5d6d, 1627 0x5d6f, 1628 0x5d72, 1629 0x5d77, 1630 0x5e6b, 1631 0x5e6d, 1632 0x7120, 1633 0x7124, 1634 0x7129, 1635 0x712e, 1636 0x712f, 1637 0x7162, 1638 0x7163, 1639 0x7166, 1640 0x7167, 1641 0x7172, 1642 0x7173, 1643 0x71a0, 1644 0x71a1, 1645 0x71a3, 1646 0x71a7, 1647 0x71bb, 1648 0x71e0, 1649 0x71e1, 1650 0x71e2, 1651 0x71e6, 1652 0x71e7, 1653 0x71f2, 1654 0x7269, 1655 0x726b, 1656 0x726e, 1657 0x72a0, 1658 0x72a8, 1659 0x72b1, 1660 0x72b3, 1661 0x793f, 1662 }; 1663 1664 static const struct pci_device_id pciidlist[] = { 1665 #ifdef CONFIG_DRM_AMDGPU_SI 1666 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1668 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1669 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1670 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1671 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1672 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1673 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1674 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1675 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1676 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1677 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1678 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1679 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1680 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1681 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1682 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1683 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1684 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1685 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1686 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1687 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1688 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1689 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1690 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1691 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1692 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1693 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1694 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1700 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1701 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1702 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1703 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1708 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1710 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1711 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1717 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1718 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1719 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1720 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1721 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1722 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1726 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1727 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1728 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1729 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1730 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1731 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1732 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1737 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1738 #endif 1739 #ifdef CONFIG_DRM_AMDGPU_CIK 1740 /* Kaveri */ 1741 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1743 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1744 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1745 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1746 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1747 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1748 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1752 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1753 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1754 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1755 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1756 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1757 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1758 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1761 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1762 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1763 /* Bonaire */ 1764 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1765 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1766 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1767 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1768 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1769 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1770 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1771 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1772 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1773 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1774 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1775 /* Hawaii */ 1776 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1777 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1778 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1779 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1780 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1781 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1782 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1783 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1784 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1785 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1786 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1787 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1788 /* Kabini */ 1789 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1790 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1791 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1792 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1793 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1794 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1795 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1796 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1797 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1798 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1800 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1801 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1802 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1803 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1804 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1805 /* mullins */ 1806 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1814 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1815 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1816 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1817 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1818 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1822 #endif 1823 /* topaz */ 1824 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1825 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1826 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1827 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1828 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1829 /* tonga */ 1830 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1831 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1832 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1833 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1834 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1835 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1836 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1837 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1838 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1839 /* fiji */ 1840 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1841 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1842 /* carrizo */ 1843 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1844 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1845 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1846 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1847 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1848 /* stoney */ 1849 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1850 /* Polaris11 */ 1851 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1852 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1853 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1854 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1855 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1856 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1857 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1858 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1859 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1860 /* Polaris10 */ 1861 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1863 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1864 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1865 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1866 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1867 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1868 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1869 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1870 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1871 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1872 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1873 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1874 /* Polaris12 */ 1875 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1876 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1877 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1878 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1879 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1880 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1881 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1882 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1883 /* VEGAM */ 1884 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1885 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1886 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1887 /* Vega 10 */ 1888 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1893 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1894 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1895 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1896 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1897 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1898 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1899 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1900 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1901 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1902 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1903 /* Vega 12 */ 1904 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1905 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1906 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1907 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1908 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1909 /* Vega 20 */ 1910 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1911 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1912 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1913 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1914 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1915 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1916 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1917 /* Raven */ 1918 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1919 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1920 /* Arcturus */ 1921 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1922 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1923 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1924 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1925 /* Navi10 */ 1926 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1927 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1928 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1929 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1930 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1931 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1932 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1933 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1934 /* Navi14 */ 1935 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1936 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1937 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1938 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1939 1940 /* Renoir */ 1941 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1942 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1943 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1944 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1945 1946 /* Navi12 */ 1947 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1948 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1949 1950 /* Sienna_Cichlid */ 1951 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1953 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1954 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1955 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1956 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1957 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1958 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1959 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1960 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1961 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1962 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1963 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1964 1965 /* Yellow Carp */ 1966 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1967 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1968 1969 /* Navy_Flounder */ 1970 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1971 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1972 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1973 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1974 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1975 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1976 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1977 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1978 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1979 1980 /* DIMGREY_CAVEFISH */ 1981 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1982 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1983 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1984 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1985 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1986 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1987 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1988 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1989 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1990 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1991 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1992 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1993 1994 /* Aldebaran */ 1995 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1996 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1997 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1998 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1999 2000 /* CYAN_SKILLFISH */ 2001 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2002 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2003 2004 /* BEIGE_GOBY */ 2005 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2006 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2007 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2008 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2009 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2010 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2011 2012 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2013 .class = PCI_CLASS_DISPLAY_VGA << 8, 2014 .class_mask = 0xffffff, 2015 .driver_data = CHIP_IP_DISCOVERY }, 2016 2017 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2018 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2019 .class_mask = 0xffffff, 2020 .driver_data = CHIP_IP_DISCOVERY }, 2021 2022 {0, 0, 0} 2023 }; 2024 2025 MODULE_DEVICE_TABLE(pci, pciidlist); 2026 2027 static const struct drm_driver amdgpu_kms_driver; 2028 2029 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2030 { 2031 struct pci_dev *p = NULL; 2032 int i; 2033 2034 /* 0 - GPU 2035 * 1 - audio 2036 * 2 - USB 2037 * 3 - UCSI 2038 */ 2039 for (i = 1; i < 4; i++) { 2040 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2041 adev->pdev->bus->number, i); 2042 if (p) { 2043 pm_runtime_get_sync(&p->dev); 2044 pm_runtime_mark_last_busy(&p->dev); 2045 pm_runtime_put_autosuspend(&p->dev); 2046 pci_dev_put(p); 2047 } 2048 } 2049 } 2050 2051 static int amdgpu_pci_probe(struct pci_dev *pdev, 2052 const struct pci_device_id *ent) 2053 { 2054 struct drm_device *ddev; 2055 struct amdgpu_device *adev; 2056 unsigned long flags = ent->driver_data; 2057 int ret, retry = 0, i; 2058 bool supports_atomic = false; 2059 2060 /* skip devices which are owned by radeon */ 2061 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2062 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2063 return -ENODEV; 2064 } 2065 2066 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2067 amdgpu_aspm = 0; 2068 2069 if (amdgpu_virtual_display || 2070 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2071 supports_atomic = true; 2072 2073 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2074 DRM_INFO("This hardware requires experimental hardware support.\n" 2075 "See modparam exp_hw_support\n"); 2076 return -ENODEV; 2077 } 2078 /* differentiate between P10 and P11 asics with the same DID */ 2079 if (pdev->device == 0x67FF && 2080 (pdev->revision == 0xE3 || 2081 pdev->revision == 0xE7 || 2082 pdev->revision == 0xF3 || 2083 pdev->revision == 0xF7)) { 2084 flags &= ~AMD_ASIC_MASK; 2085 flags |= CHIP_POLARIS10; 2086 } 2087 2088 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2089 * however, SME requires an indirect IOMMU mapping because the encryption 2090 * bit is beyond the DMA mask of the chip. 2091 */ 2092 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2093 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2094 dev_info(&pdev->dev, 2095 "SME is not compatible with RAVEN\n"); 2096 return -ENOTSUPP; 2097 } 2098 2099 #ifdef CONFIG_DRM_AMDGPU_SI 2100 if (!amdgpu_si_support) { 2101 switch (flags & AMD_ASIC_MASK) { 2102 case CHIP_TAHITI: 2103 case CHIP_PITCAIRN: 2104 case CHIP_VERDE: 2105 case CHIP_OLAND: 2106 case CHIP_HAINAN: 2107 dev_info(&pdev->dev, 2108 "SI support provided by radeon.\n"); 2109 dev_info(&pdev->dev, 2110 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2111 ); 2112 return -ENODEV; 2113 } 2114 } 2115 #endif 2116 #ifdef CONFIG_DRM_AMDGPU_CIK 2117 if (!amdgpu_cik_support) { 2118 switch (flags & AMD_ASIC_MASK) { 2119 case CHIP_KAVERI: 2120 case CHIP_BONAIRE: 2121 case CHIP_HAWAII: 2122 case CHIP_KABINI: 2123 case CHIP_MULLINS: 2124 dev_info(&pdev->dev, 2125 "CIK support provided by radeon.\n"); 2126 dev_info(&pdev->dev, 2127 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2128 ); 2129 return -ENODEV; 2130 } 2131 } 2132 #endif 2133 2134 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2135 if (IS_ERR(adev)) 2136 return PTR_ERR(adev); 2137 2138 adev->dev = &pdev->dev; 2139 adev->pdev = pdev; 2140 ddev = adev_to_drm(adev); 2141 2142 if (!supports_atomic) 2143 ddev->driver_features &= ~DRIVER_ATOMIC; 2144 2145 ret = pci_enable_device(pdev); 2146 if (ret) 2147 return ret; 2148 2149 pci_set_drvdata(pdev, ddev); 2150 2151 ret = amdgpu_driver_load_kms(adev, flags); 2152 if (ret) 2153 goto err_pci; 2154 2155 retry_init: 2156 ret = drm_dev_register(ddev, flags); 2157 if (ret == -EAGAIN && ++retry <= 3) { 2158 DRM_INFO("retry init %d\n", retry); 2159 /* Don't request EX mode too frequently which is attacking */ 2160 msleep(5000); 2161 goto retry_init; 2162 } else if (ret) { 2163 goto err_pci; 2164 } 2165 2166 /* 2167 * 1. don't init fbdev on hw without DCE 2168 * 2. don't init fbdev if there are no connectors 2169 */ 2170 if (adev->mode_info.mode_config_initialized && 2171 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2172 /* select 8 bpp console on low vram cards */ 2173 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2174 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2175 else 2176 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2177 } 2178 2179 ret = amdgpu_debugfs_init(adev); 2180 if (ret) 2181 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2182 2183 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2184 /* only need to skip on ATPX */ 2185 if (amdgpu_device_supports_px(ddev)) 2186 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2187 /* we want direct complete for BOCO */ 2188 if (amdgpu_device_supports_boco(ddev)) 2189 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2190 DPM_FLAG_SMART_SUSPEND | 2191 DPM_FLAG_MAY_SKIP_RESUME); 2192 pm_runtime_use_autosuspend(ddev->dev); 2193 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2194 2195 pm_runtime_allow(ddev->dev); 2196 2197 pm_runtime_mark_last_busy(ddev->dev); 2198 pm_runtime_put_autosuspend(ddev->dev); 2199 2200 /* 2201 * For runpm implemented via BACO, PMFW will handle the 2202 * timing for BACO in and out: 2203 * - put ASIC into BACO state only when both video and 2204 * audio functions are in D3 state. 2205 * - pull ASIC out of BACO state when either video or 2206 * audio function is in D0 state. 2207 * Also, at startup, PMFW assumes both functions are in 2208 * D0 state. 2209 * 2210 * So if snd driver was loaded prior to amdgpu driver 2211 * and audio function was put into D3 state, there will 2212 * be no PMFW-aware D-state transition(D0->D3) on runpm 2213 * suspend. Thus the BACO will be not correctly kicked in. 2214 * 2215 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2216 * into D0 state. Then there will be a PMFW-aware D-state 2217 * transition(D0->D3) on runpm suspend. 2218 */ 2219 if (amdgpu_device_supports_baco(ddev) && 2220 !(adev->flags & AMD_IS_APU) && 2221 (adev->asic_type >= CHIP_NAVI10)) 2222 amdgpu_get_secondary_funcs(adev); 2223 } 2224 2225 return 0; 2226 2227 err_pci: 2228 pci_disable_device(pdev); 2229 return ret; 2230 } 2231 2232 static void 2233 amdgpu_pci_remove(struct pci_dev *pdev) 2234 { 2235 struct drm_device *dev = pci_get_drvdata(pdev); 2236 struct amdgpu_device *adev = drm_to_adev(dev); 2237 2238 drm_dev_unplug(dev); 2239 2240 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2241 pm_runtime_get_sync(dev->dev); 2242 pm_runtime_forbid(dev->dev); 2243 } 2244 2245 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2246 !amdgpu_sriov_vf(adev)) { 2247 bool need_to_reset_gpu = false; 2248 2249 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2250 struct amdgpu_hive_info *hive; 2251 2252 hive = amdgpu_get_xgmi_hive(adev); 2253 if (hive->device_remove_count == 0) 2254 need_to_reset_gpu = true; 2255 hive->device_remove_count++; 2256 amdgpu_put_xgmi_hive(hive); 2257 } else { 2258 need_to_reset_gpu = true; 2259 } 2260 2261 /* Workaround for ASICs need to reset SMU. 2262 * Called only when the first device is removed. 2263 */ 2264 if (need_to_reset_gpu) { 2265 struct amdgpu_reset_context reset_context; 2266 2267 adev->shutdown = true; 2268 memset(&reset_context, 0, sizeof(reset_context)); 2269 reset_context.method = AMD_RESET_METHOD_NONE; 2270 reset_context.reset_req_dev = adev; 2271 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2272 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2273 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2274 } 2275 } 2276 2277 amdgpu_driver_unload_kms(dev); 2278 2279 /* 2280 * Flush any in flight DMA operations from device. 2281 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2282 * StatusTransactions Pending bit. 2283 */ 2284 pci_disable_device(pdev); 2285 pci_wait_for_pending_transaction(pdev); 2286 } 2287 2288 static void 2289 amdgpu_pci_shutdown(struct pci_dev *pdev) 2290 { 2291 struct drm_device *dev = pci_get_drvdata(pdev); 2292 struct amdgpu_device *adev = drm_to_adev(dev); 2293 2294 if (amdgpu_ras_intr_triggered()) 2295 return; 2296 2297 /* if we are running in a VM, make sure the device 2298 * torn down properly on reboot/shutdown. 2299 * unfortunately we can't detect certain 2300 * hypervisors so just do this all the time. 2301 */ 2302 if (!amdgpu_passthrough(adev)) 2303 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2304 amdgpu_device_ip_suspend(adev); 2305 adev->mp1_state = PP_MP1_STATE_NONE; 2306 } 2307 2308 /** 2309 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2310 * 2311 * @work: work_struct. 2312 */ 2313 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2314 { 2315 struct list_head device_list; 2316 struct amdgpu_device *adev; 2317 int i, r; 2318 struct amdgpu_reset_context reset_context; 2319 2320 memset(&reset_context, 0, sizeof(reset_context)); 2321 2322 mutex_lock(&mgpu_info.mutex); 2323 if (mgpu_info.pending_reset == true) { 2324 mutex_unlock(&mgpu_info.mutex); 2325 return; 2326 } 2327 mgpu_info.pending_reset = true; 2328 mutex_unlock(&mgpu_info.mutex); 2329 2330 /* Use a common context, just need to make sure full reset is done */ 2331 reset_context.method = AMD_RESET_METHOD_NONE; 2332 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2333 2334 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2335 adev = mgpu_info.gpu_ins[i].adev; 2336 reset_context.reset_req_dev = adev; 2337 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2338 if (r) { 2339 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2340 r, adev_to_drm(adev)->unique); 2341 } 2342 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2343 r = -EALREADY; 2344 } 2345 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2346 adev = mgpu_info.gpu_ins[i].adev; 2347 flush_work(&adev->xgmi_reset_work); 2348 adev->gmc.xgmi.pending_reset = false; 2349 } 2350 2351 /* reset function will rebuild the xgmi hive info , clear it now */ 2352 for (i = 0; i < mgpu_info.num_dgpu; i++) 2353 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2354 2355 INIT_LIST_HEAD(&device_list); 2356 2357 for (i = 0; i < mgpu_info.num_dgpu; i++) 2358 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2359 2360 /* unregister the GPU first, reset function will add them back */ 2361 list_for_each_entry(adev, &device_list, reset_list) 2362 amdgpu_unregister_gpu_instance(adev); 2363 2364 /* Use a common context, just need to make sure full reset is done */ 2365 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2366 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2367 2368 if (r) { 2369 DRM_ERROR("reinit gpus failure"); 2370 return; 2371 } 2372 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2373 adev = mgpu_info.gpu_ins[i].adev; 2374 if (!adev->kfd.init_complete) 2375 amdgpu_amdkfd_device_init(adev); 2376 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2377 } 2378 return; 2379 } 2380 2381 static int amdgpu_pmops_prepare(struct device *dev) 2382 { 2383 struct drm_device *drm_dev = dev_get_drvdata(dev); 2384 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2385 2386 /* Return a positive number here so 2387 * DPM_FLAG_SMART_SUSPEND works properly 2388 */ 2389 if (amdgpu_device_supports_boco(drm_dev)) 2390 return pm_runtime_suspended(dev); 2391 2392 /* if we will not support s3 or s2i for the device 2393 * then skip suspend 2394 */ 2395 if (!amdgpu_acpi_is_s0ix_active(adev) && 2396 !amdgpu_acpi_is_s3_active(adev)) 2397 return 1; 2398 2399 return 0; 2400 } 2401 2402 static void amdgpu_pmops_complete(struct device *dev) 2403 { 2404 /* nothing to do */ 2405 } 2406 2407 static int amdgpu_pmops_suspend(struct device *dev) 2408 { 2409 struct drm_device *drm_dev = dev_get_drvdata(dev); 2410 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2411 2412 if (amdgpu_acpi_is_s0ix_active(adev)) 2413 adev->in_s0ix = true; 2414 else if (amdgpu_acpi_is_s3_active(adev)) 2415 adev->in_s3 = true; 2416 if (!adev->in_s0ix && !adev->in_s3) 2417 return 0; 2418 return amdgpu_device_suspend(drm_dev, true); 2419 } 2420 2421 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2422 { 2423 struct drm_device *drm_dev = dev_get_drvdata(dev); 2424 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2425 2426 if (amdgpu_acpi_should_gpu_reset(adev)) 2427 return amdgpu_asic_reset(adev); 2428 2429 return 0; 2430 } 2431 2432 static int amdgpu_pmops_resume(struct device *dev) 2433 { 2434 struct drm_device *drm_dev = dev_get_drvdata(dev); 2435 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2436 int r; 2437 2438 if (!adev->in_s0ix && !adev->in_s3) 2439 return 0; 2440 2441 /* Avoids registers access if device is physically gone */ 2442 if (!pci_device_is_present(adev->pdev)) 2443 adev->no_hw_access = true; 2444 2445 r = amdgpu_device_resume(drm_dev, true); 2446 if (amdgpu_acpi_is_s0ix_active(adev)) 2447 adev->in_s0ix = false; 2448 else 2449 adev->in_s3 = false; 2450 return r; 2451 } 2452 2453 static int amdgpu_pmops_freeze(struct device *dev) 2454 { 2455 struct drm_device *drm_dev = dev_get_drvdata(dev); 2456 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2457 int r; 2458 2459 adev->in_s4 = true; 2460 r = amdgpu_device_suspend(drm_dev, true); 2461 adev->in_s4 = false; 2462 if (r) 2463 return r; 2464 2465 if (amdgpu_acpi_should_gpu_reset(adev)) 2466 return amdgpu_asic_reset(adev); 2467 return 0; 2468 } 2469 2470 static int amdgpu_pmops_thaw(struct device *dev) 2471 { 2472 struct drm_device *drm_dev = dev_get_drvdata(dev); 2473 2474 return amdgpu_device_resume(drm_dev, true); 2475 } 2476 2477 static int amdgpu_pmops_poweroff(struct device *dev) 2478 { 2479 struct drm_device *drm_dev = dev_get_drvdata(dev); 2480 2481 return amdgpu_device_suspend(drm_dev, true); 2482 } 2483 2484 static int amdgpu_pmops_restore(struct device *dev) 2485 { 2486 struct drm_device *drm_dev = dev_get_drvdata(dev); 2487 2488 return amdgpu_device_resume(drm_dev, true); 2489 } 2490 2491 static int amdgpu_runtime_idle_check_display(struct device *dev) 2492 { 2493 struct pci_dev *pdev = to_pci_dev(dev); 2494 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2495 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2496 2497 if (adev->mode_info.num_crtc) { 2498 struct drm_connector *list_connector; 2499 struct drm_connector_list_iter iter; 2500 int ret = 0; 2501 2502 /* XXX: Return busy if any displays are connected to avoid 2503 * possible display wakeups after runtime resume due to 2504 * hotplug events in case any displays were connected while 2505 * the GPU was in suspend. Remove this once that is fixed. 2506 */ 2507 mutex_lock(&drm_dev->mode_config.mutex); 2508 drm_connector_list_iter_begin(drm_dev, &iter); 2509 drm_for_each_connector_iter(list_connector, &iter) { 2510 if (list_connector->status == connector_status_connected) { 2511 ret = -EBUSY; 2512 break; 2513 } 2514 } 2515 drm_connector_list_iter_end(&iter); 2516 mutex_unlock(&drm_dev->mode_config.mutex); 2517 2518 if (ret) 2519 return ret; 2520 2521 if (adev->dc_enabled) { 2522 struct drm_crtc *crtc; 2523 2524 drm_for_each_crtc(crtc, drm_dev) { 2525 drm_modeset_lock(&crtc->mutex, NULL); 2526 if (crtc->state->active) 2527 ret = -EBUSY; 2528 drm_modeset_unlock(&crtc->mutex); 2529 if (ret < 0) 2530 break; 2531 } 2532 } else { 2533 mutex_lock(&drm_dev->mode_config.mutex); 2534 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2535 2536 drm_connector_list_iter_begin(drm_dev, &iter); 2537 drm_for_each_connector_iter(list_connector, &iter) { 2538 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2539 ret = -EBUSY; 2540 break; 2541 } 2542 } 2543 2544 drm_connector_list_iter_end(&iter); 2545 2546 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2547 mutex_unlock(&drm_dev->mode_config.mutex); 2548 } 2549 if (ret) 2550 return ret; 2551 } 2552 2553 return 0; 2554 } 2555 2556 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2557 { 2558 struct pci_dev *pdev = to_pci_dev(dev); 2559 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2560 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2561 int ret, i; 2562 2563 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2564 pm_runtime_forbid(dev); 2565 return -EBUSY; 2566 } 2567 2568 ret = amdgpu_runtime_idle_check_display(dev); 2569 if (ret) 2570 return ret; 2571 2572 /* wait for all rings to drain before suspending */ 2573 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2574 struct amdgpu_ring *ring = adev->rings[i]; 2575 if (ring && ring->sched.ready) { 2576 ret = amdgpu_fence_wait_empty(ring); 2577 if (ret) 2578 return -EBUSY; 2579 } 2580 } 2581 2582 adev->in_runpm = true; 2583 if (amdgpu_device_supports_px(drm_dev)) 2584 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2585 2586 /* 2587 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2588 * proper cleanups and put itself into a state ready for PNP. That 2589 * can address some random resuming failure observed on BOCO capable 2590 * platforms. 2591 * TODO: this may be also needed for PX capable platform. 2592 */ 2593 if (amdgpu_device_supports_boco(drm_dev)) 2594 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2595 2596 ret = amdgpu_device_suspend(drm_dev, false); 2597 if (ret) { 2598 adev->in_runpm = false; 2599 if (amdgpu_device_supports_boco(drm_dev)) 2600 adev->mp1_state = PP_MP1_STATE_NONE; 2601 return ret; 2602 } 2603 2604 if (amdgpu_device_supports_boco(drm_dev)) 2605 adev->mp1_state = PP_MP1_STATE_NONE; 2606 2607 if (amdgpu_device_supports_px(drm_dev)) { 2608 /* Only need to handle PCI state in the driver for ATPX 2609 * PCI core handles it for _PR3. 2610 */ 2611 amdgpu_device_cache_pci_state(pdev); 2612 pci_disable_device(pdev); 2613 pci_ignore_hotplug(pdev); 2614 pci_set_power_state(pdev, PCI_D3cold); 2615 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2616 } else if (amdgpu_device_supports_boco(drm_dev)) { 2617 /* nothing to do */ 2618 } else if (amdgpu_device_supports_baco(drm_dev)) { 2619 amdgpu_device_baco_enter(drm_dev); 2620 } 2621 2622 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2623 2624 return 0; 2625 } 2626 2627 static int amdgpu_pmops_runtime_resume(struct device *dev) 2628 { 2629 struct pci_dev *pdev = to_pci_dev(dev); 2630 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2631 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2632 int ret; 2633 2634 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2635 return -EINVAL; 2636 2637 /* Avoids registers access if device is physically gone */ 2638 if (!pci_device_is_present(adev->pdev)) 2639 adev->no_hw_access = true; 2640 2641 if (amdgpu_device_supports_px(drm_dev)) { 2642 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2643 2644 /* Only need to handle PCI state in the driver for ATPX 2645 * PCI core handles it for _PR3. 2646 */ 2647 pci_set_power_state(pdev, PCI_D0); 2648 amdgpu_device_load_pci_state(pdev); 2649 ret = pci_enable_device(pdev); 2650 if (ret) 2651 return ret; 2652 pci_set_master(pdev); 2653 } else if (amdgpu_device_supports_boco(drm_dev)) { 2654 /* Only need to handle PCI state in the driver for ATPX 2655 * PCI core handles it for _PR3. 2656 */ 2657 pci_set_master(pdev); 2658 } else if (amdgpu_device_supports_baco(drm_dev)) { 2659 amdgpu_device_baco_exit(drm_dev); 2660 } 2661 ret = amdgpu_device_resume(drm_dev, false); 2662 if (ret) { 2663 if (amdgpu_device_supports_px(drm_dev)) 2664 pci_disable_device(pdev); 2665 return ret; 2666 } 2667 2668 if (amdgpu_device_supports_px(drm_dev)) 2669 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2670 adev->in_runpm = false; 2671 return 0; 2672 } 2673 2674 static int amdgpu_pmops_runtime_idle(struct device *dev) 2675 { 2676 struct drm_device *drm_dev = dev_get_drvdata(dev); 2677 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2678 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2679 int ret = 1; 2680 2681 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2682 pm_runtime_forbid(dev); 2683 return -EBUSY; 2684 } 2685 2686 ret = amdgpu_runtime_idle_check_display(dev); 2687 2688 pm_runtime_mark_last_busy(dev); 2689 pm_runtime_autosuspend(dev); 2690 return ret; 2691 } 2692 2693 long amdgpu_drm_ioctl(struct file *filp, 2694 unsigned int cmd, unsigned long arg) 2695 { 2696 struct drm_file *file_priv = filp->private_data; 2697 struct drm_device *dev; 2698 long ret; 2699 dev = file_priv->minor->dev; 2700 ret = pm_runtime_get_sync(dev->dev); 2701 if (ret < 0) 2702 goto out; 2703 2704 ret = drm_ioctl(filp, cmd, arg); 2705 2706 pm_runtime_mark_last_busy(dev->dev); 2707 out: 2708 pm_runtime_put_autosuspend(dev->dev); 2709 return ret; 2710 } 2711 2712 static const struct dev_pm_ops amdgpu_pm_ops = { 2713 .prepare = amdgpu_pmops_prepare, 2714 .complete = amdgpu_pmops_complete, 2715 .suspend = amdgpu_pmops_suspend, 2716 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2717 .resume = amdgpu_pmops_resume, 2718 .freeze = amdgpu_pmops_freeze, 2719 .thaw = amdgpu_pmops_thaw, 2720 .poweroff = amdgpu_pmops_poweroff, 2721 .restore = amdgpu_pmops_restore, 2722 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2723 .runtime_resume = amdgpu_pmops_runtime_resume, 2724 .runtime_idle = amdgpu_pmops_runtime_idle, 2725 }; 2726 2727 static int amdgpu_flush(struct file *f, fl_owner_t id) 2728 { 2729 struct drm_file *file_priv = f->private_data; 2730 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2731 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2732 2733 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2734 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2735 2736 return timeout >= 0 ? 0 : timeout; 2737 } 2738 2739 static const struct file_operations amdgpu_driver_kms_fops = { 2740 .owner = THIS_MODULE, 2741 .open = drm_open, 2742 .flush = amdgpu_flush, 2743 .release = drm_release, 2744 .unlocked_ioctl = amdgpu_drm_ioctl, 2745 .mmap = drm_gem_mmap, 2746 .poll = drm_poll, 2747 .read = drm_read, 2748 #ifdef CONFIG_COMPAT 2749 .compat_ioctl = amdgpu_kms_compat_ioctl, 2750 #endif 2751 #ifdef CONFIG_PROC_FS 2752 .show_fdinfo = amdgpu_show_fdinfo 2753 #endif 2754 }; 2755 2756 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2757 { 2758 struct drm_file *file; 2759 2760 if (!filp) 2761 return -EINVAL; 2762 2763 if (filp->f_op != &amdgpu_driver_kms_fops) { 2764 return -EINVAL; 2765 } 2766 2767 file = filp->private_data; 2768 *fpriv = file->driver_priv; 2769 return 0; 2770 } 2771 2772 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2773 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2774 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2775 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2776 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2777 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2778 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2779 /* KMS */ 2780 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2781 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2782 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2783 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2784 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2785 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2786 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2787 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2788 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2789 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2790 }; 2791 2792 static const struct drm_driver amdgpu_kms_driver = { 2793 .driver_features = 2794 DRIVER_ATOMIC | 2795 DRIVER_GEM | 2796 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2797 DRIVER_SYNCOBJ_TIMELINE, 2798 .open = amdgpu_driver_open_kms, 2799 .postclose = amdgpu_driver_postclose_kms, 2800 .lastclose = amdgpu_driver_lastclose_kms, 2801 .ioctls = amdgpu_ioctls_kms, 2802 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2803 .dumb_create = amdgpu_mode_dumb_create, 2804 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2805 .fops = &amdgpu_driver_kms_fops, 2806 .release = &amdgpu_driver_release_kms, 2807 2808 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2809 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2810 .gem_prime_import = amdgpu_gem_prime_import, 2811 .gem_prime_mmap = drm_gem_prime_mmap, 2812 2813 .name = DRIVER_NAME, 2814 .desc = DRIVER_DESC, 2815 .date = DRIVER_DATE, 2816 .major = KMS_DRIVER_MAJOR, 2817 .minor = KMS_DRIVER_MINOR, 2818 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2819 }; 2820 2821 static struct pci_error_handlers amdgpu_pci_err_handler = { 2822 .error_detected = amdgpu_pci_error_detected, 2823 .mmio_enabled = amdgpu_pci_mmio_enabled, 2824 .slot_reset = amdgpu_pci_slot_reset, 2825 .resume = amdgpu_pci_resume, 2826 }; 2827 2828 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2829 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2830 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2831 2832 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2833 &amdgpu_vram_mgr_attr_group, 2834 &amdgpu_gtt_mgr_attr_group, 2835 &amdgpu_vbios_version_attr_group, 2836 NULL, 2837 }; 2838 2839 2840 static struct pci_driver amdgpu_kms_pci_driver = { 2841 .name = DRIVER_NAME, 2842 .id_table = pciidlist, 2843 .probe = amdgpu_pci_probe, 2844 .remove = amdgpu_pci_remove, 2845 .shutdown = amdgpu_pci_shutdown, 2846 .driver.pm = &amdgpu_pm_ops, 2847 .err_handler = &amdgpu_pci_err_handler, 2848 .dev_groups = amdgpu_sysfs_groups, 2849 }; 2850 2851 static int __init amdgpu_init(void) 2852 { 2853 int r; 2854 2855 if (drm_firmware_drivers_only()) 2856 return -EINVAL; 2857 2858 r = amdgpu_sync_init(); 2859 if (r) 2860 goto error_sync; 2861 2862 r = amdgpu_fence_slab_init(); 2863 if (r) 2864 goto error_fence; 2865 2866 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2867 amdgpu_register_atpx_handler(); 2868 amdgpu_acpi_detect(); 2869 2870 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2871 amdgpu_amdkfd_init(); 2872 2873 /* let modprobe override vga console setting */ 2874 return pci_register_driver(&amdgpu_kms_pci_driver); 2875 2876 error_fence: 2877 amdgpu_sync_fini(); 2878 2879 error_sync: 2880 return r; 2881 } 2882 2883 static void __exit amdgpu_exit(void) 2884 { 2885 amdgpu_amdkfd_fini(); 2886 pci_unregister_driver(&amdgpu_kms_pci_driver); 2887 amdgpu_unregister_atpx_handler(); 2888 amdgpu_sync_fini(); 2889 amdgpu_fence_slab_fini(); 2890 mmu_notifier_synchronize(); 2891 } 2892 2893 module_init(amdgpu_init); 2894 module_exit(amdgpu_exit); 2895 2896 MODULE_AUTHOR(DRIVER_AUTHOR); 2897 MODULE_DESCRIPTION(DRIVER_DESC); 2898 MODULE_LICENSE("GPL and additional rights"); 2899