1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/fb.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 * * 3.46.0 - To enable hot plug amdgpu tests in libdrm 104 */ 105 #define KMS_DRIVER_MAJOR 3 106 #define KMS_DRIVER_MINOR 46 107 #define KMS_DRIVER_PATCHLEVEL 0 108 109 int amdgpu_vram_limit; 110 int amdgpu_vis_vram_limit; 111 int amdgpu_gart_size = -1; /* auto */ 112 int amdgpu_gtt_size = -1; /* auto */ 113 int amdgpu_moverate = -1; /* auto */ 114 int amdgpu_audio = -1; 115 int amdgpu_disp_priority; 116 int amdgpu_hw_i2c; 117 int amdgpu_pcie_gen2 = -1; 118 int amdgpu_msi = -1; 119 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 120 int amdgpu_dpm = -1; 121 int amdgpu_fw_load_type = -1; 122 int amdgpu_aspm = -1; 123 int amdgpu_runtime_pm = -1; 124 uint amdgpu_ip_block_mask = 0xffffffff; 125 int amdgpu_bapm = -1; 126 int amdgpu_deep_color; 127 int amdgpu_vm_size = -1; 128 int amdgpu_vm_fragment_size = -1; 129 int amdgpu_vm_block_size = -1; 130 int amdgpu_vm_fault_stop; 131 int amdgpu_vm_debug; 132 int amdgpu_vm_update_mode = -1; 133 int amdgpu_exp_hw_support; 134 int amdgpu_dc = -1; 135 int amdgpu_sched_jobs = 32; 136 int amdgpu_sched_hw_submission = 2; 137 uint amdgpu_pcie_gen_cap; 138 uint amdgpu_pcie_lane_cap; 139 u64 amdgpu_cg_mask = 0xffffffffffffffff; 140 uint amdgpu_pg_mask = 0xffffffff; 141 uint amdgpu_sdma_phase_quantum = 32; 142 char *amdgpu_disable_cu = NULL; 143 char *amdgpu_virtual_display = NULL; 144 145 /* 146 * OverDrive(bit 14) disabled by default 147 * GFX DCS(bit 19) disabled by default 148 */ 149 uint amdgpu_pp_feature_mask = 0xfff7bfff; 150 uint amdgpu_force_long_training; 151 int amdgpu_job_hang_limit; 152 int amdgpu_lbpw = -1; 153 int amdgpu_compute_multipipe = -1; 154 int amdgpu_gpu_recovery = -1; /* auto */ 155 int amdgpu_emu_mode; 156 uint amdgpu_smu_memory_pool_size; 157 int amdgpu_smu_pptable_id = -1; 158 /* 159 * FBC (bit 0) disabled by default 160 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 161 * - With this, for multiple monitors in sync(e.g. with the same model), 162 * mclk switching will be allowed. And the mclk will be not foced to the 163 * highest. That helps saving some idle power. 164 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 165 * PSR (bit 3) disabled by default 166 * EDP NO POWER SEQUENCING (bit 4) disabled by default 167 */ 168 uint amdgpu_dc_feature_mask = 2; 169 uint amdgpu_dc_debug_mask; 170 int amdgpu_async_gfx_ring = 1; 171 int amdgpu_mcbp; 172 int amdgpu_discovery = -1; 173 int amdgpu_mes; 174 int amdgpu_noretry = -1; 175 int amdgpu_force_asic_type = -1; 176 int amdgpu_tmz = -1; /* auto */ 177 int amdgpu_reset_method = -1; /* auto */ 178 int amdgpu_num_kcq = -1; 179 int amdgpu_smartshift_bias; 180 int amdgpu_use_xgmi_p2p = 1; 181 int amdgpu_vcnfw_log; 182 183 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 184 185 struct amdgpu_mgpu_info mgpu_info = { 186 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 187 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 188 mgpu_info.delayed_reset_work, 189 amdgpu_drv_delayed_reset_work_handler, 0), 190 }; 191 int amdgpu_ras_enable = -1; 192 uint amdgpu_ras_mask = 0xffffffff; 193 int amdgpu_bad_page_threshold = -1; 194 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 195 .timeout_fatal_disable = false, 196 .period = 0x0, /* default to 0x0 (timeout disable) */ 197 }; 198 199 /** 200 * DOC: vramlimit (int) 201 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 202 */ 203 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 204 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 205 206 /** 207 * DOC: vis_vramlimit (int) 208 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 209 */ 210 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 211 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 212 213 /** 214 * DOC: gartsize (uint) 215 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 216 */ 217 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 218 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 219 220 /** 221 * DOC: gttsize (int) 222 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 223 * otherwise 3/4 RAM size). 224 */ 225 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 226 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 227 228 /** 229 * DOC: moverate (int) 230 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 231 */ 232 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 233 module_param_named(moverate, amdgpu_moverate, int, 0600); 234 235 /** 236 * DOC: audio (int) 237 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 238 */ 239 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 240 module_param_named(audio, amdgpu_audio, int, 0444); 241 242 /** 243 * DOC: disp_priority (int) 244 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 245 */ 246 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 247 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 248 249 /** 250 * DOC: hw_i2c (int) 251 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 252 */ 253 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 254 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 255 256 /** 257 * DOC: pcie_gen2 (int) 258 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 259 */ 260 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 261 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 262 263 /** 264 * DOC: msi (int) 265 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 266 */ 267 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 268 module_param_named(msi, amdgpu_msi, int, 0444); 269 270 /** 271 * DOC: lockup_timeout (string) 272 * Set GPU scheduler timeout value in ms. 273 * 274 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 275 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 276 * to the default timeout. 277 * 278 * - With one value specified, the setting will apply to all non-compute jobs. 279 * - With multiple values specified, the first one will be for GFX. 280 * The second one is for Compute. The third and fourth ones are 281 * for SDMA and Video. 282 * 283 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 284 * jobs is 10000. The timeout for compute is 60000. 285 */ 286 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 287 "for passthrough or sriov, 10000 for all jobs." 288 " 0: keep default value. negative: infinity timeout), " 289 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 290 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 291 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 292 293 /** 294 * DOC: dpm (int) 295 * Override for dynamic power management setting 296 * (0 = disable, 1 = enable) 297 * The default is -1 (auto). 298 */ 299 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 300 module_param_named(dpm, amdgpu_dpm, int, 0444); 301 302 /** 303 * DOC: fw_load_type (int) 304 * Set different firmware loading type for debugging, if supported. 305 * Set to 0 to force direct loading if supported by the ASIC. Set 306 * to -1 to select the default loading mode for the ASIC, as defined 307 * by the driver. The default is -1 (auto). 308 */ 309 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)"); 310 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 311 312 /** 313 * DOC: aspm (int) 314 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 315 */ 316 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 317 module_param_named(aspm, amdgpu_aspm, int, 0444); 318 319 /** 320 * DOC: runpm (int) 321 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 322 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 323 * Setting the value to 0 disables this functionality. 324 */ 325 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 326 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 327 328 /** 329 * DOC: ip_block_mask (uint) 330 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 331 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 332 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 333 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 334 */ 335 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 336 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 337 338 /** 339 * DOC: bapm (int) 340 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 341 * The default -1 (auto, enabled) 342 */ 343 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 344 module_param_named(bapm, amdgpu_bapm, int, 0444); 345 346 /** 347 * DOC: deep_color (int) 348 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 349 */ 350 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 351 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 352 353 /** 354 * DOC: vm_size (int) 355 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 356 */ 357 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 358 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 359 360 /** 361 * DOC: vm_fragment_size (int) 362 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 363 */ 364 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 365 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 366 367 /** 368 * DOC: vm_block_size (int) 369 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 370 */ 371 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 372 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 373 374 /** 375 * DOC: vm_fault_stop (int) 376 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 377 */ 378 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 379 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 380 381 /** 382 * DOC: vm_debug (int) 383 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 384 */ 385 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 386 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 387 388 /** 389 * DOC: vm_update_mode (int) 390 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 391 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 392 */ 393 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 394 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 395 396 /** 397 * DOC: exp_hw_support (int) 398 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 399 */ 400 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 401 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 402 403 /** 404 * DOC: dc (int) 405 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 406 */ 407 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 408 module_param_named(dc, amdgpu_dc, int, 0444); 409 410 /** 411 * DOC: sched_jobs (int) 412 * Override the max number of jobs supported in the sw queue. The default is 32. 413 */ 414 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 415 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 416 417 /** 418 * DOC: sched_hw_submission (int) 419 * Override the max number of HW submissions. The default is 2. 420 */ 421 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 422 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 423 424 /** 425 * DOC: ppfeaturemask (hexint) 426 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 427 * The default is the current set of stable power features. 428 */ 429 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 430 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 431 432 /** 433 * DOC: forcelongtraining (uint) 434 * Force long memory training in resume. 435 * The default is zero, indicates short training in resume. 436 */ 437 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 438 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 439 440 /** 441 * DOC: pcie_gen_cap (uint) 442 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 443 * The default is 0 (automatic for each asic). 444 */ 445 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 446 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 447 448 /** 449 * DOC: pcie_lane_cap (uint) 450 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 451 * The default is 0 (automatic for each asic). 452 */ 453 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 454 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 455 456 /** 457 * DOC: cg_mask (ullong) 458 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 459 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 460 */ 461 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 462 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 463 464 /** 465 * DOC: pg_mask (uint) 466 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 467 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 468 */ 469 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 470 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 471 472 /** 473 * DOC: sdma_phase_quantum (uint) 474 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 475 */ 476 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 477 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 478 479 /** 480 * DOC: disable_cu (charp) 481 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 482 */ 483 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 484 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 485 486 /** 487 * DOC: virtual_display (charp) 488 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 489 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 490 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 491 * device at 26:00.0. The default is NULL. 492 */ 493 MODULE_PARM_DESC(virtual_display, 494 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 495 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 496 497 /** 498 * DOC: job_hang_limit (int) 499 * Set how much time allow a job hang and not drop it. The default is 0. 500 */ 501 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 502 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 503 504 /** 505 * DOC: lbpw (int) 506 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 507 */ 508 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 509 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 510 511 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 512 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 513 514 /** 515 * DOC: gpu_recovery (int) 516 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 517 */ 518 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 519 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 520 521 /** 522 * DOC: emu_mode (int) 523 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 524 */ 525 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 526 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 527 528 /** 529 * DOC: ras_enable (int) 530 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 531 */ 532 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 533 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 534 535 /** 536 * DOC: ras_mask (uint) 537 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 538 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 539 */ 540 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 541 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 542 543 /** 544 * DOC: timeout_fatal_disable (bool) 545 * Disable Watchdog timeout fatal error event 546 */ 547 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 548 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 549 550 /** 551 * DOC: timeout_period (uint) 552 * Modify the watchdog timeout max_cycles as (1 << period) 553 */ 554 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 555 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 556 557 /** 558 * DOC: si_support (int) 559 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 560 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 561 * otherwise using amdgpu driver. 562 */ 563 #ifdef CONFIG_DRM_AMDGPU_SI 564 565 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 566 int amdgpu_si_support = 0; 567 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 568 #else 569 int amdgpu_si_support = 1; 570 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 571 #endif 572 573 module_param_named(si_support, amdgpu_si_support, int, 0444); 574 #endif 575 576 /** 577 * DOC: cik_support (int) 578 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 580 * otherwise using amdgpu driver. 581 */ 582 #ifdef CONFIG_DRM_AMDGPU_CIK 583 584 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 585 int amdgpu_cik_support = 0; 586 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 587 #else 588 int amdgpu_cik_support = 1; 589 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 590 #endif 591 592 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 593 #endif 594 595 /** 596 * DOC: smu_memory_pool_size (uint) 597 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 598 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 599 */ 600 MODULE_PARM_DESC(smu_memory_pool_size, 601 "reserve gtt for smu debug usage, 0 = disable," 602 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 603 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 604 605 /** 606 * DOC: async_gfx_ring (int) 607 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 608 */ 609 MODULE_PARM_DESC(async_gfx_ring, 610 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 611 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 612 613 /** 614 * DOC: mcbp (int) 615 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 616 */ 617 MODULE_PARM_DESC(mcbp, 618 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 619 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 620 621 /** 622 * DOC: discovery (int) 623 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 624 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 625 */ 626 MODULE_PARM_DESC(discovery, 627 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 628 module_param_named(discovery, amdgpu_discovery, int, 0444); 629 630 /** 631 * DOC: mes (int) 632 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 633 * (0 = disabled (default), 1 = enabled) 634 */ 635 MODULE_PARM_DESC(mes, 636 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 637 module_param_named(mes, amdgpu_mes, int, 0444); 638 639 /** 640 * DOC: noretry (int) 641 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 642 * do not support per-process XNACK this also disables retry page faults. 643 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 644 */ 645 MODULE_PARM_DESC(noretry, 646 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 647 module_param_named(noretry, amdgpu_noretry, int, 0644); 648 649 /** 650 * DOC: force_asic_type (int) 651 * A non negative value used to specify the asic type for all supported GPUs. 652 */ 653 MODULE_PARM_DESC(force_asic_type, 654 "A non negative value used to specify the asic type for all supported GPUs"); 655 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 656 657 /** 658 * DOC: use_xgmi_p2p (int) 659 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 660 */ 661 MODULE_PARM_DESC(use_xgmi_p2p, 662 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 663 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 664 665 666 #ifdef CONFIG_HSA_AMD 667 /** 668 * DOC: sched_policy (int) 669 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 670 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 671 * assigns queues to HQDs. 672 */ 673 int sched_policy = KFD_SCHED_POLICY_HWS; 674 module_param(sched_policy, int, 0444); 675 MODULE_PARM_DESC(sched_policy, 676 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 677 678 /** 679 * DOC: hws_max_conc_proc (int) 680 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 681 * number of VMIDs assigned to the HWS, which is also the default. 682 */ 683 int hws_max_conc_proc = -1; 684 module_param(hws_max_conc_proc, int, 0444); 685 MODULE_PARM_DESC(hws_max_conc_proc, 686 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 687 688 /** 689 * DOC: cwsr_enable (int) 690 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 691 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 692 * disables it. 693 */ 694 int cwsr_enable = 1; 695 module_param(cwsr_enable, int, 0444); 696 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 697 698 /** 699 * DOC: max_num_of_queues_per_device (int) 700 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 701 * is 4096. 702 */ 703 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 704 module_param(max_num_of_queues_per_device, int, 0444); 705 MODULE_PARM_DESC(max_num_of_queues_per_device, 706 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 707 708 /** 709 * DOC: send_sigterm (int) 710 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 711 * but just print errors on dmesg. Setting 1 enables sending sigterm. 712 */ 713 int send_sigterm; 714 module_param(send_sigterm, int, 0444); 715 MODULE_PARM_DESC(send_sigterm, 716 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 717 718 /** 719 * DOC: debug_largebar (int) 720 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 721 * system. This limits the VRAM size reported to ROCm applications to the visible 722 * size, usually 256MB. 723 * Default value is 0, diabled. 724 */ 725 int debug_largebar; 726 module_param(debug_largebar, int, 0444); 727 MODULE_PARM_DESC(debug_largebar, 728 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 729 730 /** 731 * DOC: ignore_crat (int) 732 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 733 * table to get information about AMD APUs. This option can serve as a workaround on 734 * systems with a broken CRAT table. 735 * 736 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 737 * whether use CRAT) 738 */ 739 int ignore_crat; 740 module_param(ignore_crat, int, 0444); 741 MODULE_PARM_DESC(ignore_crat, 742 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 743 744 /** 745 * DOC: halt_if_hws_hang (int) 746 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 747 * Setting 1 enables halt on hang. 748 */ 749 int halt_if_hws_hang; 750 module_param(halt_if_hws_hang, int, 0644); 751 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 752 753 /** 754 * DOC: hws_gws_support(bool) 755 * Assume that HWS supports GWS barriers regardless of what firmware version 756 * check says. Default value: false (rely on MEC2 firmware version check). 757 */ 758 bool hws_gws_support; 759 module_param(hws_gws_support, bool, 0444); 760 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 761 762 /** 763 * DOC: queue_preemption_timeout_ms (int) 764 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 765 */ 766 int queue_preemption_timeout_ms = 9000; 767 module_param(queue_preemption_timeout_ms, int, 0644); 768 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 769 770 /** 771 * DOC: debug_evictions(bool) 772 * Enable extra debug messages to help determine the cause of evictions 773 */ 774 bool debug_evictions; 775 module_param(debug_evictions, bool, 0644); 776 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 777 778 /** 779 * DOC: no_system_mem_limit(bool) 780 * Disable system memory limit, to support multiple process shared memory 781 */ 782 bool no_system_mem_limit; 783 module_param(no_system_mem_limit, bool, 0644); 784 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 785 786 /** 787 * DOC: no_queue_eviction_on_vm_fault (int) 788 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 789 */ 790 int amdgpu_no_queue_eviction_on_vm_fault = 0; 791 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 792 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 793 #endif 794 795 /** 796 * DOC: dcfeaturemask (uint) 797 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 798 * The default is the current set of stable display features. 799 */ 800 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 801 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 802 803 /** 804 * DOC: dcdebugmask (uint) 805 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 806 */ 807 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 808 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 809 810 /** 811 * DOC: abmlevel (uint) 812 * Override the default ABM (Adaptive Backlight Management) level used for DC 813 * enabled hardware. Requires DMCU to be supported and loaded. 814 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 815 * default. Values 1-4 control the maximum allowable brightness reduction via 816 * the ABM algorithm, with 1 being the least reduction and 4 being the most 817 * reduction. 818 * 819 * Defaults to 0, or disabled. Userspace can still override this level later 820 * after boot. 821 */ 822 uint amdgpu_dm_abm_level; 823 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 824 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 825 826 int amdgpu_backlight = -1; 827 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 828 module_param_named(backlight, amdgpu_backlight, bint, 0444); 829 830 /** 831 * DOC: tmz (int) 832 * Trusted Memory Zone (TMZ) is a method to protect data being written 833 * to or read from memory. 834 * 835 * The default value: 0 (off). TODO: change to auto till it is completed. 836 */ 837 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 838 module_param_named(tmz, amdgpu_tmz, int, 0444); 839 840 /** 841 * DOC: reset_method (int) 842 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 843 */ 844 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 845 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 846 847 /** 848 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 849 * threshold value of faulty pages detected by RAS ECC, which may 850 * result in the GPU entering bad status when the number of total 851 * faulty pages by ECC exceeds the threshold value. 852 */ 853 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 854 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 855 856 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 857 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 858 859 /** 860 * DOC: vcnfw_log (int) 861 * Enable vcnfw log output for debugging, the default is disabled. 862 */ 863 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 864 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 865 866 /** 867 * DOC: smu_pptable_id (int) 868 * Used to override pptable id. id = 0 use VBIOS pptable. 869 * id > 0 use the soft pptable with specicfied id. 870 */ 871 MODULE_PARM_DESC(smu_pptable_id, 872 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 873 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 874 875 /* These devices are not supported by amdgpu. 876 * They are supported by the mach64, r128, radeon drivers 877 */ 878 static const u16 amdgpu_unsupported_pciidlist[] = { 879 /* mach64 */ 880 0x4354, 881 0x4358, 882 0x4554, 883 0x4742, 884 0x4744, 885 0x4749, 886 0x474C, 887 0x474D, 888 0x474E, 889 0x474F, 890 0x4750, 891 0x4751, 892 0x4752, 893 0x4753, 894 0x4754, 895 0x4755, 896 0x4756, 897 0x4757, 898 0x4758, 899 0x4759, 900 0x475A, 901 0x4C42, 902 0x4C44, 903 0x4C47, 904 0x4C49, 905 0x4C4D, 906 0x4C4E, 907 0x4C50, 908 0x4C51, 909 0x4C52, 910 0x4C53, 911 0x5654, 912 0x5655, 913 0x5656, 914 /* r128 */ 915 0x4c45, 916 0x4c46, 917 0x4d46, 918 0x4d4c, 919 0x5041, 920 0x5042, 921 0x5043, 922 0x5044, 923 0x5045, 924 0x5046, 925 0x5047, 926 0x5048, 927 0x5049, 928 0x504A, 929 0x504B, 930 0x504C, 931 0x504D, 932 0x504E, 933 0x504F, 934 0x5050, 935 0x5051, 936 0x5052, 937 0x5053, 938 0x5054, 939 0x5055, 940 0x5056, 941 0x5057, 942 0x5058, 943 0x5245, 944 0x5246, 945 0x5247, 946 0x524b, 947 0x524c, 948 0x534d, 949 0x5446, 950 0x544C, 951 0x5452, 952 /* radeon */ 953 0x3150, 954 0x3151, 955 0x3152, 956 0x3154, 957 0x3155, 958 0x3E50, 959 0x3E54, 960 0x4136, 961 0x4137, 962 0x4144, 963 0x4145, 964 0x4146, 965 0x4147, 966 0x4148, 967 0x4149, 968 0x414A, 969 0x414B, 970 0x4150, 971 0x4151, 972 0x4152, 973 0x4153, 974 0x4154, 975 0x4155, 976 0x4156, 977 0x4237, 978 0x4242, 979 0x4336, 980 0x4337, 981 0x4437, 982 0x4966, 983 0x4967, 984 0x4A48, 985 0x4A49, 986 0x4A4A, 987 0x4A4B, 988 0x4A4C, 989 0x4A4D, 990 0x4A4E, 991 0x4A4F, 992 0x4A50, 993 0x4A54, 994 0x4B48, 995 0x4B49, 996 0x4B4A, 997 0x4B4B, 998 0x4B4C, 999 0x4C57, 1000 0x4C58, 1001 0x4C59, 1002 0x4C5A, 1003 0x4C64, 1004 0x4C66, 1005 0x4C67, 1006 0x4E44, 1007 0x4E45, 1008 0x4E46, 1009 0x4E47, 1010 0x4E48, 1011 0x4E49, 1012 0x4E4A, 1013 0x4E4B, 1014 0x4E50, 1015 0x4E51, 1016 0x4E52, 1017 0x4E53, 1018 0x4E54, 1019 0x4E56, 1020 0x5144, 1021 0x5145, 1022 0x5146, 1023 0x5147, 1024 0x5148, 1025 0x514C, 1026 0x514D, 1027 0x5157, 1028 0x5158, 1029 0x5159, 1030 0x515A, 1031 0x515E, 1032 0x5460, 1033 0x5462, 1034 0x5464, 1035 0x5548, 1036 0x5549, 1037 0x554A, 1038 0x554B, 1039 0x554C, 1040 0x554D, 1041 0x554E, 1042 0x554F, 1043 0x5550, 1044 0x5551, 1045 0x5552, 1046 0x5554, 1047 0x564A, 1048 0x564B, 1049 0x564F, 1050 0x5652, 1051 0x5653, 1052 0x5657, 1053 0x5834, 1054 0x5835, 1055 0x5954, 1056 0x5955, 1057 0x5974, 1058 0x5975, 1059 0x5960, 1060 0x5961, 1061 0x5962, 1062 0x5964, 1063 0x5965, 1064 0x5969, 1065 0x5a41, 1066 0x5a42, 1067 0x5a61, 1068 0x5a62, 1069 0x5b60, 1070 0x5b62, 1071 0x5b63, 1072 0x5b64, 1073 0x5b65, 1074 0x5c61, 1075 0x5c63, 1076 0x5d48, 1077 0x5d49, 1078 0x5d4a, 1079 0x5d4c, 1080 0x5d4d, 1081 0x5d4e, 1082 0x5d4f, 1083 0x5d50, 1084 0x5d52, 1085 0x5d57, 1086 0x5e48, 1087 0x5e4a, 1088 0x5e4b, 1089 0x5e4c, 1090 0x5e4d, 1091 0x5e4f, 1092 0x6700, 1093 0x6701, 1094 0x6702, 1095 0x6703, 1096 0x6704, 1097 0x6705, 1098 0x6706, 1099 0x6707, 1100 0x6708, 1101 0x6709, 1102 0x6718, 1103 0x6719, 1104 0x671c, 1105 0x671d, 1106 0x671f, 1107 0x6720, 1108 0x6721, 1109 0x6722, 1110 0x6723, 1111 0x6724, 1112 0x6725, 1113 0x6726, 1114 0x6727, 1115 0x6728, 1116 0x6729, 1117 0x6738, 1118 0x6739, 1119 0x673e, 1120 0x6740, 1121 0x6741, 1122 0x6742, 1123 0x6743, 1124 0x6744, 1125 0x6745, 1126 0x6746, 1127 0x6747, 1128 0x6748, 1129 0x6749, 1130 0x674A, 1131 0x6750, 1132 0x6751, 1133 0x6758, 1134 0x6759, 1135 0x675B, 1136 0x675D, 1137 0x675F, 1138 0x6760, 1139 0x6761, 1140 0x6762, 1141 0x6763, 1142 0x6764, 1143 0x6765, 1144 0x6766, 1145 0x6767, 1146 0x6768, 1147 0x6770, 1148 0x6771, 1149 0x6772, 1150 0x6778, 1151 0x6779, 1152 0x677B, 1153 0x6840, 1154 0x6841, 1155 0x6842, 1156 0x6843, 1157 0x6849, 1158 0x684C, 1159 0x6850, 1160 0x6858, 1161 0x6859, 1162 0x6880, 1163 0x6888, 1164 0x6889, 1165 0x688A, 1166 0x688C, 1167 0x688D, 1168 0x6898, 1169 0x6899, 1170 0x689b, 1171 0x689c, 1172 0x689d, 1173 0x689e, 1174 0x68a0, 1175 0x68a1, 1176 0x68a8, 1177 0x68a9, 1178 0x68b0, 1179 0x68b8, 1180 0x68b9, 1181 0x68ba, 1182 0x68be, 1183 0x68bf, 1184 0x68c0, 1185 0x68c1, 1186 0x68c7, 1187 0x68c8, 1188 0x68c9, 1189 0x68d8, 1190 0x68d9, 1191 0x68da, 1192 0x68de, 1193 0x68e0, 1194 0x68e1, 1195 0x68e4, 1196 0x68e5, 1197 0x68e8, 1198 0x68e9, 1199 0x68f1, 1200 0x68f2, 1201 0x68f8, 1202 0x68f9, 1203 0x68fa, 1204 0x68fe, 1205 0x7100, 1206 0x7101, 1207 0x7102, 1208 0x7103, 1209 0x7104, 1210 0x7105, 1211 0x7106, 1212 0x7108, 1213 0x7109, 1214 0x710A, 1215 0x710B, 1216 0x710C, 1217 0x710E, 1218 0x710F, 1219 0x7140, 1220 0x7141, 1221 0x7142, 1222 0x7143, 1223 0x7144, 1224 0x7145, 1225 0x7146, 1226 0x7147, 1227 0x7149, 1228 0x714A, 1229 0x714B, 1230 0x714C, 1231 0x714D, 1232 0x714E, 1233 0x714F, 1234 0x7151, 1235 0x7152, 1236 0x7153, 1237 0x715E, 1238 0x715F, 1239 0x7180, 1240 0x7181, 1241 0x7183, 1242 0x7186, 1243 0x7187, 1244 0x7188, 1245 0x718A, 1246 0x718B, 1247 0x718C, 1248 0x718D, 1249 0x718F, 1250 0x7193, 1251 0x7196, 1252 0x719B, 1253 0x719F, 1254 0x71C0, 1255 0x71C1, 1256 0x71C2, 1257 0x71C3, 1258 0x71C4, 1259 0x71C5, 1260 0x71C6, 1261 0x71C7, 1262 0x71CD, 1263 0x71CE, 1264 0x71D2, 1265 0x71D4, 1266 0x71D5, 1267 0x71D6, 1268 0x71DA, 1269 0x71DE, 1270 0x7200, 1271 0x7210, 1272 0x7211, 1273 0x7240, 1274 0x7243, 1275 0x7244, 1276 0x7245, 1277 0x7246, 1278 0x7247, 1279 0x7248, 1280 0x7249, 1281 0x724A, 1282 0x724B, 1283 0x724C, 1284 0x724D, 1285 0x724E, 1286 0x724F, 1287 0x7280, 1288 0x7281, 1289 0x7283, 1290 0x7284, 1291 0x7287, 1292 0x7288, 1293 0x7289, 1294 0x728B, 1295 0x728C, 1296 0x7290, 1297 0x7291, 1298 0x7293, 1299 0x7297, 1300 0x7834, 1301 0x7835, 1302 0x791e, 1303 0x791f, 1304 0x793f, 1305 0x7941, 1306 0x7942, 1307 0x796c, 1308 0x796d, 1309 0x796e, 1310 0x796f, 1311 0x9400, 1312 0x9401, 1313 0x9402, 1314 0x9403, 1315 0x9405, 1316 0x940A, 1317 0x940B, 1318 0x940F, 1319 0x94A0, 1320 0x94A1, 1321 0x94A3, 1322 0x94B1, 1323 0x94B3, 1324 0x94B4, 1325 0x94B5, 1326 0x94B9, 1327 0x9440, 1328 0x9441, 1329 0x9442, 1330 0x9443, 1331 0x9444, 1332 0x9446, 1333 0x944A, 1334 0x944B, 1335 0x944C, 1336 0x944E, 1337 0x9450, 1338 0x9452, 1339 0x9456, 1340 0x945A, 1341 0x945B, 1342 0x945E, 1343 0x9460, 1344 0x9462, 1345 0x946A, 1346 0x946B, 1347 0x947A, 1348 0x947B, 1349 0x9480, 1350 0x9487, 1351 0x9488, 1352 0x9489, 1353 0x948A, 1354 0x948F, 1355 0x9490, 1356 0x9491, 1357 0x9495, 1358 0x9498, 1359 0x949C, 1360 0x949E, 1361 0x949F, 1362 0x94C0, 1363 0x94C1, 1364 0x94C3, 1365 0x94C4, 1366 0x94C5, 1367 0x94C6, 1368 0x94C7, 1369 0x94C8, 1370 0x94C9, 1371 0x94CB, 1372 0x94CC, 1373 0x94CD, 1374 0x9500, 1375 0x9501, 1376 0x9504, 1377 0x9505, 1378 0x9506, 1379 0x9507, 1380 0x9508, 1381 0x9509, 1382 0x950F, 1383 0x9511, 1384 0x9515, 1385 0x9517, 1386 0x9519, 1387 0x9540, 1388 0x9541, 1389 0x9542, 1390 0x954E, 1391 0x954F, 1392 0x9552, 1393 0x9553, 1394 0x9555, 1395 0x9557, 1396 0x955f, 1397 0x9580, 1398 0x9581, 1399 0x9583, 1400 0x9586, 1401 0x9587, 1402 0x9588, 1403 0x9589, 1404 0x958A, 1405 0x958B, 1406 0x958C, 1407 0x958D, 1408 0x958E, 1409 0x958F, 1410 0x9590, 1411 0x9591, 1412 0x9593, 1413 0x9595, 1414 0x9596, 1415 0x9597, 1416 0x9598, 1417 0x9599, 1418 0x959B, 1419 0x95C0, 1420 0x95C2, 1421 0x95C4, 1422 0x95C5, 1423 0x95C6, 1424 0x95C7, 1425 0x95C9, 1426 0x95CC, 1427 0x95CD, 1428 0x95CE, 1429 0x95CF, 1430 0x9610, 1431 0x9611, 1432 0x9612, 1433 0x9613, 1434 0x9614, 1435 0x9615, 1436 0x9616, 1437 0x9640, 1438 0x9641, 1439 0x9642, 1440 0x9643, 1441 0x9644, 1442 0x9645, 1443 0x9647, 1444 0x9648, 1445 0x9649, 1446 0x964a, 1447 0x964b, 1448 0x964c, 1449 0x964e, 1450 0x964f, 1451 0x9710, 1452 0x9711, 1453 0x9712, 1454 0x9713, 1455 0x9714, 1456 0x9715, 1457 0x9802, 1458 0x9803, 1459 0x9804, 1460 0x9805, 1461 0x9806, 1462 0x9807, 1463 0x9808, 1464 0x9809, 1465 0x980A, 1466 0x9900, 1467 0x9901, 1468 0x9903, 1469 0x9904, 1470 0x9905, 1471 0x9906, 1472 0x9907, 1473 0x9908, 1474 0x9909, 1475 0x990A, 1476 0x990B, 1477 0x990C, 1478 0x990D, 1479 0x990E, 1480 0x990F, 1481 0x9910, 1482 0x9913, 1483 0x9917, 1484 0x9918, 1485 0x9919, 1486 0x9990, 1487 0x9991, 1488 0x9992, 1489 0x9993, 1490 0x9994, 1491 0x9995, 1492 0x9996, 1493 0x9997, 1494 0x9998, 1495 0x9999, 1496 0x999A, 1497 0x999B, 1498 0x999C, 1499 0x999D, 1500 0x99A0, 1501 0x99A2, 1502 0x99A4, 1503 /* radeon secondary ids */ 1504 0x3171, 1505 0x3e70, 1506 0x4164, 1507 0x4165, 1508 0x4166, 1509 0x4168, 1510 0x4170, 1511 0x4171, 1512 0x4172, 1513 0x4173, 1514 0x496e, 1515 0x4a69, 1516 0x4a6a, 1517 0x4a6b, 1518 0x4a70, 1519 0x4a74, 1520 0x4b69, 1521 0x4b6b, 1522 0x4b6c, 1523 0x4c6e, 1524 0x4e64, 1525 0x4e65, 1526 0x4e66, 1527 0x4e67, 1528 0x4e68, 1529 0x4e69, 1530 0x4e6a, 1531 0x4e71, 1532 0x4f73, 1533 0x5569, 1534 0x556b, 1535 0x556d, 1536 0x556f, 1537 0x5571, 1538 0x5854, 1539 0x5874, 1540 0x5940, 1541 0x5941, 1542 0x5b72, 1543 0x5b73, 1544 0x5b74, 1545 0x5b75, 1546 0x5d44, 1547 0x5d45, 1548 0x5d6d, 1549 0x5d6f, 1550 0x5d72, 1551 0x5d77, 1552 0x5e6b, 1553 0x5e6d, 1554 0x7120, 1555 0x7124, 1556 0x7129, 1557 0x712e, 1558 0x712f, 1559 0x7162, 1560 0x7163, 1561 0x7166, 1562 0x7167, 1563 0x7172, 1564 0x7173, 1565 0x71a0, 1566 0x71a1, 1567 0x71a3, 1568 0x71a7, 1569 0x71bb, 1570 0x71e0, 1571 0x71e1, 1572 0x71e2, 1573 0x71e6, 1574 0x71e7, 1575 0x71f2, 1576 0x7269, 1577 0x726b, 1578 0x726e, 1579 0x72a0, 1580 0x72a8, 1581 0x72b1, 1582 0x72b3, 1583 0x793f, 1584 }; 1585 1586 static const struct pci_device_id pciidlist[] = { 1587 #ifdef CONFIG_DRM_AMDGPU_SI 1588 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1589 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1590 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1591 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1592 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1593 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1594 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1595 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1596 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1597 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1598 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1599 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1600 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1601 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1602 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1603 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1604 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1605 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1606 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1607 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1608 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1609 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1610 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1611 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1612 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1613 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1614 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1615 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1616 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1617 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1618 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1619 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1620 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1621 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1622 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1623 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1624 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1625 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1626 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1627 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1630 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1631 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1632 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1633 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1634 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1635 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1636 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1637 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1638 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1639 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1640 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1641 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1642 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1643 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1644 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1647 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1648 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1649 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1650 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1651 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1652 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1653 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1654 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1658 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1659 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1660 #endif 1661 #ifdef CONFIG_DRM_AMDGPU_CIK 1662 /* Kaveri */ 1663 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1664 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1665 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1666 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1667 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1668 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1669 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1670 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1671 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1672 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1673 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1674 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1675 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1676 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1677 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1678 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1679 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1680 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1681 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1682 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1683 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1684 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1685 /* Bonaire */ 1686 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1689 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1690 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1691 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1692 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1693 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1694 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1695 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1696 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1697 /* Hawaii */ 1698 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1699 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1700 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1701 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1702 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1703 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1704 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1705 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1706 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1707 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1708 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1709 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1710 /* Kabini */ 1711 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1713 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1714 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1715 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1716 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1717 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1718 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1719 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1720 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1721 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1722 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1723 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1724 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1725 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1726 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1727 /* mullins */ 1728 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1729 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1730 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1731 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1733 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1735 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1736 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1737 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1743 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1744 #endif 1745 /* topaz */ 1746 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1747 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1748 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1749 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1750 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1751 /* tonga */ 1752 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1753 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1754 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1755 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1756 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1757 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1758 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1759 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1760 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1761 /* fiji */ 1762 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1763 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1764 /* carrizo */ 1765 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1766 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1767 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1768 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1769 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1770 /* stoney */ 1771 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1772 /* Polaris11 */ 1773 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1774 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1775 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1776 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1777 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1778 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1779 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1780 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1781 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1782 /* Polaris10 */ 1783 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1784 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1785 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1786 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1787 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1788 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1789 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1790 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1791 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1792 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1793 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1794 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1795 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1796 /* Polaris12 */ 1797 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1798 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1799 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1800 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1801 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1802 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1803 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1804 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1805 /* VEGAM */ 1806 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1807 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1808 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1809 /* Vega 10 */ 1810 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1811 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1812 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1813 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1814 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1815 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1816 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1817 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1818 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1819 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1820 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1821 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1822 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1823 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1824 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1825 /* Vega 12 */ 1826 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1827 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1828 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1829 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1830 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1831 /* Vega 20 */ 1832 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1833 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1834 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1835 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1836 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1837 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1838 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1839 /* Raven */ 1840 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1841 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1842 /* Arcturus */ 1843 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1844 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1845 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1846 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1847 /* Navi10 */ 1848 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1849 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1850 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1851 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1852 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1853 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1854 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1855 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1856 /* Navi14 */ 1857 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1858 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1859 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1860 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1861 1862 /* Renoir */ 1863 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1864 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1865 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1866 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1867 1868 /* Navi12 */ 1869 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1870 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1871 1872 /* Sienna_Cichlid */ 1873 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1874 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1875 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1876 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1877 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1878 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1879 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1880 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1881 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1882 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1883 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1884 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1885 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1886 1887 /* Van Gogh */ 1888 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1889 1890 /* Yellow Carp */ 1891 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1892 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1893 1894 /* Navy_Flounder */ 1895 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1896 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1897 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1898 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1899 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1900 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1901 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1902 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1903 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1904 1905 /* DIMGREY_CAVEFISH */ 1906 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1907 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1908 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1909 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1910 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1911 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1912 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1913 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1914 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1915 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1916 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1917 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1918 1919 /* Aldebaran */ 1920 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1921 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1922 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1923 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1924 1925 /* CYAN_SKILLFISH */ 1926 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1927 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1928 1929 /* BEIGE_GOBY */ 1930 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1931 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1932 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1933 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1934 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1935 1936 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1937 .class = PCI_CLASS_DISPLAY_VGA << 8, 1938 .class_mask = 0xffffff, 1939 .driver_data = CHIP_IP_DISCOVERY }, 1940 1941 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1942 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1943 .class_mask = 0xffffff, 1944 .driver_data = CHIP_IP_DISCOVERY }, 1945 1946 {0, 0, 0} 1947 }; 1948 1949 MODULE_DEVICE_TABLE(pci, pciidlist); 1950 1951 static const struct drm_driver amdgpu_kms_driver; 1952 1953 static bool amdgpu_is_fw_framebuffer(resource_size_t base, 1954 resource_size_t size) 1955 { 1956 bool found = false; 1957 #if IS_REACHABLE(CONFIG_FB) 1958 struct apertures_struct *a; 1959 1960 a = alloc_apertures(1); 1961 if (!a) 1962 return false; 1963 1964 a->ranges[0].base = base; 1965 a->ranges[0].size = size; 1966 1967 found = is_firmware_framebuffer(a); 1968 kfree(a); 1969 #endif 1970 return found; 1971 } 1972 1973 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1974 { 1975 struct pci_dev *p = NULL; 1976 int i; 1977 1978 /* 0 - GPU 1979 * 1 - audio 1980 * 2 - USB 1981 * 3 - UCSI 1982 */ 1983 for (i = 1; i < 4; i++) { 1984 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1985 adev->pdev->bus->number, i); 1986 if (p) { 1987 pm_runtime_get_sync(&p->dev); 1988 pm_runtime_mark_last_busy(&p->dev); 1989 pm_runtime_put_autosuspend(&p->dev); 1990 pci_dev_put(p); 1991 } 1992 } 1993 } 1994 1995 static int amdgpu_pci_probe(struct pci_dev *pdev, 1996 const struct pci_device_id *ent) 1997 { 1998 struct drm_device *ddev; 1999 struct amdgpu_device *adev; 2000 unsigned long flags = ent->driver_data; 2001 int ret, retry = 0, i; 2002 bool supports_atomic = false; 2003 bool is_fw_fb; 2004 resource_size_t base, size; 2005 2006 /* skip devices which are owned by radeon */ 2007 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2008 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2009 return -ENODEV; 2010 } 2011 2012 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2013 amdgpu_aspm = 0; 2014 2015 if (amdgpu_virtual_display || 2016 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2017 supports_atomic = true; 2018 2019 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2020 DRM_INFO("This hardware requires experimental hardware support.\n" 2021 "See modparam exp_hw_support\n"); 2022 return -ENODEV; 2023 } 2024 2025 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2026 * however, SME requires an indirect IOMMU mapping because the encryption 2027 * bit is beyond the DMA mask of the chip. 2028 */ 2029 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2030 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2031 dev_info(&pdev->dev, 2032 "SME is not compatible with RAVEN\n"); 2033 return -ENOTSUPP; 2034 } 2035 2036 #ifdef CONFIG_DRM_AMDGPU_SI 2037 if (!amdgpu_si_support) { 2038 switch (flags & AMD_ASIC_MASK) { 2039 case CHIP_TAHITI: 2040 case CHIP_PITCAIRN: 2041 case CHIP_VERDE: 2042 case CHIP_OLAND: 2043 case CHIP_HAINAN: 2044 dev_info(&pdev->dev, 2045 "SI support provided by radeon.\n"); 2046 dev_info(&pdev->dev, 2047 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2048 ); 2049 return -ENODEV; 2050 } 2051 } 2052 #endif 2053 #ifdef CONFIG_DRM_AMDGPU_CIK 2054 if (!amdgpu_cik_support) { 2055 switch (flags & AMD_ASIC_MASK) { 2056 case CHIP_KAVERI: 2057 case CHIP_BONAIRE: 2058 case CHIP_HAWAII: 2059 case CHIP_KABINI: 2060 case CHIP_MULLINS: 2061 dev_info(&pdev->dev, 2062 "CIK support provided by radeon.\n"); 2063 dev_info(&pdev->dev, 2064 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2065 ); 2066 return -ENODEV; 2067 } 2068 } 2069 #endif 2070 2071 base = pci_resource_start(pdev, 0); 2072 size = pci_resource_len(pdev, 0); 2073 is_fw_fb = amdgpu_is_fw_framebuffer(base, size); 2074 2075 /* Get rid of things like offb */ 2076 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2077 if (ret) 2078 return ret; 2079 2080 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2081 if (IS_ERR(adev)) 2082 return PTR_ERR(adev); 2083 2084 adev->dev = &pdev->dev; 2085 adev->pdev = pdev; 2086 ddev = adev_to_drm(adev); 2087 adev->is_fw_fb = is_fw_fb; 2088 2089 if (!supports_atomic) 2090 ddev->driver_features &= ~DRIVER_ATOMIC; 2091 2092 ret = pci_enable_device(pdev); 2093 if (ret) 2094 return ret; 2095 2096 pci_set_drvdata(pdev, ddev); 2097 2098 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2099 if (ret) 2100 goto err_pci; 2101 2102 retry_init: 2103 ret = drm_dev_register(ddev, ent->driver_data); 2104 if (ret == -EAGAIN && ++retry <= 3) { 2105 DRM_INFO("retry init %d\n", retry); 2106 /* Don't request EX mode too frequently which is attacking */ 2107 msleep(5000); 2108 goto retry_init; 2109 } else if (ret) { 2110 goto err_pci; 2111 } 2112 2113 /* 2114 * 1. don't init fbdev on hw without DCE 2115 * 2. don't init fbdev if there are no connectors 2116 */ 2117 if (adev->mode_info.mode_config_initialized && 2118 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2119 /* select 8 bpp console on low vram cards */ 2120 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2121 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2122 else 2123 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2124 } 2125 2126 ret = amdgpu_debugfs_init(adev); 2127 if (ret) 2128 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2129 2130 if (adev->runpm) { 2131 /* only need to skip on ATPX */ 2132 if (amdgpu_device_supports_px(ddev)) 2133 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2134 /* we want direct complete for BOCO */ 2135 if (amdgpu_device_supports_boco(ddev)) 2136 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2137 DPM_FLAG_SMART_SUSPEND | 2138 DPM_FLAG_MAY_SKIP_RESUME); 2139 pm_runtime_use_autosuspend(ddev->dev); 2140 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2141 2142 pm_runtime_allow(ddev->dev); 2143 2144 pm_runtime_mark_last_busy(ddev->dev); 2145 pm_runtime_put_autosuspend(ddev->dev); 2146 2147 /* 2148 * For runpm implemented via BACO, PMFW will handle the 2149 * timing for BACO in and out: 2150 * - put ASIC into BACO state only when both video and 2151 * audio functions are in D3 state. 2152 * - pull ASIC out of BACO state when either video or 2153 * audio function is in D0 state. 2154 * Also, at startup, PMFW assumes both functions are in 2155 * D0 state. 2156 * 2157 * So if snd driver was loaded prior to amdgpu driver 2158 * and audio function was put into D3 state, there will 2159 * be no PMFW-aware D-state transition(D0->D3) on runpm 2160 * suspend. Thus the BACO will be not correctly kicked in. 2161 * 2162 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2163 * into D0 state. Then there will be a PMFW-aware D-state 2164 * transition(D0->D3) on runpm suspend. 2165 */ 2166 if (amdgpu_device_supports_baco(ddev) && 2167 !(adev->flags & AMD_IS_APU) && 2168 (adev->asic_type >= CHIP_NAVI10)) 2169 amdgpu_get_secondary_funcs(adev); 2170 } 2171 2172 return 0; 2173 2174 err_pci: 2175 pci_disable_device(pdev); 2176 return ret; 2177 } 2178 2179 static void 2180 amdgpu_pci_remove(struct pci_dev *pdev) 2181 { 2182 struct drm_device *dev = pci_get_drvdata(pdev); 2183 struct amdgpu_device *adev = drm_to_adev(dev); 2184 2185 drm_dev_unplug(dev); 2186 2187 if (adev->runpm) { 2188 pm_runtime_get_sync(dev->dev); 2189 pm_runtime_forbid(dev->dev); 2190 } 2191 2192 amdgpu_driver_unload_kms(dev); 2193 2194 /* 2195 * Flush any in flight DMA operations from device. 2196 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2197 * StatusTransactions Pending bit. 2198 */ 2199 pci_disable_device(pdev); 2200 pci_wait_for_pending_transaction(pdev); 2201 } 2202 2203 static void 2204 amdgpu_pci_shutdown(struct pci_dev *pdev) 2205 { 2206 struct drm_device *dev = pci_get_drvdata(pdev); 2207 struct amdgpu_device *adev = drm_to_adev(dev); 2208 2209 if (amdgpu_ras_intr_triggered()) 2210 return; 2211 2212 /* if we are running in a VM, make sure the device 2213 * torn down properly on reboot/shutdown. 2214 * unfortunately we can't detect certain 2215 * hypervisors so just do this all the time. 2216 */ 2217 if (!amdgpu_passthrough(adev)) 2218 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2219 amdgpu_device_ip_suspend(adev); 2220 adev->mp1_state = PP_MP1_STATE_NONE; 2221 } 2222 2223 /** 2224 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2225 * 2226 * @work: work_struct. 2227 */ 2228 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2229 { 2230 struct list_head device_list; 2231 struct amdgpu_device *adev; 2232 int i, r; 2233 struct amdgpu_reset_context reset_context; 2234 2235 memset(&reset_context, 0, sizeof(reset_context)); 2236 2237 mutex_lock(&mgpu_info.mutex); 2238 if (mgpu_info.pending_reset == true) { 2239 mutex_unlock(&mgpu_info.mutex); 2240 return; 2241 } 2242 mgpu_info.pending_reset = true; 2243 mutex_unlock(&mgpu_info.mutex); 2244 2245 /* Use a common context, just need to make sure full reset is done */ 2246 reset_context.method = AMD_RESET_METHOD_NONE; 2247 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2248 2249 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2250 adev = mgpu_info.gpu_ins[i].adev; 2251 reset_context.reset_req_dev = adev; 2252 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2253 if (r) { 2254 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2255 r, adev_to_drm(adev)->unique); 2256 } 2257 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2258 r = -EALREADY; 2259 } 2260 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2261 adev = mgpu_info.gpu_ins[i].adev; 2262 flush_work(&adev->xgmi_reset_work); 2263 adev->gmc.xgmi.pending_reset = false; 2264 } 2265 2266 /* reset function will rebuild the xgmi hive info , clear it now */ 2267 for (i = 0; i < mgpu_info.num_dgpu; i++) 2268 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2269 2270 INIT_LIST_HEAD(&device_list); 2271 2272 for (i = 0; i < mgpu_info.num_dgpu; i++) 2273 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2274 2275 /* unregister the GPU first, reset function will add them back */ 2276 list_for_each_entry(adev, &device_list, reset_list) 2277 amdgpu_unregister_gpu_instance(adev); 2278 2279 /* Use a common context, just need to make sure full reset is done */ 2280 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2281 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2282 2283 if (r) { 2284 DRM_ERROR("reinit gpus failure"); 2285 return; 2286 } 2287 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2288 adev = mgpu_info.gpu_ins[i].adev; 2289 if (!adev->kfd.init_complete) 2290 amdgpu_amdkfd_device_init(adev); 2291 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2292 } 2293 return; 2294 } 2295 2296 static int amdgpu_pmops_prepare(struct device *dev) 2297 { 2298 struct drm_device *drm_dev = dev_get_drvdata(dev); 2299 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2300 2301 /* Return a positive number here so 2302 * DPM_FLAG_SMART_SUSPEND works properly 2303 */ 2304 if (amdgpu_device_supports_boco(drm_dev)) 2305 return pm_runtime_suspended(dev); 2306 2307 /* if we will not support s3 or s2i for the device 2308 * then skip suspend 2309 */ 2310 if (!amdgpu_acpi_is_s0ix_active(adev) && 2311 !amdgpu_acpi_is_s3_active(adev)) 2312 return 1; 2313 2314 return 0; 2315 } 2316 2317 static void amdgpu_pmops_complete(struct device *dev) 2318 { 2319 /* nothing to do */ 2320 } 2321 2322 static int amdgpu_pmops_suspend(struct device *dev) 2323 { 2324 struct drm_device *drm_dev = dev_get_drvdata(dev); 2325 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2326 2327 if (amdgpu_acpi_is_s0ix_active(adev)) 2328 adev->in_s0ix = true; 2329 else 2330 adev->in_s3 = true; 2331 return amdgpu_device_suspend(drm_dev, true); 2332 } 2333 2334 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2335 { 2336 struct drm_device *drm_dev = dev_get_drvdata(dev); 2337 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2338 2339 if (!adev->in_s0ix) 2340 return amdgpu_asic_reset(adev); 2341 2342 return 0; 2343 } 2344 2345 static int amdgpu_pmops_resume(struct device *dev) 2346 { 2347 struct drm_device *drm_dev = dev_get_drvdata(dev); 2348 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2349 int r; 2350 2351 /* Avoids registers access if device is physically gone */ 2352 if (!pci_device_is_present(adev->pdev)) 2353 adev->no_hw_access = true; 2354 2355 r = amdgpu_device_resume(drm_dev, true); 2356 if (amdgpu_acpi_is_s0ix_active(adev)) 2357 adev->in_s0ix = false; 2358 else 2359 adev->in_s3 = false; 2360 return r; 2361 } 2362 2363 static int amdgpu_pmops_freeze(struct device *dev) 2364 { 2365 struct drm_device *drm_dev = dev_get_drvdata(dev); 2366 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2367 int r; 2368 2369 adev->in_s4 = true; 2370 r = amdgpu_device_suspend(drm_dev, true); 2371 adev->in_s4 = false; 2372 if (r) 2373 return r; 2374 return amdgpu_asic_reset(adev); 2375 } 2376 2377 static int amdgpu_pmops_thaw(struct device *dev) 2378 { 2379 struct drm_device *drm_dev = dev_get_drvdata(dev); 2380 2381 return amdgpu_device_resume(drm_dev, true); 2382 } 2383 2384 static int amdgpu_pmops_poweroff(struct device *dev) 2385 { 2386 struct drm_device *drm_dev = dev_get_drvdata(dev); 2387 2388 return amdgpu_device_suspend(drm_dev, true); 2389 } 2390 2391 static int amdgpu_pmops_restore(struct device *dev) 2392 { 2393 struct drm_device *drm_dev = dev_get_drvdata(dev); 2394 2395 return amdgpu_device_resume(drm_dev, true); 2396 } 2397 2398 static int amdgpu_runtime_idle_check_display(struct device *dev) 2399 { 2400 struct pci_dev *pdev = to_pci_dev(dev); 2401 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2402 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2403 2404 if (adev->mode_info.num_crtc) { 2405 struct drm_connector *list_connector; 2406 struct drm_connector_list_iter iter; 2407 int ret = 0; 2408 2409 /* XXX: Return busy if any displays are connected to avoid 2410 * possible display wakeups after runtime resume due to 2411 * hotplug events in case any displays were connected while 2412 * the GPU was in suspend. Remove this once that is fixed. 2413 */ 2414 mutex_lock(&drm_dev->mode_config.mutex); 2415 drm_connector_list_iter_begin(drm_dev, &iter); 2416 drm_for_each_connector_iter(list_connector, &iter) { 2417 if (list_connector->status == connector_status_connected) { 2418 ret = -EBUSY; 2419 break; 2420 } 2421 } 2422 drm_connector_list_iter_end(&iter); 2423 mutex_unlock(&drm_dev->mode_config.mutex); 2424 2425 if (ret) 2426 return ret; 2427 2428 if (amdgpu_device_has_dc_support(adev)) { 2429 struct drm_crtc *crtc; 2430 2431 drm_for_each_crtc(crtc, drm_dev) { 2432 drm_modeset_lock(&crtc->mutex, NULL); 2433 if (crtc->state->active) 2434 ret = -EBUSY; 2435 drm_modeset_unlock(&crtc->mutex); 2436 if (ret < 0) 2437 break; 2438 } 2439 } else { 2440 mutex_lock(&drm_dev->mode_config.mutex); 2441 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2442 2443 drm_connector_list_iter_begin(drm_dev, &iter); 2444 drm_for_each_connector_iter(list_connector, &iter) { 2445 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2446 ret = -EBUSY; 2447 break; 2448 } 2449 } 2450 2451 drm_connector_list_iter_end(&iter); 2452 2453 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2454 mutex_unlock(&drm_dev->mode_config.mutex); 2455 } 2456 if (ret) 2457 return ret; 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2464 { 2465 struct pci_dev *pdev = to_pci_dev(dev); 2466 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2467 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2468 int ret, i; 2469 2470 if (!adev->runpm) { 2471 pm_runtime_forbid(dev); 2472 return -EBUSY; 2473 } 2474 2475 ret = amdgpu_runtime_idle_check_display(dev); 2476 if (ret) 2477 return ret; 2478 2479 /* wait for all rings to drain before suspending */ 2480 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2481 struct amdgpu_ring *ring = adev->rings[i]; 2482 if (ring && ring->sched.ready) { 2483 ret = amdgpu_fence_wait_empty(ring); 2484 if (ret) 2485 return -EBUSY; 2486 } 2487 } 2488 2489 adev->in_runpm = true; 2490 if (amdgpu_device_supports_px(drm_dev)) 2491 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2492 2493 /* 2494 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2495 * proper cleanups and put itself into a state ready for PNP. That 2496 * can address some random resuming failure observed on BOCO capable 2497 * platforms. 2498 * TODO: this may be also needed for PX capable platform. 2499 */ 2500 if (amdgpu_device_supports_boco(drm_dev)) 2501 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2502 2503 ret = amdgpu_device_suspend(drm_dev, false); 2504 if (ret) { 2505 adev->in_runpm = false; 2506 if (amdgpu_device_supports_boco(drm_dev)) 2507 adev->mp1_state = PP_MP1_STATE_NONE; 2508 return ret; 2509 } 2510 2511 if (amdgpu_device_supports_boco(drm_dev)) 2512 adev->mp1_state = PP_MP1_STATE_NONE; 2513 2514 if (amdgpu_device_supports_px(drm_dev)) { 2515 /* Only need to handle PCI state in the driver for ATPX 2516 * PCI core handles it for _PR3. 2517 */ 2518 amdgpu_device_cache_pci_state(pdev); 2519 pci_disable_device(pdev); 2520 pci_ignore_hotplug(pdev); 2521 pci_set_power_state(pdev, PCI_D3cold); 2522 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2523 } else if (amdgpu_device_supports_boco(drm_dev)) { 2524 /* nothing to do */ 2525 } else if (amdgpu_device_supports_baco(drm_dev)) { 2526 amdgpu_device_baco_enter(drm_dev); 2527 } 2528 2529 return 0; 2530 } 2531 2532 static int amdgpu_pmops_runtime_resume(struct device *dev) 2533 { 2534 struct pci_dev *pdev = to_pci_dev(dev); 2535 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2536 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2537 int ret; 2538 2539 if (!adev->runpm) 2540 return -EINVAL; 2541 2542 /* Avoids registers access if device is physically gone */ 2543 if (!pci_device_is_present(adev->pdev)) 2544 adev->no_hw_access = true; 2545 2546 if (amdgpu_device_supports_px(drm_dev)) { 2547 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2548 2549 /* Only need to handle PCI state in the driver for ATPX 2550 * PCI core handles it for _PR3. 2551 */ 2552 pci_set_power_state(pdev, PCI_D0); 2553 amdgpu_device_load_pci_state(pdev); 2554 ret = pci_enable_device(pdev); 2555 if (ret) 2556 return ret; 2557 pci_set_master(pdev); 2558 } else if (amdgpu_device_supports_boco(drm_dev)) { 2559 /* Only need to handle PCI state in the driver for ATPX 2560 * PCI core handles it for _PR3. 2561 */ 2562 pci_set_master(pdev); 2563 } else if (amdgpu_device_supports_baco(drm_dev)) { 2564 amdgpu_device_baco_exit(drm_dev); 2565 } 2566 ret = amdgpu_device_resume(drm_dev, false); 2567 if (ret) 2568 return ret; 2569 2570 if (amdgpu_device_supports_px(drm_dev)) 2571 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2572 adev->in_runpm = false; 2573 return 0; 2574 } 2575 2576 static int amdgpu_pmops_runtime_idle(struct device *dev) 2577 { 2578 struct drm_device *drm_dev = dev_get_drvdata(dev); 2579 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2580 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2581 int ret = 1; 2582 2583 if (!adev->runpm) { 2584 pm_runtime_forbid(dev); 2585 return -EBUSY; 2586 } 2587 2588 ret = amdgpu_runtime_idle_check_display(dev); 2589 2590 pm_runtime_mark_last_busy(dev); 2591 pm_runtime_autosuspend(dev); 2592 return ret; 2593 } 2594 2595 long amdgpu_drm_ioctl(struct file *filp, 2596 unsigned int cmd, unsigned long arg) 2597 { 2598 struct drm_file *file_priv = filp->private_data; 2599 struct drm_device *dev; 2600 long ret; 2601 dev = file_priv->minor->dev; 2602 ret = pm_runtime_get_sync(dev->dev); 2603 if (ret < 0) 2604 goto out; 2605 2606 ret = drm_ioctl(filp, cmd, arg); 2607 2608 pm_runtime_mark_last_busy(dev->dev); 2609 out: 2610 pm_runtime_put_autosuspend(dev->dev); 2611 return ret; 2612 } 2613 2614 static const struct dev_pm_ops amdgpu_pm_ops = { 2615 .prepare = amdgpu_pmops_prepare, 2616 .complete = amdgpu_pmops_complete, 2617 .suspend = amdgpu_pmops_suspend, 2618 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2619 .resume = amdgpu_pmops_resume, 2620 .freeze = amdgpu_pmops_freeze, 2621 .thaw = amdgpu_pmops_thaw, 2622 .poweroff = amdgpu_pmops_poweroff, 2623 .restore = amdgpu_pmops_restore, 2624 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2625 .runtime_resume = amdgpu_pmops_runtime_resume, 2626 .runtime_idle = amdgpu_pmops_runtime_idle, 2627 }; 2628 2629 static int amdgpu_flush(struct file *f, fl_owner_t id) 2630 { 2631 struct drm_file *file_priv = f->private_data; 2632 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2633 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2634 2635 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2636 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2637 2638 return timeout >= 0 ? 0 : timeout; 2639 } 2640 2641 static const struct file_operations amdgpu_driver_kms_fops = { 2642 .owner = THIS_MODULE, 2643 .open = drm_open, 2644 .flush = amdgpu_flush, 2645 .release = drm_release, 2646 .unlocked_ioctl = amdgpu_drm_ioctl, 2647 .mmap = drm_gem_mmap, 2648 .poll = drm_poll, 2649 .read = drm_read, 2650 #ifdef CONFIG_COMPAT 2651 .compat_ioctl = amdgpu_kms_compat_ioctl, 2652 #endif 2653 #ifdef CONFIG_PROC_FS 2654 .show_fdinfo = amdgpu_show_fdinfo 2655 #endif 2656 }; 2657 2658 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2659 { 2660 struct drm_file *file; 2661 2662 if (!filp) 2663 return -EINVAL; 2664 2665 if (filp->f_op != &amdgpu_driver_kms_fops) { 2666 return -EINVAL; 2667 } 2668 2669 file = filp->private_data; 2670 *fpriv = file->driver_priv; 2671 return 0; 2672 } 2673 2674 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2675 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2676 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2677 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2678 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2679 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2680 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2681 /* KMS */ 2682 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2683 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2684 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2685 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2686 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2687 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2688 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2689 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2690 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2691 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2692 }; 2693 2694 static const struct drm_driver amdgpu_kms_driver = { 2695 .driver_features = 2696 DRIVER_ATOMIC | 2697 DRIVER_GEM | 2698 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2699 DRIVER_SYNCOBJ_TIMELINE, 2700 .open = amdgpu_driver_open_kms, 2701 .postclose = amdgpu_driver_postclose_kms, 2702 .lastclose = amdgpu_driver_lastclose_kms, 2703 .ioctls = amdgpu_ioctls_kms, 2704 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2705 .dumb_create = amdgpu_mode_dumb_create, 2706 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2707 .fops = &amdgpu_driver_kms_fops, 2708 .release = &amdgpu_driver_release_kms, 2709 2710 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2711 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2712 .gem_prime_import = amdgpu_gem_prime_import, 2713 .gem_prime_mmap = drm_gem_prime_mmap, 2714 2715 .name = DRIVER_NAME, 2716 .desc = DRIVER_DESC, 2717 .date = DRIVER_DATE, 2718 .major = KMS_DRIVER_MAJOR, 2719 .minor = KMS_DRIVER_MINOR, 2720 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2721 }; 2722 2723 static struct pci_error_handlers amdgpu_pci_err_handler = { 2724 .error_detected = amdgpu_pci_error_detected, 2725 .mmio_enabled = amdgpu_pci_mmio_enabled, 2726 .slot_reset = amdgpu_pci_slot_reset, 2727 .resume = amdgpu_pci_resume, 2728 }; 2729 2730 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2731 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2732 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2733 2734 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2735 &amdgpu_vram_mgr_attr_group, 2736 &amdgpu_gtt_mgr_attr_group, 2737 &amdgpu_vbios_version_attr_group, 2738 NULL, 2739 }; 2740 2741 2742 static struct pci_driver amdgpu_kms_pci_driver = { 2743 .name = DRIVER_NAME, 2744 .id_table = pciidlist, 2745 .probe = amdgpu_pci_probe, 2746 .remove = amdgpu_pci_remove, 2747 .shutdown = amdgpu_pci_shutdown, 2748 .driver.pm = &amdgpu_pm_ops, 2749 .err_handler = &amdgpu_pci_err_handler, 2750 .dev_groups = amdgpu_sysfs_groups, 2751 }; 2752 2753 static int __init amdgpu_init(void) 2754 { 2755 int r; 2756 2757 if (drm_firmware_drivers_only()) 2758 return -EINVAL; 2759 2760 r = amdgpu_sync_init(); 2761 if (r) 2762 goto error_sync; 2763 2764 r = amdgpu_fence_slab_init(); 2765 if (r) 2766 goto error_fence; 2767 2768 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2769 amdgpu_register_atpx_handler(); 2770 amdgpu_acpi_detect(); 2771 2772 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2773 amdgpu_amdkfd_init(); 2774 2775 /* let modprobe override vga console setting */ 2776 return pci_register_driver(&amdgpu_kms_pci_driver); 2777 2778 error_fence: 2779 amdgpu_sync_fini(); 2780 2781 error_sync: 2782 return r; 2783 } 2784 2785 static void __exit amdgpu_exit(void) 2786 { 2787 amdgpu_amdkfd_fini(); 2788 pci_unregister_driver(&amdgpu_kms_pci_driver); 2789 amdgpu_unregister_atpx_handler(); 2790 amdgpu_sync_fini(); 2791 amdgpu_fence_slab_fini(); 2792 mmu_notifier_synchronize(); 2793 } 2794 2795 module_init(amdgpu_init); 2796 module_exit(amdgpu_exit); 2797 2798 MODULE_AUTHOR(DRIVER_AUTHOR); 2799 MODULE_DESCRIPTION(DRIVER_DESC); 2800 MODULE_LICENSE("GPL and additional rights"); 2801