1 /*
2  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_fbdev_generic.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_vblank.h>
30 #include <drm/drm_managed.h>
31 #include "amdgpu_drv.h"
32 
33 #include <drm/drm_pciids.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/cc_platform.h>
41 #include <linux/dynamic_debug.h>
42 
43 #include "amdgpu.h"
44 #include "amdgpu_irq.h"
45 #include "amdgpu_dma_buf.h"
46 #include "amdgpu_sched.h"
47 #include "amdgpu_fdinfo.h"
48 #include "amdgpu_amdkfd.h"
49 
50 #include "amdgpu_ras.h"
51 #include "amdgpu_xgmi.h"
52 #include "amdgpu_reset.h"
53 
54 /*
55  * KMS wrapper.
56  * - 3.0.0 - initial driver
57  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
58  * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
59  *           at the end of IBs.
60  * - 3.3.0 - Add VM support for UVD on supported hardware.
61  * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
62  * - 3.5.0 - Add support for new UVD_NO_OP register.
63  * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
64  * - 3.7.0 - Add support for VCE clock list packet
65  * - 3.8.0 - Add support raster config init in the kernel
66  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
67  * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
68  * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
69  * - 3.12.0 - Add query for double offchip LDS buffers
70  * - 3.13.0 - Add PRT support
71  * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
72  * - 3.15.0 - Export more gpu info for gfx9
73  * - 3.16.0 - Add reserved vmid support
74  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
75  * - 3.18.0 - Export gpu always on cu bitmap
76  * - 3.19.0 - Add support for UVD MJPEG decode
77  * - 3.20.0 - Add support for local BOs
78  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
79  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
80  * - 3.23.0 - Add query for VRAM lost counter
81  * - 3.24.0 - Add high priority compute support for gfx9
82  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
83  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
84  * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
85  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
86  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
87  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
88  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
89  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
90  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
91  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
92  * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
93  * - 3.36.0 - Allow reading more status registers on si/cik
94  * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
95  * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
96  * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
97  * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
98  * - 3.41.0 - Add video codec query
99  * - 3.42.0 - Add 16bpc fixed point display support
100  * - 3.43.0 - Add device hot plug/unplug support
101  * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
102  * - 3.45.0 - Add context ioctl stable pstate interface
103  * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
104  * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
105  * - 3.48.0 - Add IP discovery version info to HW INFO
106  * - 3.49.0 - Add gang submit into CS IOCTL
107  * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
108  *            Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
109  *   3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
110  *   3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
111  *            tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
112  *            gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
113  */
114 #define KMS_DRIVER_MAJOR	3
115 #define KMS_DRIVER_MINOR	52
116 #define KMS_DRIVER_PATCHLEVEL	0
117 
118 unsigned int amdgpu_vram_limit = UINT_MAX;
119 int amdgpu_vis_vram_limit;
120 int amdgpu_gart_size = -1; /* auto */
121 int amdgpu_gtt_size = -1; /* auto */
122 int amdgpu_moverate = -1; /* auto */
123 int amdgpu_audio = -1;
124 int amdgpu_disp_priority;
125 int amdgpu_hw_i2c;
126 int amdgpu_pcie_gen2 = -1;
127 int amdgpu_msi = -1;
128 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
129 int amdgpu_dpm = -1;
130 int amdgpu_fw_load_type = -1;
131 int amdgpu_aspm = -1;
132 int amdgpu_runtime_pm = -1;
133 uint amdgpu_ip_block_mask = 0xffffffff;
134 int amdgpu_bapm = -1;
135 int amdgpu_deep_color;
136 int amdgpu_vm_size = -1;
137 int amdgpu_vm_fragment_size = -1;
138 int amdgpu_vm_block_size = -1;
139 int amdgpu_vm_fault_stop;
140 int amdgpu_vm_debug;
141 int amdgpu_vm_update_mode = -1;
142 int amdgpu_exp_hw_support;
143 int amdgpu_dc = -1;
144 int amdgpu_sched_jobs = 32;
145 int amdgpu_sched_hw_submission = 2;
146 uint amdgpu_pcie_gen_cap;
147 uint amdgpu_pcie_lane_cap;
148 u64 amdgpu_cg_mask = 0xffffffffffffffff;
149 uint amdgpu_pg_mask = 0xffffffff;
150 uint amdgpu_sdma_phase_quantum = 32;
151 char *amdgpu_disable_cu = NULL;
152 char *amdgpu_virtual_display = NULL;
153 
154 /*
155  * OverDrive(bit 14) disabled by default
156  * GFX DCS(bit 19) disabled by default
157  */
158 uint amdgpu_pp_feature_mask = 0xfff7bfff;
159 uint amdgpu_force_long_training;
160 int amdgpu_job_hang_limit;
161 int amdgpu_lbpw = -1;
162 int amdgpu_compute_multipipe = -1;
163 int amdgpu_gpu_recovery = -1; /* auto */
164 int amdgpu_emu_mode;
165 uint amdgpu_smu_memory_pool_size;
166 int amdgpu_smu_pptable_id = -1;
167 /*
168  * FBC (bit 0) disabled by default
169  * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
170  *   - With this, for multiple monitors in sync(e.g. with the same model),
171  *     mclk switching will be allowed. And the mclk will be not foced to the
172  *     highest. That helps saving some idle power.
173  * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
174  * PSR (bit 3) disabled by default
175  * EDP NO POWER SEQUENCING (bit 4) disabled by default
176  */
177 uint amdgpu_dc_feature_mask = 2;
178 uint amdgpu_dc_debug_mask;
179 uint amdgpu_dc_visual_confirm;
180 int amdgpu_async_gfx_ring = 1;
181 int amdgpu_mcbp;
182 int amdgpu_discovery = -1;
183 int amdgpu_mes;
184 int amdgpu_mes_kiq;
185 int amdgpu_noretry = -1;
186 int amdgpu_force_asic_type = -1;
187 int amdgpu_tmz = -1; /* auto */
188 uint amdgpu_freesync_vid_mode;
189 int amdgpu_reset_method = -1; /* auto */
190 int amdgpu_num_kcq = -1;
191 int amdgpu_smartshift_bias;
192 int amdgpu_use_xgmi_p2p = 1;
193 int amdgpu_vcnfw_log;
194 int amdgpu_sg_display = -1; /* auto */
195 
196 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
197 
198 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
199 			"DRM_UT_CORE",
200 			"DRM_UT_DRIVER",
201 			"DRM_UT_KMS",
202 			"DRM_UT_PRIME",
203 			"DRM_UT_ATOMIC",
204 			"DRM_UT_VBL",
205 			"DRM_UT_STATE",
206 			"DRM_UT_LEASE",
207 			"DRM_UT_DP",
208 			"DRM_UT_DRMRES");
209 
210 struct amdgpu_mgpu_info mgpu_info = {
211 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
212 	.delayed_reset_work = __DELAYED_WORK_INITIALIZER(
213 			mgpu_info.delayed_reset_work,
214 			amdgpu_drv_delayed_reset_work_handler, 0),
215 };
216 int amdgpu_ras_enable = -1;
217 uint amdgpu_ras_mask = 0xffffffff;
218 int amdgpu_bad_page_threshold = -1;
219 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
220 	.timeout_fatal_disable = false,
221 	.period = 0x0, /* default to 0x0 (timeout disable) */
222 };
223 
224 /**
225  * DOC: vramlimit (int)
226  * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
227  */
228 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
229 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
230 
231 /**
232  * DOC: vis_vramlimit (int)
233  * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visible VRAM).
234  */
235 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
236 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
237 
238 /**
239  * DOC: gartsize (uint)
240  * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
241  * The default is -1 (The size depends on asic).
242  */
243 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
244 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
245 
246 /**
247  * DOC: gttsize (int)
248  * Restrict the size of GTT domain (for userspace use) in MiB for testing.
249  * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
250  */
251 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
252 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
253 
254 /**
255  * DOC: moverate (int)
256  * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
257  */
258 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
259 module_param_named(moverate, amdgpu_moverate, int, 0600);
260 
261 /**
262  * DOC: audio (int)
263  * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
264  */
265 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
266 module_param_named(audio, amdgpu_audio, int, 0444);
267 
268 /**
269  * DOC: disp_priority (int)
270  * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
271  */
272 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
273 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
274 
275 /**
276  * DOC: hw_i2c (int)
277  * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
278  */
279 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
280 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
281 
282 /**
283  * DOC: pcie_gen2 (int)
284  * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
285  */
286 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
287 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
288 
289 /**
290  * DOC: msi (int)
291  * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
292  */
293 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
294 module_param_named(msi, amdgpu_msi, int, 0444);
295 
296 /**
297  * DOC: lockup_timeout (string)
298  * Set GPU scheduler timeout value in ms.
299  *
300  * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
301  * multiple values specified. 0 and negative values are invalidated. They will be adjusted
302  * to the default timeout.
303  *
304  * - With one value specified, the setting will apply to all non-compute jobs.
305  * - With multiple values specified, the first one will be for GFX.
306  *   The second one is for Compute. The third and fourth ones are
307  *   for SDMA and Video.
308  *
309  * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
310  * jobs is 10000. The timeout for compute is 60000.
311  */
312 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
313 		"for passthrough or sriov, 10000 for all jobs."
314 		" 0: keep default value. negative: infinity timeout), "
315 		"format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
316 		"for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
317 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
318 
319 /**
320  * DOC: dpm (int)
321  * Override for dynamic power management setting
322  * (0 = disable, 1 = enable)
323  * The default is -1 (auto).
324  */
325 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
326 module_param_named(dpm, amdgpu_dpm, int, 0444);
327 
328 /**
329  * DOC: fw_load_type (int)
330  * Set different firmware loading type for debugging, if supported.
331  * Set to 0 to force direct loading if supported by the ASIC.  Set
332  * to -1 to select the default loading mode for the ASIC, as defined
333  * by the driver.  The default is -1 (auto).
334  */
335 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
336 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
337 
338 /**
339  * DOC: aspm (int)
340  * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
341  */
342 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
343 module_param_named(aspm, amdgpu_aspm, int, 0444);
344 
345 /**
346  * DOC: runpm (int)
347  * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
348  * the dGPUs when they are idle if supported. The default is -1 (auto enable).
349  * Setting the value to 0 disables this functionality.
350  */
351 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
352 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
353 
354 /**
355  * DOC: ip_block_mask (uint)
356  * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
357  * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
358  * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
359  * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
360  */
361 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
362 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
363 
364 /**
365  * DOC: bapm (int)
366  * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
367  * The default -1 (auto, enabled)
368  */
369 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
370 module_param_named(bapm, amdgpu_bapm, int, 0444);
371 
372 /**
373  * DOC: deep_color (int)
374  * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
375  */
376 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
377 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
378 
379 /**
380  * DOC: vm_size (int)
381  * Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (automatic for each asic).
382  */
383 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
384 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
385 
386 /**
387  * DOC: vm_fragment_size (int)
388  * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
389  */
390 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
391 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
392 
393 /**
394  * DOC: vm_block_size (int)
395  * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
396  */
397 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
398 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
399 
400 /**
401  * DOC: vm_fault_stop (int)
402  * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
403  */
404 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
405 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
406 
407 /**
408  * DOC: vm_debug (int)
409  * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
410  */
411 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
412 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
413 
414 /**
415  * DOC: vm_update_mode (int)
416  * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
417  * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
418  */
419 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
420 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
421 
422 /**
423  * DOC: exp_hw_support (int)
424  * Enable experimental hw support (1 = enable). The default is 0 (disabled).
425  */
426 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
427 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
428 
429 /**
430  * DOC: dc (int)
431  * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
432  */
433 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
434 module_param_named(dc, amdgpu_dc, int, 0444);
435 
436 /**
437  * DOC: sched_jobs (int)
438  * Override the max number of jobs supported in the sw queue. The default is 32.
439  */
440 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
441 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
442 
443 /**
444  * DOC: sched_hw_submission (int)
445  * Override the max number of HW submissions. The default is 2.
446  */
447 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
448 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
449 
450 /**
451  * DOC: ppfeaturemask (hexint)
452  * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
453  * The default is the current set of stable power features.
454  */
455 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
456 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
457 
458 /**
459  * DOC: forcelongtraining (uint)
460  * Force long memory training in resume.
461  * The default is zero, indicates short training in resume.
462  */
463 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
464 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
465 
466 /**
467  * DOC: pcie_gen_cap (uint)
468  * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
469  * The default is 0 (automatic for each asic).
470  */
471 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
472 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
473 
474 /**
475  * DOC: pcie_lane_cap (uint)
476  * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
477  * The default is 0 (automatic for each asic).
478  */
479 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
480 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
481 
482 /**
483  * DOC: cg_mask (ullong)
484  * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
485  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
486  */
487 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
488 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
489 
490 /**
491  * DOC: pg_mask (uint)
492  * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
493  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
494  */
495 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
496 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
497 
498 /**
499  * DOC: sdma_phase_quantum (uint)
500  * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
501  */
502 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
503 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
504 
505 /**
506  * DOC: disable_cu (charp)
507  * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
508  */
509 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
510 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
511 
512 /**
513  * DOC: virtual_display (charp)
514  * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
515  * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
516  * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
517  * device at 26:00.0. The default is NULL.
518  */
519 MODULE_PARM_DESC(virtual_display,
520 		 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
521 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
522 
523 /**
524  * DOC: job_hang_limit (int)
525  * Set how much time allow a job hang and not drop it. The default is 0.
526  */
527 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
528 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
529 
530 /**
531  * DOC: lbpw (int)
532  * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
533  */
534 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
535 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
536 
537 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
538 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
539 
540 /**
541  * DOC: gpu_recovery (int)
542  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
543  */
544 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
545 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
546 
547 /**
548  * DOC: emu_mode (int)
549  * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
550  */
551 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
552 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
553 
554 /**
555  * DOC: ras_enable (int)
556  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
557  */
558 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
559 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
560 
561 /**
562  * DOC: ras_mask (uint)
563  * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
564  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
565  */
566 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
567 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
568 
569 /**
570  * DOC: timeout_fatal_disable (bool)
571  * Disable Watchdog timeout fatal error event
572  */
573 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
574 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
575 
576 /**
577  * DOC: timeout_period (uint)
578  * Modify the watchdog timeout max_cycles as (1 << period)
579  */
580 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
581 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
582 
583 /**
584  * DOC: si_support (int)
585  * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
586  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
587  * otherwise using amdgpu driver.
588  */
589 #ifdef CONFIG_DRM_AMDGPU_SI
590 
591 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
592 int amdgpu_si_support = 0;
593 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
594 #else
595 int amdgpu_si_support = 1;
596 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
597 #endif
598 
599 module_param_named(si_support, amdgpu_si_support, int, 0444);
600 #endif
601 
602 /**
603  * DOC: cik_support (int)
604  * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
605  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
606  * otherwise using amdgpu driver.
607  */
608 #ifdef CONFIG_DRM_AMDGPU_CIK
609 
610 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
611 int amdgpu_cik_support = 0;
612 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
613 #else
614 int amdgpu_cik_support = 1;
615 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
616 #endif
617 
618 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
619 #endif
620 
621 /**
622  * DOC: smu_memory_pool_size (uint)
623  * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
624  * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
625  */
626 MODULE_PARM_DESC(smu_memory_pool_size,
627 	"reserve gtt for smu debug usage, 0 = disable,"
628 		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
629 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
630 
631 /**
632  * DOC: async_gfx_ring (int)
633  * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
634  */
635 MODULE_PARM_DESC(async_gfx_ring,
636 	"Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
637 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
638 
639 /**
640  * DOC: mcbp (int)
641  * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
642  */
643 MODULE_PARM_DESC(mcbp,
644 	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
645 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
646 
647 /**
648  * DOC: discovery (int)
649  * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
650  * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
651  */
652 MODULE_PARM_DESC(discovery,
653 	"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
654 module_param_named(discovery, amdgpu_discovery, int, 0444);
655 
656 /**
657  * DOC: mes (int)
658  * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
659  * (0 = disabled (default), 1 = enabled)
660  */
661 MODULE_PARM_DESC(mes,
662 	"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
663 module_param_named(mes, amdgpu_mes, int, 0444);
664 
665 /**
666  * DOC: mes_kiq (int)
667  * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
668  * (0 = disabled (default), 1 = enabled)
669  */
670 MODULE_PARM_DESC(mes_kiq,
671 	"Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
672 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
673 
674 /**
675  * DOC: noretry (int)
676  * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
677  * do not support per-process XNACK this also disables retry page faults.
678  * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
679  */
680 MODULE_PARM_DESC(noretry,
681 	"Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
682 module_param_named(noretry, amdgpu_noretry, int, 0644);
683 
684 /**
685  * DOC: force_asic_type (int)
686  * A non negative value used to specify the asic type for all supported GPUs.
687  */
688 MODULE_PARM_DESC(force_asic_type,
689 	"A non negative value used to specify the asic type for all supported GPUs");
690 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
691 
692 /**
693  * DOC: use_xgmi_p2p (int)
694  * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
695  */
696 MODULE_PARM_DESC(use_xgmi_p2p,
697 	"Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
698 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
699 
700 
701 #ifdef CONFIG_HSA_AMD
702 /**
703  * DOC: sched_policy (int)
704  * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
705  * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
706  * assigns queues to HQDs.
707  */
708 int sched_policy = KFD_SCHED_POLICY_HWS;
709 module_param(sched_policy, int, 0444);
710 MODULE_PARM_DESC(sched_policy,
711 	"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
712 
713 /**
714  * DOC: hws_max_conc_proc (int)
715  * Maximum number of processes that HWS can schedule concurrently. The maximum is the
716  * number of VMIDs assigned to the HWS, which is also the default.
717  */
718 int hws_max_conc_proc = -1;
719 module_param(hws_max_conc_proc, int, 0444);
720 MODULE_PARM_DESC(hws_max_conc_proc,
721 	"Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
722 
723 /**
724  * DOC: cwsr_enable (int)
725  * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
726  * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
727  * disables it.
728  */
729 int cwsr_enable = 1;
730 module_param(cwsr_enable, int, 0444);
731 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
732 
733 /**
734  * DOC: max_num_of_queues_per_device (int)
735  * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
736  * is 4096.
737  */
738 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
739 module_param(max_num_of_queues_per_device, int, 0444);
740 MODULE_PARM_DESC(max_num_of_queues_per_device,
741 	"Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
742 
743 /**
744  * DOC: send_sigterm (int)
745  * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
746  * but just print errors on dmesg. Setting 1 enables sending sigterm.
747  */
748 int send_sigterm;
749 module_param(send_sigterm, int, 0444);
750 MODULE_PARM_DESC(send_sigterm,
751 	"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
752 
753 /**
754  * DOC: debug_largebar (int)
755  * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
756  * system. This limits the VRAM size reported to ROCm applications to the visible
757  * size, usually 256MB.
758  * Default value is 0, diabled.
759  */
760 int debug_largebar;
761 module_param(debug_largebar, int, 0444);
762 MODULE_PARM_DESC(debug_largebar,
763 	"Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
764 
765 /**
766  * DOC: ignore_crat (int)
767  * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
768  * table to get information about AMD APUs. This option can serve as a workaround on
769  * systems with a broken CRAT table.
770  *
771  * Default is auto (according to asic type, iommu_v2, and crat table, to decide
772  * whether use CRAT)
773  */
774 int ignore_crat;
775 module_param(ignore_crat, int, 0444);
776 MODULE_PARM_DESC(ignore_crat,
777 	"Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
778 
779 /**
780  * DOC: halt_if_hws_hang (int)
781  * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
782  * Setting 1 enables halt on hang.
783  */
784 int halt_if_hws_hang;
785 module_param(halt_if_hws_hang, int, 0644);
786 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
787 
788 /**
789  * DOC: hws_gws_support(bool)
790  * Assume that HWS supports GWS barriers regardless of what firmware version
791  * check says. Default value: false (rely on MEC2 firmware version check).
792  */
793 bool hws_gws_support;
794 module_param(hws_gws_support, bool, 0444);
795 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
796 
797 /**
798   * DOC: queue_preemption_timeout_ms (int)
799   * queue preemption timeout in ms (1 = Minimum, 9000 = default)
800   */
801 int queue_preemption_timeout_ms = 9000;
802 module_param(queue_preemption_timeout_ms, int, 0644);
803 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
804 
805 /**
806  * DOC: debug_evictions(bool)
807  * Enable extra debug messages to help determine the cause of evictions
808  */
809 bool debug_evictions;
810 module_param(debug_evictions, bool, 0644);
811 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
812 
813 /**
814  * DOC: no_system_mem_limit(bool)
815  * Disable system memory limit, to support multiple process shared memory
816  */
817 bool no_system_mem_limit;
818 module_param(no_system_mem_limit, bool, 0644);
819 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
820 
821 /**
822  * DOC: no_queue_eviction_on_vm_fault (int)
823  * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
824  */
825 int amdgpu_no_queue_eviction_on_vm_fault = 0;
826 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
827 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
828 #endif
829 
830 /**
831  * DOC: pcie_p2p (bool)
832  * Enable PCIe P2P (requires large-BAR). Default value: true (on)
833  */
834 #ifdef CONFIG_HSA_AMD_P2P
835 bool pcie_p2p = true;
836 module_param(pcie_p2p, bool, 0444);
837 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
838 #endif
839 
840 /**
841  * DOC: dcfeaturemask (uint)
842  * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
843  * The default is the current set of stable display features.
844  */
845 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
846 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
847 
848 /**
849  * DOC: dcdebugmask (uint)
850  * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
851  */
852 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
853 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
854 
855 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
856 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
857 
858 /**
859  * DOC: abmlevel (uint)
860  * Override the default ABM (Adaptive Backlight Management) level used for DC
861  * enabled hardware. Requires DMCU to be supported and loaded.
862  * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
863  * default. Values 1-4 control the maximum allowable brightness reduction via
864  * the ABM algorithm, with 1 being the least reduction and 4 being the most
865  * reduction.
866  *
867  * Defaults to 0, or disabled. Userspace can still override this level later
868  * after boot.
869  */
870 uint amdgpu_dm_abm_level;
871 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
872 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
873 
874 int amdgpu_backlight = -1;
875 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
876 module_param_named(backlight, amdgpu_backlight, bint, 0444);
877 
878 /**
879  * DOC: tmz (int)
880  * Trusted Memory Zone (TMZ) is a method to protect data being written
881  * to or read from memory.
882  *
883  * The default value: 0 (off).  TODO: change to auto till it is completed.
884  */
885 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
886 module_param_named(tmz, amdgpu_tmz, int, 0444);
887 
888 /**
889  * DOC: freesync_video (uint)
890  * Enable the optimization to adjust front porch timing to achieve seamless
891  * mode change experience when setting a freesync supported mode for which full
892  * modeset is not needed.
893  *
894  * The Display Core will add a set of modes derived from the base FreeSync
895  * video mode into the corresponding connector's mode list based on commonly
896  * used refresh rates and VRR range of the connected display, when users enable
897  * this feature. From the userspace perspective, they can see a seamless mode
898  * change experience when the change between different refresh rates under the
899  * same resolution. Additionally, userspace applications such as Video playback
900  * can read this modeset list and change the refresh rate based on the video
901  * frame rate. Finally, the userspace can also derive an appropriate mode for a
902  * particular refresh rate based on the FreeSync Mode and add it to the
903  * connector's mode list.
904  *
905  * Note: This is an experimental feature.
906  *
907  * The default value: 0 (off).
908  */
909 MODULE_PARM_DESC(
910 	freesync_video,
911 	"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
912 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
913 
914 /**
915  * DOC: reset_method (int)
916  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
917  */
918 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
919 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
920 
921 /**
922  * DOC: bad_page_threshold (int) Bad page threshold is specifies the
923  * threshold value of faulty pages detected by RAS ECC, which may
924  * result in the GPU entering bad status when the number of total
925  * faulty pages by ECC exceeds the threshold value.
926  */
927 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
928 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
929 
930 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
931 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
932 
933 /**
934  * DOC: vcnfw_log (int)
935  * Enable vcnfw log output for debugging, the default is disabled.
936  */
937 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
938 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
939 
940 /**
941  * DOC: sg_display (int)
942  * Disable S/G (scatter/gather) display (i.e., display from system memory).
943  * This option is only relevant on APUs.  Set this option to 0 to disable
944  * S/G display if you experience flickering or other issues under memory
945  * pressure and report the issue.
946  */
947 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
948 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
949 
950 /**
951  * DOC: smu_pptable_id (int)
952  * Used to override pptable id. id = 0 use VBIOS pptable.
953  * id > 0 use the soft pptable with specicfied id.
954  */
955 MODULE_PARM_DESC(smu_pptable_id,
956 	"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
957 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
958 
959 /* These devices are not supported by amdgpu.
960  * They are supported by the mach64, r128, radeon drivers
961  */
962 static const u16 amdgpu_unsupported_pciidlist[] = {
963 	/* mach64 */
964 	0x4354,
965 	0x4358,
966 	0x4554,
967 	0x4742,
968 	0x4744,
969 	0x4749,
970 	0x474C,
971 	0x474D,
972 	0x474E,
973 	0x474F,
974 	0x4750,
975 	0x4751,
976 	0x4752,
977 	0x4753,
978 	0x4754,
979 	0x4755,
980 	0x4756,
981 	0x4757,
982 	0x4758,
983 	0x4759,
984 	0x475A,
985 	0x4C42,
986 	0x4C44,
987 	0x4C47,
988 	0x4C49,
989 	0x4C4D,
990 	0x4C4E,
991 	0x4C50,
992 	0x4C51,
993 	0x4C52,
994 	0x4C53,
995 	0x5654,
996 	0x5655,
997 	0x5656,
998 	/* r128 */
999 	0x4c45,
1000 	0x4c46,
1001 	0x4d46,
1002 	0x4d4c,
1003 	0x5041,
1004 	0x5042,
1005 	0x5043,
1006 	0x5044,
1007 	0x5045,
1008 	0x5046,
1009 	0x5047,
1010 	0x5048,
1011 	0x5049,
1012 	0x504A,
1013 	0x504B,
1014 	0x504C,
1015 	0x504D,
1016 	0x504E,
1017 	0x504F,
1018 	0x5050,
1019 	0x5051,
1020 	0x5052,
1021 	0x5053,
1022 	0x5054,
1023 	0x5055,
1024 	0x5056,
1025 	0x5057,
1026 	0x5058,
1027 	0x5245,
1028 	0x5246,
1029 	0x5247,
1030 	0x524b,
1031 	0x524c,
1032 	0x534d,
1033 	0x5446,
1034 	0x544C,
1035 	0x5452,
1036 	/* radeon */
1037 	0x3150,
1038 	0x3151,
1039 	0x3152,
1040 	0x3154,
1041 	0x3155,
1042 	0x3E50,
1043 	0x3E54,
1044 	0x4136,
1045 	0x4137,
1046 	0x4144,
1047 	0x4145,
1048 	0x4146,
1049 	0x4147,
1050 	0x4148,
1051 	0x4149,
1052 	0x414A,
1053 	0x414B,
1054 	0x4150,
1055 	0x4151,
1056 	0x4152,
1057 	0x4153,
1058 	0x4154,
1059 	0x4155,
1060 	0x4156,
1061 	0x4237,
1062 	0x4242,
1063 	0x4336,
1064 	0x4337,
1065 	0x4437,
1066 	0x4966,
1067 	0x4967,
1068 	0x4A48,
1069 	0x4A49,
1070 	0x4A4A,
1071 	0x4A4B,
1072 	0x4A4C,
1073 	0x4A4D,
1074 	0x4A4E,
1075 	0x4A4F,
1076 	0x4A50,
1077 	0x4A54,
1078 	0x4B48,
1079 	0x4B49,
1080 	0x4B4A,
1081 	0x4B4B,
1082 	0x4B4C,
1083 	0x4C57,
1084 	0x4C58,
1085 	0x4C59,
1086 	0x4C5A,
1087 	0x4C64,
1088 	0x4C66,
1089 	0x4C67,
1090 	0x4E44,
1091 	0x4E45,
1092 	0x4E46,
1093 	0x4E47,
1094 	0x4E48,
1095 	0x4E49,
1096 	0x4E4A,
1097 	0x4E4B,
1098 	0x4E50,
1099 	0x4E51,
1100 	0x4E52,
1101 	0x4E53,
1102 	0x4E54,
1103 	0x4E56,
1104 	0x5144,
1105 	0x5145,
1106 	0x5146,
1107 	0x5147,
1108 	0x5148,
1109 	0x514C,
1110 	0x514D,
1111 	0x5157,
1112 	0x5158,
1113 	0x5159,
1114 	0x515A,
1115 	0x515E,
1116 	0x5460,
1117 	0x5462,
1118 	0x5464,
1119 	0x5548,
1120 	0x5549,
1121 	0x554A,
1122 	0x554B,
1123 	0x554C,
1124 	0x554D,
1125 	0x554E,
1126 	0x554F,
1127 	0x5550,
1128 	0x5551,
1129 	0x5552,
1130 	0x5554,
1131 	0x564A,
1132 	0x564B,
1133 	0x564F,
1134 	0x5652,
1135 	0x5653,
1136 	0x5657,
1137 	0x5834,
1138 	0x5835,
1139 	0x5954,
1140 	0x5955,
1141 	0x5974,
1142 	0x5975,
1143 	0x5960,
1144 	0x5961,
1145 	0x5962,
1146 	0x5964,
1147 	0x5965,
1148 	0x5969,
1149 	0x5a41,
1150 	0x5a42,
1151 	0x5a61,
1152 	0x5a62,
1153 	0x5b60,
1154 	0x5b62,
1155 	0x5b63,
1156 	0x5b64,
1157 	0x5b65,
1158 	0x5c61,
1159 	0x5c63,
1160 	0x5d48,
1161 	0x5d49,
1162 	0x5d4a,
1163 	0x5d4c,
1164 	0x5d4d,
1165 	0x5d4e,
1166 	0x5d4f,
1167 	0x5d50,
1168 	0x5d52,
1169 	0x5d57,
1170 	0x5e48,
1171 	0x5e4a,
1172 	0x5e4b,
1173 	0x5e4c,
1174 	0x5e4d,
1175 	0x5e4f,
1176 	0x6700,
1177 	0x6701,
1178 	0x6702,
1179 	0x6703,
1180 	0x6704,
1181 	0x6705,
1182 	0x6706,
1183 	0x6707,
1184 	0x6708,
1185 	0x6709,
1186 	0x6718,
1187 	0x6719,
1188 	0x671c,
1189 	0x671d,
1190 	0x671f,
1191 	0x6720,
1192 	0x6721,
1193 	0x6722,
1194 	0x6723,
1195 	0x6724,
1196 	0x6725,
1197 	0x6726,
1198 	0x6727,
1199 	0x6728,
1200 	0x6729,
1201 	0x6738,
1202 	0x6739,
1203 	0x673e,
1204 	0x6740,
1205 	0x6741,
1206 	0x6742,
1207 	0x6743,
1208 	0x6744,
1209 	0x6745,
1210 	0x6746,
1211 	0x6747,
1212 	0x6748,
1213 	0x6749,
1214 	0x674A,
1215 	0x6750,
1216 	0x6751,
1217 	0x6758,
1218 	0x6759,
1219 	0x675B,
1220 	0x675D,
1221 	0x675F,
1222 	0x6760,
1223 	0x6761,
1224 	0x6762,
1225 	0x6763,
1226 	0x6764,
1227 	0x6765,
1228 	0x6766,
1229 	0x6767,
1230 	0x6768,
1231 	0x6770,
1232 	0x6771,
1233 	0x6772,
1234 	0x6778,
1235 	0x6779,
1236 	0x677B,
1237 	0x6840,
1238 	0x6841,
1239 	0x6842,
1240 	0x6843,
1241 	0x6849,
1242 	0x684C,
1243 	0x6850,
1244 	0x6858,
1245 	0x6859,
1246 	0x6880,
1247 	0x6888,
1248 	0x6889,
1249 	0x688A,
1250 	0x688C,
1251 	0x688D,
1252 	0x6898,
1253 	0x6899,
1254 	0x689b,
1255 	0x689c,
1256 	0x689d,
1257 	0x689e,
1258 	0x68a0,
1259 	0x68a1,
1260 	0x68a8,
1261 	0x68a9,
1262 	0x68b0,
1263 	0x68b8,
1264 	0x68b9,
1265 	0x68ba,
1266 	0x68be,
1267 	0x68bf,
1268 	0x68c0,
1269 	0x68c1,
1270 	0x68c7,
1271 	0x68c8,
1272 	0x68c9,
1273 	0x68d8,
1274 	0x68d9,
1275 	0x68da,
1276 	0x68de,
1277 	0x68e0,
1278 	0x68e1,
1279 	0x68e4,
1280 	0x68e5,
1281 	0x68e8,
1282 	0x68e9,
1283 	0x68f1,
1284 	0x68f2,
1285 	0x68f8,
1286 	0x68f9,
1287 	0x68fa,
1288 	0x68fe,
1289 	0x7100,
1290 	0x7101,
1291 	0x7102,
1292 	0x7103,
1293 	0x7104,
1294 	0x7105,
1295 	0x7106,
1296 	0x7108,
1297 	0x7109,
1298 	0x710A,
1299 	0x710B,
1300 	0x710C,
1301 	0x710E,
1302 	0x710F,
1303 	0x7140,
1304 	0x7141,
1305 	0x7142,
1306 	0x7143,
1307 	0x7144,
1308 	0x7145,
1309 	0x7146,
1310 	0x7147,
1311 	0x7149,
1312 	0x714A,
1313 	0x714B,
1314 	0x714C,
1315 	0x714D,
1316 	0x714E,
1317 	0x714F,
1318 	0x7151,
1319 	0x7152,
1320 	0x7153,
1321 	0x715E,
1322 	0x715F,
1323 	0x7180,
1324 	0x7181,
1325 	0x7183,
1326 	0x7186,
1327 	0x7187,
1328 	0x7188,
1329 	0x718A,
1330 	0x718B,
1331 	0x718C,
1332 	0x718D,
1333 	0x718F,
1334 	0x7193,
1335 	0x7196,
1336 	0x719B,
1337 	0x719F,
1338 	0x71C0,
1339 	0x71C1,
1340 	0x71C2,
1341 	0x71C3,
1342 	0x71C4,
1343 	0x71C5,
1344 	0x71C6,
1345 	0x71C7,
1346 	0x71CD,
1347 	0x71CE,
1348 	0x71D2,
1349 	0x71D4,
1350 	0x71D5,
1351 	0x71D6,
1352 	0x71DA,
1353 	0x71DE,
1354 	0x7200,
1355 	0x7210,
1356 	0x7211,
1357 	0x7240,
1358 	0x7243,
1359 	0x7244,
1360 	0x7245,
1361 	0x7246,
1362 	0x7247,
1363 	0x7248,
1364 	0x7249,
1365 	0x724A,
1366 	0x724B,
1367 	0x724C,
1368 	0x724D,
1369 	0x724E,
1370 	0x724F,
1371 	0x7280,
1372 	0x7281,
1373 	0x7283,
1374 	0x7284,
1375 	0x7287,
1376 	0x7288,
1377 	0x7289,
1378 	0x728B,
1379 	0x728C,
1380 	0x7290,
1381 	0x7291,
1382 	0x7293,
1383 	0x7297,
1384 	0x7834,
1385 	0x7835,
1386 	0x791e,
1387 	0x791f,
1388 	0x793f,
1389 	0x7941,
1390 	0x7942,
1391 	0x796c,
1392 	0x796d,
1393 	0x796e,
1394 	0x796f,
1395 	0x9400,
1396 	0x9401,
1397 	0x9402,
1398 	0x9403,
1399 	0x9405,
1400 	0x940A,
1401 	0x940B,
1402 	0x940F,
1403 	0x94A0,
1404 	0x94A1,
1405 	0x94A3,
1406 	0x94B1,
1407 	0x94B3,
1408 	0x94B4,
1409 	0x94B5,
1410 	0x94B9,
1411 	0x9440,
1412 	0x9441,
1413 	0x9442,
1414 	0x9443,
1415 	0x9444,
1416 	0x9446,
1417 	0x944A,
1418 	0x944B,
1419 	0x944C,
1420 	0x944E,
1421 	0x9450,
1422 	0x9452,
1423 	0x9456,
1424 	0x945A,
1425 	0x945B,
1426 	0x945E,
1427 	0x9460,
1428 	0x9462,
1429 	0x946A,
1430 	0x946B,
1431 	0x947A,
1432 	0x947B,
1433 	0x9480,
1434 	0x9487,
1435 	0x9488,
1436 	0x9489,
1437 	0x948A,
1438 	0x948F,
1439 	0x9490,
1440 	0x9491,
1441 	0x9495,
1442 	0x9498,
1443 	0x949C,
1444 	0x949E,
1445 	0x949F,
1446 	0x94C0,
1447 	0x94C1,
1448 	0x94C3,
1449 	0x94C4,
1450 	0x94C5,
1451 	0x94C6,
1452 	0x94C7,
1453 	0x94C8,
1454 	0x94C9,
1455 	0x94CB,
1456 	0x94CC,
1457 	0x94CD,
1458 	0x9500,
1459 	0x9501,
1460 	0x9504,
1461 	0x9505,
1462 	0x9506,
1463 	0x9507,
1464 	0x9508,
1465 	0x9509,
1466 	0x950F,
1467 	0x9511,
1468 	0x9515,
1469 	0x9517,
1470 	0x9519,
1471 	0x9540,
1472 	0x9541,
1473 	0x9542,
1474 	0x954E,
1475 	0x954F,
1476 	0x9552,
1477 	0x9553,
1478 	0x9555,
1479 	0x9557,
1480 	0x955f,
1481 	0x9580,
1482 	0x9581,
1483 	0x9583,
1484 	0x9586,
1485 	0x9587,
1486 	0x9588,
1487 	0x9589,
1488 	0x958A,
1489 	0x958B,
1490 	0x958C,
1491 	0x958D,
1492 	0x958E,
1493 	0x958F,
1494 	0x9590,
1495 	0x9591,
1496 	0x9593,
1497 	0x9595,
1498 	0x9596,
1499 	0x9597,
1500 	0x9598,
1501 	0x9599,
1502 	0x959B,
1503 	0x95C0,
1504 	0x95C2,
1505 	0x95C4,
1506 	0x95C5,
1507 	0x95C6,
1508 	0x95C7,
1509 	0x95C9,
1510 	0x95CC,
1511 	0x95CD,
1512 	0x95CE,
1513 	0x95CF,
1514 	0x9610,
1515 	0x9611,
1516 	0x9612,
1517 	0x9613,
1518 	0x9614,
1519 	0x9615,
1520 	0x9616,
1521 	0x9640,
1522 	0x9641,
1523 	0x9642,
1524 	0x9643,
1525 	0x9644,
1526 	0x9645,
1527 	0x9647,
1528 	0x9648,
1529 	0x9649,
1530 	0x964a,
1531 	0x964b,
1532 	0x964c,
1533 	0x964e,
1534 	0x964f,
1535 	0x9710,
1536 	0x9711,
1537 	0x9712,
1538 	0x9713,
1539 	0x9714,
1540 	0x9715,
1541 	0x9802,
1542 	0x9803,
1543 	0x9804,
1544 	0x9805,
1545 	0x9806,
1546 	0x9807,
1547 	0x9808,
1548 	0x9809,
1549 	0x980A,
1550 	0x9900,
1551 	0x9901,
1552 	0x9903,
1553 	0x9904,
1554 	0x9905,
1555 	0x9906,
1556 	0x9907,
1557 	0x9908,
1558 	0x9909,
1559 	0x990A,
1560 	0x990B,
1561 	0x990C,
1562 	0x990D,
1563 	0x990E,
1564 	0x990F,
1565 	0x9910,
1566 	0x9913,
1567 	0x9917,
1568 	0x9918,
1569 	0x9919,
1570 	0x9990,
1571 	0x9991,
1572 	0x9992,
1573 	0x9993,
1574 	0x9994,
1575 	0x9995,
1576 	0x9996,
1577 	0x9997,
1578 	0x9998,
1579 	0x9999,
1580 	0x999A,
1581 	0x999B,
1582 	0x999C,
1583 	0x999D,
1584 	0x99A0,
1585 	0x99A2,
1586 	0x99A4,
1587 	/* radeon secondary ids */
1588 	0x3171,
1589 	0x3e70,
1590 	0x4164,
1591 	0x4165,
1592 	0x4166,
1593 	0x4168,
1594 	0x4170,
1595 	0x4171,
1596 	0x4172,
1597 	0x4173,
1598 	0x496e,
1599 	0x4a69,
1600 	0x4a6a,
1601 	0x4a6b,
1602 	0x4a70,
1603 	0x4a74,
1604 	0x4b69,
1605 	0x4b6b,
1606 	0x4b6c,
1607 	0x4c6e,
1608 	0x4e64,
1609 	0x4e65,
1610 	0x4e66,
1611 	0x4e67,
1612 	0x4e68,
1613 	0x4e69,
1614 	0x4e6a,
1615 	0x4e71,
1616 	0x4f73,
1617 	0x5569,
1618 	0x556b,
1619 	0x556d,
1620 	0x556f,
1621 	0x5571,
1622 	0x5854,
1623 	0x5874,
1624 	0x5940,
1625 	0x5941,
1626 	0x5b72,
1627 	0x5b73,
1628 	0x5b74,
1629 	0x5b75,
1630 	0x5d44,
1631 	0x5d45,
1632 	0x5d6d,
1633 	0x5d6f,
1634 	0x5d72,
1635 	0x5d77,
1636 	0x5e6b,
1637 	0x5e6d,
1638 	0x7120,
1639 	0x7124,
1640 	0x7129,
1641 	0x712e,
1642 	0x712f,
1643 	0x7162,
1644 	0x7163,
1645 	0x7166,
1646 	0x7167,
1647 	0x7172,
1648 	0x7173,
1649 	0x71a0,
1650 	0x71a1,
1651 	0x71a3,
1652 	0x71a7,
1653 	0x71bb,
1654 	0x71e0,
1655 	0x71e1,
1656 	0x71e2,
1657 	0x71e6,
1658 	0x71e7,
1659 	0x71f2,
1660 	0x7269,
1661 	0x726b,
1662 	0x726e,
1663 	0x72a0,
1664 	0x72a8,
1665 	0x72b1,
1666 	0x72b3,
1667 	0x793f,
1668 };
1669 
1670 static const struct pci_device_id pciidlist[] = {
1671 #ifdef  CONFIG_DRM_AMDGPU_SI
1672 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1673 	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1674 	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1675 	{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1676 	{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1677 	{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1678 	{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1679 	{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1680 	{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1681 	{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1682 	{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1683 	{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1684 	{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1685 	{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1686 	{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1687 	{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1688 	{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1689 	{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1690 	{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1691 	{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1692 	{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1693 	{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1694 	{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1695 	{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1696 	{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1697 	{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1698 	{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1699 	{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1700 	{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1701 	{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1702 	{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1703 	{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1704 	{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1705 	{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1706 	{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1707 	{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1708 	{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1709 	{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1710 	{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1711 	{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1712 	{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1713 	{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1714 	{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1715 	{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1716 	{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1717 	{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1718 	{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1719 	{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1720 	{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1721 	{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1722 	{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1723 	{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1724 	{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1725 	{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1726 	{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1727 	{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1728 	{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1729 	{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1730 	{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1731 	{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1732 	{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1733 	{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1734 	{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1735 	{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1736 	{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1737 	{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1738 	{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1739 	{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1740 	{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1741 	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1742 	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1743 	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1744 #endif
1745 #ifdef CONFIG_DRM_AMDGPU_CIK
1746 	/* Kaveri */
1747 	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1748 	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1749 	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1750 	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1751 	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1752 	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1753 	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1754 	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1755 	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1756 	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1757 	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1758 	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1759 	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1760 	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1761 	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1762 	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1763 	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1764 	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1765 	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1766 	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1767 	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1768 	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1769 	/* Bonaire */
1770 	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1771 	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1772 	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1773 	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1774 	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1775 	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1776 	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1777 	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1778 	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1779 	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1780 	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1781 	/* Hawaii */
1782 	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1783 	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1784 	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1785 	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1786 	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1787 	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1788 	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1789 	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1790 	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1791 	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1792 	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1793 	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1794 	/* Kabini */
1795 	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1796 	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1797 	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1798 	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1799 	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1800 	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1801 	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1802 	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1803 	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1804 	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1805 	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1806 	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1807 	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1808 	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1809 	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1810 	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1811 	/* mullins */
1812 	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1813 	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1814 	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1815 	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1816 	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1817 	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1818 	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1819 	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1820 	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1821 	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1822 	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1823 	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1824 	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1825 	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1826 	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1827 	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1828 #endif
1829 	/* topaz */
1830 	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1831 	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1832 	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1833 	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1834 	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1835 	/* tonga */
1836 	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1837 	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1838 	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1839 	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1840 	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1841 	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1842 	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1843 	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1844 	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1845 	/* fiji */
1846 	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1847 	{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1848 	/* carrizo */
1849 	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1850 	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1851 	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1852 	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1853 	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1854 	/* stoney */
1855 	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1856 	/* Polaris11 */
1857 	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1858 	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1859 	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1860 	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1861 	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1862 	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1863 	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1864 	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1865 	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1866 	/* Polaris10 */
1867 	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1868 	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1869 	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1870 	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1871 	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1872 	{0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1873 	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1874 	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1875 	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1876 	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1877 	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1878 	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1879 	{0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1880 	/* Polaris12 */
1881 	{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1882 	{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1883 	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1884 	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1885 	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1886 	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1887 	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1888 	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1889 	/* VEGAM */
1890 	{0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1891 	{0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1892 	{0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1893 	/* Vega 10 */
1894 	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1895 	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1896 	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1897 	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1898 	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1899 	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1900 	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1901 	{0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1902 	{0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1903 	{0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1904 	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1905 	{0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1906 	{0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1907 	{0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1908 	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1909 	/* Vega 12 */
1910 	{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1911 	{0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1912 	{0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1913 	{0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1914 	{0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1915 	/* Vega 20 */
1916 	{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1917 	{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1918 	{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1919 	{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1920 	{0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1921 	{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1922 	{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1923 	/* Raven */
1924 	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1925 	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1926 	/* Arcturus */
1927 	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1928 	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1929 	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1930 	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1931 	/* Navi10 */
1932 	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1933 	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1934 	{0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1935 	{0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1936 	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1937 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1938 	{0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1939 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1940 	/* Navi14 */
1941 	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1942 	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1943 	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1944 	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1945 
1946 	/* Renoir */
1947 	{0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1948 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1949 	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1950 	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1951 
1952 	/* Navi12 */
1953 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1954 	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1955 
1956 	/* Sienna_Cichlid */
1957 	{0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1958 	{0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1959 	{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1960 	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1961 	{0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1962 	{0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1963 	{0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1964 	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1965 	{0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1966 	{0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1967 	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1968 	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1969 	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1970 
1971 	/* Yellow Carp */
1972 	{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1973 	{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1974 
1975 	/* Navy_Flounder */
1976 	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1977 	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1978 	{0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1979 	{0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1980 	{0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1981 	{0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1982 	{0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1983 	{0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1984 	{0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1985 
1986 	/* DIMGREY_CAVEFISH */
1987 	{0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1988 	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1989 	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1990 	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1991 	{0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1992 	{0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1993 	{0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1994 	{0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1995 	{0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1996 	{0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1997 	{0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1998 	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1999 
2000 	/* Aldebaran */
2001 	{0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2002 	{0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2003 	{0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2004 	{0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2005 
2006 	/* CYAN_SKILLFISH */
2007 	{0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2008 	{0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2009 
2010 	/* BEIGE_GOBY */
2011 	{0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2012 	{0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2013 	{0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2014 	{0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2015 	{0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2016 	{0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2017 
2018 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
2019 	  .class = PCI_CLASS_DISPLAY_VGA << 8,
2020 	  .class_mask = 0xffffff,
2021 	  .driver_data = CHIP_IP_DISCOVERY },
2022 
2023 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
2024 	  .class = PCI_CLASS_DISPLAY_OTHER << 8,
2025 	  .class_mask = 0xffffff,
2026 	  .driver_data = CHIP_IP_DISCOVERY },
2027 
2028 	{0, 0, 0}
2029 };
2030 
2031 MODULE_DEVICE_TABLE(pci, pciidlist);
2032 
2033 static const struct drm_driver amdgpu_kms_driver;
2034 
2035 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2036 {
2037 	struct pci_dev *p = NULL;
2038 	int i;
2039 
2040 	/* 0 - GPU
2041 	 * 1 - audio
2042 	 * 2 - USB
2043 	 * 3 - UCSI
2044 	 */
2045 	for (i = 1; i < 4; i++) {
2046 		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2047 						adev->pdev->bus->number, i);
2048 		if (p) {
2049 			pm_runtime_get_sync(&p->dev);
2050 			pm_runtime_mark_last_busy(&p->dev);
2051 			pm_runtime_put_autosuspend(&p->dev);
2052 			pci_dev_put(p);
2053 		}
2054 	}
2055 }
2056 
2057 static int amdgpu_pci_probe(struct pci_dev *pdev,
2058 			    const struct pci_device_id *ent)
2059 {
2060 	struct drm_device *ddev;
2061 	struct amdgpu_device *adev;
2062 	unsigned long flags = ent->driver_data;
2063 	int ret, retry = 0, i;
2064 	bool supports_atomic = false;
2065 
2066 	/* skip devices which are owned by radeon */
2067 	for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2068 		if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2069 			return -ENODEV;
2070 	}
2071 
2072 	if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2073 		amdgpu_aspm = 0;
2074 
2075 	if (amdgpu_virtual_display ||
2076 	    amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2077 		supports_atomic = true;
2078 
2079 	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2080 		DRM_INFO("This hardware requires experimental hardware support.\n"
2081 			 "See modparam exp_hw_support\n");
2082 		return -ENODEV;
2083 	}
2084 	/* differentiate between P10 and P11 asics with the same DID */
2085 	if (pdev->device == 0x67FF &&
2086 	    (pdev->revision == 0xE3 ||
2087 	     pdev->revision == 0xE7 ||
2088 	     pdev->revision == 0xF3 ||
2089 	     pdev->revision == 0xF7)) {
2090 		flags &= ~AMD_ASIC_MASK;
2091 		flags |= CHIP_POLARIS10;
2092 	}
2093 
2094 	/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2095 	 * however, SME requires an indirect IOMMU mapping because the encryption
2096 	 * bit is beyond the DMA mask of the chip.
2097 	 */
2098 	if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2099 	    ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2100 		dev_info(&pdev->dev,
2101 			 "SME is not compatible with RAVEN\n");
2102 		return -ENOTSUPP;
2103 	}
2104 
2105 #ifdef CONFIG_DRM_AMDGPU_SI
2106 	if (!amdgpu_si_support) {
2107 		switch (flags & AMD_ASIC_MASK) {
2108 		case CHIP_TAHITI:
2109 		case CHIP_PITCAIRN:
2110 		case CHIP_VERDE:
2111 		case CHIP_OLAND:
2112 		case CHIP_HAINAN:
2113 			dev_info(&pdev->dev,
2114 				 "SI support provided by radeon.\n");
2115 			dev_info(&pdev->dev,
2116 				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2117 				);
2118 			return -ENODEV;
2119 		}
2120 	}
2121 #endif
2122 #ifdef CONFIG_DRM_AMDGPU_CIK
2123 	if (!amdgpu_cik_support) {
2124 		switch (flags & AMD_ASIC_MASK) {
2125 		case CHIP_KAVERI:
2126 		case CHIP_BONAIRE:
2127 		case CHIP_HAWAII:
2128 		case CHIP_KABINI:
2129 		case CHIP_MULLINS:
2130 			dev_info(&pdev->dev,
2131 				 "CIK support provided by radeon.\n");
2132 			dev_info(&pdev->dev,
2133 				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2134 				);
2135 			return -ENODEV;
2136 		}
2137 	}
2138 #endif
2139 
2140 	adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2141 	if (IS_ERR(adev))
2142 		return PTR_ERR(adev);
2143 
2144 	adev->dev  = &pdev->dev;
2145 	adev->pdev = pdev;
2146 	ddev = adev_to_drm(adev);
2147 
2148 	if (!supports_atomic)
2149 		ddev->driver_features &= ~DRIVER_ATOMIC;
2150 
2151 	ret = pci_enable_device(pdev);
2152 	if (ret)
2153 		return ret;
2154 
2155 	pci_set_drvdata(pdev, ddev);
2156 
2157 	ret = amdgpu_driver_load_kms(adev, flags);
2158 	if (ret)
2159 		goto err_pci;
2160 
2161 retry_init:
2162 	ret = drm_dev_register(ddev, flags);
2163 	if (ret == -EAGAIN && ++retry <= 3) {
2164 		DRM_INFO("retry init %d\n", retry);
2165 		/* Don't request EX mode too frequently which is attacking */
2166 		msleep(5000);
2167 		goto retry_init;
2168 	} else if (ret) {
2169 		goto err_pci;
2170 	}
2171 
2172 	/*
2173 	 * 1. don't init fbdev on hw without DCE
2174 	 * 2. don't init fbdev if there are no connectors
2175 	 */
2176 	if (adev->mode_info.mode_config_initialized &&
2177 	    !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2178 		/* select 8 bpp console on low vram cards */
2179 		if (adev->gmc.real_vram_size <= (32*1024*1024))
2180 			drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2181 		else
2182 			drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2183 	}
2184 
2185 	ret = amdgpu_debugfs_init(adev);
2186 	if (ret)
2187 		DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2188 
2189 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2190 		/* only need to skip on ATPX */
2191 		if (amdgpu_device_supports_px(ddev))
2192 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2193 		/* we want direct complete for BOCO */
2194 		if (amdgpu_device_supports_boco(ddev))
2195 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2196 						DPM_FLAG_SMART_SUSPEND |
2197 						DPM_FLAG_MAY_SKIP_RESUME);
2198 		pm_runtime_use_autosuspend(ddev->dev);
2199 		pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2200 
2201 		pm_runtime_allow(ddev->dev);
2202 
2203 		pm_runtime_mark_last_busy(ddev->dev);
2204 		pm_runtime_put_autosuspend(ddev->dev);
2205 
2206 		/*
2207 		 * For runpm implemented via BACO, PMFW will handle the
2208 		 * timing for BACO in and out:
2209 		 *   - put ASIC into BACO state only when both video and
2210 		 *     audio functions are in D3 state.
2211 		 *   - pull ASIC out of BACO state when either video or
2212 		 *     audio function is in D0 state.
2213 		 * Also, at startup, PMFW assumes both functions are in
2214 		 * D0 state.
2215 		 *
2216 		 * So if snd driver was loaded prior to amdgpu driver
2217 		 * and audio function was put into D3 state, there will
2218 		 * be no PMFW-aware D-state transition(D0->D3) on runpm
2219 		 * suspend. Thus the BACO will be not correctly kicked in.
2220 		 *
2221 		 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2222 		 * into D0 state. Then there will be a PMFW-aware D-state
2223 		 * transition(D0->D3) on runpm suspend.
2224 		 */
2225 		if (amdgpu_device_supports_baco(ddev) &&
2226 		    !(adev->flags & AMD_IS_APU) &&
2227 		    (adev->asic_type >= CHIP_NAVI10))
2228 			amdgpu_get_secondary_funcs(adev);
2229 	}
2230 
2231 	return 0;
2232 
2233 err_pci:
2234 	pci_disable_device(pdev);
2235 	return ret;
2236 }
2237 
2238 static void
2239 amdgpu_pci_remove(struct pci_dev *pdev)
2240 {
2241 	struct drm_device *dev = pci_get_drvdata(pdev);
2242 	struct amdgpu_device *adev = drm_to_adev(dev);
2243 
2244 	drm_dev_unplug(dev);
2245 
2246 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2247 		pm_runtime_get_sync(dev->dev);
2248 		pm_runtime_forbid(dev->dev);
2249 	}
2250 
2251 	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2252 	    !amdgpu_sriov_vf(adev)) {
2253 		bool need_to_reset_gpu = false;
2254 
2255 		if (adev->gmc.xgmi.num_physical_nodes > 1) {
2256 			struct amdgpu_hive_info *hive;
2257 
2258 			hive = amdgpu_get_xgmi_hive(adev);
2259 			if (hive->device_remove_count == 0)
2260 				need_to_reset_gpu = true;
2261 			hive->device_remove_count++;
2262 			amdgpu_put_xgmi_hive(hive);
2263 		} else {
2264 			need_to_reset_gpu = true;
2265 		}
2266 
2267 		/* Workaround for ASICs need to reset SMU.
2268 		 * Called only when the first device is removed.
2269 		 */
2270 		if (need_to_reset_gpu) {
2271 			struct amdgpu_reset_context reset_context;
2272 
2273 			adev->shutdown = true;
2274 			memset(&reset_context, 0, sizeof(reset_context));
2275 			reset_context.method = AMD_RESET_METHOD_NONE;
2276 			reset_context.reset_req_dev = adev;
2277 			set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2278 			set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2279 			amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2280 		}
2281 	}
2282 
2283 	amdgpu_driver_unload_kms(dev);
2284 
2285 	/*
2286 	 * Flush any in flight DMA operations from device.
2287 	 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2288 	 * StatusTransactions Pending bit.
2289 	 */
2290 	pci_disable_device(pdev);
2291 	pci_wait_for_pending_transaction(pdev);
2292 }
2293 
2294 static void
2295 amdgpu_pci_shutdown(struct pci_dev *pdev)
2296 {
2297 	struct drm_device *dev = pci_get_drvdata(pdev);
2298 	struct amdgpu_device *adev = drm_to_adev(dev);
2299 
2300 	if (amdgpu_ras_intr_triggered())
2301 		return;
2302 
2303 	/* if we are running in a VM, make sure the device
2304 	 * torn down properly on reboot/shutdown.
2305 	 * unfortunately we can't detect certain
2306 	 * hypervisors so just do this all the time.
2307 	 */
2308 	if (!amdgpu_passthrough(adev))
2309 		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2310 	amdgpu_device_ip_suspend(adev);
2311 	adev->mp1_state = PP_MP1_STATE_NONE;
2312 }
2313 
2314 /**
2315  * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2316  *
2317  * @work: work_struct.
2318  */
2319 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2320 {
2321 	struct list_head device_list;
2322 	struct amdgpu_device *adev;
2323 	int i, r;
2324 	struct amdgpu_reset_context reset_context;
2325 
2326 	memset(&reset_context, 0, sizeof(reset_context));
2327 
2328 	mutex_lock(&mgpu_info.mutex);
2329 	if (mgpu_info.pending_reset == true) {
2330 		mutex_unlock(&mgpu_info.mutex);
2331 		return;
2332 	}
2333 	mgpu_info.pending_reset = true;
2334 	mutex_unlock(&mgpu_info.mutex);
2335 
2336 	/* Use a common context, just need to make sure full reset is done */
2337 	reset_context.method = AMD_RESET_METHOD_NONE;
2338 	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2339 
2340 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2341 		adev = mgpu_info.gpu_ins[i].adev;
2342 		reset_context.reset_req_dev = adev;
2343 		r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2344 		if (r) {
2345 			dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2346 				r, adev_to_drm(adev)->unique);
2347 		}
2348 		if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2349 			r = -EALREADY;
2350 	}
2351 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2352 		adev = mgpu_info.gpu_ins[i].adev;
2353 		flush_work(&adev->xgmi_reset_work);
2354 		adev->gmc.xgmi.pending_reset = false;
2355 	}
2356 
2357 	/* reset function will rebuild the xgmi hive info , clear it now */
2358 	for (i = 0; i < mgpu_info.num_dgpu; i++)
2359 		amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2360 
2361 	INIT_LIST_HEAD(&device_list);
2362 
2363 	for (i = 0; i < mgpu_info.num_dgpu; i++)
2364 		list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2365 
2366 	/* unregister the GPU first, reset function will add them back */
2367 	list_for_each_entry(adev, &device_list, reset_list)
2368 		amdgpu_unregister_gpu_instance(adev);
2369 
2370 	/* Use a common context, just need to make sure full reset is done */
2371 	set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2372 	r = amdgpu_do_asic_reset(&device_list, &reset_context);
2373 
2374 	if (r) {
2375 		DRM_ERROR("reinit gpus failure");
2376 		return;
2377 	}
2378 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2379 		adev = mgpu_info.gpu_ins[i].adev;
2380 		if (!adev->kfd.init_complete)
2381 			amdgpu_amdkfd_device_init(adev);
2382 		amdgpu_ttm_set_buffer_funcs_status(adev, true);
2383 	}
2384 	return;
2385 }
2386 
2387 static int amdgpu_pmops_prepare(struct device *dev)
2388 {
2389 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2390 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2391 
2392 	/* Return a positive number here so
2393 	 * DPM_FLAG_SMART_SUSPEND works properly
2394 	 */
2395 	if (amdgpu_device_supports_boco(drm_dev))
2396 		return pm_runtime_suspended(dev);
2397 
2398 	/* if we will not support s3 or s2i for the device
2399 	 *  then skip suspend
2400 	 */
2401 	if (!amdgpu_acpi_is_s0ix_active(adev) &&
2402 	    !amdgpu_acpi_is_s3_active(adev))
2403 		return 1;
2404 
2405 	return 0;
2406 }
2407 
2408 static void amdgpu_pmops_complete(struct device *dev)
2409 {
2410 	/* nothing to do */
2411 }
2412 
2413 static int amdgpu_pmops_suspend(struct device *dev)
2414 {
2415 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2416 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2417 
2418 	if (amdgpu_acpi_is_s0ix_active(adev))
2419 		adev->in_s0ix = true;
2420 	else if (amdgpu_acpi_is_s3_active(adev))
2421 		adev->in_s3 = true;
2422 	if (!adev->in_s0ix && !adev->in_s3)
2423 		return 0;
2424 	return amdgpu_device_suspend(drm_dev, true);
2425 }
2426 
2427 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2428 {
2429 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2430 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2431 
2432 	if (amdgpu_acpi_should_gpu_reset(adev))
2433 		return amdgpu_asic_reset(adev);
2434 
2435 	return 0;
2436 }
2437 
2438 static int amdgpu_pmops_resume(struct device *dev)
2439 {
2440 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2441 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2442 	int r;
2443 
2444 	if (!adev->in_s0ix && !adev->in_s3)
2445 		return 0;
2446 
2447 	/* Avoids registers access if device is physically gone */
2448 	if (!pci_device_is_present(adev->pdev))
2449 		adev->no_hw_access = true;
2450 
2451 	r = amdgpu_device_resume(drm_dev, true);
2452 	if (amdgpu_acpi_is_s0ix_active(adev))
2453 		adev->in_s0ix = false;
2454 	else
2455 		adev->in_s3 = false;
2456 	return r;
2457 }
2458 
2459 static int amdgpu_pmops_freeze(struct device *dev)
2460 {
2461 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2462 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2463 	int r;
2464 
2465 	adev->in_s4 = true;
2466 	r = amdgpu_device_suspend(drm_dev, true);
2467 	adev->in_s4 = false;
2468 	if (r)
2469 		return r;
2470 
2471 	if (amdgpu_acpi_should_gpu_reset(adev))
2472 		return amdgpu_asic_reset(adev);
2473 	return 0;
2474 }
2475 
2476 static int amdgpu_pmops_thaw(struct device *dev)
2477 {
2478 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2479 
2480 	return amdgpu_device_resume(drm_dev, true);
2481 }
2482 
2483 static int amdgpu_pmops_poweroff(struct device *dev)
2484 {
2485 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2486 
2487 	return amdgpu_device_suspend(drm_dev, true);
2488 }
2489 
2490 static int amdgpu_pmops_restore(struct device *dev)
2491 {
2492 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2493 
2494 	return amdgpu_device_resume(drm_dev, true);
2495 }
2496 
2497 static int amdgpu_runtime_idle_check_display(struct device *dev)
2498 {
2499 	struct pci_dev *pdev = to_pci_dev(dev);
2500 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2501 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2502 
2503 	if (adev->mode_info.num_crtc) {
2504 		struct drm_connector *list_connector;
2505 		struct drm_connector_list_iter iter;
2506 		int ret = 0;
2507 
2508 		/* XXX: Return busy if any displays are connected to avoid
2509 		 * possible display wakeups after runtime resume due to
2510 		 * hotplug events in case any displays were connected while
2511 		 * the GPU was in suspend.  Remove this once that is fixed.
2512 		 */
2513 		mutex_lock(&drm_dev->mode_config.mutex);
2514 		drm_connector_list_iter_begin(drm_dev, &iter);
2515 		drm_for_each_connector_iter(list_connector, &iter) {
2516 			if (list_connector->status == connector_status_connected) {
2517 				ret = -EBUSY;
2518 				break;
2519 			}
2520 		}
2521 		drm_connector_list_iter_end(&iter);
2522 		mutex_unlock(&drm_dev->mode_config.mutex);
2523 
2524 		if (ret)
2525 			return ret;
2526 
2527 		if (adev->dc_enabled) {
2528 			struct drm_crtc *crtc;
2529 
2530 			drm_for_each_crtc(crtc, drm_dev) {
2531 				drm_modeset_lock(&crtc->mutex, NULL);
2532 				if (crtc->state->active)
2533 					ret = -EBUSY;
2534 				drm_modeset_unlock(&crtc->mutex);
2535 				if (ret < 0)
2536 					break;
2537 			}
2538 		} else {
2539 			mutex_lock(&drm_dev->mode_config.mutex);
2540 			drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2541 
2542 			drm_connector_list_iter_begin(drm_dev, &iter);
2543 			drm_for_each_connector_iter(list_connector, &iter) {
2544 				if (list_connector->dpms ==  DRM_MODE_DPMS_ON) {
2545 					ret = -EBUSY;
2546 					break;
2547 				}
2548 			}
2549 
2550 			drm_connector_list_iter_end(&iter);
2551 
2552 			drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2553 			mutex_unlock(&drm_dev->mode_config.mutex);
2554 		}
2555 		if (ret)
2556 			return ret;
2557 	}
2558 
2559 	return 0;
2560 }
2561 
2562 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2563 {
2564 	struct pci_dev *pdev = to_pci_dev(dev);
2565 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2566 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2567 	int ret, i;
2568 
2569 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2570 		pm_runtime_forbid(dev);
2571 		return -EBUSY;
2572 	}
2573 
2574 	ret = amdgpu_runtime_idle_check_display(dev);
2575 	if (ret)
2576 		return ret;
2577 
2578 	/* wait for all rings to drain before suspending */
2579 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2580 		struct amdgpu_ring *ring = adev->rings[i];
2581 		if (ring && ring->sched.ready) {
2582 			ret = amdgpu_fence_wait_empty(ring);
2583 			if (ret)
2584 				return -EBUSY;
2585 		}
2586 	}
2587 
2588 	adev->in_runpm = true;
2589 	if (amdgpu_device_supports_px(drm_dev))
2590 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2591 
2592 	/*
2593 	 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2594 	 * proper cleanups and put itself into a state ready for PNP. That
2595 	 * can address some random resuming failure observed on BOCO capable
2596 	 * platforms.
2597 	 * TODO: this may be also needed for PX capable platform.
2598 	 */
2599 	if (amdgpu_device_supports_boco(drm_dev))
2600 		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2601 
2602 	ret = amdgpu_device_suspend(drm_dev, false);
2603 	if (ret) {
2604 		adev->in_runpm = false;
2605 		if (amdgpu_device_supports_boco(drm_dev))
2606 			adev->mp1_state = PP_MP1_STATE_NONE;
2607 		return ret;
2608 	}
2609 
2610 	if (amdgpu_device_supports_boco(drm_dev))
2611 		adev->mp1_state = PP_MP1_STATE_NONE;
2612 
2613 	if (amdgpu_device_supports_px(drm_dev)) {
2614 		/* Only need to handle PCI state in the driver for ATPX
2615 		 * PCI core handles it for _PR3.
2616 		 */
2617 		amdgpu_device_cache_pci_state(pdev);
2618 		pci_disable_device(pdev);
2619 		pci_ignore_hotplug(pdev);
2620 		pci_set_power_state(pdev, PCI_D3cold);
2621 		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2622 	} else if (amdgpu_device_supports_boco(drm_dev)) {
2623 		/* nothing to do */
2624 	} else if (amdgpu_device_supports_baco(drm_dev)) {
2625 		amdgpu_device_baco_enter(drm_dev);
2626 	}
2627 
2628 	dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2629 
2630 	return 0;
2631 }
2632 
2633 static int amdgpu_pmops_runtime_resume(struct device *dev)
2634 {
2635 	struct pci_dev *pdev = to_pci_dev(dev);
2636 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2637 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2638 	int ret;
2639 
2640 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2641 		return -EINVAL;
2642 
2643 	/* Avoids registers access if device is physically gone */
2644 	if (!pci_device_is_present(adev->pdev))
2645 		adev->no_hw_access = true;
2646 
2647 	if (amdgpu_device_supports_px(drm_dev)) {
2648 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2649 
2650 		/* Only need to handle PCI state in the driver for ATPX
2651 		 * PCI core handles it for _PR3.
2652 		 */
2653 		pci_set_power_state(pdev, PCI_D0);
2654 		amdgpu_device_load_pci_state(pdev);
2655 		ret = pci_enable_device(pdev);
2656 		if (ret)
2657 			return ret;
2658 		pci_set_master(pdev);
2659 	} else if (amdgpu_device_supports_boco(drm_dev)) {
2660 		/* Only need to handle PCI state in the driver for ATPX
2661 		 * PCI core handles it for _PR3.
2662 		 */
2663 		pci_set_master(pdev);
2664 	} else if (amdgpu_device_supports_baco(drm_dev)) {
2665 		amdgpu_device_baco_exit(drm_dev);
2666 	}
2667 	ret = amdgpu_device_resume(drm_dev, false);
2668 	if (ret) {
2669 		if (amdgpu_device_supports_px(drm_dev))
2670 			pci_disable_device(pdev);
2671 		return ret;
2672 	}
2673 
2674 	if (amdgpu_device_supports_px(drm_dev))
2675 		drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2676 	adev->in_runpm = false;
2677 	return 0;
2678 }
2679 
2680 static int amdgpu_pmops_runtime_idle(struct device *dev)
2681 {
2682 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2683 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2684 	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2685 	int ret = 1;
2686 
2687 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2688 		pm_runtime_forbid(dev);
2689 		return -EBUSY;
2690 	}
2691 
2692 	ret = amdgpu_runtime_idle_check_display(dev);
2693 
2694 	pm_runtime_mark_last_busy(dev);
2695 	pm_runtime_autosuspend(dev);
2696 	return ret;
2697 }
2698 
2699 long amdgpu_drm_ioctl(struct file *filp,
2700 		      unsigned int cmd, unsigned long arg)
2701 {
2702 	struct drm_file *file_priv = filp->private_data;
2703 	struct drm_device *dev;
2704 	long ret;
2705 	dev = file_priv->minor->dev;
2706 	ret = pm_runtime_get_sync(dev->dev);
2707 	if (ret < 0)
2708 		goto out;
2709 
2710 	ret = drm_ioctl(filp, cmd, arg);
2711 
2712 	pm_runtime_mark_last_busy(dev->dev);
2713 out:
2714 	pm_runtime_put_autosuspend(dev->dev);
2715 	return ret;
2716 }
2717 
2718 static const struct dev_pm_ops amdgpu_pm_ops = {
2719 	.prepare = amdgpu_pmops_prepare,
2720 	.complete = amdgpu_pmops_complete,
2721 	.suspend = amdgpu_pmops_suspend,
2722 	.suspend_noirq = amdgpu_pmops_suspend_noirq,
2723 	.resume = amdgpu_pmops_resume,
2724 	.freeze = amdgpu_pmops_freeze,
2725 	.thaw = amdgpu_pmops_thaw,
2726 	.poweroff = amdgpu_pmops_poweroff,
2727 	.restore = amdgpu_pmops_restore,
2728 	.runtime_suspend = amdgpu_pmops_runtime_suspend,
2729 	.runtime_resume = amdgpu_pmops_runtime_resume,
2730 	.runtime_idle = amdgpu_pmops_runtime_idle,
2731 };
2732 
2733 static int amdgpu_flush(struct file *f, fl_owner_t id)
2734 {
2735 	struct drm_file *file_priv = f->private_data;
2736 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2737 	long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2738 
2739 	timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2740 	timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2741 
2742 	return timeout >= 0 ? 0 : timeout;
2743 }
2744 
2745 static const struct file_operations amdgpu_driver_kms_fops = {
2746 	.owner = THIS_MODULE,
2747 	.open = drm_open,
2748 	.flush = amdgpu_flush,
2749 	.release = drm_release,
2750 	.unlocked_ioctl = amdgpu_drm_ioctl,
2751 	.mmap = drm_gem_mmap,
2752 	.poll = drm_poll,
2753 	.read = drm_read,
2754 #ifdef CONFIG_COMPAT
2755 	.compat_ioctl = amdgpu_kms_compat_ioctl,
2756 #endif
2757 #ifdef CONFIG_PROC_FS
2758 	.show_fdinfo = amdgpu_show_fdinfo
2759 #endif
2760 };
2761 
2762 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2763 {
2764 	struct drm_file *file;
2765 
2766 	if (!filp)
2767 		return -EINVAL;
2768 
2769 	if (filp->f_op != &amdgpu_driver_kms_fops) {
2770 		return -EINVAL;
2771 	}
2772 
2773 	file = filp->private_data;
2774 	*fpriv = file->driver_priv;
2775 	return 0;
2776 }
2777 
2778 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2779 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2780 	DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2781 	DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2782 	DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2783 	DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2784 	DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2785 	/* KMS */
2786 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2787 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2788 	DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2789 	DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2790 	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2791 	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2792 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2793 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2794 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2795 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2796 };
2797 
2798 static const struct drm_driver amdgpu_kms_driver = {
2799 	.driver_features =
2800 	    DRIVER_ATOMIC |
2801 	    DRIVER_GEM |
2802 	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2803 	    DRIVER_SYNCOBJ_TIMELINE,
2804 	.open = amdgpu_driver_open_kms,
2805 	.postclose = amdgpu_driver_postclose_kms,
2806 	.lastclose = amdgpu_driver_lastclose_kms,
2807 	.ioctls = amdgpu_ioctls_kms,
2808 	.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2809 	.dumb_create = amdgpu_mode_dumb_create,
2810 	.dumb_map_offset = amdgpu_mode_dumb_mmap,
2811 	.fops = &amdgpu_driver_kms_fops,
2812 	.release = &amdgpu_driver_release_kms,
2813 
2814 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2815 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2816 	.gem_prime_import = amdgpu_gem_prime_import,
2817 	.gem_prime_mmap = drm_gem_prime_mmap,
2818 
2819 	.name = DRIVER_NAME,
2820 	.desc = DRIVER_DESC,
2821 	.date = DRIVER_DATE,
2822 	.major = KMS_DRIVER_MAJOR,
2823 	.minor = KMS_DRIVER_MINOR,
2824 	.patchlevel = KMS_DRIVER_PATCHLEVEL,
2825 };
2826 
2827 static struct pci_error_handlers amdgpu_pci_err_handler = {
2828 	.error_detected	= amdgpu_pci_error_detected,
2829 	.mmio_enabled	= amdgpu_pci_mmio_enabled,
2830 	.slot_reset	= amdgpu_pci_slot_reset,
2831 	.resume		= amdgpu_pci_resume,
2832 };
2833 
2834 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2835 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2836 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2837 
2838 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2839 	&amdgpu_vram_mgr_attr_group,
2840 	&amdgpu_gtt_mgr_attr_group,
2841 	&amdgpu_vbios_version_attr_group,
2842 	NULL,
2843 };
2844 
2845 
2846 static struct pci_driver amdgpu_kms_pci_driver = {
2847 	.name = DRIVER_NAME,
2848 	.id_table = pciidlist,
2849 	.probe = amdgpu_pci_probe,
2850 	.remove = amdgpu_pci_remove,
2851 	.shutdown = amdgpu_pci_shutdown,
2852 	.driver.pm = &amdgpu_pm_ops,
2853 	.err_handler = &amdgpu_pci_err_handler,
2854 	.dev_groups = amdgpu_sysfs_groups,
2855 };
2856 
2857 static int __init amdgpu_init(void)
2858 {
2859 	int r;
2860 
2861 	if (drm_firmware_drivers_only())
2862 		return -EINVAL;
2863 
2864 	r = amdgpu_sync_init();
2865 	if (r)
2866 		goto error_sync;
2867 
2868 	r = amdgpu_fence_slab_init();
2869 	if (r)
2870 		goto error_fence;
2871 
2872 	DRM_INFO("amdgpu kernel modesetting enabled.\n");
2873 	amdgpu_register_atpx_handler();
2874 	amdgpu_acpi_detect();
2875 
2876 	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2877 	amdgpu_amdkfd_init();
2878 
2879 	/* let modprobe override vga console setting */
2880 	return pci_register_driver(&amdgpu_kms_pci_driver);
2881 
2882 error_fence:
2883 	amdgpu_sync_fini();
2884 
2885 error_sync:
2886 	return r;
2887 }
2888 
2889 static void __exit amdgpu_exit(void)
2890 {
2891 	amdgpu_amdkfd_fini();
2892 	pci_unregister_driver(&amdgpu_kms_pci_driver);
2893 	amdgpu_unregister_atpx_handler();
2894 	amdgpu_sync_fini();
2895 	amdgpu_fence_slab_fini();
2896 	mmu_notifier_synchronize();
2897 }
2898 
2899 module_init(amdgpu_init);
2900 module_exit(amdgpu_exit);
2901 
2902 MODULE_AUTHOR(DRIVER_AUTHOR);
2903 MODULE_DESCRIPTION(DRIVER_DESC);
2904 MODULE_LICENSE("GPL and additional rights");
2905