1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 * - 3.42.0 - Add 16bpc fixed point display support 99 * - 3.43.0 - Add device hot plug/unplug support 100 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 101 * - 3.45.0 - Add context ioctl stable pstate interface 102 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 103 * * 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 104 */ 105 #define KMS_DRIVER_MAJOR 3 106 #define KMS_DRIVER_MINOR 47 107 #define KMS_DRIVER_PATCHLEVEL 0 108 109 int amdgpu_vram_limit; 110 int amdgpu_vis_vram_limit; 111 int amdgpu_gart_size = -1; /* auto */ 112 int amdgpu_gtt_size = -1; /* auto */ 113 int amdgpu_moverate = -1; /* auto */ 114 int amdgpu_audio = -1; 115 int amdgpu_disp_priority; 116 int amdgpu_hw_i2c; 117 int amdgpu_pcie_gen2 = -1; 118 int amdgpu_msi = -1; 119 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 120 int amdgpu_dpm = -1; 121 int amdgpu_fw_load_type = -1; 122 int amdgpu_aspm = -1; 123 int amdgpu_runtime_pm = -1; 124 uint amdgpu_ip_block_mask = 0xffffffff; 125 int amdgpu_bapm = -1; 126 int amdgpu_deep_color; 127 int amdgpu_vm_size = -1; 128 int amdgpu_vm_fragment_size = -1; 129 int amdgpu_vm_block_size = -1; 130 int amdgpu_vm_fault_stop; 131 int amdgpu_vm_debug; 132 int amdgpu_vm_update_mode = -1; 133 int amdgpu_exp_hw_support; 134 int amdgpu_dc = -1; 135 int amdgpu_sched_jobs = 32; 136 int amdgpu_sched_hw_submission = 2; 137 uint amdgpu_pcie_gen_cap; 138 uint amdgpu_pcie_lane_cap; 139 u64 amdgpu_cg_mask = 0xffffffffffffffff; 140 uint amdgpu_pg_mask = 0xffffffff; 141 uint amdgpu_sdma_phase_quantum = 32; 142 char *amdgpu_disable_cu = NULL; 143 char *amdgpu_virtual_display = NULL; 144 145 /* 146 * OverDrive(bit 14) disabled by default 147 * GFX DCS(bit 19) disabled by default 148 */ 149 uint amdgpu_pp_feature_mask = 0xfff7bfff; 150 uint amdgpu_force_long_training; 151 int amdgpu_job_hang_limit; 152 int amdgpu_lbpw = -1; 153 int amdgpu_compute_multipipe = -1; 154 int amdgpu_gpu_recovery = -1; /* auto */ 155 int amdgpu_emu_mode; 156 uint amdgpu_smu_memory_pool_size; 157 int amdgpu_smu_pptable_id = -1; 158 /* 159 * FBC (bit 0) disabled by default 160 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 161 * - With this, for multiple monitors in sync(e.g. with the same model), 162 * mclk switching will be allowed. And the mclk will be not foced to the 163 * highest. That helps saving some idle power. 164 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 165 * PSR (bit 3) disabled by default 166 * EDP NO POWER SEQUENCING (bit 4) disabled by default 167 */ 168 uint amdgpu_dc_feature_mask = 2; 169 uint amdgpu_dc_debug_mask; 170 int amdgpu_async_gfx_ring = 1; 171 int amdgpu_mcbp; 172 int amdgpu_discovery = -1; 173 int amdgpu_mes; 174 int amdgpu_mes_kiq; 175 int amdgpu_noretry = -1; 176 int amdgpu_force_asic_type = -1; 177 int amdgpu_tmz = -1; /* auto */ 178 int amdgpu_reset_method = -1; /* auto */ 179 int amdgpu_num_kcq = -1; 180 int amdgpu_smartshift_bias; 181 int amdgpu_use_xgmi_p2p = 1; 182 int amdgpu_vcnfw_log; 183 184 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 185 186 struct amdgpu_mgpu_info mgpu_info = { 187 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 188 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 189 mgpu_info.delayed_reset_work, 190 amdgpu_drv_delayed_reset_work_handler, 0), 191 }; 192 int amdgpu_ras_enable = -1; 193 uint amdgpu_ras_mask = 0xffffffff; 194 int amdgpu_bad_page_threshold = -1; 195 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 196 .timeout_fatal_disable = false, 197 .period = 0x0, /* default to 0x0 (timeout disable) */ 198 }; 199 200 /** 201 * DOC: vramlimit (int) 202 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 203 */ 204 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 205 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 206 207 /** 208 * DOC: vis_vramlimit (int) 209 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 210 */ 211 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 212 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 213 214 /** 215 * DOC: gartsize (uint) 216 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 217 */ 218 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 219 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 220 221 /** 222 * DOC: gttsize (int) 223 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 224 * otherwise 3/4 RAM size). 225 */ 226 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 227 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 228 229 /** 230 * DOC: moverate (int) 231 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 232 */ 233 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 234 module_param_named(moverate, amdgpu_moverate, int, 0600); 235 236 /** 237 * DOC: audio (int) 238 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 239 */ 240 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 241 module_param_named(audio, amdgpu_audio, int, 0444); 242 243 /** 244 * DOC: disp_priority (int) 245 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 246 */ 247 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 248 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 249 250 /** 251 * DOC: hw_i2c (int) 252 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 253 */ 254 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 255 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 256 257 /** 258 * DOC: pcie_gen2 (int) 259 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 260 */ 261 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 262 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 263 264 /** 265 * DOC: msi (int) 266 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 267 */ 268 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 269 module_param_named(msi, amdgpu_msi, int, 0444); 270 271 /** 272 * DOC: lockup_timeout (string) 273 * Set GPU scheduler timeout value in ms. 274 * 275 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 276 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 277 * to the default timeout. 278 * 279 * - With one value specified, the setting will apply to all non-compute jobs. 280 * - With multiple values specified, the first one will be for GFX. 281 * The second one is for Compute. The third and fourth ones are 282 * for SDMA and Video. 283 * 284 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 285 * jobs is 10000. The timeout for compute is 60000. 286 */ 287 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 288 "for passthrough or sriov, 10000 for all jobs." 289 " 0: keep default value. negative: infinity timeout), " 290 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 291 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 292 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 293 294 /** 295 * DOC: dpm (int) 296 * Override for dynamic power management setting 297 * (0 = disable, 1 = enable) 298 * The default is -1 (auto). 299 */ 300 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 301 module_param_named(dpm, amdgpu_dpm, int, 0444); 302 303 /** 304 * DOC: fw_load_type (int) 305 * Set different firmware loading type for debugging, if supported. 306 * Set to 0 to force direct loading if supported by the ASIC. Set 307 * to -1 to select the default loading mode for the ASIC, as defined 308 * by the driver. The default is -1 (auto). 309 */ 310 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 311 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 312 313 /** 314 * DOC: aspm (int) 315 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 316 */ 317 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 318 module_param_named(aspm, amdgpu_aspm, int, 0444); 319 320 /** 321 * DOC: runpm (int) 322 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 323 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 324 * Setting the value to 0 disables this functionality. 325 */ 326 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 327 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 328 329 /** 330 * DOC: ip_block_mask (uint) 331 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 332 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 333 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 334 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 335 */ 336 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 337 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 338 339 /** 340 * DOC: bapm (int) 341 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 342 * The default -1 (auto, enabled) 343 */ 344 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 345 module_param_named(bapm, amdgpu_bapm, int, 0444); 346 347 /** 348 * DOC: deep_color (int) 349 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 350 */ 351 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 352 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 353 354 /** 355 * DOC: vm_size (int) 356 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 357 */ 358 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 359 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 360 361 /** 362 * DOC: vm_fragment_size (int) 363 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 364 */ 365 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 366 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 367 368 /** 369 * DOC: vm_block_size (int) 370 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 371 */ 372 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 373 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 374 375 /** 376 * DOC: vm_fault_stop (int) 377 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 378 */ 379 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 380 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 381 382 /** 383 * DOC: vm_debug (int) 384 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 385 */ 386 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 387 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 388 389 /** 390 * DOC: vm_update_mode (int) 391 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 392 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 393 */ 394 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 395 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 396 397 /** 398 * DOC: exp_hw_support (int) 399 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 400 */ 401 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 402 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 403 404 /** 405 * DOC: dc (int) 406 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 407 */ 408 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 409 module_param_named(dc, amdgpu_dc, int, 0444); 410 411 /** 412 * DOC: sched_jobs (int) 413 * Override the max number of jobs supported in the sw queue. The default is 32. 414 */ 415 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 416 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 417 418 /** 419 * DOC: sched_hw_submission (int) 420 * Override the max number of HW submissions. The default is 2. 421 */ 422 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 423 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 424 425 /** 426 * DOC: ppfeaturemask (hexint) 427 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 428 * The default is the current set of stable power features. 429 */ 430 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 431 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 432 433 /** 434 * DOC: forcelongtraining (uint) 435 * Force long memory training in resume. 436 * The default is zero, indicates short training in resume. 437 */ 438 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 439 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 440 441 /** 442 * DOC: pcie_gen_cap (uint) 443 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 444 * The default is 0 (automatic for each asic). 445 */ 446 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 447 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 448 449 /** 450 * DOC: pcie_lane_cap (uint) 451 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 452 * The default is 0 (automatic for each asic). 453 */ 454 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 455 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 456 457 /** 458 * DOC: cg_mask (ullong) 459 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 460 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 461 */ 462 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 463 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 464 465 /** 466 * DOC: pg_mask (uint) 467 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 468 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 469 */ 470 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 471 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 472 473 /** 474 * DOC: sdma_phase_quantum (uint) 475 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 476 */ 477 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 478 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 479 480 /** 481 * DOC: disable_cu (charp) 482 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 483 */ 484 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 485 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 486 487 /** 488 * DOC: virtual_display (charp) 489 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 490 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 491 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 492 * device at 26:00.0. The default is NULL. 493 */ 494 MODULE_PARM_DESC(virtual_display, 495 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 496 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 497 498 /** 499 * DOC: job_hang_limit (int) 500 * Set how much time allow a job hang and not drop it. The default is 0. 501 */ 502 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 503 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 504 505 /** 506 * DOC: lbpw (int) 507 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 508 */ 509 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 510 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 511 512 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 513 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 514 515 /** 516 * DOC: gpu_recovery (int) 517 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 518 */ 519 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 520 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 521 522 /** 523 * DOC: emu_mode (int) 524 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 525 */ 526 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 527 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 528 529 /** 530 * DOC: ras_enable (int) 531 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 532 */ 533 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 534 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 535 536 /** 537 * DOC: ras_mask (uint) 538 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 539 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 540 */ 541 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 542 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 543 544 /** 545 * DOC: timeout_fatal_disable (bool) 546 * Disable Watchdog timeout fatal error event 547 */ 548 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 549 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 550 551 /** 552 * DOC: timeout_period (uint) 553 * Modify the watchdog timeout max_cycles as (1 << period) 554 */ 555 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 556 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 557 558 /** 559 * DOC: si_support (int) 560 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 561 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 562 * otherwise using amdgpu driver. 563 */ 564 #ifdef CONFIG_DRM_AMDGPU_SI 565 566 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 567 int amdgpu_si_support = 0; 568 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 569 #else 570 int amdgpu_si_support = 1; 571 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 572 #endif 573 574 module_param_named(si_support, amdgpu_si_support, int, 0444); 575 #endif 576 577 /** 578 * DOC: cik_support (int) 579 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 581 * otherwise using amdgpu driver. 582 */ 583 #ifdef CONFIG_DRM_AMDGPU_CIK 584 585 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 586 int amdgpu_cik_support = 0; 587 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 588 #else 589 int amdgpu_cik_support = 1; 590 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 591 #endif 592 593 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 594 #endif 595 596 /** 597 * DOC: smu_memory_pool_size (uint) 598 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 599 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 600 */ 601 MODULE_PARM_DESC(smu_memory_pool_size, 602 "reserve gtt for smu debug usage, 0 = disable," 603 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 604 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 605 606 /** 607 * DOC: async_gfx_ring (int) 608 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 609 */ 610 MODULE_PARM_DESC(async_gfx_ring, 611 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 612 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 613 614 /** 615 * DOC: mcbp (int) 616 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 617 */ 618 MODULE_PARM_DESC(mcbp, 619 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 620 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 621 622 /** 623 * DOC: discovery (int) 624 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 625 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 626 */ 627 MODULE_PARM_DESC(discovery, 628 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 629 module_param_named(discovery, amdgpu_discovery, int, 0444); 630 631 /** 632 * DOC: mes (int) 633 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 634 * (0 = disabled (default), 1 = enabled) 635 */ 636 MODULE_PARM_DESC(mes, 637 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 638 module_param_named(mes, amdgpu_mes, int, 0444); 639 640 /** 641 * DOC: mes_kiq (int) 642 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 643 * (0 = disabled (default), 1 = enabled) 644 */ 645 MODULE_PARM_DESC(mes_kiq, 646 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 647 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 648 649 /** 650 * DOC: noretry (int) 651 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 652 * do not support per-process XNACK this also disables retry page faults. 653 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 654 */ 655 MODULE_PARM_DESC(noretry, 656 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 657 module_param_named(noretry, amdgpu_noretry, int, 0644); 658 659 /** 660 * DOC: force_asic_type (int) 661 * A non negative value used to specify the asic type for all supported GPUs. 662 */ 663 MODULE_PARM_DESC(force_asic_type, 664 "A non negative value used to specify the asic type for all supported GPUs"); 665 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 666 667 /** 668 * DOC: use_xgmi_p2p (int) 669 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 670 */ 671 MODULE_PARM_DESC(use_xgmi_p2p, 672 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 673 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 674 675 676 #ifdef CONFIG_HSA_AMD 677 /** 678 * DOC: sched_policy (int) 679 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 680 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 681 * assigns queues to HQDs. 682 */ 683 int sched_policy = KFD_SCHED_POLICY_HWS; 684 module_param(sched_policy, int, 0444); 685 MODULE_PARM_DESC(sched_policy, 686 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 687 688 /** 689 * DOC: hws_max_conc_proc (int) 690 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 691 * number of VMIDs assigned to the HWS, which is also the default. 692 */ 693 int hws_max_conc_proc = -1; 694 module_param(hws_max_conc_proc, int, 0444); 695 MODULE_PARM_DESC(hws_max_conc_proc, 696 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 697 698 /** 699 * DOC: cwsr_enable (int) 700 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 701 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 702 * disables it. 703 */ 704 int cwsr_enable = 1; 705 module_param(cwsr_enable, int, 0444); 706 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 707 708 /** 709 * DOC: max_num_of_queues_per_device (int) 710 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 711 * is 4096. 712 */ 713 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 714 module_param(max_num_of_queues_per_device, int, 0444); 715 MODULE_PARM_DESC(max_num_of_queues_per_device, 716 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 717 718 /** 719 * DOC: send_sigterm (int) 720 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 721 * but just print errors on dmesg. Setting 1 enables sending sigterm. 722 */ 723 int send_sigterm; 724 module_param(send_sigterm, int, 0444); 725 MODULE_PARM_DESC(send_sigterm, 726 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 727 728 /** 729 * DOC: debug_largebar (int) 730 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 731 * system. This limits the VRAM size reported to ROCm applications to the visible 732 * size, usually 256MB. 733 * Default value is 0, diabled. 734 */ 735 int debug_largebar; 736 module_param(debug_largebar, int, 0444); 737 MODULE_PARM_DESC(debug_largebar, 738 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 739 740 /** 741 * DOC: ignore_crat (int) 742 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 743 * table to get information about AMD APUs. This option can serve as a workaround on 744 * systems with a broken CRAT table. 745 * 746 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 747 * whether use CRAT) 748 */ 749 int ignore_crat; 750 module_param(ignore_crat, int, 0444); 751 MODULE_PARM_DESC(ignore_crat, 752 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 753 754 /** 755 * DOC: halt_if_hws_hang (int) 756 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 757 * Setting 1 enables halt on hang. 758 */ 759 int halt_if_hws_hang; 760 module_param(halt_if_hws_hang, int, 0644); 761 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 762 763 /** 764 * DOC: hws_gws_support(bool) 765 * Assume that HWS supports GWS barriers regardless of what firmware version 766 * check says. Default value: false (rely on MEC2 firmware version check). 767 */ 768 bool hws_gws_support; 769 module_param(hws_gws_support, bool, 0444); 770 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 771 772 /** 773 * DOC: queue_preemption_timeout_ms (int) 774 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 775 */ 776 int queue_preemption_timeout_ms = 9000; 777 module_param(queue_preemption_timeout_ms, int, 0644); 778 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 779 780 /** 781 * DOC: debug_evictions(bool) 782 * Enable extra debug messages to help determine the cause of evictions 783 */ 784 bool debug_evictions; 785 module_param(debug_evictions, bool, 0644); 786 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 787 788 /** 789 * DOC: no_system_mem_limit(bool) 790 * Disable system memory limit, to support multiple process shared memory 791 */ 792 bool no_system_mem_limit; 793 module_param(no_system_mem_limit, bool, 0644); 794 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 795 796 /** 797 * DOC: no_queue_eviction_on_vm_fault (int) 798 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 799 */ 800 int amdgpu_no_queue_eviction_on_vm_fault = 0; 801 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 802 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 803 #endif 804 805 /** 806 * DOC: pcie_p2p (bool) 807 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 808 */ 809 #ifdef CONFIG_HSA_AMD_P2P 810 bool pcie_p2p = true; 811 module_param(pcie_p2p, bool, 0444); 812 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 813 #endif 814 815 /** 816 * DOC: dcfeaturemask (uint) 817 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 818 * The default is the current set of stable display features. 819 */ 820 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 821 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 822 823 /** 824 * DOC: dcdebugmask (uint) 825 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 826 */ 827 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 828 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 829 830 /** 831 * DOC: abmlevel (uint) 832 * Override the default ABM (Adaptive Backlight Management) level used for DC 833 * enabled hardware. Requires DMCU to be supported and loaded. 834 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 835 * default. Values 1-4 control the maximum allowable brightness reduction via 836 * the ABM algorithm, with 1 being the least reduction and 4 being the most 837 * reduction. 838 * 839 * Defaults to 0, or disabled. Userspace can still override this level later 840 * after boot. 841 */ 842 uint amdgpu_dm_abm_level; 843 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 844 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 845 846 int amdgpu_backlight = -1; 847 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 848 module_param_named(backlight, amdgpu_backlight, bint, 0444); 849 850 /** 851 * DOC: tmz (int) 852 * Trusted Memory Zone (TMZ) is a method to protect data being written 853 * to or read from memory. 854 * 855 * The default value: 0 (off). TODO: change to auto till it is completed. 856 */ 857 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 858 module_param_named(tmz, amdgpu_tmz, int, 0444); 859 860 /** 861 * DOC: reset_method (int) 862 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 863 */ 864 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 865 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 866 867 /** 868 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 869 * threshold value of faulty pages detected by RAS ECC, which may 870 * result in the GPU entering bad status when the number of total 871 * faulty pages by ECC exceeds the threshold value. 872 */ 873 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 874 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 875 876 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 877 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 878 879 /** 880 * DOC: vcnfw_log (int) 881 * Enable vcnfw log output for debugging, the default is disabled. 882 */ 883 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 884 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 885 886 /** 887 * DOC: smu_pptable_id (int) 888 * Used to override pptable id. id = 0 use VBIOS pptable. 889 * id > 0 use the soft pptable with specicfied id. 890 */ 891 MODULE_PARM_DESC(smu_pptable_id, 892 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 893 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 894 895 /* These devices are not supported by amdgpu. 896 * They are supported by the mach64, r128, radeon drivers 897 */ 898 static const u16 amdgpu_unsupported_pciidlist[] = { 899 /* mach64 */ 900 0x4354, 901 0x4358, 902 0x4554, 903 0x4742, 904 0x4744, 905 0x4749, 906 0x474C, 907 0x474D, 908 0x474E, 909 0x474F, 910 0x4750, 911 0x4751, 912 0x4752, 913 0x4753, 914 0x4754, 915 0x4755, 916 0x4756, 917 0x4757, 918 0x4758, 919 0x4759, 920 0x475A, 921 0x4C42, 922 0x4C44, 923 0x4C47, 924 0x4C49, 925 0x4C4D, 926 0x4C4E, 927 0x4C50, 928 0x4C51, 929 0x4C52, 930 0x4C53, 931 0x5654, 932 0x5655, 933 0x5656, 934 /* r128 */ 935 0x4c45, 936 0x4c46, 937 0x4d46, 938 0x4d4c, 939 0x5041, 940 0x5042, 941 0x5043, 942 0x5044, 943 0x5045, 944 0x5046, 945 0x5047, 946 0x5048, 947 0x5049, 948 0x504A, 949 0x504B, 950 0x504C, 951 0x504D, 952 0x504E, 953 0x504F, 954 0x5050, 955 0x5051, 956 0x5052, 957 0x5053, 958 0x5054, 959 0x5055, 960 0x5056, 961 0x5057, 962 0x5058, 963 0x5245, 964 0x5246, 965 0x5247, 966 0x524b, 967 0x524c, 968 0x534d, 969 0x5446, 970 0x544C, 971 0x5452, 972 /* radeon */ 973 0x3150, 974 0x3151, 975 0x3152, 976 0x3154, 977 0x3155, 978 0x3E50, 979 0x3E54, 980 0x4136, 981 0x4137, 982 0x4144, 983 0x4145, 984 0x4146, 985 0x4147, 986 0x4148, 987 0x4149, 988 0x414A, 989 0x414B, 990 0x4150, 991 0x4151, 992 0x4152, 993 0x4153, 994 0x4154, 995 0x4155, 996 0x4156, 997 0x4237, 998 0x4242, 999 0x4336, 1000 0x4337, 1001 0x4437, 1002 0x4966, 1003 0x4967, 1004 0x4A48, 1005 0x4A49, 1006 0x4A4A, 1007 0x4A4B, 1008 0x4A4C, 1009 0x4A4D, 1010 0x4A4E, 1011 0x4A4F, 1012 0x4A50, 1013 0x4A54, 1014 0x4B48, 1015 0x4B49, 1016 0x4B4A, 1017 0x4B4B, 1018 0x4B4C, 1019 0x4C57, 1020 0x4C58, 1021 0x4C59, 1022 0x4C5A, 1023 0x4C64, 1024 0x4C66, 1025 0x4C67, 1026 0x4E44, 1027 0x4E45, 1028 0x4E46, 1029 0x4E47, 1030 0x4E48, 1031 0x4E49, 1032 0x4E4A, 1033 0x4E4B, 1034 0x4E50, 1035 0x4E51, 1036 0x4E52, 1037 0x4E53, 1038 0x4E54, 1039 0x4E56, 1040 0x5144, 1041 0x5145, 1042 0x5146, 1043 0x5147, 1044 0x5148, 1045 0x514C, 1046 0x514D, 1047 0x5157, 1048 0x5158, 1049 0x5159, 1050 0x515A, 1051 0x515E, 1052 0x5460, 1053 0x5462, 1054 0x5464, 1055 0x5548, 1056 0x5549, 1057 0x554A, 1058 0x554B, 1059 0x554C, 1060 0x554D, 1061 0x554E, 1062 0x554F, 1063 0x5550, 1064 0x5551, 1065 0x5552, 1066 0x5554, 1067 0x564A, 1068 0x564B, 1069 0x564F, 1070 0x5652, 1071 0x5653, 1072 0x5657, 1073 0x5834, 1074 0x5835, 1075 0x5954, 1076 0x5955, 1077 0x5974, 1078 0x5975, 1079 0x5960, 1080 0x5961, 1081 0x5962, 1082 0x5964, 1083 0x5965, 1084 0x5969, 1085 0x5a41, 1086 0x5a42, 1087 0x5a61, 1088 0x5a62, 1089 0x5b60, 1090 0x5b62, 1091 0x5b63, 1092 0x5b64, 1093 0x5b65, 1094 0x5c61, 1095 0x5c63, 1096 0x5d48, 1097 0x5d49, 1098 0x5d4a, 1099 0x5d4c, 1100 0x5d4d, 1101 0x5d4e, 1102 0x5d4f, 1103 0x5d50, 1104 0x5d52, 1105 0x5d57, 1106 0x5e48, 1107 0x5e4a, 1108 0x5e4b, 1109 0x5e4c, 1110 0x5e4d, 1111 0x5e4f, 1112 0x6700, 1113 0x6701, 1114 0x6702, 1115 0x6703, 1116 0x6704, 1117 0x6705, 1118 0x6706, 1119 0x6707, 1120 0x6708, 1121 0x6709, 1122 0x6718, 1123 0x6719, 1124 0x671c, 1125 0x671d, 1126 0x671f, 1127 0x6720, 1128 0x6721, 1129 0x6722, 1130 0x6723, 1131 0x6724, 1132 0x6725, 1133 0x6726, 1134 0x6727, 1135 0x6728, 1136 0x6729, 1137 0x6738, 1138 0x6739, 1139 0x673e, 1140 0x6740, 1141 0x6741, 1142 0x6742, 1143 0x6743, 1144 0x6744, 1145 0x6745, 1146 0x6746, 1147 0x6747, 1148 0x6748, 1149 0x6749, 1150 0x674A, 1151 0x6750, 1152 0x6751, 1153 0x6758, 1154 0x6759, 1155 0x675B, 1156 0x675D, 1157 0x675F, 1158 0x6760, 1159 0x6761, 1160 0x6762, 1161 0x6763, 1162 0x6764, 1163 0x6765, 1164 0x6766, 1165 0x6767, 1166 0x6768, 1167 0x6770, 1168 0x6771, 1169 0x6772, 1170 0x6778, 1171 0x6779, 1172 0x677B, 1173 0x6840, 1174 0x6841, 1175 0x6842, 1176 0x6843, 1177 0x6849, 1178 0x684C, 1179 0x6850, 1180 0x6858, 1181 0x6859, 1182 0x6880, 1183 0x6888, 1184 0x6889, 1185 0x688A, 1186 0x688C, 1187 0x688D, 1188 0x6898, 1189 0x6899, 1190 0x689b, 1191 0x689c, 1192 0x689d, 1193 0x689e, 1194 0x68a0, 1195 0x68a1, 1196 0x68a8, 1197 0x68a9, 1198 0x68b0, 1199 0x68b8, 1200 0x68b9, 1201 0x68ba, 1202 0x68be, 1203 0x68bf, 1204 0x68c0, 1205 0x68c1, 1206 0x68c7, 1207 0x68c8, 1208 0x68c9, 1209 0x68d8, 1210 0x68d9, 1211 0x68da, 1212 0x68de, 1213 0x68e0, 1214 0x68e1, 1215 0x68e4, 1216 0x68e5, 1217 0x68e8, 1218 0x68e9, 1219 0x68f1, 1220 0x68f2, 1221 0x68f8, 1222 0x68f9, 1223 0x68fa, 1224 0x68fe, 1225 0x7100, 1226 0x7101, 1227 0x7102, 1228 0x7103, 1229 0x7104, 1230 0x7105, 1231 0x7106, 1232 0x7108, 1233 0x7109, 1234 0x710A, 1235 0x710B, 1236 0x710C, 1237 0x710E, 1238 0x710F, 1239 0x7140, 1240 0x7141, 1241 0x7142, 1242 0x7143, 1243 0x7144, 1244 0x7145, 1245 0x7146, 1246 0x7147, 1247 0x7149, 1248 0x714A, 1249 0x714B, 1250 0x714C, 1251 0x714D, 1252 0x714E, 1253 0x714F, 1254 0x7151, 1255 0x7152, 1256 0x7153, 1257 0x715E, 1258 0x715F, 1259 0x7180, 1260 0x7181, 1261 0x7183, 1262 0x7186, 1263 0x7187, 1264 0x7188, 1265 0x718A, 1266 0x718B, 1267 0x718C, 1268 0x718D, 1269 0x718F, 1270 0x7193, 1271 0x7196, 1272 0x719B, 1273 0x719F, 1274 0x71C0, 1275 0x71C1, 1276 0x71C2, 1277 0x71C3, 1278 0x71C4, 1279 0x71C5, 1280 0x71C6, 1281 0x71C7, 1282 0x71CD, 1283 0x71CE, 1284 0x71D2, 1285 0x71D4, 1286 0x71D5, 1287 0x71D6, 1288 0x71DA, 1289 0x71DE, 1290 0x7200, 1291 0x7210, 1292 0x7211, 1293 0x7240, 1294 0x7243, 1295 0x7244, 1296 0x7245, 1297 0x7246, 1298 0x7247, 1299 0x7248, 1300 0x7249, 1301 0x724A, 1302 0x724B, 1303 0x724C, 1304 0x724D, 1305 0x724E, 1306 0x724F, 1307 0x7280, 1308 0x7281, 1309 0x7283, 1310 0x7284, 1311 0x7287, 1312 0x7288, 1313 0x7289, 1314 0x728B, 1315 0x728C, 1316 0x7290, 1317 0x7291, 1318 0x7293, 1319 0x7297, 1320 0x7834, 1321 0x7835, 1322 0x791e, 1323 0x791f, 1324 0x793f, 1325 0x7941, 1326 0x7942, 1327 0x796c, 1328 0x796d, 1329 0x796e, 1330 0x796f, 1331 0x9400, 1332 0x9401, 1333 0x9402, 1334 0x9403, 1335 0x9405, 1336 0x940A, 1337 0x940B, 1338 0x940F, 1339 0x94A0, 1340 0x94A1, 1341 0x94A3, 1342 0x94B1, 1343 0x94B3, 1344 0x94B4, 1345 0x94B5, 1346 0x94B9, 1347 0x9440, 1348 0x9441, 1349 0x9442, 1350 0x9443, 1351 0x9444, 1352 0x9446, 1353 0x944A, 1354 0x944B, 1355 0x944C, 1356 0x944E, 1357 0x9450, 1358 0x9452, 1359 0x9456, 1360 0x945A, 1361 0x945B, 1362 0x945E, 1363 0x9460, 1364 0x9462, 1365 0x946A, 1366 0x946B, 1367 0x947A, 1368 0x947B, 1369 0x9480, 1370 0x9487, 1371 0x9488, 1372 0x9489, 1373 0x948A, 1374 0x948F, 1375 0x9490, 1376 0x9491, 1377 0x9495, 1378 0x9498, 1379 0x949C, 1380 0x949E, 1381 0x949F, 1382 0x94C0, 1383 0x94C1, 1384 0x94C3, 1385 0x94C4, 1386 0x94C5, 1387 0x94C6, 1388 0x94C7, 1389 0x94C8, 1390 0x94C9, 1391 0x94CB, 1392 0x94CC, 1393 0x94CD, 1394 0x9500, 1395 0x9501, 1396 0x9504, 1397 0x9505, 1398 0x9506, 1399 0x9507, 1400 0x9508, 1401 0x9509, 1402 0x950F, 1403 0x9511, 1404 0x9515, 1405 0x9517, 1406 0x9519, 1407 0x9540, 1408 0x9541, 1409 0x9542, 1410 0x954E, 1411 0x954F, 1412 0x9552, 1413 0x9553, 1414 0x9555, 1415 0x9557, 1416 0x955f, 1417 0x9580, 1418 0x9581, 1419 0x9583, 1420 0x9586, 1421 0x9587, 1422 0x9588, 1423 0x9589, 1424 0x958A, 1425 0x958B, 1426 0x958C, 1427 0x958D, 1428 0x958E, 1429 0x958F, 1430 0x9590, 1431 0x9591, 1432 0x9593, 1433 0x9595, 1434 0x9596, 1435 0x9597, 1436 0x9598, 1437 0x9599, 1438 0x959B, 1439 0x95C0, 1440 0x95C2, 1441 0x95C4, 1442 0x95C5, 1443 0x95C6, 1444 0x95C7, 1445 0x95C9, 1446 0x95CC, 1447 0x95CD, 1448 0x95CE, 1449 0x95CF, 1450 0x9610, 1451 0x9611, 1452 0x9612, 1453 0x9613, 1454 0x9614, 1455 0x9615, 1456 0x9616, 1457 0x9640, 1458 0x9641, 1459 0x9642, 1460 0x9643, 1461 0x9644, 1462 0x9645, 1463 0x9647, 1464 0x9648, 1465 0x9649, 1466 0x964a, 1467 0x964b, 1468 0x964c, 1469 0x964e, 1470 0x964f, 1471 0x9710, 1472 0x9711, 1473 0x9712, 1474 0x9713, 1475 0x9714, 1476 0x9715, 1477 0x9802, 1478 0x9803, 1479 0x9804, 1480 0x9805, 1481 0x9806, 1482 0x9807, 1483 0x9808, 1484 0x9809, 1485 0x980A, 1486 0x9900, 1487 0x9901, 1488 0x9903, 1489 0x9904, 1490 0x9905, 1491 0x9906, 1492 0x9907, 1493 0x9908, 1494 0x9909, 1495 0x990A, 1496 0x990B, 1497 0x990C, 1498 0x990D, 1499 0x990E, 1500 0x990F, 1501 0x9910, 1502 0x9913, 1503 0x9917, 1504 0x9918, 1505 0x9919, 1506 0x9990, 1507 0x9991, 1508 0x9992, 1509 0x9993, 1510 0x9994, 1511 0x9995, 1512 0x9996, 1513 0x9997, 1514 0x9998, 1515 0x9999, 1516 0x999A, 1517 0x999B, 1518 0x999C, 1519 0x999D, 1520 0x99A0, 1521 0x99A2, 1522 0x99A4, 1523 /* radeon secondary ids */ 1524 0x3171, 1525 0x3e70, 1526 0x4164, 1527 0x4165, 1528 0x4166, 1529 0x4168, 1530 0x4170, 1531 0x4171, 1532 0x4172, 1533 0x4173, 1534 0x496e, 1535 0x4a69, 1536 0x4a6a, 1537 0x4a6b, 1538 0x4a70, 1539 0x4a74, 1540 0x4b69, 1541 0x4b6b, 1542 0x4b6c, 1543 0x4c6e, 1544 0x4e64, 1545 0x4e65, 1546 0x4e66, 1547 0x4e67, 1548 0x4e68, 1549 0x4e69, 1550 0x4e6a, 1551 0x4e71, 1552 0x4f73, 1553 0x5569, 1554 0x556b, 1555 0x556d, 1556 0x556f, 1557 0x5571, 1558 0x5854, 1559 0x5874, 1560 0x5940, 1561 0x5941, 1562 0x5b72, 1563 0x5b73, 1564 0x5b74, 1565 0x5b75, 1566 0x5d44, 1567 0x5d45, 1568 0x5d6d, 1569 0x5d6f, 1570 0x5d72, 1571 0x5d77, 1572 0x5e6b, 1573 0x5e6d, 1574 0x7120, 1575 0x7124, 1576 0x7129, 1577 0x712e, 1578 0x712f, 1579 0x7162, 1580 0x7163, 1581 0x7166, 1582 0x7167, 1583 0x7172, 1584 0x7173, 1585 0x71a0, 1586 0x71a1, 1587 0x71a3, 1588 0x71a7, 1589 0x71bb, 1590 0x71e0, 1591 0x71e1, 1592 0x71e2, 1593 0x71e6, 1594 0x71e7, 1595 0x71f2, 1596 0x7269, 1597 0x726b, 1598 0x726e, 1599 0x72a0, 1600 0x72a8, 1601 0x72b1, 1602 0x72b3, 1603 0x793f, 1604 }; 1605 1606 static const struct pci_device_id pciidlist[] = { 1607 #ifdef CONFIG_DRM_AMDGPU_SI 1608 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1609 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1610 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1611 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1612 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1613 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1614 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1615 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1616 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1617 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1618 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1619 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1620 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1621 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1622 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1623 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1624 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1625 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1626 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1627 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1628 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1629 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1630 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1631 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1632 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1633 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1634 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1635 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1636 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1637 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1638 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1639 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1640 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1641 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1642 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1643 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1644 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1645 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1647 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1648 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1649 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1650 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1651 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1652 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1653 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1654 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1658 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1659 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1660 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1661 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1662 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1663 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1664 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1665 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1666 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1667 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1668 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1669 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1670 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1671 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1672 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1673 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1674 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1675 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1676 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1677 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1678 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1679 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1680 #endif 1681 #ifdef CONFIG_DRM_AMDGPU_CIK 1682 /* Kaveri */ 1683 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1684 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1685 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1686 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1687 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1688 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1689 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1690 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1691 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1692 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1693 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1694 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1695 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1696 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1697 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1698 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1699 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1700 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1701 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1702 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1703 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1704 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1705 /* Bonaire */ 1706 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1708 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1710 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1711 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1712 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1713 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1714 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1715 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1716 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1717 /* Hawaii */ 1718 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1719 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1720 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1721 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1722 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1723 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1724 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1725 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1726 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1727 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1728 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1729 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1730 /* Kabini */ 1731 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1733 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1735 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1736 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1737 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1739 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1742 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1743 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1744 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1745 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1746 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1747 /* mullins */ 1748 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1752 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1753 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1754 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1755 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1756 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1757 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1761 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1763 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1764 #endif 1765 /* topaz */ 1766 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1767 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1768 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1769 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1770 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1771 /* tonga */ 1772 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1773 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1774 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1775 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1776 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1777 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1778 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1779 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1780 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1781 /* fiji */ 1782 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1783 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1784 /* carrizo */ 1785 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1786 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1787 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1788 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1789 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1790 /* stoney */ 1791 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1792 /* Polaris11 */ 1793 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1794 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1795 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1796 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1797 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1798 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1799 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1800 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1801 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1802 /* Polaris10 */ 1803 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1804 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1805 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1806 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1807 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1808 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1809 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1810 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1811 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1812 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1813 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1814 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1815 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1816 /* Polaris12 */ 1817 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1818 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1819 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1820 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1821 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1822 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1823 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1824 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1825 /* VEGAM */ 1826 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1827 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1828 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1829 /* Vega 10 */ 1830 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1831 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1832 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1833 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1834 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1835 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1836 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1837 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1838 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1839 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1840 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1841 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1842 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1843 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1844 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1845 /* Vega 12 */ 1846 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1847 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1848 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1849 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1850 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1851 /* Vega 20 */ 1852 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1853 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1854 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1855 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1856 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1857 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1858 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1859 /* Raven */ 1860 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1861 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1862 /* Arcturus */ 1863 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1864 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1865 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1866 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1867 /* Navi10 */ 1868 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1869 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1870 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1871 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1872 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1873 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1874 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1875 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1876 /* Navi14 */ 1877 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1878 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1879 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1880 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1881 1882 /* Renoir */ 1883 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1884 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1885 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1886 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1887 1888 /* Navi12 */ 1889 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1890 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1891 1892 /* Sienna_Cichlid */ 1893 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1894 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1895 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1896 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1897 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1898 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1899 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1900 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1901 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1902 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1903 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1904 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1905 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1906 1907 /* Van Gogh */ 1908 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1909 1910 /* Yellow Carp */ 1911 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1912 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1913 1914 /* Navy_Flounder */ 1915 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1916 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1917 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1918 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1919 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1920 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1921 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1922 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1923 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1924 1925 /* DIMGREY_CAVEFISH */ 1926 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1927 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1928 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1929 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1930 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1931 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1932 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1933 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1934 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1935 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1936 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1937 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1938 1939 /* Aldebaran */ 1940 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1941 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1942 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1943 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1944 1945 /* CYAN_SKILLFISH */ 1946 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1947 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1948 1949 /* BEIGE_GOBY */ 1950 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1951 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1952 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1953 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1954 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1955 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1956 1957 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1958 .class = PCI_CLASS_DISPLAY_VGA << 8, 1959 .class_mask = 0xffffff, 1960 .driver_data = CHIP_IP_DISCOVERY }, 1961 1962 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1963 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1964 .class_mask = 0xffffff, 1965 .driver_data = CHIP_IP_DISCOVERY }, 1966 1967 {0, 0, 0} 1968 }; 1969 1970 MODULE_DEVICE_TABLE(pci, pciidlist); 1971 1972 static const struct drm_driver amdgpu_kms_driver; 1973 1974 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1975 { 1976 struct pci_dev *p = NULL; 1977 int i; 1978 1979 /* 0 - GPU 1980 * 1 - audio 1981 * 2 - USB 1982 * 3 - UCSI 1983 */ 1984 for (i = 1; i < 4; i++) { 1985 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1986 adev->pdev->bus->number, i); 1987 if (p) { 1988 pm_runtime_get_sync(&p->dev); 1989 pm_runtime_mark_last_busy(&p->dev); 1990 pm_runtime_put_autosuspend(&p->dev); 1991 pci_dev_put(p); 1992 } 1993 } 1994 } 1995 1996 static int amdgpu_pci_probe(struct pci_dev *pdev, 1997 const struct pci_device_id *ent) 1998 { 1999 struct drm_device *ddev; 2000 struct amdgpu_device *adev; 2001 unsigned long flags = ent->driver_data; 2002 int ret, retry = 0, i; 2003 bool supports_atomic = false; 2004 2005 /* skip devices which are owned by radeon */ 2006 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2007 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2008 return -ENODEV; 2009 } 2010 2011 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2012 amdgpu_aspm = 0; 2013 2014 if (amdgpu_virtual_display || 2015 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2016 supports_atomic = true; 2017 2018 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2019 DRM_INFO("This hardware requires experimental hardware support.\n" 2020 "See modparam exp_hw_support\n"); 2021 return -ENODEV; 2022 } 2023 2024 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2025 * however, SME requires an indirect IOMMU mapping because the encryption 2026 * bit is beyond the DMA mask of the chip. 2027 */ 2028 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2029 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2030 dev_info(&pdev->dev, 2031 "SME is not compatible with RAVEN\n"); 2032 return -ENOTSUPP; 2033 } 2034 2035 #ifdef CONFIG_DRM_AMDGPU_SI 2036 if (!amdgpu_si_support) { 2037 switch (flags & AMD_ASIC_MASK) { 2038 case CHIP_TAHITI: 2039 case CHIP_PITCAIRN: 2040 case CHIP_VERDE: 2041 case CHIP_OLAND: 2042 case CHIP_HAINAN: 2043 dev_info(&pdev->dev, 2044 "SI support provided by radeon.\n"); 2045 dev_info(&pdev->dev, 2046 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2047 ); 2048 return -ENODEV; 2049 } 2050 } 2051 #endif 2052 #ifdef CONFIG_DRM_AMDGPU_CIK 2053 if (!amdgpu_cik_support) { 2054 switch (flags & AMD_ASIC_MASK) { 2055 case CHIP_KAVERI: 2056 case CHIP_BONAIRE: 2057 case CHIP_HAWAII: 2058 case CHIP_KABINI: 2059 case CHIP_MULLINS: 2060 dev_info(&pdev->dev, 2061 "CIK support provided by radeon.\n"); 2062 dev_info(&pdev->dev, 2063 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2064 ); 2065 return -ENODEV; 2066 } 2067 } 2068 #endif 2069 2070 /* Get rid of things like offb */ 2071 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2072 if (ret) 2073 return ret; 2074 2075 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2076 if (IS_ERR(adev)) 2077 return PTR_ERR(adev); 2078 2079 adev->dev = &pdev->dev; 2080 adev->pdev = pdev; 2081 ddev = adev_to_drm(adev); 2082 2083 if (!supports_atomic) 2084 ddev->driver_features &= ~DRIVER_ATOMIC; 2085 2086 ret = pci_enable_device(pdev); 2087 if (ret) 2088 return ret; 2089 2090 pci_set_drvdata(pdev, ddev); 2091 2092 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2093 if (ret) 2094 goto err_pci; 2095 2096 retry_init: 2097 ret = drm_dev_register(ddev, ent->driver_data); 2098 if (ret == -EAGAIN && ++retry <= 3) { 2099 DRM_INFO("retry init %d\n", retry); 2100 /* Don't request EX mode too frequently which is attacking */ 2101 msleep(5000); 2102 goto retry_init; 2103 } else if (ret) { 2104 goto err_pci; 2105 } 2106 2107 /* 2108 * 1. don't init fbdev on hw without DCE 2109 * 2. don't init fbdev if there are no connectors 2110 */ 2111 if (adev->mode_info.mode_config_initialized && 2112 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2113 /* select 8 bpp console on low vram cards */ 2114 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2115 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2116 else 2117 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2118 } 2119 2120 ret = amdgpu_debugfs_init(adev); 2121 if (ret) 2122 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2123 2124 if (adev->runpm) { 2125 /* only need to skip on ATPX */ 2126 if (amdgpu_device_supports_px(ddev)) 2127 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2128 /* we want direct complete for BOCO */ 2129 if (amdgpu_device_supports_boco(ddev)) 2130 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2131 DPM_FLAG_SMART_SUSPEND | 2132 DPM_FLAG_MAY_SKIP_RESUME); 2133 pm_runtime_use_autosuspend(ddev->dev); 2134 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2135 2136 pm_runtime_allow(ddev->dev); 2137 2138 pm_runtime_mark_last_busy(ddev->dev); 2139 pm_runtime_put_autosuspend(ddev->dev); 2140 2141 /* 2142 * For runpm implemented via BACO, PMFW will handle the 2143 * timing for BACO in and out: 2144 * - put ASIC into BACO state only when both video and 2145 * audio functions are in D3 state. 2146 * - pull ASIC out of BACO state when either video or 2147 * audio function is in D0 state. 2148 * Also, at startup, PMFW assumes both functions are in 2149 * D0 state. 2150 * 2151 * So if snd driver was loaded prior to amdgpu driver 2152 * and audio function was put into D3 state, there will 2153 * be no PMFW-aware D-state transition(D0->D3) on runpm 2154 * suspend. Thus the BACO will be not correctly kicked in. 2155 * 2156 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2157 * into D0 state. Then there will be a PMFW-aware D-state 2158 * transition(D0->D3) on runpm suspend. 2159 */ 2160 if (amdgpu_device_supports_baco(ddev) && 2161 !(adev->flags & AMD_IS_APU) && 2162 (adev->asic_type >= CHIP_NAVI10)) 2163 amdgpu_get_secondary_funcs(adev); 2164 } 2165 2166 return 0; 2167 2168 err_pci: 2169 pci_disable_device(pdev); 2170 return ret; 2171 } 2172 2173 static void 2174 amdgpu_pci_remove(struct pci_dev *pdev) 2175 { 2176 struct drm_device *dev = pci_get_drvdata(pdev); 2177 struct amdgpu_device *adev = drm_to_adev(dev); 2178 2179 drm_dev_unplug(dev); 2180 2181 if (adev->runpm) { 2182 pm_runtime_get_sync(dev->dev); 2183 pm_runtime_forbid(dev->dev); 2184 } 2185 2186 amdgpu_driver_unload_kms(dev); 2187 2188 /* 2189 * Flush any in flight DMA operations from device. 2190 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2191 * StatusTransactions Pending bit. 2192 */ 2193 pci_disable_device(pdev); 2194 pci_wait_for_pending_transaction(pdev); 2195 } 2196 2197 static void 2198 amdgpu_pci_shutdown(struct pci_dev *pdev) 2199 { 2200 struct drm_device *dev = pci_get_drvdata(pdev); 2201 struct amdgpu_device *adev = drm_to_adev(dev); 2202 2203 if (amdgpu_ras_intr_triggered()) 2204 return; 2205 2206 /* if we are running in a VM, make sure the device 2207 * torn down properly on reboot/shutdown. 2208 * unfortunately we can't detect certain 2209 * hypervisors so just do this all the time. 2210 */ 2211 if (!amdgpu_passthrough(adev)) 2212 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2213 amdgpu_device_ip_suspend(adev); 2214 adev->mp1_state = PP_MP1_STATE_NONE; 2215 } 2216 2217 /** 2218 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2219 * 2220 * @work: work_struct. 2221 */ 2222 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2223 { 2224 struct list_head device_list; 2225 struct amdgpu_device *adev; 2226 int i, r; 2227 struct amdgpu_reset_context reset_context; 2228 2229 memset(&reset_context, 0, sizeof(reset_context)); 2230 2231 mutex_lock(&mgpu_info.mutex); 2232 if (mgpu_info.pending_reset == true) { 2233 mutex_unlock(&mgpu_info.mutex); 2234 return; 2235 } 2236 mgpu_info.pending_reset = true; 2237 mutex_unlock(&mgpu_info.mutex); 2238 2239 /* Use a common context, just need to make sure full reset is done */ 2240 reset_context.method = AMD_RESET_METHOD_NONE; 2241 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2242 2243 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2244 adev = mgpu_info.gpu_ins[i].adev; 2245 reset_context.reset_req_dev = adev; 2246 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2247 if (r) { 2248 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2249 r, adev_to_drm(adev)->unique); 2250 } 2251 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2252 r = -EALREADY; 2253 } 2254 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2255 adev = mgpu_info.gpu_ins[i].adev; 2256 flush_work(&adev->xgmi_reset_work); 2257 adev->gmc.xgmi.pending_reset = false; 2258 } 2259 2260 /* reset function will rebuild the xgmi hive info , clear it now */ 2261 for (i = 0; i < mgpu_info.num_dgpu; i++) 2262 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2263 2264 INIT_LIST_HEAD(&device_list); 2265 2266 for (i = 0; i < mgpu_info.num_dgpu; i++) 2267 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2268 2269 /* unregister the GPU first, reset function will add them back */ 2270 list_for_each_entry(adev, &device_list, reset_list) 2271 amdgpu_unregister_gpu_instance(adev); 2272 2273 /* Use a common context, just need to make sure full reset is done */ 2274 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2275 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2276 2277 if (r) { 2278 DRM_ERROR("reinit gpus failure"); 2279 return; 2280 } 2281 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2282 adev = mgpu_info.gpu_ins[i].adev; 2283 if (!adev->kfd.init_complete) 2284 amdgpu_amdkfd_device_init(adev); 2285 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2286 } 2287 return; 2288 } 2289 2290 static int amdgpu_pmops_prepare(struct device *dev) 2291 { 2292 struct drm_device *drm_dev = dev_get_drvdata(dev); 2293 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2294 2295 /* Return a positive number here so 2296 * DPM_FLAG_SMART_SUSPEND works properly 2297 */ 2298 if (amdgpu_device_supports_boco(drm_dev)) 2299 return pm_runtime_suspended(dev); 2300 2301 /* if we will not support s3 or s2i for the device 2302 * then skip suspend 2303 */ 2304 if (!amdgpu_acpi_is_s0ix_active(adev) && 2305 !amdgpu_acpi_is_s3_active(adev)) 2306 return 1; 2307 2308 return 0; 2309 } 2310 2311 static void amdgpu_pmops_complete(struct device *dev) 2312 { 2313 /* nothing to do */ 2314 } 2315 2316 static int amdgpu_pmops_suspend(struct device *dev) 2317 { 2318 struct drm_device *drm_dev = dev_get_drvdata(dev); 2319 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2320 2321 if (amdgpu_acpi_is_s0ix_active(adev)) 2322 adev->in_s0ix = true; 2323 else 2324 adev->in_s3 = true; 2325 return amdgpu_device_suspend(drm_dev, true); 2326 } 2327 2328 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2329 { 2330 struct drm_device *drm_dev = dev_get_drvdata(dev); 2331 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2332 2333 if (amdgpu_acpi_should_gpu_reset(adev)) 2334 return amdgpu_asic_reset(adev); 2335 2336 return 0; 2337 } 2338 2339 static int amdgpu_pmops_resume(struct device *dev) 2340 { 2341 struct drm_device *drm_dev = dev_get_drvdata(dev); 2342 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2343 int r; 2344 2345 /* Avoids registers access if device is physically gone */ 2346 if (!pci_device_is_present(adev->pdev)) 2347 adev->no_hw_access = true; 2348 2349 r = amdgpu_device_resume(drm_dev, true); 2350 if (amdgpu_acpi_is_s0ix_active(adev)) 2351 adev->in_s0ix = false; 2352 else 2353 adev->in_s3 = false; 2354 return r; 2355 } 2356 2357 static int amdgpu_pmops_freeze(struct device *dev) 2358 { 2359 struct drm_device *drm_dev = dev_get_drvdata(dev); 2360 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2361 int r; 2362 2363 adev->in_s4 = true; 2364 r = amdgpu_device_suspend(drm_dev, true); 2365 adev->in_s4 = false; 2366 if (r) 2367 return r; 2368 return amdgpu_asic_reset(adev); 2369 } 2370 2371 static int amdgpu_pmops_thaw(struct device *dev) 2372 { 2373 struct drm_device *drm_dev = dev_get_drvdata(dev); 2374 2375 return amdgpu_device_resume(drm_dev, true); 2376 } 2377 2378 static int amdgpu_pmops_poweroff(struct device *dev) 2379 { 2380 struct drm_device *drm_dev = dev_get_drvdata(dev); 2381 2382 return amdgpu_device_suspend(drm_dev, true); 2383 } 2384 2385 static int amdgpu_pmops_restore(struct device *dev) 2386 { 2387 struct drm_device *drm_dev = dev_get_drvdata(dev); 2388 2389 return amdgpu_device_resume(drm_dev, true); 2390 } 2391 2392 static int amdgpu_runtime_idle_check_display(struct device *dev) 2393 { 2394 struct pci_dev *pdev = to_pci_dev(dev); 2395 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2396 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2397 2398 if (adev->mode_info.num_crtc) { 2399 struct drm_connector *list_connector; 2400 struct drm_connector_list_iter iter; 2401 int ret = 0; 2402 2403 /* XXX: Return busy if any displays are connected to avoid 2404 * possible display wakeups after runtime resume due to 2405 * hotplug events in case any displays were connected while 2406 * the GPU was in suspend. Remove this once that is fixed. 2407 */ 2408 mutex_lock(&drm_dev->mode_config.mutex); 2409 drm_connector_list_iter_begin(drm_dev, &iter); 2410 drm_for_each_connector_iter(list_connector, &iter) { 2411 if (list_connector->status == connector_status_connected) { 2412 ret = -EBUSY; 2413 break; 2414 } 2415 } 2416 drm_connector_list_iter_end(&iter); 2417 mutex_unlock(&drm_dev->mode_config.mutex); 2418 2419 if (ret) 2420 return ret; 2421 2422 if (amdgpu_device_has_dc_support(adev)) { 2423 struct drm_crtc *crtc; 2424 2425 drm_for_each_crtc(crtc, drm_dev) { 2426 drm_modeset_lock(&crtc->mutex, NULL); 2427 if (crtc->state->active) 2428 ret = -EBUSY; 2429 drm_modeset_unlock(&crtc->mutex); 2430 if (ret < 0) 2431 break; 2432 } 2433 } else { 2434 mutex_lock(&drm_dev->mode_config.mutex); 2435 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2436 2437 drm_connector_list_iter_begin(drm_dev, &iter); 2438 drm_for_each_connector_iter(list_connector, &iter) { 2439 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2440 ret = -EBUSY; 2441 break; 2442 } 2443 } 2444 2445 drm_connector_list_iter_end(&iter); 2446 2447 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2448 mutex_unlock(&drm_dev->mode_config.mutex); 2449 } 2450 if (ret) 2451 return ret; 2452 } 2453 2454 return 0; 2455 } 2456 2457 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2458 { 2459 struct pci_dev *pdev = to_pci_dev(dev); 2460 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2461 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2462 int ret, i; 2463 2464 if (!adev->runpm) { 2465 pm_runtime_forbid(dev); 2466 return -EBUSY; 2467 } 2468 2469 ret = amdgpu_runtime_idle_check_display(dev); 2470 if (ret) 2471 return ret; 2472 2473 /* wait for all rings to drain before suspending */ 2474 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2475 struct amdgpu_ring *ring = adev->rings[i]; 2476 if (ring && ring->sched.ready) { 2477 ret = amdgpu_fence_wait_empty(ring); 2478 if (ret) 2479 return -EBUSY; 2480 } 2481 } 2482 2483 adev->in_runpm = true; 2484 if (amdgpu_device_supports_px(drm_dev)) 2485 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2486 2487 /* 2488 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2489 * proper cleanups and put itself into a state ready for PNP. That 2490 * can address some random resuming failure observed on BOCO capable 2491 * platforms. 2492 * TODO: this may be also needed for PX capable platform. 2493 */ 2494 if (amdgpu_device_supports_boco(drm_dev)) 2495 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2496 2497 ret = amdgpu_device_suspend(drm_dev, false); 2498 if (ret) { 2499 adev->in_runpm = false; 2500 if (amdgpu_device_supports_boco(drm_dev)) 2501 adev->mp1_state = PP_MP1_STATE_NONE; 2502 return ret; 2503 } 2504 2505 if (amdgpu_device_supports_boco(drm_dev)) 2506 adev->mp1_state = PP_MP1_STATE_NONE; 2507 2508 if (amdgpu_device_supports_px(drm_dev)) { 2509 /* Only need to handle PCI state in the driver for ATPX 2510 * PCI core handles it for _PR3. 2511 */ 2512 amdgpu_device_cache_pci_state(pdev); 2513 pci_disable_device(pdev); 2514 pci_ignore_hotplug(pdev); 2515 pci_set_power_state(pdev, PCI_D3cold); 2516 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2517 } else if (amdgpu_device_supports_boco(drm_dev)) { 2518 /* nothing to do */ 2519 } else if (amdgpu_device_supports_baco(drm_dev)) { 2520 amdgpu_device_baco_enter(drm_dev); 2521 } 2522 2523 return 0; 2524 } 2525 2526 static int amdgpu_pmops_runtime_resume(struct device *dev) 2527 { 2528 struct pci_dev *pdev = to_pci_dev(dev); 2529 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2530 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2531 int ret; 2532 2533 if (!adev->runpm) 2534 return -EINVAL; 2535 2536 /* Avoids registers access if device is physically gone */ 2537 if (!pci_device_is_present(adev->pdev)) 2538 adev->no_hw_access = true; 2539 2540 if (amdgpu_device_supports_px(drm_dev)) { 2541 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2542 2543 /* Only need to handle PCI state in the driver for ATPX 2544 * PCI core handles it for _PR3. 2545 */ 2546 pci_set_power_state(pdev, PCI_D0); 2547 amdgpu_device_load_pci_state(pdev); 2548 ret = pci_enable_device(pdev); 2549 if (ret) 2550 return ret; 2551 pci_set_master(pdev); 2552 } else if (amdgpu_device_supports_boco(drm_dev)) { 2553 /* Only need to handle PCI state in the driver for ATPX 2554 * PCI core handles it for _PR3. 2555 */ 2556 pci_set_master(pdev); 2557 } else if (amdgpu_device_supports_baco(drm_dev)) { 2558 amdgpu_device_baco_exit(drm_dev); 2559 } 2560 ret = amdgpu_device_resume(drm_dev, false); 2561 if (ret) 2562 return ret; 2563 2564 if (amdgpu_device_supports_px(drm_dev)) 2565 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2566 adev->in_runpm = false; 2567 return 0; 2568 } 2569 2570 static int amdgpu_pmops_runtime_idle(struct device *dev) 2571 { 2572 struct drm_device *drm_dev = dev_get_drvdata(dev); 2573 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2574 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2575 int ret = 1; 2576 2577 if (!adev->runpm) { 2578 pm_runtime_forbid(dev); 2579 return -EBUSY; 2580 } 2581 2582 ret = amdgpu_runtime_idle_check_display(dev); 2583 2584 pm_runtime_mark_last_busy(dev); 2585 pm_runtime_autosuspend(dev); 2586 return ret; 2587 } 2588 2589 long amdgpu_drm_ioctl(struct file *filp, 2590 unsigned int cmd, unsigned long arg) 2591 { 2592 struct drm_file *file_priv = filp->private_data; 2593 struct drm_device *dev; 2594 long ret; 2595 dev = file_priv->minor->dev; 2596 ret = pm_runtime_get_sync(dev->dev); 2597 if (ret < 0) 2598 goto out; 2599 2600 ret = drm_ioctl(filp, cmd, arg); 2601 2602 pm_runtime_mark_last_busy(dev->dev); 2603 out: 2604 pm_runtime_put_autosuspend(dev->dev); 2605 return ret; 2606 } 2607 2608 static const struct dev_pm_ops amdgpu_pm_ops = { 2609 .prepare = amdgpu_pmops_prepare, 2610 .complete = amdgpu_pmops_complete, 2611 .suspend = amdgpu_pmops_suspend, 2612 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2613 .resume = amdgpu_pmops_resume, 2614 .freeze = amdgpu_pmops_freeze, 2615 .thaw = amdgpu_pmops_thaw, 2616 .poweroff = amdgpu_pmops_poweroff, 2617 .restore = amdgpu_pmops_restore, 2618 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2619 .runtime_resume = amdgpu_pmops_runtime_resume, 2620 .runtime_idle = amdgpu_pmops_runtime_idle, 2621 }; 2622 2623 static int amdgpu_flush(struct file *f, fl_owner_t id) 2624 { 2625 struct drm_file *file_priv = f->private_data; 2626 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2627 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2628 2629 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2630 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2631 2632 return timeout >= 0 ? 0 : timeout; 2633 } 2634 2635 static const struct file_operations amdgpu_driver_kms_fops = { 2636 .owner = THIS_MODULE, 2637 .open = drm_open, 2638 .flush = amdgpu_flush, 2639 .release = drm_release, 2640 .unlocked_ioctl = amdgpu_drm_ioctl, 2641 .mmap = drm_gem_mmap, 2642 .poll = drm_poll, 2643 .read = drm_read, 2644 #ifdef CONFIG_COMPAT 2645 .compat_ioctl = amdgpu_kms_compat_ioctl, 2646 #endif 2647 #ifdef CONFIG_PROC_FS 2648 .show_fdinfo = amdgpu_show_fdinfo 2649 #endif 2650 }; 2651 2652 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2653 { 2654 struct drm_file *file; 2655 2656 if (!filp) 2657 return -EINVAL; 2658 2659 if (filp->f_op != &amdgpu_driver_kms_fops) { 2660 return -EINVAL; 2661 } 2662 2663 file = filp->private_data; 2664 *fpriv = file->driver_priv; 2665 return 0; 2666 } 2667 2668 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2669 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2670 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2671 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2672 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2673 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2674 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2675 /* KMS */ 2676 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2677 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2678 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2679 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2680 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2681 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2682 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2683 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2684 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2685 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2686 }; 2687 2688 static const struct drm_driver amdgpu_kms_driver = { 2689 .driver_features = 2690 DRIVER_ATOMIC | 2691 DRIVER_GEM | 2692 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2693 DRIVER_SYNCOBJ_TIMELINE, 2694 .open = amdgpu_driver_open_kms, 2695 .postclose = amdgpu_driver_postclose_kms, 2696 .lastclose = amdgpu_driver_lastclose_kms, 2697 .ioctls = amdgpu_ioctls_kms, 2698 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2699 .dumb_create = amdgpu_mode_dumb_create, 2700 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2701 .fops = &amdgpu_driver_kms_fops, 2702 .release = &amdgpu_driver_release_kms, 2703 2704 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2705 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2706 .gem_prime_import = amdgpu_gem_prime_import, 2707 .gem_prime_mmap = drm_gem_prime_mmap, 2708 2709 .name = DRIVER_NAME, 2710 .desc = DRIVER_DESC, 2711 .date = DRIVER_DATE, 2712 .major = KMS_DRIVER_MAJOR, 2713 .minor = KMS_DRIVER_MINOR, 2714 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2715 }; 2716 2717 static struct pci_error_handlers amdgpu_pci_err_handler = { 2718 .error_detected = amdgpu_pci_error_detected, 2719 .mmio_enabled = amdgpu_pci_mmio_enabled, 2720 .slot_reset = amdgpu_pci_slot_reset, 2721 .resume = amdgpu_pci_resume, 2722 }; 2723 2724 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2725 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2726 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2727 2728 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2729 &amdgpu_vram_mgr_attr_group, 2730 &amdgpu_gtt_mgr_attr_group, 2731 &amdgpu_vbios_version_attr_group, 2732 NULL, 2733 }; 2734 2735 2736 static struct pci_driver amdgpu_kms_pci_driver = { 2737 .name = DRIVER_NAME, 2738 .id_table = pciidlist, 2739 .probe = amdgpu_pci_probe, 2740 .remove = amdgpu_pci_remove, 2741 .shutdown = amdgpu_pci_shutdown, 2742 .driver.pm = &amdgpu_pm_ops, 2743 .err_handler = &amdgpu_pci_err_handler, 2744 .dev_groups = amdgpu_sysfs_groups, 2745 }; 2746 2747 static int __init amdgpu_init(void) 2748 { 2749 int r; 2750 2751 if (drm_firmware_drivers_only()) 2752 return -EINVAL; 2753 2754 r = amdgpu_sync_init(); 2755 if (r) 2756 goto error_sync; 2757 2758 r = amdgpu_fence_slab_init(); 2759 if (r) 2760 goto error_fence; 2761 2762 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2763 amdgpu_register_atpx_handler(); 2764 amdgpu_acpi_detect(); 2765 2766 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2767 amdgpu_amdkfd_init(); 2768 2769 /* let modprobe override vga console setting */ 2770 return pci_register_driver(&amdgpu_kms_pci_driver); 2771 2772 error_fence: 2773 amdgpu_sync_fini(); 2774 2775 error_sync: 2776 return r; 2777 } 2778 2779 static void __exit amdgpu_exit(void) 2780 { 2781 amdgpu_amdkfd_fini(); 2782 pci_unregister_driver(&amdgpu_kms_pci_driver); 2783 amdgpu_unregister_atpx_handler(); 2784 amdgpu_sync_fini(); 2785 amdgpu_fence_slab_fini(); 2786 mmu_notifier_synchronize(); 2787 } 2788 2789 module_init(amdgpu_init); 2790 module_exit(amdgpu_exit); 2791 2792 MODULE_AUTHOR(DRIVER_AUTHOR); 2793 MODULE_DESCRIPTION(DRIVER_DESC); 2794 MODULE_LICENSE("GPL and additional rights"); 2795