1 /*
2  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_fbdev_generic.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_vblank.h>
30 #include <drm/drm_managed.h>
31 #include "amdgpu_drv.h"
32 
33 #include <drm/drm_pciids.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/cc_platform.h>
41 #include <linux/dynamic_debug.h>
42 
43 #include "amdgpu.h"
44 #include "amdgpu_irq.h"
45 #include "amdgpu_dma_buf.h"
46 #include "amdgpu_sched.h"
47 #include "amdgpu_fdinfo.h"
48 #include "amdgpu_amdkfd.h"
49 
50 #include "amdgpu_ras.h"
51 #include "amdgpu_xgmi.h"
52 #include "amdgpu_reset.h"
53 
54 /*
55  * KMS wrapper.
56  * - 3.0.0 - initial driver
57  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
58  * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
59  *           at the end of IBs.
60  * - 3.3.0 - Add VM support for UVD on supported hardware.
61  * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
62  * - 3.5.0 - Add support for new UVD_NO_OP register.
63  * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
64  * - 3.7.0 - Add support for VCE clock list packet
65  * - 3.8.0 - Add support raster config init in the kernel
66  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
67  * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
68  * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
69  * - 3.12.0 - Add query for double offchip LDS buffers
70  * - 3.13.0 - Add PRT support
71  * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
72  * - 3.15.0 - Export more gpu info for gfx9
73  * - 3.16.0 - Add reserved vmid support
74  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
75  * - 3.18.0 - Export gpu always on cu bitmap
76  * - 3.19.0 - Add support for UVD MJPEG decode
77  * - 3.20.0 - Add support for local BOs
78  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
79  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
80  * - 3.23.0 - Add query for VRAM lost counter
81  * - 3.24.0 - Add high priority compute support for gfx9
82  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
83  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
84  * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
85  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
86  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
87  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
88  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
89  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
90  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
91  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
92  * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
93  * - 3.36.0 - Allow reading more status registers on si/cik
94  * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
95  * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
96  * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
97  * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
98  * - 3.41.0 - Add video codec query
99  * - 3.42.0 - Add 16bpc fixed point display support
100  * - 3.43.0 - Add device hot plug/unplug support
101  * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
102  * - 3.45.0 - Add context ioctl stable pstate interface
103  * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
104  * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
105  * - 3.48.0 - Add IP discovery version info to HW INFO
106  * - 3.49.0 - Add gang submit into CS IOCTL
107  * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
108  *            Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
109  *   3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
110  *   3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
111  *            tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
112  *            gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
113  */
114 #define KMS_DRIVER_MAJOR	3
115 #define KMS_DRIVER_MINOR	52
116 #define KMS_DRIVER_PATCHLEVEL	0
117 
118 unsigned int amdgpu_vram_limit = UINT_MAX;
119 int amdgpu_vis_vram_limit;
120 int amdgpu_gart_size = -1; /* auto */
121 int amdgpu_gtt_size = -1; /* auto */
122 int amdgpu_moverate = -1; /* auto */
123 int amdgpu_audio = -1;
124 int amdgpu_disp_priority;
125 int amdgpu_hw_i2c;
126 int amdgpu_pcie_gen2 = -1;
127 int amdgpu_msi = -1;
128 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
129 int amdgpu_dpm = -1;
130 int amdgpu_fw_load_type = -1;
131 int amdgpu_aspm = -1;
132 int amdgpu_runtime_pm = -1;
133 uint amdgpu_ip_block_mask = 0xffffffff;
134 int amdgpu_bapm = -1;
135 int amdgpu_deep_color;
136 int amdgpu_vm_size = -1;
137 int amdgpu_vm_fragment_size = -1;
138 int amdgpu_vm_block_size = -1;
139 int amdgpu_vm_fault_stop;
140 int amdgpu_vm_debug;
141 int amdgpu_vm_update_mode = -1;
142 int amdgpu_exp_hw_support;
143 int amdgpu_dc = -1;
144 int amdgpu_sched_jobs = 32;
145 int amdgpu_sched_hw_submission = 2;
146 uint amdgpu_pcie_gen_cap;
147 uint amdgpu_pcie_lane_cap;
148 u64 amdgpu_cg_mask = 0xffffffffffffffff;
149 uint amdgpu_pg_mask = 0xffffffff;
150 uint amdgpu_sdma_phase_quantum = 32;
151 char *amdgpu_disable_cu;
152 char *amdgpu_virtual_display;
153 
154 /*
155  * OverDrive(bit 14) disabled by default
156  * GFX DCS(bit 19) disabled by default
157  */
158 uint amdgpu_pp_feature_mask = 0xfff7bfff;
159 uint amdgpu_force_long_training;
160 int amdgpu_lbpw = -1;
161 int amdgpu_compute_multipipe = -1;
162 int amdgpu_gpu_recovery = -1; /* auto */
163 int amdgpu_emu_mode;
164 uint amdgpu_smu_memory_pool_size;
165 int amdgpu_smu_pptable_id = -1;
166 /*
167  * FBC (bit 0) disabled by default
168  * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
169  *   - With this, for multiple monitors in sync(e.g. with the same model),
170  *     mclk switching will be allowed. And the mclk will be not foced to the
171  *     highest. That helps saving some idle power.
172  * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
173  * PSR (bit 3) disabled by default
174  * EDP NO POWER SEQUENCING (bit 4) disabled by default
175  */
176 uint amdgpu_dc_feature_mask = 2;
177 uint amdgpu_dc_debug_mask;
178 uint amdgpu_dc_visual_confirm;
179 int amdgpu_async_gfx_ring = 1;
180 int amdgpu_mcbp;
181 int amdgpu_discovery = -1;
182 int amdgpu_mes;
183 int amdgpu_mes_kiq;
184 int amdgpu_noretry = -1;
185 int amdgpu_force_asic_type = -1;
186 int amdgpu_tmz = -1; /* auto */
187 uint amdgpu_freesync_vid_mode;
188 int amdgpu_reset_method = -1; /* auto */
189 int amdgpu_num_kcq = -1;
190 int amdgpu_smartshift_bias;
191 int amdgpu_use_xgmi_p2p = 1;
192 int amdgpu_vcnfw_log;
193 int amdgpu_sg_display = -1; /* auto */
194 
195 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
196 
197 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
198 			"DRM_UT_CORE",
199 			"DRM_UT_DRIVER",
200 			"DRM_UT_KMS",
201 			"DRM_UT_PRIME",
202 			"DRM_UT_ATOMIC",
203 			"DRM_UT_VBL",
204 			"DRM_UT_STATE",
205 			"DRM_UT_LEASE",
206 			"DRM_UT_DP",
207 			"DRM_UT_DRMRES");
208 
209 struct amdgpu_mgpu_info mgpu_info = {
210 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
211 	.delayed_reset_work = __DELAYED_WORK_INITIALIZER(
212 			mgpu_info.delayed_reset_work,
213 			amdgpu_drv_delayed_reset_work_handler, 0),
214 };
215 int amdgpu_ras_enable = -1;
216 uint amdgpu_ras_mask = 0xffffffff;
217 int amdgpu_bad_page_threshold = -1;
218 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
219 	.timeout_fatal_disable = false,
220 	.period = 0x0, /* default to 0x0 (timeout disable) */
221 };
222 
223 /**
224  * DOC: vramlimit (int)
225  * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
226  */
227 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
228 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
229 
230 /**
231  * DOC: vis_vramlimit (int)
232  * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visible VRAM).
233  */
234 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
235 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
236 
237 /**
238  * DOC: gartsize (uint)
239  * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
240  * The default is -1 (The size depends on asic).
241  */
242 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
243 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
244 
245 /**
246  * DOC: gttsize (int)
247  * Restrict the size of GTT domain (for userspace use) in MiB for testing.
248  * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
249  */
250 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
251 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
252 
253 /**
254  * DOC: moverate (int)
255  * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
256  */
257 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
258 module_param_named(moverate, amdgpu_moverate, int, 0600);
259 
260 /**
261  * DOC: audio (int)
262  * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
263  */
264 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
265 module_param_named(audio, amdgpu_audio, int, 0444);
266 
267 /**
268  * DOC: disp_priority (int)
269  * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
270  */
271 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
272 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
273 
274 /**
275  * DOC: hw_i2c (int)
276  * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
277  */
278 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
279 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
280 
281 /**
282  * DOC: pcie_gen2 (int)
283  * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
284  */
285 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
286 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
287 
288 /**
289  * DOC: msi (int)
290  * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
291  */
292 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
293 module_param_named(msi, amdgpu_msi, int, 0444);
294 
295 /**
296  * DOC: lockup_timeout (string)
297  * Set GPU scheduler timeout value in ms.
298  *
299  * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
300  * multiple values specified. 0 and negative values are invalidated. They will be adjusted
301  * to the default timeout.
302  *
303  * - With one value specified, the setting will apply to all non-compute jobs.
304  * - With multiple values specified, the first one will be for GFX.
305  *   The second one is for Compute. The third and fourth ones are
306  *   for SDMA and Video.
307  *
308  * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
309  * jobs is 10000. The timeout for compute is 60000.
310  */
311 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
312 		"for passthrough or sriov, 10000 for all jobs."
313 		" 0: keep default value. negative: infinity timeout), "
314 		"format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
315 		"for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
316 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
317 
318 /**
319  * DOC: dpm (int)
320  * Override for dynamic power management setting
321  * (0 = disable, 1 = enable)
322  * The default is -1 (auto).
323  */
324 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
325 module_param_named(dpm, amdgpu_dpm, int, 0444);
326 
327 /**
328  * DOC: fw_load_type (int)
329  * Set different firmware loading type for debugging, if supported.
330  * Set to 0 to force direct loading if supported by the ASIC.  Set
331  * to -1 to select the default loading mode for the ASIC, as defined
332  * by the driver.  The default is -1 (auto).
333  */
334 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
335 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
336 
337 /**
338  * DOC: aspm (int)
339  * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
340  */
341 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
342 module_param_named(aspm, amdgpu_aspm, int, 0444);
343 
344 /**
345  * DOC: runpm (int)
346  * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
347  * the dGPUs when they are idle if supported. The default is -1 (auto enable).
348  * Setting the value to 0 disables this functionality.
349  */
350 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
351 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
352 
353 /**
354  * DOC: ip_block_mask (uint)
355  * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
356  * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
357  * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
358  * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
359  */
360 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
361 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
362 
363 /**
364  * DOC: bapm (int)
365  * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
366  * The default -1 (auto, enabled)
367  */
368 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
369 module_param_named(bapm, amdgpu_bapm, int, 0444);
370 
371 /**
372  * DOC: deep_color (int)
373  * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
374  */
375 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
376 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
377 
378 /**
379  * DOC: vm_size (int)
380  * Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (automatic for each asic).
381  */
382 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
383 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
384 
385 /**
386  * DOC: vm_fragment_size (int)
387  * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
388  */
389 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
390 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
391 
392 /**
393  * DOC: vm_block_size (int)
394  * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
395  */
396 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
397 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
398 
399 /**
400  * DOC: vm_fault_stop (int)
401  * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
402  */
403 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
404 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
405 
406 /**
407  * DOC: vm_debug (int)
408  * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
409  */
410 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
411 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
412 
413 /**
414  * DOC: vm_update_mode (int)
415  * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
416  * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
417  */
418 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
419 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
420 
421 /**
422  * DOC: exp_hw_support (int)
423  * Enable experimental hw support (1 = enable). The default is 0 (disabled).
424  */
425 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
426 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
427 
428 /**
429  * DOC: dc (int)
430  * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
431  */
432 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
433 module_param_named(dc, amdgpu_dc, int, 0444);
434 
435 /**
436  * DOC: sched_jobs (int)
437  * Override the max number of jobs supported in the sw queue. The default is 32.
438  */
439 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
440 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
441 
442 /**
443  * DOC: sched_hw_submission (int)
444  * Override the max number of HW submissions. The default is 2.
445  */
446 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
447 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
448 
449 /**
450  * DOC: ppfeaturemask (hexint)
451  * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
452  * The default is the current set of stable power features.
453  */
454 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
455 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
456 
457 /**
458  * DOC: forcelongtraining (uint)
459  * Force long memory training in resume.
460  * The default is zero, indicates short training in resume.
461  */
462 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
463 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
464 
465 /**
466  * DOC: pcie_gen_cap (uint)
467  * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
468  * The default is 0 (automatic for each asic).
469  */
470 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
471 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
472 
473 /**
474  * DOC: pcie_lane_cap (uint)
475  * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
476  * The default is 0 (automatic for each asic).
477  */
478 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
479 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
480 
481 /**
482  * DOC: cg_mask (ullong)
483  * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
484  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
485  */
486 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
487 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
488 
489 /**
490  * DOC: pg_mask (uint)
491  * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
492  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
493  */
494 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
495 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
496 
497 /**
498  * DOC: sdma_phase_quantum (uint)
499  * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
500  */
501 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
502 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
503 
504 /**
505  * DOC: disable_cu (charp)
506  * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
507  */
508 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
509 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
510 
511 /**
512  * DOC: virtual_display (charp)
513  * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
514  * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
515  * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
516  * device at 26:00.0. The default is NULL.
517  */
518 MODULE_PARM_DESC(virtual_display,
519 		 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
520 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
521 
522 /**
523  * DOC: lbpw (int)
524  * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
525  */
526 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
527 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
528 
529 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
530 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
531 
532 /**
533  * DOC: gpu_recovery (int)
534  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
535  */
536 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
537 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
538 
539 /**
540  * DOC: emu_mode (int)
541  * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
542  */
543 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
544 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
545 
546 /**
547  * DOC: ras_enable (int)
548  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
549  */
550 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
551 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
552 
553 /**
554  * DOC: ras_mask (uint)
555  * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
556  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
557  */
558 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
559 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
560 
561 /**
562  * DOC: timeout_fatal_disable (bool)
563  * Disable Watchdog timeout fatal error event
564  */
565 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
566 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
567 
568 /**
569  * DOC: timeout_period (uint)
570  * Modify the watchdog timeout max_cycles as (1 << period)
571  */
572 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
573 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
574 
575 /**
576  * DOC: si_support (int)
577  * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
578  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
579  * otherwise using amdgpu driver.
580  */
581 #ifdef CONFIG_DRM_AMDGPU_SI
582 
583 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
584 int amdgpu_si_support = 0;
585 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
586 #else
587 int amdgpu_si_support = 1;
588 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
589 #endif
590 
591 module_param_named(si_support, amdgpu_si_support, int, 0444);
592 #endif
593 
594 /**
595  * DOC: cik_support (int)
596  * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
597  * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
598  * otherwise using amdgpu driver.
599  */
600 #ifdef CONFIG_DRM_AMDGPU_CIK
601 
602 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
603 int amdgpu_cik_support = 0;
604 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
605 #else
606 int amdgpu_cik_support = 1;
607 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
608 #endif
609 
610 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
611 #endif
612 
613 /**
614  * DOC: smu_memory_pool_size (uint)
615  * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
616  * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
617  */
618 MODULE_PARM_DESC(smu_memory_pool_size,
619 	"reserve gtt for smu debug usage, 0 = disable,"
620 		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
621 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
622 
623 /**
624  * DOC: async_gfx_ring (int)
625  * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
626  */
627 MODULE_PARM_DESC(async_gfx_ring,
628 	"Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
629 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
630 
631 /**
632  * DOC: mcbp (int)
633  * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
634  */
635 MODULE_PARM_DESC(mcbp,
636 	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
637 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
638 
639 /**
640  * DOC: discovery (int)
641  * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
642  * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
643  */
644 MODULE_PARM_DESC(discovery,
645 	"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
646 module_param_named(discovery, amdgpu_discovery, int, 0444);
647 
648 /**
649  * DOC: mes (int)
650  * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
651  * (0 = disabled (default), 1 = enabled)
652  */
653 MODULE_PARM_DESC(mes,
654 	"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
655 module_param_named(mes, amdgpu_mes, int, 0444);
656 
657 /**
658  * DOC: mes_kiq (int)
659  * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
660  * (0 = disabled (default), 1 = enabled)
661  */
662 MODULE_PARM_DESC(mes_kiq,
663 	"Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
664 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
665 
666 /**
667  * DOC: noretry (int)
668  * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
669  * do not support per-process XNACK this also disables retry page faults.
670  * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
671  */
672 MODULE_PARM_DESC(noretry,
673 	"Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
674 module_param_named(noretry, amdgpu_noretry, int, 0644);
675 
676 /**
677  * DOC: force_asic_type (int)
678  * A non negative value used to specify the asic type for all supported GPUs.
679  */
680 MODULE_PARM_DESC(force_asic_type,
681 	"A non negative value used to specify the asic type for all supported GPUs");
682 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
683 
684 /**
685  * DOC: use_xgmi_p2p (int)
686  * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
687  */
688 MODULE_PARM_DESC(use_xgmi_p2p,
689 	"Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
690 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
691 
692 
693 #ifdef CONFIG_HSA_AMD
694 /**
695  * DOC: sched_policy (int)
696  * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
697  * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
698  * assigns queues to HQDs.
699  */
700 int sched_policy = KFD_SCHED_POLICY_HWS;
701 module_param(sched_policy, int, 0444);
702 MODULE_PARM_DESC(sched_policy,
703 	"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
704 
705 /**
706  * DOC: hws_max_conc_proc (int)
707  * Maximum number of processes that HWS can schedule concurrently. The maximum is the
708  * number of VMIDs assigned to the HWS, which is also the default.
709  */
710 int hws_max_conc_proc = -1;
711 module_param(hws_max_conc_proc, int, 0444);
712 MODULE_PARM_DESC(hws_max_conc_proc,
713 	"Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
714 
715 /**
716  * DOC: cwsr_enable (int)
717  * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
718  * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
719  * disables it.
720  */
721 int cwsr_enable = 1;
722 module_param(cwsr_enable, int, 0444);
723 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
724 
725 /**
726  * DOC: max_num_of_queues_per_device (int)
727  * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
728  * is 4096.
729  */
730 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
731 module_param(max_num_of_queues_per_device, int, 0444);
732 MODULE_PARM_DESC(max_num_of_queues_per_device,
733 	"Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
734 
735 /**
736  * DOC: send_sigterm (int)
737  * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
738  * but just print errors on dmesg. Setting 1 enables sending sigterm.
739  */
740 int send_sigterm;
741 module_param(send_sigterm, int, 0444);
742 MODULE_PARM_DESC(send_sigterm,
743 	"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
744 
745 /**
746  * DOC: debug_largebar (int)
747  * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
748  * system. This limits the VRAM size reported to ROCm applications to the visible
749  * size, usually 256MB.
750  * Default value is 0, diabled.
751  */
752 int debug_largebar;
753 module_param(debug_largebar, int, 0444);
754 MODULE_PARM_DESC(debug_largebar,
755 	"Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
756 
757 /**
758  * DOC: ignore_crat (int)
759  * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
760  * table to get information about AMD APUs. This option can serve as a workaround on
761  * systems with a broken CRAT table.
762  *
763  * Default is auto (according to asic type, iommu_v2, and crat table, to decide
764  * whether use CRAT)
765  */
766 int ignore_crat;
767 module_param(ignore_crat, int, 0444);
768 MODULE_PARM_DESC(ignore_crat,
769 	"Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
770 
771 /**
772  * DOC: halt_if_hws_hang (int)
773  * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
774  * Setting 1 enables halt on hang.
775  */
776 int halt_if_hws_hang;
777 module_param(halt_if_hws_hang, int, 0644);
778 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
779 
780 /**
781  * DOC: hws_gws_support(bool)
782  * Assume that HWS supports GWS barriers regardless of what firmware version
783  * check says. Default value: false (rely on MEC2 firmware version check).
784  */
785 bool hws_gws_support;
786 module_param(hws_gws_support, bool, 0444);
787 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
788 
789 /**
790   * DOC: queue_preemption_timeout_ms (int)
791   * queue preemption timeout in ms (1 = Minimum, 9000 = default)
792   */
793 int queue_preemption_timeout_ms = 9000;
794 module_param(queue_preemption_timeout_ms, int, 0644);
795 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
796 
797 /**
798  * DOC: debug_evictions(bool)
799  * Enable extra debug messages to help determine the cause of evictions
800  */
801 bool debug_evictions;
802 module_param(debug_evictions, bool, 0644);
803 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
804 
805 /**
806  * DOC: no_system_mem_limit(bool)
807  * Disable system memory limit, to support multiple process shared memory
808  */
809 bool no_system_mem_limit;
810 module_param(no_system_mem_limit, bool, 0644);
811 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
812 
813 /**
814  * DOC: no_queue_eviction_on_vm_fault (int)
815  * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
816  */
817 int amdgpu_no_queue_eviction_on_vm_fault;
818 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
819 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
820 #endif
821 
822 /**
823  * DOC: pcie_p2p (bool)
824  * Enable PCIe P2P (requires large-BAR). Default value: true (on)
825  */
826 #ifdef CONFIG_HSA_AMD_P2P
827 bool pcie_p2p = true;
828 module_param(pcie_p2p, bool, 0444);
829 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
830 #endif
831 
832 /**
833  * DOC: dcfeaturemask (uint)
834  * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
835  * The default is the current set of stable display features.
836  */
837 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
838 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
839 
840 /**
841  * DOC: dcdebugmask (uint)
842  * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
843  */
844 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
845 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
846 
847 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
848 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
849 
850 /**
851  * DOC: abmlevel (uint)
852  * Override the default ABM (Adaptive Backlight Management) level used for DC
853  * enabled hardware. Requires DMCU to be supported and loaded.
854  * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
855  * default. Values 1-4 control the maximum allowable brightness reduction via
856  * the ABM algorithm, with 1 being the least reduction and 4 being the most
857  * reduction.
858  *
859  * Defaults to 0, or disabled. Userspace can still override this level later
860  * after boot.
861  */
862 uint amdgpu_dm_abm_level;
863 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
864 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
865 
866 int amdgpu_backlight = -1;
867 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
868 module_param_named(backlight, amdgpu_backlight, bint, 0444);
869 
870 /**
871  * DOC: tmz (int)
872  * Trusted Memory Zone (TMZ) is a method to protect data being written
873  * to or read from memory.
874  *
875  * The default value: 0 (off).  TODO: change to auto till it is completed.
876  */
877 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
878 module_param_named(tmz, amdgpu_tmz, int, 0444);
879 
880 /**
881  * DOC: freesync_video (uint)
882  * Enable the optimization to adjust front porch timing to achieve seamless
883  * mode change experience when setting a freesync supported mode for which full
884  * modeset is not needed.
885  *
886  * The Display Core will add a set of modes derived from the base FreeSync
887  * video mode into the corresponding connector's mode list based on commonly
888  * used refresh rates and VRR range of the connected display, when users enable
889  * this feature. From the userspace perspective, they can see a seamless mode
890  * change experience when the change between different refresh rates under the
891  * same resolution. Additionally, userspace applications such as Video playback
892  * can read this modeset list and change the refresh rate based on the video
893  * frame rate. Finally, the userspace can also derive an appropriate mode for a
894  * particular refresh rate based on the FreeSync Mode and add it to the
895  * connector's mode list.
896  *
897  * Note: This is an experimental feature.
898  *
899  * The default value: 0 (off).
900  */
901 MODULE_PARM_DESC(
902 	freesync_video,
903 	"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
904 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
905 
906 /**
907  * DOC: reset_method (int)
908  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
909  */
910 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
911 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
912 
913 /**
914  * DOC: bad_page_threshold (int) Bad page threshold is specifies the
915  * threshold value of faulty pages detected by RAS ECC, which may
916  * result in the GPU entering bad status when the number of total
917  * faulty pages by ECC exceeds the threshold value.
918  */
919 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
920 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
921 
922 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
923 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
924 
925 /**
926  * DOC: vcnfw_log (int)
927  * Enable vcnfw log output for debugging, the default is disabled.
928  */
929 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
930 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
931 
932 /**
933  * DOC: sg_display (int)
934  * Disable S/G (scatter/gather) display (i.e., display from system memory).
935  * This option is only relevant on APUs.  Set this option to 0 to disable
936  * S/G display if you experience flickering or other issues under memory
937  * pressure and report the issue.
938  */
939 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
940 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
941 
942 /**
943  * DOC: smu_pptable_id (int)
944  * Used to override pptable id. id = 0 use VBIOS pptable.
945  * id > 0 use the soft pptable with specicfied id.
946  */
947 MODULE_PARM_DESC(smu_pptable_id,
948 	"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
949 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
950 
951 /* These devices are not supported by amdgpu.
952  * They are supported by the mach64, r128, radeon drivers
953  */
954 static const u16 amdgpu_unsupported_pciidlist[] = {
955 	/* mach64 */
956 	0x4354,
957 	0x4358,
958 	0x4554,
959 	0x4742,
960 	0x4744,
961 	0x4749,
962 	0x474C,
963 	0x474D,
964 	0x474E,
965 	0x474F,
966 	0x4750,
967 	0x4751,
968 	0x4752,
969 	0x4753,
970 	0x4754,
971 	0x4755,
972 	0x4756,
973 	0x4757,
974 	0x4758,
975 	0x4759,
976 	0x475A,
977 	0x4C42,
978 	0x4C44,
979 	0x4C47,
980 	0x4C49,
981 	0x4C4D,
982 	0x4C4E,
983 	0x4C50,
984 	0x4C51,
985 	0x4C52,
986 	0x4C53,
987 	0x5654,
988 	0x5655,
989 	0x5656,
990 	/* r128 */
991 	0x4c45,
992 	0x4c46,
993 	0x4d46,
994 	0x4d4c,
995 	0x5041,
996 	0x5042,
997 	0x5043,
998 	0x5044,
999 	0x5045,
1000 	0x5046,
1001 	0x5047,
1002 	0x5048,
1003 	0x5049,
1004 	0x504A,
1005 	0x504B,
1006 	0x504C,
1007 	0x504D,
1008 	0x504E,
1009 	0x504F,
1010 	0x5050,
1011 	0x5051,
1012 	0x5052,
1013 	0x5053,
1014 	0x5054,
1015 	0x5055,
1016 	0x5056,
1017 	0x5057,
1018 	0x5058,
1019 	0x5245,
1020 	0x5246,
1021 	0x5247,
1022 	0x524b,
1023 	0x524c,
1024 	0x534d,
1025 	0x5446,
1026 	0x544C,
1027 	0x5452,
1028 	/* radeon */
1029 	0x3150,
1030 	0x3151,
1031 	0x3152,
1032 	0x3154,
1033 	0x3155,
1034 	0x3E50,
1035 	0x3E54,
1036 	0x4136,
1037 	0x4137,
1038 	0x4144,
1039 	0x4145,
1040 	0x4146,
1041 	0x4147,
1042 	0x4148,
1043 	0x4149,
1044 	0x414A,
1045 	0x414B,
1046 	0x4150,
1047 	0x4151,
1048 	0x4152,
1049 	0x4153,
1050 	0x4154,
1051 	0x4155,
1052 	0x4156,
1053 	0x4237,
1054 	0x4242,
1055 	0x4336,
1056 	0x4337,
1057 	0x4437,
1058 	0x4966,
1059 	0x4967,
1060 	0x4A48,
1061 	0x4A49,
1062 	0x4A4A,
1063 	0x4A4B,
1064 	0x4A4C,
1065 	0x4A4D,
1066 	0x4A4E,
1067 	0x4A4F,
1068 	0x4A50,
1069 	0x4A54,
1070 	0x4B48,
1071 	0x4B49,
1072 	0x4B4A,
1073 	0x4B4B,
1074 	0x4B4C,
1075 	0x4C57,
1076 	0x4C58,
1077 	0x4C59,
1078 	0x4C5A,
1079 	0x4C64,
1080 	0x4C66,
1081 	0x4C67,
1082 	0x4E44,
1083 	0x4E45,
1084 	0x4E46,
1085 	0x4E47,
1086 	0x4E48,
1087 	0x4E49,
1088 	0x4E4A,
1089 	0x4E4B,
1090 	0x4E50,
1091 	0x4E51,
1092 	0x4E52,
1093 	0x4E53,
1094 	0x4E54,
1095 	0x4E56,
1096 	0x5144,
1097 	0x5145,
1098 	0x5146,
1099 	0x5147,
1100 	0x5148,
1101 	0x514C,
1102 	0x514D,
1103 	0x5157,
1104 	0x5158,
1105 	0x5159,
1106 	0x515A,
1107 	0x515E,
1108 	0x5460,
1109 	0x5462,
1110 	0x5464,
1111 	0x5548,
1112 	0x5549,
1113 	0x554A,
1114 	0x554B,
1115 	0x554C,
1116 	0x554D,
1117 	0x554E,
1118 	0x554F,
1119 	0x5550,
1120 	0x5551,
1121 	0x5552,
1122 	0x5554,
1123 	0x564A,
1124 	0x564B,
1125 	0x564F,
1126 	0x5652,
1127 	0x5653,
1128 	0x5657,
1129 	0x5834,
1130 	0x5835,
1131 	0x5954,
1132 	0x5955,
1133 	0x5974,
1134 	0x5975,
1135 	0x5960,
1136 	0x5961,
1137 	0x5962,
1138 	0x5964,
1139 	0x5965,
1140 	0x5969,
1141 	0x5a41,
1142 	0x5a42,
1143 	0x5a61,
1144 	0x5a62,
1145 	0x5b60,
1146 	0x5b62,
1147 	0x5b63,
1148 	0x5b64,
1149 	0x5b65,
1150 	0x5c61,
1151 	0x5c63,
1152 	0x5d48,
1153 	0x5d49,
1154 	0x5d4a,
1155 	0x5d4c,
1156 	0x5d4d,
1157 	0x5d4e,
1158 	0x5d4f,
1159 	0x5d50,
1160 	0x5d52,
1161 	0x5d57,
1162 	0x5e48,
1163 	0x5e4a,
1164 	0x5e4b,
1165 	0x5e4c,
1166 	0x5e4d,
1167 	0x5e4f,
1168 	0x6700,
1169 	0x6701,
1170 	0x6702,
1171 	0x6703,
1172 	0x6704,
1173 	0x6705,
1174 	0x6706,
1175 	0x6707,
1176 	0x6708,
1177 	0x6709,
1178 	0x6718,
1179 	0x6719,
1180 	0x671c,
1181 	0x671d,
1182 	0x671f,
1183 	0x6720,
1184 	0x6721,
1185 	0x6722,
1186 	0x6723,
1187 	0x6724,
1188 	0x6725,
1189 	0x6726,
1190 	0x6727,
1191 	0x6728,
1192 	0x6729,
1193 	0x6738,
1194 	0x6739,
1195 	0x673e,
1196 	0x6740,
1197 	0x6741,
1198 	0x6742,
1199 	0x6743,
1200 	0x6744,
1201 	0x6745,
1202 	0x6746,
1203 	0x6747,
1204 	0x6748,
1205 	0x6749,
1206 	0x674A,
1207 	0x6750,
1208 	0x6751,
1209 	0x6758,
1210 	0x6759,
1211 	0x675B,
1212 	0x675D,
1213 	0x675F,
1214 	0x6760,
1215 	0x6761,
1216 	0x6762,
1217 	0x6763,
1218 	0x6764,
1219 	0x6765,
1220 	0x6766,
1221 	0x6767,
1222 	0x6768,
1223 	0x6770,
1224 	0x6771,
1225 	0x6772,
1226 	0x6778,
1227 	0x6779,
1228 	0x677B,
1229 	0x6840,
1230 	0x6841,
1231 	0x6842,
1232 	0x6843,
1233 	0x6849,
1234 	0x684C,
1235 	0x6850,
1236 	0x6858,
1237 	0x6859,
1238 	0x6880,
1239 	0x6888,
1240 	0x6889,
1241 	0x688A,
1242 	0x688C,
1243 	0x688D,
1244 	0x6898,
1245 	0x6899,
1246 	0x689b,
1247 	0x689c,
1248 	0x689d,
1249 	0x689e,
1250 	0x68a0,
1251 	0x68a1,
1252 	0x68a8,
1253 	0x68a9,
1254 	0x68b0,
1255 	0x68b8,
1256 	0x68b9,
1257 	0x68ba,
1258 	0x68be,
1259 	0x68bf,
1260 	0x68c0,
1261 	0x68c1,
1262 	0x68c7,
1263 	0x68c8,
1264 	0x68c9,
1265 	0x68d8,
1266 	0x68d9,
1267 	0x68da,
1268 	0x68de,
1269 	0x68e0,
1270 	0x68e1,
1271 	0x68e4,
1272 	0x68e5,
1273 	0x68e8,
1274 	0x68e9,
1275 	0x68f1,
1276 	0x68f2,
1277 	0x68f8,
1278 	0x68f9,
1279 	0x68fa,
1280 	0x68fe,
1281 	0x7100,
1282 	0x7101,
1283 	0x7102,
1284 	0x7103,
1285 	0x7104,
1286 	0x7105,
1287 	0x7106,
1288 	0x7108,
1289 	0x7109,
1290 	0x710A,
1291 	0x710B,
1292 	0x710C,
1293 	0x710E,
1294 	0x710F,
1295 	0x7140,
1296 	0x7141,
1297 	0x7142,
1298 	0x7143,
1299 	0x7144,
1300 	0x7145,
1301 	0x7146,
1302 	0x7147,
1303 	0x7149,
1304 	0x714A,
1305 	0x714B,
1306 	0x714C,
1307 	0x714D,
1308 	0x714E,
1309 	0x714F,
1310 	0x7151,
1311 	0x7152,
1312 	0x7153,
1313 	0x715E,
1314 	0x715F,
1315 	0x7180,
1316 	0x7181,
1317 	0x7183,
1318 	0x7186,
1319 	0x7187,
1320 	0x7188,
1321 	0x718A,
1322 	0x718B,
1323 	0x718C,
1324 	0x718D,
1325 	0x718F,
1326 	0x7193,
1327 	0x7196,
1328 	0x719B,
1329 	0x719F,
1330 	0x71C0,
1331 	0x71C1,
1332 	0x71C2,
1333 	0x71C3,
1334 	0x71C4,
1335 	0x71C5,
1336 	0x71C6,
1337 	0x71C7,
1338 	0x71CD,
1339 	0x71CE,
1340 	0x71D2,
1341 	0x71D4,
1342 	0x71D5,
1343 	0x71D6,
1344 	0x71DA,
1345 	0x71DE,
1346 	0x7200,
1347 	0x7210,
1348 	0x7211,
1349 	0x7240,
1350 	0x7243,
1351 	0x7244,
1352 	0x7245,
1353 	0x7246,
1354 	0x7247,
1355 	0x7248,
1356 	0x7249,
1357 	0x724A,
1358 	0x724B,
1359 	0x724C,
1360 	0x724D,
1361 	0x724E,
1362 	0x724F,
1363 	0x7280,
1364 	0x7281,
1365 	0x7283,
1366 	0x7284,
1367 	0x7287,
1368 	0x7288,
1369 	0x7289,
1370 	0x728B,
1371 	0x728C,
1372 	0x7290,
1373 	0x7291,
1374 	0x7293,
1375 	0x7297,
1376 	0x7834,
1377 	0x7835,
1378 	0x791e,
1379 	0x791f,
1380 	0x793f,
1381 	0x7941,
1382 	0x7942,
1383 	0x796c,
1384 	0x796d,
1385 	0x796e,
1386 	0x796f,
1387 	0x9400,
1388 	0x9401,
1389 	0x9402,
1390 	0x9403,
1391 	0x9405,
1392 	0x940A,
1393 	0x940B,
1394 	0x940F,
1395 	0x94A0,
1396 	0x94A1,
1397 	0x94A3,
1398 	0x94B1,
1399 	0x94B3,
1400 	0x94B4,
1401 	0x94B5,
1402 	0x94B9,
1403 	0x9440,
1404 	0x9441,
1405 	0x9442,
1406 	0x9443,
1407 	0x9444,
1408 	0x9446,
1409 	0x944A,
1410 	0x944B,
1411 	0x944C,
1412 	0x944E,
1413 	0x9450,
1414 	0x9452,
1415 	0x9456,
1416 	0x945A,
1417 	0x945B,
1418 	0x945E,
1419 	0x9460,
1420 	0x9462,
1421 	0x946A,
1422 	0x946B,
1423 	0x947A,
1424 	0x947B,
1425 	0x9480,
1426 	0x9487,
1427 	0x9488,
1428 	0x9489,
1429 	0x948A,
1430 	0x948F,
1431 	0x9490,
1432 	0x9491,
1433 	0x9495,
1434 	0x9498,
1435 	0x949C,
1436 	0x949E,
1437 	0x949F,
1438 	0x94C0,
1439 	0x94C1,
1440 	0x94C3,
1441 	0x94C4,
1442 	0x94C5,
1443 	0x94C6,
1444 	0x94C7,
1445 	0x94C8,
1446 	0x94C9,
1447 	0x94CB,
1448 	0x94CC,
1449 	0x94CD,
1450 	0x9500,
1451 	0x9501,
1452 	0x9504,
1453 	0x9505,
1454 	0x9506,
1455 	0x9507,
1456 	0x9508,
1457 	0x9509,
1458 	0x950F,
1459 	0x9511,
1460 	0x9515,
1461 	0x9517,
1462 	0x9519,
1463 	0x9540,
1464 	0x9541,
1465 	0x9542,
1466 	0x954E,
1467 	0x954F,
1468 	0x9552,
1469 	0x9553,
1470 	0x9555,
1471 	0x9557,
1472 	0x955f,
1473 	0x9580,
1474 	0x9581,
1475 	0x9583,
1476 	0x9586,
1477 	0x9587,
1478 	0x9588,
1479 	0x9589,
1480 	0x958A,
1481 	0x958B,
1482 	0x958C,
1483 	0x958D,
1484 	0x958E,
1485 	0x958F,
1486 	0x9590,
1487 	0x9591,
1488 	0x9593,
1489 	0x9595,
1490 	0x9596,
1491 	0x9597,
1492 	0x9598,
1493 	0x9599,
1494 	0x959B,
1495 	0x95C0,
1496 	0x95C2,
1497 	0x95C4,
1498 	0x95C5,
1499 	0x95C6,
1500 	0x95C7,
1501 	0x95C9,
1502 	0x95CC,
1503 	0x95CD,
1504 	0x95CE,
1505 	0x95CF,
1506 	0x9610,
1507 	0x9611,
1508 	0x9612,
1509 	0x9613,
1510 	0x9614,
1511 	0x9615,
1512 	0x9616,
1513 	0x9640,
1514 	0x9641,
1515 	0x9642,
1516 	0x9643,
1517 	0x9644,
1518 	0x9645,
1519 	0x9647,
1520 	0x9648,
1521 	0x9649,
1522 	0x964a,
1523 	0x964b,
1524 	0x964c,
1525 	0x964e,
1526 	0x964f,
1527 	0x9710,
1528 	0x9711,
1529 	0x9712,
1530 	0x9713,
1531 	0x9714,
1532 	0x9715,
1533 	0x9802,
1534 	0x9803,
1535 	0x9804,
1536 	0x9805,
1537 	0x9806,
1538 	0x9807,
1539 	0x9808,
1540 	0x9809,
1541 	0x980A,
1542 	0x9900,
1543 	0x9901,
1544 	0x9903,
1545 	0x9904,
1546 	0x9905,
1547 	0x9906,
1548 	0x9907,
1549 	0x9908,
1550 	0x9909,
1551 	0x990A,
1552 	0x990B,
1553 	0x990C,
1554 	0x990D,
1555 	0x990E,
1556 	0x990F,
1557 	0x9910,
1558 	0x9913,
1559 	0x9917,
1560 	0x9918,
1561 	0x9919,
1562 	0x9990,
1563 	0x9991,
1564 	0x9992,
1565 	0x9993,
1566 	0x9994,
1567 	0x9995,
1568 	0x9996,
1569 	0x9997,
1570 	0x9998,
1571 	0x9999,
1572 	0x999A,
1573 	0x999B,
1574 	0x999C,
1575 	0x999D,
1576 	0x99A0,
1577 	0x99A2,
1578 	0x99A4,
1579 	/* radeon secondary ids */
1580 	0x3171,
1581 	0x3e70,
1582 	0x4164,
1583 	0x4165,
1584 	0x4166,
1585 	0x4168,
1586 	0x4170,
1587 	0x4171,
1588 	0x4172,
1589 	0x4173,
1590 	0x496e,
1591 	0x4a69,
1592 	0x4a6a,
1593 	0x4a6b,
1594 	0x4a70,
1595 	0x4a74,
1596 	0x4b69,
1597 	0x4b6b,
1598 	0x4b6c,
1599 	0x4c6e,
1600 	0x4e64,
1601 	0x4e65,
1602 	0x4e66,
1603 	0x4e67,
1604 	0x4e68,
1605 	0x4e69,
1606 	0x4e6a,
1607 	0x4e71,
1608 	0x4f73,
1609 	0x5569,
1610 	0x556b,
1611 	0x556d,
1612 	0x556f,
1613 	0x5571,
1614 	0x5854,
1615 	0x5874,
1616 	0x5940,
1617 	0x5941,
1618 	0x5b72,
1619 	0x5b73,
1620 	0x5b74,
1621 	0x5b75,
1622 	0x5d44,
1623 	0x5d45,
1624 	0x5d6d,
1625 	0x5d6f,
1626 	0x5d72,
1627 	0x5d77,
1628 	0x5e6b,
1629 	0x5e6d,
1630 	0x7120,
1631 	0x7124,
1632 	0x7129,
1633 	0x712e,
1634 	0x712f,
1635 	0x7162,
1636 	0x7163,
1637 	0x7166,
1638 	0x7167,
1639 	0x7172,
1640 	0x7173,
1641 	0x71a0,
1642 	0x71a1,
1643 	0x71a3,
1644 	0x71a7,
1645 	0x71bb,
1646 	0x71e0,
1647 	0x71e1,
1648 	0x71e2,
1649 	0x71e6,
1650 	0x71e7,
1651 	0x71f2,
1652 	0x7269,
1653 	0x726b,
1654 	0x726e,
1655 	0x72a0,
1656 	0x72a8,
1657 	0x72b1,
1658 	0x72b3,
1659 	0x793f,
1660 };
1661 
1662 static const struct pci_device_id pciidlist[] = {
1663 #ifdef  CONFIG_DRM_AMDGPU_SI
1664 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1665 	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1666 	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1667 	{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1668 	{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1669 	{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1670 	{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1671 	{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1672 	{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1673 	{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1674 	{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1675 	{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1676 	{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1677 	{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1678 	{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1679 	{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1680 	{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1681 	{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1682 	{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1683 	{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1684 	{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1685 	{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1686 	{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1687 	{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1688 	{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1689 	{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1690 	{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1691 	{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1692 	{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1693 	{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1694 	{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1695 	{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1696 	{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1697 	{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1698 	{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1699 	{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1700 	{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1701 	{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1702 	{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1703 	{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1704 	{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1705 	{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1706 	{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1707 	{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1708 	{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1709 	{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1710 	{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1711 	{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1712 	{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1713 	{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1714 	{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1715 	{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1716 	{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1717 	{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1718 	{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1719 	{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1720 	{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1721 	{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1722 	{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1723 	{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1724 	{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1725 	{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1726 	{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1727 	{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1728 	{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1729 	{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1730 	{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1731 	{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1732 	{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1733 	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1734 	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1735 	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1736 #endif
1737 #ifdef CONFIG_DRM_AMDGPU_CIK
1738 	/* Kaveri */
1739 	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1740 	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1741 	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1742 	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1743 	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1744 	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1745 	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1746 	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1747 	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1748 	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1749 	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1750 	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1751 	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1752 	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1753 	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1754 	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1755 	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1756 	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1757 	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1758 	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1759 	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1760 	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1761 	/* Bonaire */
1762 	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1763 	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1764 	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1765 	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1766 	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1767 	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1768 	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1769 	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1770 	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1771 	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1772 	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1773 	/* Hawaii */
1774 	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1775 	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1776 	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1777 	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1778 	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1779 	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1780 	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1781 	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1782 	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1783 	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1784 	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1785 	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1786 	/* Kabini */
1787 	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1788 	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1789 	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1790 	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1791 	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1792 	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1793 	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1794 	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1795 	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1796 	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1797 	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1798 	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1799 	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1800 	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1801 	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1802 	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1803 	/* mullins */
1804 	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1805 	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1806 	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1807 	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1808 	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1809 	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1810 	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1811 	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1812 	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1813 	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1814 	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1815 	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1816 	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1817 	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1818 	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1819 	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1820 #endif
1821 	/* topaz */
1822 	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1823 	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1824 	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1825 	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1826 	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1827 	/* tonga */
1828 	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1829 	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1830 	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1831 	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1832 	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1833 	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1834 	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1835 	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1836 	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1837 	/* fiji */
1838 	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1839 	{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1840 	/* carrizo */
1841 	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1842 	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1843 	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1844 	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1845 	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1846 	/* stoney */
1847 	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1848 	/* Polaris11 */
1849 	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1850 	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1851 	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1852 	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1853 	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1854 	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1855 	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1856 	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1857 	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1858 	/* Polaris10 */
1859 	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1860 	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1861 	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1862 	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1863 	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1864 	{0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1865 	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1866 	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1867 	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1868 	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1869 	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1870 	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1871 	{0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1872 	/* Polaris12 */
1873 	{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1874 	{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1875 	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1876 	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1877 	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1878 	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1879 	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1880 	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1881 	/* VEGAM */
1882 	{0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1883 	{0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1884 	{0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1885 	/* Vega 10 */
1886 	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1887 	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1888 	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1889 	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1890 	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1891 	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1892 	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1893 	{0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1894 	{0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1895 	{0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1896 	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1897 	{0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1898 	{0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1899 	{0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1900 	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1901 	/* Vega 12 */
1902 	{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1903 	{0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1904 	{0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1905 	{0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1906 	{0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1907 	/* Vega 20 */
1908 	{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1909 	{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1910 	{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1911 	{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1912 	{0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1913 	{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1914 	{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1915 	/* Raven */
1916 	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1917 	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1918 	/* Arcturus */
1919 	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1920 	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1921 	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1922 	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1923 	/* Navi10 */
1924 	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1925 	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1926 	{0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1927 	{0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1928 	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1929 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1930 	{0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1931 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1932 	/* Navi14 */
1933 	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1934 	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1935 	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1936 	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1937 
1938 	/* Renoir */
1939 	{0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1940 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1941 	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1942 	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1943 
1944 	/* Navi12 */
1945 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1946 	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1947 
1948 	/* Sienna_Cichlid */
1949 	{0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1950 	{0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1951 	{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1952 	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1953 	{0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1954 	{0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1955 	{0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1956 	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1957 	{0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1958 	{0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1959 	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1960 	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1961 	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1962 
1963 	/* Yellow Carp */
1964 	{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1965 	{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1966 
1967 	/* Navy_Flounder */
1968 	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1969 	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1970 	{0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1971 	{0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1972 	{0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1973 	{0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1974 	{0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1975 	{0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1976 	{0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1977 
1978 	/* DIMGREY_CAVEFISH */
1979 	{0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1980 	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1981 	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1982 	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1983 	{0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1984 	{0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1985 	{0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1986 	{0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1987 	{0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1988 	{0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1989 	{0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1990 	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1991 
1992 	/* Aldebaran */
1993 	{0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1994 	{0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1995 	{0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1996 	{0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1997 
1998 	/* CYAN_SKILLFISH */
1999 	{0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2000 	{0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2001 
2002 	/* BEIGE_GOBY */
2003 	{0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2004 	{0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2005 	{0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2006 	{0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2007 	{0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2008 	{0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2009 
2010 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
2011 	  .class = PCI_CLASS_DISPLAY_VGA << 8,
2012 	  .class_mask = 0xffffff,
2013 	  .driver_data = CHIP_IP_DISCOVERY },
2014 
2015 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
2016 	  .class = PCI_CLASS_DISPLAY_OTHER << 8,
2017 	  .class_mask = 0xffffff,
2018 	  .driver_data = CHIP_IP_DISCOVERY },
2019 
2020 	{0, 0, 0}
2021 };
2022 
2023 MODULE_DEVICE_TABLE(pci, pciidlist);
2024 
2025 static const struct drm_driver amdgpu_kms_driver;
2026 
2027 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2028 {
2029 	struct pci_dev *p = NULL;
2030 	int i;
2031 
2032 	/* 0 - GPU
2033 	 * 1 - audio
2034 	 * 2 - USB
2035 	 * 3 - UCSI
2036 	 */
2037 	for (i = 1; i < 4; i++) {
2038 		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2039 						adev->pdev->bus->number, i);
2040 		if (p) {
2041 			pm_runtime_get_sync(&p->dev);
2042 			pm_runtime_mark_last_busy(&p->dev);
2043 			pm_runtime_put_autosuspend(&p->dev);
2044 			pci_dev_put(p);
2045 		}
2046 	}
2047 }
2048 
2049 static int amdgpu_pci_probe(struct pci_dev *pdev,
2050 			    const struct pci_device_id *ent)
2051 {
2052 	struct drm_device *ddev;
2053 	struct amdgpu_device *adev;
2054 	unsigned long flags = ent->driver_data;
2055 	int ret, retry = 0, i;
2056 	bool supports_atomic = false;
2057 
2058 	/* skip devices which are owned by radeon */
2059 	for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2060 		if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2061 			return -ENODEV;
2062 	}
2063 
2064 	if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2065 		amdgpu_aspm = 0;
2066 
2067 	if (amdgpu_virtual_display ||
2068 	    amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2069 		supports_atomic = true;
2070 
2071 	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2072 		DRM_INFO("This hardware requires experimental hardware support.\n"
2073 			 "See modparam exp_hw_support\n");
2074 		return -ENODEV;
2075 	}
2076 	/* differentiate between P10 and P11 asics with the same DID */
2077 	if (pdev->device == 0x67FF &&
2078 	    (pdev->revision == 0xE3 ||
2079 	     pdev->revision == 0xE7 ||
2080 	     pdev->revision == 0xF3 ||
2081 	     pdev->revision == 0xF7)) {
2082 		flags &= ~AMD_ASIC_MASK;
2083 		flags |= CHIP_POLARIS10;
2084 	}
2085 
2086 	/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2087 	 * however, SME requires an indirect IOMMU mapping because the encryption
2088 	 * bit is beyond the DMA mask of the chip.
2089 	 */
2090 	if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2091 	    ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2092 		dev_info(&pdev->dev,
2093 			 "SME is not compatible with RAVEN\n");
2094 		return -ENOTSUPP;
2095 	}
2096 
2097 #ifdef CONFIG_DRM_AMDGPU_SI
2098 	if (!amdgpu_si_support) {
2099 		switch (flags & AMD_ASIC_MASK) {
2100 		case CHIP_TAHITI:
2101 		case CHIP_PITCAIRN:
2102 		case CHIP_VERDE:
2103 		case CHIP_OLAND:
2104 		case CHIP_HAINAN:
2105 			dev_info(&pdev->dev,
2106 				 "SI support provided by radeon.\n");
2107 			dev_info(&pdev->dev,
2108 				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2109 				);
2110 			return -ENODEV;
2111 		}
2112 	}
2113 #endif
2114 #ifdef CONFIG_DRM_AMDGPU_CIK
2115 	if (!amdgpu_cik_support) {
2116 		switch (flags & AMD_ASIC_MASK) {
2117 		case CHIP_KAVERI:
2118 		case CHIP_BONAIRE:
2119 		case CHIP_HAWAII:
2120 		case CHIP_KABINI:
2121 		case CHIP_MULLINS:
2122 			dev_info(&pdev->dev,
2123 				 "CIK support provided by radeon.\n");
2124 			dev_info(&pdev->dev,
2125 				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2126 				);
2127 			return -ENODEV;
2128 		}
2129 	}
2130 #endif
2131 
2132 	adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2133 	if (IS_ERR(adev))
2134 		return PTR_ERR(adev);
2135 
2136 	adev->dev  = &pdev->dev;
2137 	adev->pdev = pdev;
2138 	ddev = adev_to_drm(adev);
2139 
2140 	if (!supports_atomic)
2141 		ddev->driver_features &= ~DRIVER_ATOMIC;
2142 
2143 	ret = pci_enable_device(pdev);
2144 	if (ret)
2145 		return ret;
2146 
2147 	pci_set_drvdata(pdev, ddev);
2148 
2149 	ret = amdgpu_driver_load_kms(adev, flags);
2150 	if (ret)
2151 		goto err_pci;
2152 
2153 retry_init:
2154 	ret = drm_dev_register(ddev, flags);
2155 	if (ret == -EAGAIN && ++retry <= 3) {
2156 		DRM_INFO("retry init %d\n", retry);
2157 		/* Don't request EX mode too frequently which is attacking */
2158 		msleep(5000);
2159 		goto retry_init;
2160 	} else if (ret) {
2161 		goto err_pci;
2162 	}
2163 
2164 	/*
2165 	 * 1. don't init fbdev on hw without DCE
2166 	 * 2. don't init fbdev if there are no connectors
2167 	 */
2168 	if (adev->mode_info.mode_config_initialized &&
2169 	    !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2170 		/* select 8 bpp console on low vram cards */
2171 		if (adev->gmc.real_vram_size <= (32*1024*1024))
2172 			drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2173 		else
2174 			drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2175 	}
2176 
2177 	ret = amdgpu_debugfs_init(adev);
2178 	if (ret)
2179 		DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2180 
2181 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2182 		/* only need to skip on ATPX */
2183 		if (amdgpu_device_supports_px(ddev))
2184 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2185 		/* we want direct complete for BOCO */
2186 		if (amdgpu_device_supports_boco(ddev))
2187 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2188 						DPM_FLAG_SMART_SUSPEND |
2189 						DPM_FLAG_MAY_SKIP_RESUME);
2190 		pm_runtime_use_autosuspend(ddev->dev);
2191 		pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2192 
2193 		pm_runtime_allow(ddev->dev);
2194 
2195 		pm_runtime_mark_last_busy(ddev->dev);
2196 		pm_runtime_put_autosuspend(ddev->dev);
2197 
2198 		/*
2199 		 * For runpm implemented via BACO, PMFW will handle the
2200 		 * timing for BACO in and out:
2201 		 *   - put ASIC into BACO state only when both video and
2202 		 *     audio functions are in D3 state.
2203 		 *   - pull ASIC out of BACO state when either video or
2204 		 *     audio function is in D0 state.
2205 		 * Also, at startup, PMFW assumes both functions are in
2206 		 * D0 state.
2207 		 *
2208 		 * So if snd driver was loaded prior to amdgpu driver
2209 		 * and audio function was put into D3 state, there will
2210 		 * be no PMFW-aware D-state transition(D0->D3) on runpm
2211 		 * suspend. Thus the BACO will be not correctly kicked in.
2212 		 *
2213 		 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2214 		 * into D0 state. Then there will be a PMFW-aware D-state
2215 		 * transition(D0->D3) on runpm suspend.
2216 		 */
2217 		if (amdgpu_device_supports_baco(ddev) &&
2218 		    !(adev->flags & AMD_IS_APU) &&
2219 		    (adev->asic_type >= CHIP_NAVI10))
2220 			amdgpu_get_secondary_funcs(adev);
2221 	}
2222 
2223 	return 0;
2224 
2225 err_pci:
2226 	pci_disable_device(pdev);
2227 	return ret;
2228 }
2229 
2230 static void
2231 amdgpu_pci_remove(struct pci_dev *pdev)
2232 {
2233 	struct drm_device *dev = pci_get_drvdata(pdev);
2234 	struct amdgpu_device *adev = drm_to_adev(dev);
2235 
2236 	drm_dev_unplug(dev);
2237 
2238 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2239 		pm_runtime_get_sync(dev->dev);
2240 		pm_runtime_forbid(dev->dev);
2241 	}
2242 
2243 	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2244 	    !amdgpu_sriov_vf(adev)) {
2245 		bool need_to_reset_gpu = false;
2246 
2247 		if (adev->gmc.xgmi.num_physical_nodes > 1) {
2248 			struct amdgpu_hive_info *hive;
2249 
2250 			hive = amdgpu_get_xgmi_hive(adev);
2251 			if (hive->device_remove_count == 0)
2252 				need_to_reset_gpu = true;
2253 			hive->device_remove_count++;
2254 			amdgpu_put_xgmi_hive(hive);
2255 		} else {
2256 			need_to_reset_gpu = true;
2257 		}
2258 
2259 		/* Workaround for ASICs need to reset SMU.
2260 		 * Called only when the first device is removed.
2261 		 */
2262 		if (need_to_reset_gpu) {
2263 			struct amdgpu_reset_context reset_context;
2264 
2265 			adev->shutdown = true;
2266 			memset(&reset_context, 0, sizeof(reset_context));
2267 			reset_context.method = AMD_RESET_METHOD_NONE;
2268 			reset_context.reset_req_dev = adev;
2269 			set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2270 			set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2271 			amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2272 		}
2273 	}
2274 
2275 	amdgpu_driver_unload_kms(dev);
2276 
2277 	/*
2278 	 * Flush any in flight DMA operations from device.
2279 	 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2280 	 * StatusTransactions Pending bit.
2281 	 */
2282 	pci_disable_device(pdev);
2283 	pci_wait_for_pending_transaction(pdev);
2284 }
2285 
2286 static void
2287 amdgpu_pci_shutdown(struct pci_dev *pdev)
2288 {
2289 	struct drm_device *dev = pci_get_drvdata(pdev);
2290 	struct amdgpu_device *adev = drm_to_adev(dev);
2291 
2292 	if (amdgpu_ras_intr_triggered())
2293 		return;
2294 
2295 	/* if we are running in a VM, make sure the device
2296 	 * torn down properly on reboot/shutdown.
2297 	 * unfortunately we can't detect certain
2298 	 * hypervisors so just do this all the time.
2299 	 */
2300 	if (!amdgpu_passthrough(adev))
2301 		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2302 	amdgpu_device_ip_suspend(adev);
2303 	adev->mp1_state = PP_MP1_STATE_NONE;
2304 }
2305 
2306 /**
2307  * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2308  *
2309  * @work: work_struct.
2310  */
2311 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2312 {
2313 	struct list_head device_list;
2314 	struct amdgpu_device *adev;
2315 	int i, r;
2316 	struct amdgpu_reset_context reset_context;
2317 
2318 	memset(&reset_context, 0, sizeof(reset_context));
2319 
2320 	mutex_lock(&mgpu_info.mutex);
2321 	if (mgpu_info.pending_reset == true) {
2322 		mutex_unlock(&mgpu_info.mutex);
2323 		return;
2324 	}
2325 	mgpu_info.pending_reset = true;
2326 	mutex_unlock(&mgpu_info.mutex);
2327 
2328 	/* Use a common context, just need to make sure full reset is done */
2329 	reset_context.method = AMD_RESET_METHOD_NONE;
2330 	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2331 
2332 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2333 		adev = mgpu_info.gpu_ins[i].adev;
2334 		reset_context.reset_req_dev = adev;
2335 		r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2336 		if (r) {
2337 			dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2338 				r, adev_to_drm(adev)->unique);
2339 		}
2340 		if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2341 			r = -EALREADY;
2342 	}
2343 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2344 		adev = mgpu_info.gpu_ins[i].adev;
2345 		flush_work(&adev->xgmi_reset_work);
2346 		adev->gmc.xgmi.pending_reset = false;
2347 	}
2348 
2349 	/* reset function will rebuild the xgmi hive info , clear it now */
2350 	for (i = 0; i < mgpu_info.num_dgpu; i++)
2351 		amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2352 
2353 	INIT_LIST_HEAD(&device_list);
2354 
2355 	for (i = 0; i < mgpu_info.num_dgpu; i++)
2356 		list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2357 
2358 	/* unregister the GPU first, reset function will add them back */
2359 	list_for_each_entry(adev, &device_list, reset_list)
2360 		amdgpu_unregister_gpu_instance(adev);
2361 
2362 	/* Use a common context, just need to make sure full reset is done */
2363 	set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2364 	r = amdgpu_do_asic_reset(&device_list, &reset_context);
2365 
2366 	if (r) {
2367 		DRM_ERROR("reinit gpus failure");
2368 		return;
2369 	}
2370 	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2371 		adev = mgpu_info.gpu_ins[i].adev;
2372 		if (!adev->kfd.init_complete)
2373 			amdgpu_amdkfd_device_init(adev);
2374 		amdgpu_ttm_set_buffer_funcs_status(adev, true);
2375 	}
2376 	return;
2377 }
2378 
2379 static int amdgpu_pmops_prepare(struct device *dev)
2380 {
2381 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2382 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2383 
2384 	/* Return a positive number here so
2385 	 * DPM_FLAG_SMART_SUSPEND works properly
2386 	 */
2387 	if (amdgpu_device_supports_boco(drm_dev))
2388 		return pm_runtime_suspended(dev);
2389 
2390 	/* if we will not support s3 or s2i for the device
2391 	 *  then skip suspend
2392 	 */
2393 	if (!amdgpu_acpi_is_s0ix_active(adev) &&
2394 	    !amdgpu_acpi_is_s3_active(adev))
2395 		return 1;
2396 
2397 	return 0;
2398 }
2399 
2400 static void amdgpu_pmops_complete(struct device *dev)
2401 {
2402 	/* nothing to do */
2403 }
2404 
2405 static int amdgpu_pmops_suspend(struct device *dev)
2406 {
2407 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2408 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2409 
2410 	if (amdgpu_acpi_is_s0ix_active(adev))
2411 		adev->in_s0ix = true;
2412 	else if (amdgpu_acpi_is_s3_active(adev))
2413 		adev->in_s3 = true;
2414 	if (!adev->in_s0ix && !adev->in_s3)
2415 		return 0;
2416 	return amdgpu_device_suspend(drm_dev, true);
2417 }
2418 
2419 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2420 {
2421 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2422 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2423 
2424 	if (amdgpu_acpi_should_gpu_reset(adev))
2425 		return amdgpu_asic_reset(adev);
2426 
2427 	return 0;
2428 }
2429 
2430 static int amdgpu_pmops_resume(struct device *dev)
2431 {
2432 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2433 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2434 	int r;
2435 
2436 	if (!adev->in_s0ix && !adev->in_s3)
2437 		return 0;
2438 
2439 	/* Avoids registers access if device is physically gone */
2440 	if (!pci_device_is_present(adev->pdev))
2441 		adev->no_hw_access = true;
2442 
2443 	r = amdgpu_device_resume(drm_dev, true);
2444 	if (amdgpu_acpi_is_s0ix_active(adev))
2445 		adev->in_s0ix = false;
2446 	else
2447 		adev->in_s3 = false;
2448 	return r;
2449 }
2450 
2451 static int amdgpu_pmops_freeze(struct device *dev)
2452 {
2453 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2454 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2455 	int r;
2456 
2457 	adev->in_s4 = true;
2458 	r = amdgpu_device_suspend(drm_dev, true);
2459 	adev->in_s4 = false;
2460 	if (r)
2461 		return r;
2462 
2463 	if (amdgpu_acpi_should_gpu_reset(adev))
2464 		return amdgpu_asic_reset(adev);
2465 	return 0;
2466 }
2467 
2468 static int amdgpu_pmops_thaw(struct device *dev)
2469 {
2470 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2471 
2472 	return amdgpu_device_resume(drm_dev, true);
2473 }
2474 
2475 static int amdgpu_pmops_poweroff(struct device *dev)
2476 {
2477 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2478 
2479 	return amdgpu_device_suspend(drm_dev, true);
2480 }
2481 
2482 static int amdgpu_pmops_restore(struct device *dev)
2483 {
2484 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2485 
2486 	return amdgpu_device_resume(drm_dev, true);
2487 }
2488 
2489 static int amdgpu_runtime_idle_check_display(struct device *dev)
2490 {
2491 	struct pci_dev *pdev = to_pci_dev(dev);
2492 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2493 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2494 
2495 	if (adev->mode_info.num_crtc) {
2496 		struct drm_connector *list_connector;
2497 		struct drm_connector_list_iter iter;
2498 		int ret = 0;
2499 
2500 		/* XXX: Return busy if any displays are connected to avoid
2501 		 * possible display wakeups after runtime resume due to
2502 		 * hotplug events in case any displays were connected while
2503 		 * the GPU was in suspend.  Remove this once that is fixed.
2504 		 */
2505 		mutex_lock(&drm_dev->mode_config.mutex);
2506 		drm_connector_list_iter_begin(drm_dev, &iter);
2507 		drm_for_each_connector_iter(list_connector, &iter) {
2508 			if (list_connector->status == connector_status_connected) {
2509 				ret = -EBUSY;
2510 				break;
2511 			}
2512 		}
2513 		drm_connector_list_iter_end(&iter);
2514 		mutex_unlock(&drm_dev->mode_config.mutex);
2515 
2516 		if (ret)
2517 			return ret;
2518 
2519 		if (adev->dc_enabled) {
2520 			struct drm_crtc *crtc;
2521 
2522 			drm_for_each_crtc(crtc, drm_dev) {
2523 				drm_modeset_lock(&crtc->mutex, NULL);
2524 				if (crtc->state->active)
2525 					ret = -EBUSY;
2526 				drm_modeset_unlock(&crtc->mutex);
2527 				if (ret < 0)
2528 					break;
2529 			}
2530 		} else {
2531 			mutex_lock(&drm_dev->mode_config.mutex);
2532 			drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2533 
2534 			drm_connector_list_iter_begin(drm_dev, &iter);
2535 			drm_for_each_connector_iter(list_connector, &iter) {
2536 				if (list_connector->dpms ==  DRM_MODE_DPMS_ON) {
2537 					ret = -EBUSY;
2538 					break;
2539 				}
2540 			}
2541 
2542 			drm_connector_list_iter_end(&iter);
2543 
2544 			drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2545 			mutex_unlock(&drm_dev->mode_config.mutex);
2546 		}
2547 		if (ret)
2548 			return ret;
2549 	}
2550 
2551 	return 0;
2552 }
2553 
2554 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2555 {
2556 	struct pci_dev *pdev = to_pci_dev(dev);
2557 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2558 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2559 	int ret, i;
2560 
2561 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2562 		pm_runtime_forbid(dev);
2563 		return -EBUSY;
2564 	}
2565 
2566 	ret = amdgpu_runtime_idle_check_display(dev);
2567 	if (ret)
2568 		return ret;
2569 
2570 	/* wait for all rings to drain before suspending */
2571 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2572 		struct amdgpu_ring *ring = adev->rings[i];
2573 		if (ring && ring->sched.ready) {
2574 			ret = amdgpu_fence_wait_empty(ring);
2575 			if (ret)
2576 				return -EBUSY;
2577 		}
2578 	}
2579 
2580 	adev->in_runpm = true;
2581 	if (amdgpu_device_supports_px(drm_dev))
2582 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2583 
2584 	/*
2585 	 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2586 	 * proper cleanups and put itself into a state ready for PNP. That
2587 	 * can address some random resuming failure observed on BOCO capable
2588 	 * platforms.
2589 	 * TODO: this may be also needed for PX capable platform.
2590 	 */
2591 	if (amdgpu_device_supports_boco(drm_dev))
2592 		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2593 
2594 	ret = amdgpu_device_suspend(drm_dev, false);
2595 	if (ret) {
2596 		adev->in_runpm = false;
2597 		if (amdgpu_device_supports_boco(drm_dev))
2598 			adev->mp1_state = PP_MP1_STATE_NONE;
2599 		return ret;
2600 	}
2601 
2602 	if (amdgpu_device_supports_boco(drm_dev))
2603 		adev->mp1_state = PP_MP1_STATE_NONE;
2604 
2605 	if (amdgpu_device_supports_px(drm_dev)) {
2606 		/* Only need to handle PCI state in the driver for ATPX
2607 		 * PCI core handles it for _PR3.
2608 		 */
2609 		amdgpu_device_cache_pci_state(pdev);
2610 		pci_disable_device(pdev);
2611 		pci_ignore_hotplug(pdev);
2612 		pci_set_power_state(pdev, PCI_D3cold);
2613 		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2614 	} else if (amdgpu_device_supports_boco(drm_dev)) {
2615 		/* nothing to do */
2616 	} else if (amdgpu_device_supports_baco(drm_dev)) {
2617 		amdgpu_device_baco_enter(drm_dev);
2618 	}
2619 
2620 	dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2621 
2622 	return 0;
2623 }
2624 
2625 static int amdgpu_pmops_runtime_resume(struct device *dev)
2626 {
2627 	struct pci_dev *pdev = to_pci_dev(dev);
2628 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2629 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2630 	int ret;
2631 
2632 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2633 		return -EINVAL;
2634 
2635 	/* Avoids registers access if device is physically gone */
2636 	if (!pci_device_is_present(adev->pdev))
2637 		adev->no_hw_access = true;
2638 
2639 	if (amdgpu_device_supports_px(drm_dev)) {
2640 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2641 
2642 		/* Only need to handle PCI state in the driver for ATPX
2643 		 * PCI core handles it for _PR3.
2644 		 */
2645 		pci_set_power_state(pdev, PCI_D0);
2646 		amdgpu_device_load_pci_state(pdev);
2647 		ret = pci_enable_device(pdev);
2648 		if (ret)
2649 			return ret;
2650 		pci_set_master(pdev);
2651 	} else if (amdgpu_device_supports_boco(drm_dev)) {
2652 		/* Only need to handle PCI state in the driver for ATPX
2653 		 * PCI core handles it for _PR3.
2654 		 */
2655 		pci_set_master(pdev);
2656 	} else if (amdgpu_device_supports_baco(drm_dev)) {
2657 		amdgpu_device_baco_exit(drm_dev);
2658 	}
2659 	ret = amdgpu_device_resume(drm_dev, false);
2660 	if (ret) {
2661 		if (amdgpu_device_supports_px(drm_dev))
2662 			pci_disable_device(pdev);
2663 		return ret;
2664 	}
2665 
2666 	if (amdgpu_device_supports_px(drm_dev))
2667 		drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2668 	adev->in_runpm = false;
2669 	return 0;
2670 }
2671 
2672 static int amdgpu_pmops_runtime_idle(struct device *dev)
2673 {
2674 	struct drm_device *drm_dev = dev_get_drvdata(dev);
2675 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2676 	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2677 	int ret = 1;
2678 
2679 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2680 		pm_runtime_forbid(dev);
2681 		return -EBUSY;
2682 	}
2683 
2684 	ret = amdgpu_runtime_idle_check_display(dev);
2685 
2686 	pm_runtime_mark_last_busy(dev);
2687 	pm_runtime_autosuspend(dev);
2688 	return ret;
2689 }
2690 
2691 long amdgpu_drm_ioctl(struct file *filp,
2692 		      unsigned int cmd, unsigned long arg)
2693 {
2694 	struct drm_file *file_priv = filp->private_data;
2695 	struct drm_device *dev;
2696 	long ret;
2697 	dev = file_priv->minor->dev;
2698 	ret = pm_runtime_get_sync(dev->dev);
2699 	if (ret < 0)
2700 		goto out;
2701 
2702 	ret = drm_ioctl(filp, cmd, arg);
2703 
2704 	pm_runtime_mark_last_busy(dev->dev);
2705 out:
2706 	pm_runtime_put_autosuspend(dev->dev);
2707 	return ret;
2708 }
2709 
2710 static const struct dev_pm_ops amdgpu_pm_ops = {
2711 	.prepare = amdgpu_pmops_prepare,
2712 	.complete = amdgpu_pmops_complete,
2713 	.suspend = amdgpu_pmops_suspend,
2714 	.suspend_noirq = amdgpu_pmops_suspend_noirq,
2715 	.resume = amdgpu_pmops_resume,
2716 	.freeze = amdgpu_pmops_freeze,
2717 	.thaw = amdgpu_pmops_thaw,
2718 	.poweroff = amdgpu_pmops_poweroff,
2719 	.restore = amdgpu_pmops_restore,
2720 	.runtime_suspend = amdgpu_pmops_runtime_suspend,
2721 	.runtime_resume = amdgpu_pmops_runtime_resume,
2722 	.runtime_idle = amdgpu_pmops_runtime_idle,
2723 };
2724 
2725 static int amdgpu_flush(struct file *f, fl_owner_t id)
2726 {
2727 	struct drm_file *file_priv = f->private_data;
2728 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2729 	long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2730 
2731 	timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2732 	timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2733 
2734 	return timeout >= 0 ? 0 : timeout;
2735 }
2736 
2737 static const struct file_operations amdgpu_driver_kms_fops = {
2738 	.owner = THIS_MODULE,
2739 	.open = drm_open,
2740 	.flush = amdgpu_flush,
2741 	.release = drm_release,
2742 	.unlocked_ioctl = amdgpu_drm_ioctl,
2743 	.mmap = drm_gem_mmap,
2744 	.poll = drm_poll,
2745 	.read = drm_read,
2746 #ifdef CONFIG_COMPAT
2747 	.compat_ioctl = amdgpu_kms_compat_ioctl,
2748 #endif
2749 #ifdef CONFIG_PROC_FS
2750 	.show_fdinfo = amdgpu_show_fdinfo
2751 #endif
2752 };
2753 
2754 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2755 {
2756 	struct drm_file *file;
2757 
2758 	if (!filp)
2759 		return -EINVAL;
2760 
2761 	if (filp->f_op != &amdgpu_driver_kms_fops) {
2762 		return -EINVAL;
2763 	}
2764 
2765 	file = filp->private_data;
2766 	*fpriv = file->driver_priv;
2767 	return 0;
2768 }
2769 
2770 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2771 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2772 	DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2773 	DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2774 	DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2775 	DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2776 	DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2777 	/* KMS */
2778 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2779 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2780 	DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2781 	DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2782 	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2783 	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2784 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2785 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2786 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2787 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2788 };
2789 
2790 static const struct drm_driver amdgpu_kms_driver = {
2791 	.driver_features =
2792 	    DRIVER_ATOMIC |
2793 	    DRIVER_GEM |
2794 	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2795 	    DRIVER_SYNCOBJ_TIMELINE,
2796 	.open = amdgpu_driver_open_kms,
2797 	.postclose = amdgpu_driver_postclose_kms,
2798 	.lastclose = amdgpu_driver_lastclose_kms,
2799 	.ioctls = amdgpu_ioctls_kms,
2800 	.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2801 	.dumb_create = amdgpu_mode_dumb_create,
2802 	.dumb_map_offset = amdgpu_mode_dumb_mmap,
2803 	.fops = &amdgpu_driver_kms_fops,
2804 	.release = &amdgpu_driver_release_kms,
2805 
2806 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2807 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2808 	.gem_prime_import = amdgpu_gem_prime_import,
2809 	.gem_prime_mmap = drm_gem_prime_mmap,
2810 
2811 	.name = DRIVER_NAME,
2812 	.desc = DRIVER_DESC,
2813 	.date = DRIVER_DATE,
2814 	.major = KMS_DRIVER_MAJOR,
2815 	.minor = KMS_DRIVER_MINOR,
2816 	.patchlevel = KMS_DRIVER_PATCHLEVEL,
2817 };
2818 
2819 static struct pci_error_handlers amdgpu_pci_err_handler = {
2820 	.error_detected	= amdgpu_pci_error_detected,
2821 	.mmio_enabled	= amdgpu_pci_mmio_enabled,
2822 	.slot_reset	= amdgpu_pci_slot_reset,
2823 	.resume		= amdgpu_pci_resume,
2824 };
2825 
2826 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2827 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2828 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2829 
2830 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2831 	&amdgpu_vram_mgr_attr_group,
2832 	&amdgpu_gtt_mgr_attr_group,
2833 	&amdgpu_vbios_version_attr_group,
2834 	NULL,
2835 };
2836 
2837 
2838 static struct pci_driver amdgpu_kms_pci_driver = {
2839 	.name = DRIVER_NAME,
2840 	.id_table = pciidlist,
2841 	.probe = amdgpu_pci_probe,
2842 	.remove = amdgpu_pci_remove,
2843 	.shutdown = amdgpu_pci_shutdown,
2844 	.driver.pm = &amdgpu_pm_ops,
2845 	.err_handler = &amdgpu_pci_err_handler,
2846 	.dev_groups = amdgpu_sysfs_groups,
2847 };
2848 
2849 static int __init amdgpu_init(void)
2850 {
2851 	int r;
2852 
2853 	if (drm_firmware_drivers_only())
2854 		return -EINVAL;
2855 
2856 	r = amdgpu_sync_init();
2857 	if (r)
2858 		goto error_sync;
2859 
2860 	r = amdgpu_fence_slab_init();
2861 	if (r)
2862 		goto error_fence;
2863 
2864 	DRM_INFO("amdgpu kernel modesetting enabled.\n");
2865 	amdgpu_register_atpx_handler();
2866 	amdgpu_acpi_detect();
2867 
2868 	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2869 	amdgpu_amdkfd_init();
2870 
2871 	/* let modprobe override vga console setting */
2872 	return pci_register_driver(&amdgpu_kms_pci_driver);
2873 
2874 error_fence:
2875 	amdgpu_sync_fini();
2876 
2877 error_sync:
2878 	return r;
2879 }
2880 
2881 static void __exit amdgpu_exit(void)
2882 {
2883 	amdgpu_amdkfd_fini();
2884 	pci_unregister_driver(&amdgpu_kms_pci_driver);
2885 	amdgpu_unregister_atpx_handler();
2886 	amdgpu_sync_fini();
2887 	amdgpu_fence_slab_fini();
2888 	mmu_notifier_synchronize();
2889 }
2890 
2891 module_init(amdgpu_init);
2892 module_exit(amdgpu_exit);
2893 
2894 MODULE_AUTHOR(DRIVER_AUTHOR);
2895 MODULE_DESCRIPTION(DRIVER_DESC);
2896 MODULE_LICENSE("GPL and additional rights");
2897