1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /* 25 * GPU doorbell structures, functions & helpers 26 */ 27 struct amdgpu_doorbell { 28 /* doorbell mmio */ 29 resource_size_t base; 30 resource_size_t size; 31 u32 __iomem *ptr; 32 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 33 }; 34 35 /* Reserved doorbells for amdgpu (including multimedia). 36 * KFD can use all the rest in the 2M doorbell bar. 37 * For asic before vega10, doorbell is 32-bit, so the 38 * index/offset is in dword. For vega10 and after, doorbell 39 * can be 64-bit, so the index defined is in qword. 40 */ 41 struct amdgpu_doorbell_index { 42 uint32_t kiq; 43 uint32_t mec_ring0; 44 uint32_t mec_ring1; 45 uint32_t mec_ring2; 46 uint32_t mec_ring3; 47 uint32_t mec_ring4; 48 uint32_t mec_ring5; 49 uint32_t mec_ring6; 50 uint32_t mec_ring7; 51 uint32_t userqueue_start; 52 uint32_t userqueue_end; 53 uint32_t gfx_ring0; 54 uint32_t sdma_engine0; 55 uint32_t sdma_engine1; 56 uint32_t sdma_engine2; 57 uint32_t sdma_engine3; 58 uint32_t sdma_engine4; 59 uint32_t sdma_engine5; 60 uint32_t sdma_engine6; 61 uint32_t sdma_engine7; 62 uint32_t ih; 63 union { 64 struct { 65 uint32_t vcn_ring0_1; 66 uint32_t vcn_ring2_3; 67 uint32_t vcn_ring4_5; 68 uint32_t vcn_ring6_7; 69 } vcn; 70 struct { 71 uint32_t uvd_ring0_1; 72 uint32_t uvd_ring2_3; 73 uint32_t uvd_ring4_5; 74 uint32_t uvd_ring6_7; 75 uint32_t vce_ring0_1; 76 uint32_t vce_ring2_3; 77 uint32_t vce_ring4_5; 78 uint32_t vce_ring6_7; 79 } uvd_vce; 80 }; 81 uint32_t max_assignment; 82 }; 83 84 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 85 { 86 AMDGPU_DOORBELL_KIQ = 0x000, 87 AMDGPU_DOORBELL_HIQ = 0x001, 88 AMDGPU_DOORBELL_DIQ = 0x002, 89 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 90 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 91 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 92 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 93 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 94 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 95 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 96 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 97 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 98 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 99 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 100 AMDGPU_DOORBELL_IH = 0x1E8, 101 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 102 AMDGPU_DOORBELL_INVALID = 0xFFFF 103 } AMDGPU_DOORBELL_ASSIGNMENT; 104 105 typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT 106 { 107 /* Compute + GFX: 0~255 */ 108 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 109 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 110 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 111 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 112 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 113 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 114 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 115 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 116 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 117 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 118 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 119 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 120 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 121 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 122 /* SDMA:256~335*/ 123 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 124 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 125 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 126 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 127 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 128 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 129 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 131 /* IH: 376~391 */ 132 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 133 /* MMSCH: 392~407 134 * overlap the doorbell assignment with VCN as they are mutually exclusive 135 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 136 */ 137 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 138 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 139 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 140 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 141 142 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 143 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 144 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 145 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 146 147 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 148 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 149 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 150 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 151 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, 152 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 153 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; 154 155 /* 156 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 157 */ 158 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 159 { 160 /* 161 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 162 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 163 * Compute related doorbells are allocated from 0x00 to 0x8a 164 */ 165 166 167 /* kernel scheduling */ 168 AMDGPU_DOORBELL64_KIQ = 0x00, 169 170 /* HSA interface queue and debug queue */ 171 AMDGPU_DOORBELL64_HIQ = 0x01, 172 AMDGPU_DOORBELL64_DIQ = 0x02, 173 174 /* Compute engines */ 175 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 176 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 177 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 178 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 179 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 180 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 181 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 182 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 183 184 /* User queue doorbell range (128 doorbells) */ 185 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 186 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 187 188 /* Graphics engine */ 189 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 190 191 /* 192 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 193 * Graphics voltage island aperture 1 194 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 195 */ 196 197 /* For vega10 sriov, the sdma doorbell must be fixed as follow 198 * to keep the same setting with host driver, or it will 199 * happen conflicts 200 */ 201 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 202 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 203 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 204 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 205 206 /* Interrupt handler */ 207 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 208 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 209 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 210 211 /* VCN engine use 32 bits doorbell */ 212 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 213 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 214 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 215 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 216 217 /* overlap the doorbell assignment with VCN as they are mutually exclusive 218 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 219 */ 220 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 221 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 222 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 223 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 224 225 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 226 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 227 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 228 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 229 230 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 231 AMDGPU_DOORBELL64_INVALID = 0xFFFF 232 } AMDGPU_DOORBELL64_ASSIGNMENT; 233 234 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 235 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 236 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 237 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 238 239 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 240 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 241 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 242 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 243 244