1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * based on nouveau_prime.c 23 * 24 * Authors: Alex Deucher 25 */ 26 27 /** 28 * DOC: PRIME Buffer Sharing 29 * 30 * The following callback implementations are used for :ref:`sharing GEM buffer 31 * objects between different devices via PRIME <prime_buffer_sharing>`. 32 */ 33 34 #include "amdgpu.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_gem.h" 37 #include <drm/amdgpu_drm.h> 38 #include <linux/dma-buf.h> 39 #include <linux/dma-fence-array.h> 40 41 /** 42 * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table 43 * implementation 44 * @obj: GEM buffer object (BO) 45 * 46 * Returns: 47 * A scatter/gather table for the pinned pages of the BO's memory. 48 */ 49 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) 50 { 51 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 52 int npages = bo->tbo.num_pages; 53 54 return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages); 55 } 56 57 /** 58 * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation 59 * @obj: GEM BO 60 * 61 * Sets up an in-kernel virtual mapping of the BO's memory. 62 * 63 * Returns: 64 * The virtual address of the mapping or an error pointer. 65 */ 66 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) 67 { 68 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 69 int ret; 70 71 ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, 72 &bo->dma_buf_vmap); 73 if (ret) 74 return ERR_PTR(ret); 75 76 return bo->dma_buf_vmap.virtual; 77 } 78 79 /** 80 * amdgpu_gem_prime_vunmap - &dma_buf_ops.vunmap implementation 81 * @obj: GEM BO 82 * @vaddr: Virtual address (unused) 83 * 84 * Tears down the in-kernel virtual mapping of the BO's memory. 85 */ 86 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) 87 { 88 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 89 90 ttm_bo_kunmap(&bo->dma_buf_vmap); 91 } 92 93 /** 94 * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation 95 * @obj: GEM BO 96 * @vma: Virtual memory area 97 * 98 * Sets up a userspace mapping of the BO's memory in the given 99 * virtual memory area. 100 * 101 * Returns: 102 * 0 on success or a negative error code on failure. 103 */ 104 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, 105 struct vm_area_struct *vma) 106 { 107 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 108 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 109 unsigned asize = amdgpu_bo_size(bo); 110 int ret; 111 112 if (!vma->vm_file) 113 return -ENODEV; 114 115 if (adev == NULL) 116 return -ENODEV; 117 118 /* Check for valid size. */ 119 if (asize < vma->vm_end - vma->vm_start) 120 return -EINVAL; 121 122 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || 123 (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 124 return -EPERM; 125 } 126 vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; 127 128 /* prime mmap does not need to check access, so allow here */ 129 ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); 130 if (ret) 131 return ret; 132 133 ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); 134 drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); 135 136 return ret; 137 } 138 139 static int 140 __dma_resv_make_exclusive(struct dma_resv *obj) 141 { 142 struct dma_fence **fences; 143 unsigned int count; 144 int r; 145 146 if (!dma_resv_get_list(obj)) /* no shared fences to convert */ 147 return 0; 148 149 r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences); 150 if (r) 151 return r; 152 153 if (count == 0) { 154 /* Now that was unexpected. */ 155 } else if (count == 1) { 156 dma_resv_add_excl_fence(obj, fences[0]); 157 dma_fence_put(fences[0]); 158 kfree(fences); 159 } else { 160 struct dma_fence_array *array; 161 162 array = dma_fence_array_create(count, fences, 163 dma_fence_context_alloc(1), 0, 164 false); 165 if (!array) 166 goto err_fences_put; 167 168 dma_resv_add_excl_fence(obj, &array->base); 169 dma_fence_put(&array->base); 170 } 171 172 return 0; 173 174 err_fences_put: 175 while (count--) 176 dma_fence_put(fences[count]); 177 kfree(fences); 178 return -ENOMEM; 179 } 180 181 /** 182 * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation 183 * @dma_buf: Shared DMA buffer 184 * @attach: DMA-buf attachment 185 * 186 * Makes sure that the shared DMA buffer can be accessed by the target device. 187 * For now, simply pins it to the GTT domain, where it should be accessible by 188 * all DMA devices. 189 * 190 * Returns: 191 * 0 on success or a negative error code on failure. 192 */ 193 static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, 194 struct dma_buf_attachment *attach) 195 { 196 struct drm_gem_object *obj = dma_buf->priv; 197 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 198 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 199 long r; 200 201 r = drm_gem_map_attach(dma_buf, attach); 202 if (r) 203 return r; 204 205 r = amdgpu_bo_reserve(bo, false); 206 if (unlikely(r != 0)) 207 goto error_detach; 208 209 210 if (attach->dev->driver != adev->dev->driver) { 211 /* 212 * We only create shared fences for internal use, but importers 213 * of the dmabuf rely on exclusive fences for implicitly 214 * tracking write hazards. As any of the current fences may 215 * correspond to a write, we need to convert all existing 216 * fences on the reservation object into a single exclusive 217 * fence. 218 */ 219 r = __dma_resv_make_exclusive(bo->tbo.base.resv); 220 if (r) 221 goto error_unreserve; 222 } 223 224 /* pin buffer into GTT */ 225 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 226 if (r) 227 goto error_unreserve; 228 229 if (attach->dev->driver != adev->dev->driver) 230 bo->prime_shared_count++; 231 232 error_unreserve: 233 amdgpu_bo_unreserve(bo); 234 235 error_detach: 236 if (r) 237 drm_gem_map_detach(dma_buf, attach); 238 return r; 239 } 240 241 /** 242 * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation 243 * @dma_buf: Shared DMA buffer 244 * @attach: DMA-buf attachment 245 * 246 * This is called when a shared DMA buffer no longer needs to be accessible by 247 * another device. For now, simply unpins the buffer from GTT. 248 */ 249 static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, 250 struct dma_buf_attachment *attach) 251 { 252 struct drm_gem_object *obj = dma_buf->priv; 253 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 254 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 255 int ret = 0; 256 257 ret = amdgpu_bo_reserve(bo, true); 258 if (unlikely(ret != 0)) 259 goto error; 260 261 amdgpu_bo_unpin(bo); 262 if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) 263 bo->prime_shared_count--; 264 amdgpu_bo_unreserve(bo); 265 266 error: 267 drm_gem_map_detach(dma_buf, attach); 268 } 269 270 /** 271 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation 272 * @dma_buf: Shared DMA buffer 273 * @direction: Direction of DMA transfer 274 * 275 * This is called before CPU access to the shared DMA buffer's memory. If it's 276 * a read access, the buffer is moved to the GTT domain if possible, for optimal 277 * CPU read performance. 278 * 279 * Returns: 280 * 0 on success or a negative error code on failure. 281 */ 282 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, 283 enum dma_data_direction direction) 284 { 285 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv); 286 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 287 struct ttm_operation_ctx ctx = { true, false }; 288 u32 domain = amdgpu_display_supported_domains(adev, bo->flags); 289 int ret; 290 bool reads = (direction == DMA_BIDIRECTIONAL || 291 direction == DMA_FROM_DEVICE); 292 293 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT)) 294 return 0; 295 296 /* move to gtt */ 297 ret = amdgpu_bo_reserve(bo, false); 298 if (unlikely(ret != 0)) 299 return ret; 300 301 if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) { 302 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 303 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 304 } 305 306 amdgpu_bo_unreserve(bo); 307 return ret; 308 } 309 310 const struct dma_buf_ops amdgpu_dmabuf_ops = { 311 .attach = amdgpu_dma_buf_map_attach, 312 .detach = amdgpu_dma_buf_map_detach, 313 .map_dma_buf = drm_gem_map_dma_buf, 314 .unmap_dma_buf = drm_gem_unmap_dma_buf, 315 .release = drm_gem_dmabuf_release, 316 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, 317 .mmap = drm_gem_dmabuf_mmap, 318 .vmap = drm_gem_dmabuf_vmap, 319 .vunmap = drm_gem_dmabuf_vunmap, 320 }; 321 322 /** 323 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation 324 * @dev: DRM device 325 * @gobj: GEM BO 326 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR. 327 * 328 * The main work is done by the &drm_gem_prime_export helper. 329 * 330 * Returns: 331 * Shared DMA buffer representing the GEM BO from the given device. 332 */ 333 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, 334 int flags) 335 { 336 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 337 struct dma_buf *buf; 338 339 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || 340 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 341 return ERR_PTR(-EPERM); 342 343 buf = drm_gem_prime_export(gobj, flags); 344 if (!IS_ERR(buf)) { 345 buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; 346 buf->ops = &amdgpu_dmabuf_ops; 347 } 348 349 return buf; 350 } 351 352 /** 353 * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table 354 * implementation 355 * @dev: DRM device 356 * @attach: DMA-buf attachment 357 * @sg: Scatter/gather table 358 * 359 * Imports shared DMA buffer memory exported by another device. 360 * 361 * Returns: 362 * A new GEM BO of the given DRM device, representing the memory 363 * described by the given DMA-buf attachment and scatter/gather table. 364 */ 365 struct drm_gem_object * 366 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 367 struct dma_buf_attachment *attach, 368 struct sg_table *sg) 369 { 370 struct dma_resv *resv = attach->dmabuf->resv; 371 struct amdgpu_device *adev = dev->dev_private; 372 struct amdgpu_bo *bo; 373 struct amdgpu_bo_param bp; 374 int ret; 375 376 memset(&bp, 0, sizeof(bp)); 377 bp.size = attach->dmabuf->size; 378 bp.byte_align = PAGE_SIZE; 379 bp.domain = AMDGPU_GEM_DOMAIN_CPU; 380 bp.flags = 0; 381 bp.type = ttm_bo_type_sg; 382 bp.resv = resv; 383 dma_resv_lock(resv, NULL); 384 ret = amdgpu_bo_create(adev, &bp, &bo); 385 if (ret) 386 goto error; 387 388 bo->tbo.sg = sg; 389 bo->tbo.ttm->sg = sg; 390 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 391 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 392 if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) 393 bo->prime_shared_count = 1; 394 395 dma_resv_unlock(resv); 396 return &bo->tbo.base; 397 398 error: 399 dma_resv_unlock(resv); 400 return ERR_PTR(ret); 401 } 402 403 /** 404 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation 405 * @dev: DRM device 406 * @dma_buf: Shared DMA buffer 407 * 408 * The main work is done by the &drm_gem_prime_import helper, which in turn 409 * uses &amdgpu_gem_prime_import_sg_table. 410 * 411 * Returns: 412 * GEM BO representing the shared DMA buffer for the given device. 413 */ 414 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, 415 struct dma_buf *dma_buf) 416 { 417 struct drm_gem_object *obj; 418 419 if (dma_buf->ops == &amdgpu_dmabuf_ops) { 420 obj = dma_buf->priv; 421 if (obj->dev == dev) { 422 /* 423 * Importing dmabuf exported from out own gem increases 424 * refcount on gem itself instead of f_count of dmabuf. 425 */ 426 drm_gem_object_get(obj); 427 return obj; 428 } 429 } 430 431 return drm_gem_prime_import(dev, dma_buf); 432 } 433