1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * based on nouveau_prime.c
23  *
24  * Authors: Alex Deucher
25  */
26 
27 /**
28  * DOC: PRIME Buffer Sharing
29  *
30  * The following callback implementations are used for :ref:`sharing GEM buffer
31  * objects between different devices via PRIME <prime_buffer_sharing>`.
32  */
33 
34 #include "amdgpu.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include <drm/amdgpu_drm.h>
40 #include <linux/dma-buf.h>
41 #include <linux/dma-fence-array.h>
42 #include <linux/pci-p2pdma.h>
43 #include <linux/pm_runtime.h>
44 
45 /**
46  * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
47  *
48  * @dmabuf: DMA-buf where we attach to
49  * @attach: attachment to add
50  *
51  * Add the attachment as user to the exported DMA-buf.
52  */
53 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
54 				 struct dma_buf_attachment *attach)
55 {
56 	struct drm_gem_object *obj = dmabuf->priv;
57 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
58 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
59 	int r;
60 
61 	if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
62 		attach->peer2peer = false;
63 
64 	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
65 	if (r < 0)
66 		goto out;
67 
68 	return 0;
69 
70 out:
71 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
72 	return r;
73 }
74 
75 /**
76  * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
77  *
78  * @dmabuf: DMA-buf where we remove the attachment from
79  * @attach: the attachment to remove
80  *
81  * Called when an attachment is removed from the DMA-buf.
82  */
83 static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
84 				  struct dma_buf_attachment *attach)
85 {
86 	struct drm_gem_object *obj = dmabuf->priv;
87 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
88 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
89 
90 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
91 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
92 }
93 
94 /**
95  * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
96  *
97  * @attach: attachment to pin down
98  *
99  * Pin the BO which is backing the DMA-buf so that it can't move any more.
100  */
101 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
102 {
103 	struct drm_gem_object *obj = attach->dmabuf->priv;
104 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
105 
106 	/* pin buffer into GTT */
107 	return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
108 }
109 
110 /**
111  * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
112  *
113  * @attach: attachment to unpin
114  *
115  * Unpin a previously pinned BO to make it movable again.
116  */
117 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
118 {
119 	struct drm_gem_object *obj = attach->dmabuf->priv;
120 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
121 
122 	amdgpu_bo_unpin(bo);
123 }
124 
125 /**
126  * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
127  * @attach: DMA-buf attachment
128  * @dir: DMA direction
129  *
130  * Makes sure that the shared DMA buffer can be accessed by the target device.
131  * For now, simply pins it to the GTT domain, where it should be accessible by
132  * all DMA devices.
133  *
134  * Returns:
135  * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
136  * code.
137  */
138 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
139 					   enum dma_data_direction dir)
140 {
141 	struct dma_buf *dma_buf = attach->dmabuf;
142 	struct drm_gem_object *obj = dma_buf->priv;
143 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
144 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
145 	struct sg_table *sgt;
146 	long r;
147 
148 	if (!bo->tbo.pin_count) {
149 		/* move buffer into GTT or VRAM */
150 		struct ttm_operation_ctx ctx = { false, false };
151 		unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
152 
153 		if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
154 		    attach->peer2peer) {
155 			bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
156 			domains |= AMDGPU_GEM_DOMAIN_VRAM;
157 		}
158 		amdgpu_bo_placement_from_domain(bo, domains);
159 		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
160 		if (r)
161 			return ERR_PTR(r);
162 
163 	} else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) &
164 		     AMDGPU_GEM_DOMAIN_GTT)) {
165 		return ERR_PTR(-EBUSY);
166 	}
167 
168 	switch (bo->tbo.resource->mem_type) {
169 	case TTM_PL_TT:
170 		sgt = drm_prime_pages_to_sg(obj->dev,
171 					    bo->tbo.ttm->pages,
172 					    bo->tbo.ttm->num_pages);
173 		if (IS_ERR(sgt))
174 			return sgt;
175 
176 		if (dma_map_sgtable(attach->dev, sgt, dir,
177 				    DMA_ATTR_SKIP_CPU_SYNC))
178 			goto error_free;
179 		break;
180 
181 	case TTM_PL_VRAM:
182 		r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
183 					      bo->tbo.base.size, attach->dev,
184 					      dir, &sgt);
185 		if (r)
186 			return ERR_PTR(r);
187 		break;
188 	default:
189 		return ERR_PTR(-EINVAL);
190 	}
191 
192 	return sgt;
193 
194 error_free:
195 	sg_free_table(sgt);
196 	kfree(sgt);
197 	return ERR_PTR(-EBUSY);
198 }
199 
200 /**
201  * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
202  * @attach: DMA-buf attachment
203  * @sgt: sg_table to unmap
204  * @dir: DMA direction
205  *
206  * This is called when a shared DMA buffer no longer needs to be accessible by
207  * another device. For now, simply unpins the buffer from GTT.
208  */
209 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
210 				 struct sg_table *sgt,
211 				 enum dma_data_direction dir)
212 {
213 	if (sgt->sgl->page_link) {
214 		dma_unmap_sgtable(attach->dev, sgt, dir, 0);
215 		sg_free_table(sgt);
216 		kfree(sgt);
217 	} else {
218 		amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
219 	}
220 }
221 
222 /**
223  * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
224  * @dma_buf: Shared DMA buffer
225  * @direction: Direction of DMA transfer
226  *
227  * This is called before CPU access to the shared DMA buffer's memory. If it's
228  * a read access, the buffer is moved to the GTT domain if possible, for optimal
229  * CPU read performance.
230  *
231  * Returns:
232  * 0 on success or a negative error code on failure.
233  */
234 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
235 					   enum dma_data_direction direction)
236 {
237 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
238 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
239 	struct ttm_operation_ctx ctx = { true, false };
240 	u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
241 	int ret;
242 	bool reads = (direction == DMA_BIDIRECTIONAL ||
243 		      direction == DMA_FROM_DEVICE);
244 
245 	if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
246 		return 0;
247 
248 	/* move to gtt */
249 	ret = amdgpu_bo_reserve(bo, false);
250 	if (unlikely(ret != 0))
251 		return ret;
252 
253 	if (!bo->tbo.pin_count &&
254 	    (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
255 		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
256 		ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
257 	}
258 
259 	amdgpu_bo_unreserve(bo);
260 	return ret;
261 }
262 
263 const struct dma_buf_ops amdgpu_dmabuf_ops = {
264 	.attach = amdgpu_dma_buf_attach,
265 	.detach = amdgpu_dma_buf_detach,
266 	.pin = amdgpu_dma_buf_pin,
267 	.unpin = amdgpu_dma_buf_unpin,
268 	.map_dma_buf = amdgpu_dma_buf_map,
269 	.unmap_dma_buf = amdgpu_dma_buf_unmap,
270 	.release = drm_gem_dmabuf_release,
271 	.begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
272 	.mmap = drm_gem_dmabuf_mmap,
273 	.vmap = drm_gem_dmabuf_vmap,
274 	.vunmap = drm_gem_dmabuf_vunmap,
275 };
276 
277 /**
278  * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
279  * @gobj: GEM BO
280  * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
281  *
282  * The main work is done by the &drm_gem_prime_export helper.
283  *
284  * Returns:
285  * Shared DMA buffer representing the GEM BO from the given device.
286  */
287 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
288 					int flags)
289 {
290 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
291 	struct dma_buf *buf;
292 
293 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
294 	    bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
295 		return ERR_PTR(-EPERM);
296 
297 	buf = drm_gem_prime_export(gobj, flags);
298 	if (!IS_ERR(buf))
299 		buf->ops = &amdgpu_dmabuf_ops;
300 
301 	return buf;
302 }
303 
304 /**
305  * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
306  *
307  * @dev: DRM device
308  * @dma_buf: DMA-buf
309  *
310  * Creates an empty SG BO for DMA-buf import.
311  *
312  * Returns:
313  * A new GEM BO of the given DRM device, representing the memory
314  * described by the given DMA-buf attachment and scatter/gather table.
315  */
316 static struct drm_gem_object *
317 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
318 {
319 	struct dma_resv *resv = dma_buf->resv;
320 	struct amdgpu_device *adev = drm_to_adev(dev);
321 	struct drm_gem_object *gobj;
322 	struct amdgpu_bo *bo;
323 	uint64_t flags = 0;
324 	int ret;
325 
326 	dma_resv_lock(resv, NULL);
327 
328 	if (dma_buf->ops == &amdgpu_dmabuf_ops) {
329 		struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
330 
331 		flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
332 	}
333 
334 	ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
335 				       AMDGPU_GEM_DOMAIN_CPU, flags,
336 				       ttm_bo_type_sg, resv, &gobj);
337 	if (ret)
338 		goto error;
339 
340 	bo = gem_to_amdgpu_bo(gobj);
341 	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
342 	bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
343 
344 	dma_resv_unlock(resv);
345 	return gobj;
346 
347 error:
348 	dma_resv_unlock(resv);
349 	return ERR_PTR(ret);
350 }
351 
352 /**
353  * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
354  *
355  * @attach: the DMA-buf attachment
356  *
357  * Invalidate the DMA-buf attachment, making sure that the we re-create the
358  * mapping before the next use.
359  */
360 static void
361 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
362 {
363 	struct drm_gem_object *obj = attach->importer_priv;
364 	struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
365 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
366 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
367 	struct ttm_operation_ctx ctx = { false, false };
368 	struct ttm_placement placement = {};
369 	struct amdgpu_vm_bo_base *bo_base;
370 	int r;
371 
372 	if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
373 		return;
374 
375 	r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
376 	if (r) {
377 		DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
378 		return;
379 	}
380 
381 	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
382 		struct amdgpu_vm *vm = bo_base->vm;
383 		struct dma_resv *resv = vm->root.bo->tbo.base.resv;
384 
385 		if (ticket) {
386 			/* When we get an error here it means that somebody
387 			 * else is holding the VM lock and updating page tables
388 			 * So we can just continue here.
389 			 */
390 			r = dma_resv_lock(resv, ticket);
391 			if (r)
392 				continue;
393 
394 		} else {
395 			/* TODO: This is more problematic and we actually need
396 			 * to allow page tables updates without holding the
397 			 * lock.
398 			 */
399 			if (!dma_resv_trylock(resv))
400 				continue;
401 		}
402 
403 		r = amdgpu_vm_clear_freed(adev, vm, NULL);
404 		if (!r)
405 			r = amdgpu_vm_handle_moved(adev, vm);
406 
407 		if (r && r != -EBUSY)
408 			DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
409 				  r);
410 
411 		dma_resv_unlock(resv);
412 	}
413 }
414 
415 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
416 	.allow_peer2peer = true,
417 	.move_notify = amdgpu_dma_buf_move_notify
418 };
419 
420 /**
421  * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
422  * @dev: DRM device
423  * @dma_buf: Shared DMA buffer
424  *
425  * Import a dma_buf into a the driver and potentially create a new GEM object.
426  *
427  * Returns:
428  * GEM BO representing the shared DMA buffer for the given device.
429  */
430 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
431 					       struct dma_buf *dma_buf)
432 {
433 	struct dma_buf_attachment *attach;
434 	struct drm_gem_object *obj;
435 
436 	if (dma_buf->ops == &amdgpu_dmabuf_ops) {
437 		obj = dma_buf->priv;
438 		if (obj->dev == dev) {
439 			/*
440 			 * Importing dmabuf exported from out own gem increases
441 			 * refcount on gem itself instead of f_count of dmabuf.
442 			 */
443 			drm_gem_object_get(obj);
444 			return obj;
445 		}
446 	}
447 
448 	obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
449 	if (IS_ERR(obj))
450 		return obj;
451 
452 	attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
453 					&amdgpu_dma_buf_attach_ops, obj);
454 	if (IS_ERR(attach)) {
455 		drm_gem_object_put(obj);
456 		return ERR_CAST(attach);
457 	}
458 
459 	get_dma_buf(dma_buf);
460 	obj->import_attach = attach;
461 	return obj;
462 }
463 
464 /**
465  * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
466  *
467  * @adev: amdgpu_device pointer of the importer
468  * @bo: amdgpu buffer object
469  *
470  * Returns:
471  * True if dmabuf accessible over xgmi, false otherwise.
472  */
473 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
474 				      struct amdgpu_bo *bo)
475 {
476 	struct drm_gem_object *obj = &bo->tbo.base;
477 	struct drm_gem_object *gobj;
478 
479 	if (obj->import_attach) {
480 		struct dma_buf *dma_buf = obj->import_attach->dmabuf;
481 
482 		if (dma_buf->ops != &amdgpu_dmabuf_ops)
483 			/* No XGMI with non AMD GPUs */
484 			return false;
485 
486 		gobj = dma_buf->priv;
487 		bo = gem_to_amdgpu_bo(gobj);
488 	}
489 
490 	if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
491 			(bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
492 		return true;
493 
494 	return false;
495 }
496