1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pm_runtime.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_gem_framebuffer_helper.h> 39 #include <drm/drm_fb_helper.h> 40 41 static void amdgpu_display_flip_callback(struct dma_fence *f, 42 struct dma_fence_cb *cb) 43 { 44 struct amdgpu_flip_work *work = 45 container_of(cb, struct amdgpu_flip_work, cb); 46 47 dma_fence_put(f); 48 schedule_work(&work->flip_work.work); 49 } 50 51 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 52 struct dma_fence **f) 53 { 54 struct dma_fence *fence= *f; 55 56 if (fence == NULL) 57 return false; 58 59 *f = NULL; 60 61 if (!dma_fence_add_callback(fence, &work->cb, 62 amdgpu_display_flip_callback)) 63 return true; 64 65 dma_fence_put(fence); 66 return false; 67 } 68 69 static void amdgpu_display_flip_work_func(struct work_struct *__work) 70 { 71 struct delayed_work *delayed_work = 72 container_of(__work, struct delayed_work, work); 73 struct amdgpu_flip_work *work = 74 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 75 struct amdgpu_device *adev = work->adev; 76 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 77 78 struct drm_crtc *crtc = &amdgpu_crtc->base; 79 unsigned long flags; 80 unsigned i; 81 int vpos, hpos; 82 83 if (amdgpu_display_flip_handle_fence(work, &work->excl)) 84 return; 85 86 for (i = 0; i < work->shared_count; ++i) 87 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 88 return; 89 90 /* Wait until we're out of the vertical blank period before the one 91 * targeted by the flip 92 */ 93 if (amdgpu_crtc->enabled && 94 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, 95 &vpos, &hpos, NULL, NULL, 96 &crtc->hwmode) 97 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 98 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 99 (int)(work->target_vblank - 100 amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { 101 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 102 return; 103 } 104 105 /* We borrow the event spin lock for protecting flip_status */ 106 spin_lock_irqsave(&crtc->dev->event_lock, flags); 107 108 /* Do the flip (mmio) */ 109 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 110 111 /* Set the flip status */ 112 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 113 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 114 115 116 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 117 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 118 119 } 120 121 /* 122 * Handle unpin events outside the interrupt handler proper. 123 */ 124 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 125 { 126 struct amdgpu_flip_work *work = 127 container_of(__work, struct amdgpu_flip_work, unpin_work); 128 int r; 129 130 /* unpin of the old buffer */ 131 r = amdgpu_bo_reserve(work->old_abo, true); 132 if (likely(r == 0)) { 133 r = amdgpu_bo_unpin(work->old_abo); 134 if (unlikely(r != 0)) { 135 DRM_ERROR("failed to unpin buffer after flip\n"); 136 } 137 amdgpu_bo_unreserve(work->old_abo); 138 } else 139 DRM_ERROR("failed to reserve buffer after flip\n"); 140 141 amdgpu_bo_unref(&work->old_abo); 142 kfree(work->shared); 143 kfree(work); 144 } 145 146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 147 struct drm_framebuffer *fb, 148 struct drm_pending_vblank_event *event, 149 uint32_t page_flip_flags, uint32_t target, 150 struct drm_modeset_acquire_ctx *ctx) 151 { 152 struct drm_device *dev = crtc->dev; 153 struct amdgpu_device *adev = dev->dev_private; 154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 155 struct drm_gem_object *obj; 156 struct amdgpu_flip_work *work; 157 struct amdgpu_bo *new_abo; 158 unsigned long flags; 159 u64 tiling_flags; 160 int i, r; 161 162 work = kzalloc(sizeof *work, GFP_KERNEL); 163 if (work == NULL) 164 return -ENOMEM; 165 166 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 167 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 168 169 work->event = event; 170 work->adev = adev; 171 work->crtc_id = amdgpu_crtc->crtc_id; 172 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 173 174 /* schedule unpin of the old buffer */ 175 obj = crtc->primary->fb->obj[0]; 176 177 /* take a reference to the old object */ 178 work->old_abo = gem_to_amdgpu_bo(obj); 179 amdgpu_bo_ref(work->old_abo); 180 181 obj = fb->obj[0]; 182 new_abo = gem_to_amdgpu_bo(obj); 183 184 /* pin the new buffer */ 185 r = amdgpu_bo_reserve(new_abo, false); 186 if (unlikely(r != 0)) { 187 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 188 goto cleanup; 189 } 190 191 r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev)); 192 if (unlikely(r != 0)) { 193 DRM_ERROR("failed to pin new abo buffer before flip\n"); 194 goto unreserve; 195 } 196 197 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 198 if (unlikely(r != 0)) { 199 DRM_ERROR("%p bind failed\n", new_abo); 200 goto unpin; 201 } 202 203 r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, 204 &work->shared_count, 205 &work->shared); 206 if (unlikely(r != 0)) { 207 DRM_ERROR("failed to get fences for buffer\n"); 208 goto unpin; 209 } 210 211 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 212 amdgpu_bo_unreserve(new_abo); 213 214 work->base = amdgpu_bo_gpu_offset(new_abo); 215 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 216 amdgpu_get_vblank_counter_kms(dev, work->crtc_id); 217 218 /* we borrow the event spin lock for protecting flip_wrok */ 219 spin_lock_irqsave(&crtc->dev->event_lock, flags); 220 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 221 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 222 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 223 r = -EBUSY; 224 goto pflip_cleanup; 225 } 226 227 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 228 amdgpu_crtc->pflip_works = work; 229 230 231 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 232 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 233 /* update crtc fb */ 234 crtc->primary->fb = fb; 235 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 236 amdgpu_display_flip_work_func(&work->flip_work.work); 237 return 0; 238 239 pflip_cleanup: 240 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 241 DRM_ERROR("failed to reserve new abo in error path\n"); 242 goto cleanup; 243 } 244 unpin: 245 if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { 246 DRM_ERROR("failed to unpin new abo in error path\n"); 247 } 248 unreserve: 249 amdgpu_bo_unreserve(new_abo); 250 251 cleanup: 252 amdgpu_bo_unref(&work->old_abo); 253 dma_fence_put(work->excl); 254 for (i = 0; i < work->shared_count; ++i) 255 dma_fence_put(work->shared[i]); 256 kfree(work->shared); 257 kfree(work); 258 259 return r; 260 } 261 262 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 263 struct drm_modeset_acquire_ctx *ctx) 264 { 265 struct drm_device *dev; 266 struct amdgpu_device *adev; 267 struct drm_crtc *crtc; 268 bool active = false; 269 int ret; 270 271 if (!set || !set->crtc) 272 return -EINVAL; 273 274 dev = set->crtc->dev; 275 276 ret = pm_runtime_get_sync(dev->dev); 277 if (ret < 0) 278 return ret; 279 280 ret = drm_crtc_helper_set_config(set, ctx); 281 282 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 283 if (crtc->enabled) 284 active = true; 285 286 pm_runtime_mark_last_busy(dev->dev); 287 288 adev = dev->dev_private; 289 /* if we have active crtcs and we don't have a power ref, 290 take the current one */ 291 if (active && !adev->have_disp_power_ref) { 292 adev->have_disp_power_ref = true; 293 return ret; 294 } 295 /* if we have no active crtcs, then drop the power ref 296 we got before */ 297 if (!active && adev->have_disp_power_ref) { 298 pm_runtime_put_autosuspend(dev->dev); 299 adev->have_disp_power_ref = false; 300 } 301 302 /* drop the power reference we got coming in here */ 303 pm_runtime_put_autosuspend(dev->dev); 304 return ret; 305 } 306 307 static const char *encoder_names[41] = { 308 "NONE", 309 "INTERNAL_LVDS", 310 "INTERNAL_TMDS1", 311 "INTERNAL_TMDS2", 312 "INTERNAL_DAC1", 313 "INTERNAL_DAC2", 314 "INTERNAL_SDVOA", 315 "INTERNAL_SDVOB", 316 "SI170B", 317 "CH7303", 318 "CH7301", 319 "INTERNAL_DVO1", 320 "EXTERNAL_SDVOA", 321 "EXTERNAL_SDVOB", 322 "TITFP513", 323 "INTERNAL_LVTM1", 324 "VT1623", 325 "HDMI_SI1930", 326 "HDMI_INTERNAL", 327 "INTERNAL_KLDSCP_TMDS1", 328 "INTERNAL_KLDSCP_DVO1", 329 "INTERNAL_KLDSCP_DAC1", 330 "INTERNAL_KLDSCP_DAC2", 331 "SI178", 332 "MVPU_FPGA", 333 "INTERNAL_DDI", 334 "VT1625", 335 "HDMI_SI1932", 336 "DP_AN9801", 337 "DP_DP501", 338 "INTERNAL_UNIPHY", 339 "INTERNAL_KLDSCP_LVTMA", 340 "INTERNAL_UNIPHY1", 341 "INTERNAL_UNIPHY2", 342 "NUTMEG", 343 "TRAVIS", 344 "INTERNAL_VCE", 345 "INTERNAL_UNIPHY3", 346 "HDMI_ANX9805", 347 "INTERNAL_AMCLK", 348 "VIRTUAL", 349 }; 350 351 static const char *hpd_names[6] = { 352 "HPD1", 353 "HPD2", 354 "HPD3", 355 "HPD4", 356 "HPD5", 357 "HPD6", 358 }; 359 360 void amdgpu_display_print_display_setup(struct drm_device *dev) 361 { 362 struct drm_connector *connector; 363 struct amdgpu_connector *amdgpu_connector; 364 struct drm_encoder *encoder; 365 struct amdgpu_encoder *amdgpu_encoder; 366 uint32_t devices; 367 int i = 0; 368 369 DRM_INFO("AMDGPU Display Connectors\n"); 370 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 371 amdgpu_connector = to_amdgpu_connector(connector); 372 DRM_INFO("Connector %d:\n", i); 373 DRM_INFO(" %s\n", connector->name); 374 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 375 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 376 if (amdgpu_connector->ddc_bus) { 377 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 378 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 379 amdgpu_connector->ddc_bus->rec.mask_data_reg, 380 amdgpu_connector->ddc_bus->rec.a_clk_reg, 381 amdgpu_connector->ddc_bus->rec.a_data_reg, 382 amdgpu_connector->ddc_bus->rec.en_clk_reg, 383 amdgpu_connector->ddc_bus->rec.en_data_reg, 384 amdgpu_connector->ddc_bus->rec.y_clk_reg, 385 amdgpu_connector->ddc_bus->rec.y_data_reg); 386 if (amdgpu_connector->router.ddc_valid) 387 DRM_INFO(" DDC Router 0x%x/0x%x\n", 388 amdgpu_connector->router.ddc_mux_control_pin, 389 amdgpu_connector->router.ddc_mux_state); 390 if (amdgpu_connector->router.cd_valid) 391 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 392 amdgpu_connector->router.cd_mux_control_pin, 393 amdgpu_connector->router.cd_mux_state); 394 } else { 395 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 396 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 397 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 398 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 399 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 400 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 401 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 402 } 403 DRM_INFO(" Encoders:\n"); 404 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 405 amdgpu_encoder = to_amdgpu_encoder(encoder); 406 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 407 if (devices) { 408 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 409 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 410 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 411 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 412 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 413 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 414 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 415 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 416 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 417 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 418 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 419 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 420 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 421 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 422 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 423 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 424 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 425 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 426 if (devices & ATOM_DEVICE_TV1_SUPPORT) 427 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 428 if (devices & ATOM_DEVICE_CV_SUPPORT) 429 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 430 } 431 } 432 i++; 433 } 434 } 435 436 /** 437 * amdgpu_display_ddc_probe 438 * 439 */ 440 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 441 bool use_aux) 442 { 443 u8 out = 0x0; 444 u8 buf[8]; 445 int ret; 446 struct i2c_msg msgs[] = { 447 { 448 .addr = DDC_ADDR, 449 .flags = 0, 450 .len = 1, 451 .buf = &out, 452 }, 453 { 454 .addr = DDC_ADDR, 455 .flags = I2C_M_RD, 456 .len = 8, 457 .buf = buf, 458 } 459 }; 460 461 /* on hw with routers, select right port */ 462 if (amdgpu_connector->router.ddc_valid) 463 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 464 465 if (use_aux) { 466 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 467 } else { 468 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 469 } 470 471 if (ret != 2) 472 /* Couldn't find an accessible DDC on this connector */ 473 return false; 474 /* Probe also for valid EDID header 475 * EDID header starts with: 476 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 477 * Only the first 6 bytes must be valid as 478 * drm_edid_block_valid() can fix the last 2 bytes */ 479 if (drm_edid_header_is_valid(buf) < 6) { 480 /* Couldn't find an accessible EDID on this 481 * connector */ 482 return false; 483 } 484 return true; 485 } 486 487 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 488 .destroy = drm_gem_fb_destroy, 489 .create_handle = drm_gem_fb_create_handle, 490 }; 491 492 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) 493 { 494 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 495 496 #if defined(CONFIG_DRM_AMD_DC) 497 if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && 498 adev->flags & AMD_IS_APU && 499 amdgpu_device_asic_has_dc_support(adev->asic_type)) 500 domain |= AMDGPU_GEM_DOMAIN_GTT; 501 #endif 502 503 return domain; 504 } 505 506 int amdgpu_display_framebuffer_init(struct drm_device *dev, 507 struct amdgpu_framebuffer *rfb, 508 const struct drm_mode_fb_cmd2 *mode_cmd, 509 struct drm_gem_object *obj) 510 { 511 int ret; 512 rfb->base.obj[0] = obj; 513 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 514 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 515 if (ret) { 516 rfb->base.obj[0] = NULL; 517 return ret; 518 } 519 return 0; 520 } 521 522 struct drm_framebuffer * 523 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 524 struct drm_file *file_priv, 525 const struct drm_mode_fb_cmd2 *mode_cmd) 526 { 527 struct drm_gem_object *obj; 528 struct amdgpu_framebuffer *amdgpu_fb; 529 int ret; 530 531 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 532 if (obj == NULL) { 533 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 534 "can't create framebuffer\n", mode_cmd->handles[0]); 535 return ERR_PTR(-ENOENT); 536 } 537 538 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 539 if (obj->import_attach) { 540 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 541 return ERR_PTR(-EINVAL); 542 } 543 544 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 545 if (amdgpu_fb == NULL) { 546 drm_gem_object_put_unlocked(obj); 547 return ERR_PTR(-ENOMEM); 548 } 549 550 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 551 if (ret) { 552 kfree(amdgpu_fb); 553 drm_gem_object_put_unlocked(obj); 554 return ERR_PTR(ret); 555 } 556 557 return &amdgpu_fb->base; 558 } 559 560 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 561 .fb_create = amdgpu_display_user_framebuffer_create, 562 .output_poll_changed = drm_fb_helper_output_poll_changed, 563 }; 564 565 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 566 { { UNDERSCAN_OFF, "off" }, 567 { UNDERSCAN_ON, "on" }, 568 { UNDERSCAN_AUTO, "auto" }, 569 }; 570 571 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 572 { { AMDGPU_AUDIO_DISABLE, "off" }, 573 { AMDGPU_AUDIO_ENABLE, "on" }, 574 { AMDGPU_AUDIO_AUTO, "auto" }, 575 }; 576 577 /* XXX support different dither options? spatial, temporal, both, etc. */ 578 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 579 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 580 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 581 }; 582 583 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 584 { 585 int sz; 586 587 adev->mode_info.coherent_mode_property = 588 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 589 if (!adev->mode_info.coherent_mode_property) 590 return -ENOMEM; 591 592 adev->mode_info.load_detect_property = 593 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 594 if (!adev->mode_info.load_detect_property) 595 return -ENOMEM; 596 597 drm_mode_create_scaling_mode_property(adev->ddev); 598 599 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 600 adev->mode_info.underscan_property = 601 drm_property_create_enum(adev->ddev, 0, 602 "underscan", 603 amdgpu_underscan_enum_list, sz); 604 605 adev->mode_info.underscan_hborder_property = 606 drm_property_create_range(adev->ddev, 0, 607 "underscan hborder", 0, 128); 608 if (!adev->mode_info.underscan_hborder_property) 609 return -ENOMEM; 610 611 adev->mode_info.underscan_vborder_property = 612 drm_property_create_range(adev->ddev, 0, 613 "underscan vborder", 0, 128); 614 if (!adev->mode_info.underscan_vborder_property) 615 return -ENOMEM; 616 617 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 618 adev->mode_info.audio_property = 619 drm_property_create_enum(adev->ddev, 0, 620 "audio", 621 amdgpu_audio_enum_list, sz); 622 623 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 624 adev->mode_info.dither_property = 625 drm_property_create_enum(adev->ddev, 0, 626 "dither", 627 amdgpu_dither_enum_list, sz); 628 629 return 0; 630 } 631 632 void amdgpu_display_update_priority(struct amdgpu_device *adev) 633 { 634 /* adjustment options for the display watermarks */ 635 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 636 adev->mode_info.disp_priority = 0; 637 else 638 adev->mode_info.disp_priority = amdgpu_disp_priority; 639 640 } 641 642 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 643 { 644 /* try and guess if this is a tv or a monitor */ 645 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 646 (mode->vdisplay == 576) || /* 576p */ 647 (mode->vdisplay == 720) || /* 720p */ 648 (mode->vdisplay == 1080)) /* 1080p */ 649 return true; 650 else 651 return false; 652 } 653 654 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 655 const struct drm_display_mode *mode, 656 struct drm_display_mode *adjusted_mode) 657 { 658 struct drm_device *dev = crtc->dev; 659 struct drm_encoder *encoder; 660 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 661 struct amdgpu_encoder *amdgpu_encoder; 662 struct drm_connector *connector; 663 struct amdgpu_connector *amdgpu_connector; 664 u32 src_v = 1, dst_v = 1; 665 u32 src_h = 1, dst_h = 1; 666 667 amdgpu_crtc->h_border = 0; 668 amdgpu_crtc->v_border = 0; 669 670 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 671 if (encoder->crtc != crtc) 672 continue; 673 amdgpu_encoder = to_amdgpu_encoder(encoder); 674 connector = amdgpu_get_connector_for_encoder(encoder); 675 amdgpu_connector = to_amdgpu_connector(connector); 676 677 /* set scaling */ 678 if (amdgpu_encoder->rmx_type == RMX_OFF) 679 amdgpu_crtc->rmx_type = RMX_OFF; 680 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 681 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 682 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 683 else 684 amdgpu_crtc->rmx_type = RMX_OFF; 685 /* copy native mode */ 686 memcpy(&amdgpu_crtc->native_mode, 687 &amdgpu_encoder->native_mode, 688 sizeof(struct drm_display_mode)); 689 src_v = crtc->mode.vdisplay; 690 dst_v = amdgpu_crtc->native_mode.vdisplay; 691 src_h = crtc->mode.hdisplay; 692 dst_h = amdgpu_crtc->native_mode.hdisplay; 693 694 /* fix up for overscan on hdmi */ 695 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 696 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 697 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 698 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 699 amdgpu_display_is_hdtv_mode(mode)))) { 700 if (amdgpu_encoder->underscan_hborder != 0) 701 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 702 else 703 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 704 if (amdgpu_encoder->underscan_vborder != 0) 705 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 706 else 707 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 708 amdgpu_crtc->rmx_type = RMX_FULL; 709 src_v = crtc->mode.vdisplay; 710 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 711 src_h = crtc->mode.hdisplay; 712 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 713 } 714 } 715 if (amdgpu_crtc->rmx_type != RMX_OFF) { 716 fixed20_12 a, b; 717 a.full = dfixed_const(src_v); 718 b.full = dfixed_const(dst_v); 719 amdgpu_crtc->vsc.full = dfixed_div(a, b); 720 a.full = dfixed_const(src_h); 721 b.full = dfixed_const(dst_h); 722 amdgpu_crtc->hsc.full = dfixed_div(a, b); 723 } else { 724 amdgpu_crtc->vsc.full = dfixed_const(1); 725 amdgpu_crtc->hsc.full = dfixed_const(1); 726 } 727 return true; 728 } 729 730 /* 731 * Retrieve current video scanout position of crtc on a given gpu, and 732 * an optional accurate timestamp of when query happened. 733 * 734 * \param dev Device to query. 735 * \param pipe Crtc to query. 736 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 737 * For driver internal use only also supports these flags: 738 * 739 * USE_REAL_VBLANKSTART to use the real start of vblank instead 740 * of a fudged earlier start of vblank. 741 * 742 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 743 * fudged earlier start of vblank in *vpos and the distance 744 * to true start of vblank in *hpos. 745 * 746 * \param *vpos Location where vertical scanout position should be stored. 747 * \param *hpos Location where horizontal scanout position should go. 748 * \param *stime Target location for timestamp taken immediately before 749 * scanout position query. Can be NULL to skip timestamp. 750 * \param *etime Target location for timestamp taken immediately after 751 * scanout position query. Can be NULL to skip timestamp. 752 * 753 * Returns vpos as a positive number while in active scanout area. 754 * Returns vpos as a negative number inside vblank, counting the number 755 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 756 * until start of active scanout / end of vblank." 757 * 758 * \return Flags, or'ed together as follows: 759 * 760 * DRM_SCANOUTPOS_VALID = Query successful. 761 * DRM_SCANOUTPOS_INVBL = Inside vblank. 762 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 763 * this flag means that returned position may be offset by a constant but 764 * unknown small number of scanlines wrt. real scanout position. 765 * 766 */ 767 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 768 unsigned int pipe, unsigned int flags, int *vpos, 769 int *hpos, ktime_t *stime, ktime_t *etime, 770 const struct drm_display_mode *mode) 771 { 772 u32 vbl = 0, position = 0; 773 int vbl_start, vbl_end, vtotal, ret = 0; 774 bool in_vbl = true; 775 776 struct amdgpu_device *adev = dev->dev_private; 777 778 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 779 780 /* Get optional system timestamp before query. */ 781 if (stime) 782 *stime = ktime_get(); 783 784 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 785 ret |= DRM_SCANOUTPOS_VALID; 786 787 /* Get optional system timestamp after query. */ 788 if (etime) 789 *etime = ktime_get(); 790 791 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 792 793 /* Decode into vertical and horizontal scanout position. */ 794 *vpos = position & 0x1fff; 795 *hpos = (position >> 16) & 0x1fff; 796 797 /* Valid vblank area boundaries from gpu retrieved? */ 798 if (vbl > 0) { 799 /* Yes: Decode. */ 800 ret |= DRM_SCANOUTPOS_ACCURATE; 801 vbl_start = vbl & 0x1fff; 802 vbl_end = (vbl >> 16) & 0x1fff; 803 } 804 else { 805 /* No: Fake something reasonable which gives at least ok results. */ 806 vbl_start = mode->crtc_vdisplay; 807 vbl_end = 0; 808 } 809 810 /* Called from driver internal vblank counter query code? */ 811 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 812 /* Caller wants distance from real vbl_start in *hpos */ 813 *hpos = *vpos - vbl_start; 814 } 815 816 /* Fudge vblank to start a few scanlines earlier to handle the 817 * problem that vblank irqs fire a few scanlines before start 818 * of vblank. Some driver internal callers need the true vblank 819 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 820 * 821 * The cause of the "early" vblank irq is that the irq is triggered 822 * by the line buffer logic when the line buffer read position enters 823 * the vblank, whereas our crtc scanout position naturally lags the 824 * line buffer read position. 825 */ 826 if (!(flags & USE_REAL_VBLANKSTART)) 827 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 828 829 /* Test scanout position against vblank region. */ 830 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 831 in_vbl = false; 832 833 /* In vblank? */ 834 if (in_vbl) 835 ret |= DRM_SCANOUTPOS_IN_VBLANK; 836 837 /* Called from driver internal vblank counter query code? */ 838 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 839 /* Caller wants distance from fudged earlier vbl_start */ 840 *vpos -= vbl_start; 841 return ret; 842 } 843 844 /* Check if inside vblank area and apply corrective offsets: 845 * vpos will then be >=0 in video scanout area, but negative 846 * within vblank area, counting down the number of lines until 847 * start of scanout. 848 */ 849 850 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 851 if (in_vbl && (*vpos >= vbl_start)) { 852 vtotal = mode->crtc_vtotal; 853 *vpos = *vpos - vtotal; 854 } 855 856 /* Correct for shifted end of vbl at vbl_end. */ 857 *vpos = *vpos - vbl_end; 858 859 return ret; 860 } 861 862 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 863 { 864 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 865 return AMDGPU_CRTC_IRQ_NONE; 866 867 switch (crtc) { 868 case 0: 869 return AMDGPU_CRTC_IRQ_VBLANK1; 870 case 1: 871 return AMDGPU_CRTC_IRQ_VBLANK2; 872 case 2: 873 return AMDGPU_CRTC_IRQ_VBLANK3; 874 case 3: 875 return AMDGPU_CRTC_IRQ_VBLANK4; 876 case 4: 877 return AMDGPU_CRTC_IRQ_VBLANK5; 878 case 5: 879 return AMDGPU_CRTC_IRQ_VBLANK6; 880 default: 881 return AMDGPU_CRTC_IRQ_NONE; 882 } 883 } 884