1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_runtime.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_vblank.h> 42 43 static void amdgpu_display_flip_callback(struct dma_fence *f, 44 struct dma_fence_cb *cb) 45 { 46 struct amdgpu_flip_work *work = 47 container_of(cb, struct amdgpu_flip_work, cb); 48 49 dma_fence_put(f); 50 schedule_work(&work->flip_work.work); 51 } 52 53 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 54 struct dma_fence **f) 55 { 56 struct dma_fence *fence= *f; 57 58 if (fence == NULL) 59 return false; 60 61 *f = NULL; 62 63 if (!dma_fence_add_callback(fence, &work->cb, 64 amdgpu_display_flip_callback)) 65 return true; 66 67 dma_fence_put(fence); 68 return false; 69 } 70 71 static void amdgpu_display_flip_work_func(struct work_struct *__work) 72 { 73 struct delayed_work *delayed_work = 74 container_of(__work, struct delayed_work, work); 75 struct amdgpu_flip_work *work = 76 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 77 struct amdgpu_device *adev = work->adev; 78 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 79 80 struct drm_crtc *crtc = &amdgpu_crtc->base; 81 unsigned long flags; 82 unsigned i; 83 int vpos, hpos; 84 85 if (amdgpu_display_flip_handle_fence(work, &work->excl)) 86 return; 87 88 for (i = 0; i < work->shared_count; ++i) 89 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 90 return; 91 92 /* Wait until we're out of the vertical blank period before the one 93 * targeted by the flip 94 */ 95 if (amdgpu_crtc->enabled && 96 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, 97 &vpos, &hpos, NULL, NULL, 98 &crtc->hwmode) 99 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 100 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 101 (int)(work->target_vblank - 102 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 103 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 104 return; 105 } 106 107 /* We borrow the event spin lock for protecting flip_status */ 108 spin_lock_irqsave(&crtc->dev->event_lock, flags); 109 110 /* Do the flip (mmio) */ 111 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 112 113 /* Set the flip status */ 114 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 115 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 116 117 118 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 119 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 120 121 } 122 123 /* 124 * Handle unpin events outside the interrupt handler proper. 125 */ 126 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 127 { 128 struct amdgpu_flip_work *work = 129 container_of(__work, struct amdgpu_flip_work, unpin_work); 130 int r; 131 132 /* unpin of the old buffer */ 133 r = amdgpu_bo_reserve(work->old_abo, true); 134 if (likely(r == 0)) { 135 amdgpu_bo_unpin(work->old_abo); 136 amdgpu_bo_unreserve(work->old_abo); 137 } else 138 DRM_ERROR("failed to reserve buffer after flip\n"); 139 140 amdgpu_bo_unref(&work->old_abo); 141 kfree(work->shared); 142 kfree(work); 143 } 144 145 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 146 struct drm_framebuffer *fb, 147 struct drm_pending_vblank_event *event, 148 uint32_t page_flip_flags, uint32_t target, 149 struct drm_modeset_acquire_ctx *ctx) 150 { 151 struct drm_device *dev = crtc->dev; 152 struct amdgpu_device *adev = drm_to_adev(dev); 153 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 154 struct drm_gem_object *obj; 155 struct amdgpu_flip_work *work; 156 struct amdgpu_bo *new_abo; 157 unsigned long flags; 158 u64 tiling_flags; 159 int i, r; 160 161 work = kzalloc(sizeof *work, GFP_KERNEL); 162 if (work == NULL) 163 return -ENOMEM; 164 165 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 166 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 167 168 work->event = event; 169 work->adev = adev; 170 work->crtc_id = amdgpu_crtc->crtc_id; 171 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 172 173 /* schedule unpin of the old buffer */ 174 obj = crtc->primary->fb->obj[0]; 175 176 /* take a reference to the old object */ 177 work->old_abo = gem_to_amdgpu_bo(obj); 178 amdgpu_bo_ref(work->old_abo); 179 180 obj = fb->obj[0]; 181 new_abo = gem_to_amdgpu_bo(obj); 182 183 /* pin the new buffer */ 184 r = amdgpu_bo_reserve(new_abo, false); 185 if (unlikely(r != 0)) { 186 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 187 goto cleanup; 188 } 189 190 if (!adev->enable_virtual_display) { 191 r = amdgpu_bo_pin(new_abo, 192 amdgpu_display_supported_domains(adev, new_abo->flags)); 193 if (unlikely(r != 0)) { 194 DRM_ERROR("failed to pin new abo buffer before flip\n"); 195 goto unreserve; 196 } 197 } 198 199 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 200 if (unlikely(r != 0)) { 201 DRM_ERROR("%p bind failed\n", new_abo); 202 goto unpin; 203 } 204 205 r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl, 206 &work->shared_count, 207 &work->shared); 208 if (unlikely(r != 0)) { 209 DRM_ERROR("failed to get fences for buffer\n"); 210 goto unpin; 211 } 212 213 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 214 amdgpu_bo_unreserve(new_abo); 215 216 if (!adev->enable_virtual_display) 217 work->base = amdgpu_bo_gpu_offset(new_abo); 218 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 219 amdgpu_get_vblank_counter_kms(crtc); 220 221 /* we borrow the event spin lock for protecting flip_wrok */ 222 spin_lock_irqsave(&crtc->dev->event_lock, flags); 223 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 224 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 225 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 226 r = -EBUSY; 227 goto pflip_cleanup; 228 } 229 230 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 231 amdgpu_crtc->pflip_works = work; 232 233 234 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 235 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 236 /* update crtc fb */ 237 crtc->primary->fb = fb; 238 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 239 amdgpu_display_flip_work_func(&work->flip_work.work); 240 return 0; 241 242 pflip_cleanup: 243 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 244 DRM_ERROR("failed to reserve new abo in error path\n"); 245 goto cleanup; 246 } 247 unpin: 248 if (!adev->enable_virtual_display) 249 amdgpu_bo_unpin(new_abo); 250 251 unreserve: 252 amdgpu_bo_unreserve(new_abo); 253 254 cleanup: 255 amdgpu_bo_unref(&work->old_abo); 256 dma_fence_put(work->excl); 257 for (i = 0; i < work->shared_count; ++i) 258 dma_fence_put(work->shared[i]); 259 kfree(work->shared); 260 kfree(work); 261 262 return r; 263 } 264 265 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 266 struct drm_modeset_acquire_ctx *ctx) 267 { 268 struct drm_device *dev; 269 struct amdgpu_device *adev; 270 struct drm_crtc *crtc; 271 bool active = false; 272 int ret; 273 274 if (!set || !set->crtc) 275 return -EINVAL; 276 277 dev = set->crtc->dev; 278 279 ret = pm_runtime_get_sync(dev->dev); 280 if (ret < 0) 281 goto out; 282 283 ret = drm_crtc_helper_set_config(set, ctx); 284 285 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 286 if (crtc->enabled) 287 active = true; 288 289 pm_runtime_mark_last_busy(dev->dev); 290 291 adev = drm_to_adev(dev); 292 /* if we have active crtcs and we don't have a power ref, 293 take the current one */ 294 if (active && !adev->have_disp_power_ref) { 295 adev->have_disp_power_ref = true; 296 goto out; 297 } 298 /* if we have no active crtcs, then drop the power ref 299 we got before */ 300 if (!active && adev->have_disp_power_ref) { 301 pm_runtime_put_autosuspend(dev->dev); 302 adev->have_disp_power_ref = false; 303 } 304 305 out: 306 /* drop the power reference we got coming in here */ 307 pm_runtime_put_autosuspend(dev->dev); 308 return ret; 309 } 310 311 static const char *encoder_names[41] = { 312 "NONE", 313 "INTERNAL_LVDS", 314 "INTERNAL_TMDS1", 315 "INTERNAL_TMDS2", 316 "INTERNAL_DAC1", 317 "INTERNAL_DAC2", 318 "INTERNAL_SDVOA", 319 "INTERNAL_SDVOB", 320 "SI170B", 321 "CH7303", 322 "CH7301", 323 "INTERNAL_DVO1", 324 "EXTERNAL_SDVOA", 325 "EXTERNAL_SDVOB", 326 "TITFP513", 327 "INTERNAL_LVTM1", 328 "VT1623", 329 "HDMI_SI1930", 330 "HDMI_INTERNAL", 331 "INTERNAL_KLDSCP_TMDS1", 332 "INTERNAL_KLDSCP_DVO1", 333 "INTERNAL_KLDSCP_DAC1", 334 "INTERNAL_KLDSCP_DAC2", 335 "SI178", 336 "MVPU_FPGA", 337 "INTERNAL_DDI", 338 "VT1625", 339 "HDMI_SI1932", 340 "DP_AN9801", 341 "DP_DP501", 342 "INTERNAL_UNIPHY", 343 "INTERNAL_KLDSCP_LVTMA", 344 "INTERNAL_UNIPHY1", 345 "INTERNAL_UNIPHY2", 346 "NUTMEG", 347 "TRAVIS", 348 "INTERNAL_VCE", 349 "INTERNAL_UNIPHY3", 350 "HDMI_ANX9805", 351 "INTERNAL_AMCLK", 352 "VIRTUAL", 353 }; 354 355 static const char *hpd_names[6] = { 356 "HPD1", 357 "HPD2", 358 "HPD3", 359 "HPD4", 360 "HPD5", 361 "HPD6", 362 }; 363 364 void amdgpu_display_print_display_setup(struct drm_device *dev) 365 { 366 struct drm_connector *connector; 367 struct amdgpu_connector *amdgpu_connector; 368 struct drm_encoder *encoder; 369 struct amdgpu_encoder *amdgpu_encoder; 370 struct drm_connector_list_iter iter; 371 uint32_t devices; 372 int i = 0; 373 374 drm_connector_list_iter_begin(dev, &iter); 375 DRM_INFO("AMDGPU Display Connectors\n"); 376 drm_for_each_connector_iter(connector, &iter) { 377 amdgpu_connector = to_amdgpu_connector(connector); 378 DRM_INFO("Connector %d:\n", i); 379 DRM_INFO(" %s\n", connector->name); 380 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 381 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 382 if (amdgpu_connector->ddc_bus) { 383 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 384 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 385 amdgpu_connector->ddc_bus->rec.mask_data_reg, 386 amdgpu_connector->ddc_bus->rec.a_clk_reg, 387 amdgpu_connector->ddc_bus->rec.a_data_reg, 388 amdgpu_connector->ddc_bus->rec.en_clk_reg, 389 amdgpu_connector->ddc_bus->rec.en_data_reg, 390 amdgpu_connector->ddc_bus->rec.y_clk_reg, 391 amdgpu_connector->ddc_bus->rec.y_data_reg); 392 if (amdgpu_connector->router.ddc_valid) 393 DRM_INFO(" DDC Router 0x%x/0x%x\n", 394 amdgpu_connector->router.ddc_mux_control_pin, 395 amdgpu_connector->router.ddc_mux_state); 396 if (amdgpu_connector->router.cd_valid) 397 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 398 amdgpu_connector->router.cd_mux_control_pin, 399 amdgpu_connector->router.cd_mux_state); 400 } else { 401 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 402 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 403 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 404 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 405 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 406 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 407 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 408 } 409 DRM_INFO(" Encoders:\n"); 410 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 411 amdgpu_encoder = to_amdgpu_encoder(encoder); 412 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 413 if (devices) { 414 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 415 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 416 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 417 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 418 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 419 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 420 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 421 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 422 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 423 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 424 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 425 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 426 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 427 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 428 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 429 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 430 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 431 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 432 if (devices & ATOM_DEVICE_TV1_SUPPORT) 433 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 434 if (devices & ATOM_DEVICE_CV_SUPPORT) 435 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 436 } 437 } 438 i++; 439 } 440 drm_connector_list_iter_end(&iter); 441 } 442 443 /** 444 * amdgpu_display_ddc_probe 445 * 446 */ 447 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 448 bool use_aux) 449 { 450 u8 out = 0x0; 451 u8 buf[8]; 452 int ret; 453 struct i2c_msg msgs[] = { 454 { 455 .addr = DDC_ADDR, 456 .flags = 0, 457 .len = 1, 458 .buf = &out, 459 }, 460 { 461 .addr = DDC_ADDR, 462 .flags = I2C_M_RD, 463 .len = 8, 464 .buf = buf, 465 } 466 }; 467 468 /* on hw with routers, select right port */ 469 if (amdgpu_connector->router.ddc_valid) 470 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 471 472 if (use_aux) { 473 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 474 } else { 475 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 476 } 477 478 if (ret != 2) 479 /* Couldn't find an accessible DDC on this connector */ 480 return false; 481 /* Probe also for valid EDID header 482 * EDID header starts with: 483 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 484 * Only the first 6 bytes must be valid as 485 * drm_edid_block_valid() can fix the last 2 bytes */ 486 if (drm_edid_header_is_valid(buf) < 6) { 487 /* Couldn't find an accessible EDID on this 488 * connector */ 489 return false; 490 } 491 return true; 492 } 493 494 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 495 .destroy = drm_gem_fb_destroy, 496 .create_handle = drm_gem_fb_create_handle, 497 }; 498 499 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 500 uint64_t bo_flags) 501 { 502 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 503 504 #if defined(CONFIG_DRM_AMD_DC) 505 /* 506 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 507 * is not supported for this board. But this mapping is required 508 * to avoid hang caused by placement of scanout BO in GTT on certain 509 * APUs. So force the BO placement to VRAM in case this architecture 510 * will not allow USWC mappings. 511 * Also, don't allow GTT domain if the BO doens't have USWC falg set. 512 */ 513 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 514 amdgpu_bo_support_uswc(bo_flags) && 515 amdgpu_device_asic_has_dc_support(adev->asic_type)) { 516 switch (adev->asic_type) { 517 case CHIP_CARRIZO: 518 case CHIP_STONEY: 519 domain |= AMDGPU_GEM_DOMAIN_GTT; 520 break; 521 case CHIP_RAVEN: 522 /* enable S/G on PCO and RV2 */ 523 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 524 (adev->apu_flags & AMD_APU_IS_PICASSO)) 525 domain |= AMDGPU_GEM_DOMAIN_GTT; 526 break; 527 default: 528 break; 529 } 530 } 531 #endif 532 533 return domain; 534 } 535 536 int amdgpu_display_framebuffer_init(struct drm_device *dev, 537 struct amdgpu_framebuffer *rfb, 538 const struct drm_mode_fb_cmd2 *mode_cmd, 539 struct drm_gem_object *obj) 540 { 541 int ret; 542 rfb->base.obj[0] = obj; 543 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 544 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 545 if (ret) { 546 rfb->base.obj[0] = NULL; 547 return ret; 548 } 549 return 0; 550 } 551 552 struct drm_framebuffer * 553 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 554 struct drm_file *file_priv, 555 const struct drm_mode_fb_cmd2 *mode_cmd) 556 { 557 struct drm_gem_object *obj; 558 struct amdgpu_framebuffer *amdgpu_fb; 559 int ret; 560 561 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 562 if (obj == NULL) { 563 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 564 "can't create framebuffer\n", mode_cmd->handles[0]); 565 return ERR_PTR(-ENOENT); 566 } 567 568 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 569 if (obj->import_attach) { 570 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 571 return ERR_PTR(-EINVAL); 572 } 573 574 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 575 if (amdgpu_fb == NULL) { 576 drm_gem_object_put(obj); 577 return ERR_PTR(-ENOMEM); 578 } 579 580 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 581 if (ret) { 582 kfree(amdgpu_fb); 583 drm_gem_object_put(obj); 584 return ERR_PTR(ret); 585 } 586 587 return &amdgpu_fb->base; 588 } 589 590 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 591 .fb_create = amdgpu_display_user_framebuffer_create, 592 .output_poll_changed = drm_fb_helper_output_poll_changed, 593 }; 594 595 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 596 { { UNDERSCAN_OFF, "off" }, 597 { UNDERSCAN_ON, "on" }, 598 { UNDERSCAN_AUTO, "auto" }, 599 }; 600 601 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 602 { { AMDGPU_AUDIO_DISABLE, "off" }, 603 { AMDGPU_AUDIO_ENABLE, "on" }, 604 { AMDGPU_AUDIO_AUTO, "auto" }, 605 }; 606 607 /* XXX support different dither options? spatial, temporal, both, etc. */ 608 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 609 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 610 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 611 }; 612 613 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 614 { 615 int sz; 616 617 adev->mode_info.coherent_mode_property = 618 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1); 619 if (!adev->mode_info.coherent_mode_property) 620 return -ENOMEM; 621 622 adev->mode_info.load_detect_property = 623 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1); 624 if (!adev->mode_info.load_detect_property) 625 return -ENOMEM; 626 627 drm_mode_create_scaling_mode_property(adev_to_drm(adev)); 628 629 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 630 adev->mode_info.underscan_property = 631 drm_property_create_enum(adev_to_drm(adev), 0, 632 "underscan", 633 amdgpu_underscan_enum_list, sz); 634 635 adev->mode_info.underscan_hborder_property = 636 drm_property_create_range(adev_to_drm(adev), 0, 637 "underscan hborder", 0, 128); 638 if (!adev->mode_info.underscan_hborder_property) 639 return -ENOMEM; 640 641 adev->mode_info.underscan_vborder_property = 642 drm_property_create_range(adev_to_drm(adev), 0, 643 "underscan vborder", 0, 128); 644 if (!adev->mode_info.underscan_vborder_property) 645 return -ENOMEM; 646 647 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 648 adev->mode_info.audio_property = 649 drm_property_create_enum(adev_to_drm(adev), 0, 650 "audio", 651 amdgpu_audio_enum_list, sz); 652 653 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 654 adev->mode_info.dither_property = 655 drm_property_create_enum(adev_to_drm(adev), 0, 656 "dither", 657 amdgpu_dither_enum_list, sz); 658 659 if (amdgpu_device_has_dc_support(adev)) { 660 adev->mode_info.abm_level_property = 661 drm_property_create_range(adev_to_drm(adev), 0, 662 "abm level", 0, 4); 663 if (!adev->mode_info.abm_level_property) 664 return -ENOMEM; 665 } 666 667 return 0; 668 } 669 670 void amdgpu_display_update_priority(struct amdgpu_device *adev) 671 { 672 /* adjustment options for the display watermarks */ 673 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 674 adev->mode_info.disp_priority = 0; 675 else 676 adev->mode_info.disp_priority = amdgpu_disp_priority; 677 678 } 679 680 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 681 { 682 /* try and guess if this is a tv or a monitor */ 683 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 684 (mode->vdisplay == 576) || /* 576p */ 685 (mode->vdisplay == 720) || /* 720p */ 686 (mode->vdisplay == 1080)) /* 1080p */ 687 return true; 688 else 689 return false; 690 } 691 692 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 693 const struct drm_display_mode *mode, 694 struct drm_display_mode *adjusted_mode) 695 { 696 struct drm_device *dev = crtc->dev; 697 struct drm_encoder *encoder; 698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 699 struct amdgpu_encoder *amdgpu_encoder; 700 struct drm_connector *connector; 701 u32 src_v = 1, dst_v = 1; 702 u32 src_h = 1, dst_h = 1; 703 704 amdgpu_crtc->h_border = 0; 705 amdgpu_crtc->v_border = 0; 706 707 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 708 if (encoder->crtc != crtc) 709 continue; 710 amdgpu_encoder = to_amdgpu_encoder(encoder); 711 connector = amdgpu_get_connector_for_encoder(encoder); 712 713 /* set scaling */ 714 if (amdgpu_encoder->rmx_type == RMX_OFF) 715 amdgpu_crtc->rmx_type = RMX_OFF; 716 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 717 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 718 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 719 else 720 amdgpu_crtc->rmx_type = RMX_OFF; 721 /* copy native mode */ 722 memcpy(&amdgpu_crtc->native_mode, 723 &amdgpu_encoder->native_mode, 724 sizeof(struct drm_display_mode)); 725 src_v = crtc->mode.vdisplay; 726 dst_v = amdgpu_crtc->native_mode.vdisplay; 727 src_h = crtc->mode.hdisplay; 728 dst_h = amdgpu_crtc->native_mode.hdisplay; 729 730 /* fix up for overscan on hdmi */ 731 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 732 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 733 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 734 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 735 amdgpu_display_is_hdtv_mode(mode)))) { 736 if (amdgpu_encoder->underscan_hborder != 0) 737 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 738 else 739 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 740 if (amdgpu_encoder->underscan_vborder != 0) 741 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 742 else 743 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 744 amdgpu_crtc->rmx_type = RMX_FULL; 745 src_v = crtc->mode.vdisplay; 746 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 747 src_h = crtc->mode.hdisplay; 748 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 749 } 750 } 751 if (amdgpu_crtc->rmx_type != RMX_OFF) { 752 fixed20_12 a, b; 753 a.full = dfixed_const(src_v); 754 b.full = dfixed_const(dst_v); 755 amdgpu_crtc->vsc.full = dfixed_div(a, b); 756 a.full = dfixed_const(src_h); 757 b.full = dfixed_const(dst_h); 758 amdgpu_crtc->hsc.full = dfixed_div(a, b); 759 } else { 760 amdgpu_crtc->vsc.full = dfixed_const(1); 761 amdgpu_crtc->hsc.full = dfixed_const(1); 762 } 763 return true; 764 } 765 766 /* 767 * Retrieve current video scanout position of crtc on a given gpu, and 768 * an optional accurate timestamp of when query happened. 769 * 770 * \param dev Device to query. 771 * \param pipe Crtc to query. 772 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 773 * For driver internal use only also supports these flags: 774 * 775 * USE_REAL_VBLANKSTART to use the real start of vblank instead 776 * of a fudged earlier start of vblank. 777 * 778 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 779 * fudged earlier start of vblank in *vpos and the distance 780 * to true start of vblank in *hpos. 781 * 782 * \param *vpos Location where vertical scanout position should be stored. 783 * \param *hpos Location where horizontal scanout position should go. 784 * \param *stime Target location for timestamp taken immediately before 785 * scanout position query. Can be NULL to skip timestamp. 786 * \param *etime Target location for timestamp taken immediately after 787 * scanout position query. Can be NULL to skip timestamp. 788 * 789 * Returns vpos as a positive number while in active scanout area. 790 * Returns vpos as a negative number inside vblank, counting the number 791 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 792 * until start of active scanout / end of vblank." 793 * 794 * \return Flags, or'ed together as follows: 795 * 796 * DRM_SCANOUTPOS_VALID = Query successful. 797 * DRM_SCANOUTPOS_INVBL = Inside vblank. 798 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 799 * this flag means that returned position may be offset by a constant but 800 * unknown small number of scanlines wrt. real scanout position. 801 * 802 */ 803 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 804 unsigned int pipe, unsigned int flags, int *vpos, 805 int *hpos, ktime_t *stime, ktime_t *etime, 806 const struct drm_display_mode *mode) 807 { 808 u32 vbl = 0, position = 0; 809 int vbl_start, vbl_end, vtotal, ret = 0; 810 bool in_vbl = true; 811 812 struct amdgpu_device *adev = drm_to_adev(dev); 813 814 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 815 816 /* Get optional system timestamp before query. */ 817 if (stime) 818 *stime = ktime_get(); 819 820 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 821 ret |= DRM_SCANOUTPOS_VALID; 822 823 /* Get optional system timestamp after query. */ 824 if (etime) 825 *etime = ktime_get(); 826 827 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 828 829 /* Decode into vertical and horizontal scanout position. */ 830 *vpos = position & 0x1fff; 831 *hpos = (position >> 16) & 0x1fff; 832 833 /* Valid vblank area boundaries from gpu retrieved? */ 834 if (vbl > 0) { 835 /* Yes: Decode. */ 836 ret |= DRM_SCANOUTPOS_ACCURATE; 837 vbl_start = vbl & 0x1fff; 838 vbl_end = (vbl >> 16) & 0x1fff; 839 } 840 else { 841 /* No: Fake something reasonable which gives at least ok results. */ 842 vbl_start = mode->crtc_vdisplay; 843 vbl_end = 0; 844 } 845 846 /* Called from driver internal vblank counter query code? */ 847 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 848 /* Caller wants distance from real vbl_start in *hpos */ 849 *hpos = *vpos - vbl_start; 850 } 851 852 /* Fudge vblank to start a few scanlines earlier to handle the 853 * problem that vblank irqs fire a few scanlines before start 854 * of vblank. Some driver internal callers need the true vblank 855 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 856 * 857 * The cause of the "early" vblank irq is that the irq is triggered 858 * by the line buffer logic when the line buffer read position enters 859 * the vblank, whereas our crtc scanout position naturally lags the 860 * line buffer read position. 861 */ 862 if (!(flags & USE_REAL_VBLANKSTART)) 863 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 864 865 /* Test scanout position against vblank region. */ 866 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 867 in_vbl = false; 868 869 /* In vblank? */ 870 if (in_vbl) 871 ret |= DRM_SCANOUTPOS_IN_VBLANK; 872 873 /* Called from driver internal vblank counter query code? */ 874 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 875 /* Caller wants distance from fudged earlier vbl_start */ 876 *vpos -= vbl_start; 877 return ret; 878 } 879 880 /* Check if inside vblank area and apply corrective offsets: 881 * vpos will then be >=0 in video scanout area, but negative 882 * within vblank area, counting down the number of lines until 883 * start of scanout. 884 */ 885 886 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 887 if (in_vbl && (*vpos >= vbl_start)) { 888 vtotal = mode->crtc_vtotal; 889 890 /* With variable refresh rate displays the vpos can exceed 891 * the vtotal value. Clamp to 0 to return -vbl_end instead 892 * of guessing the remaining number of lines until scanout. 893 */ 894 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 895 } 896 897 /* Correct for shifted end of vbl at vbl_end. */ 898 *vpos = *vpos - vbl_end; 899 900 return ret; 901 } 902 903 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 904 { 905 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 906 return AMDGPU_CRTC_IRQ_NONE; 907 908 switch (crtc) { 909 case 0: 910 return AMDGPU_CRTC_IRQ_VBLANK1; 911 case 1: 912 return AMDGPU_CRTC_IRQ_VBLANK2; 913 case 2: 914 return AMDGPU_CRTC_IRQ_VBLANK3; 915 case 3: 916 return AMDGPU_CRTC_IRQ_VBLANK4; 917 case 4: 918 return AMDGPU_CRTC_IRQ_VBLANK5; 919 case 5: 920 return AMDGPU_CRTC_IRQ_VBLANK6; 921 default: 922 return AMDGPU_CRTC_IRQ_NONE; 923 } 924 } 925 926 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 927 bool in_vblank_irq, int *vpos, 928 int *hpos, ktime_t *stime, ktime_t *etime, 929 const struct drm_display_mode *mode) 930 { 931 struct drm_device *dev = crtc->dev; 932 unsigned int pipe = crtc->index; 933 934 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 935 stime, etime, mode); 936 } 937